Level shift circuit, PCB and chip

Abstract

The invention relates to the technical field of electronics, and discloses a level shift circuit, a PCB and a chip, the level shift circuit comprises a bias current unit, a primary level shift unit, a secondary level shift unit and a trigger unit; the bias current unit is electrically connected with the primary level shift unit, the primary level shift unit is electrically connected with the secondary level shift unit, and the secondary level shift unit is electrically connected with the trigger unit; the bias current unit is used for providing bias current, the primary level shift unit is used for realizing level shift, the secondary level shift unit is used for expanding an output voltage range, and the trigger unit is used for restoring a logic signal; through the collaborative design of the bias current unit, the primary level shift unit, the secondary level shift unit and the trigger unit, the stability of the output voltage is remarkably improved, the misoperation of a power tube is effectively avoided, and the strict requirement of a new generation of power modules on the stability is met.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a level shifting circuit, PCB board, and chip. Background Technology

[0002] In the field of high-voltage integrated circuits, high-voltage level shifting circuits, as a key component of high-side drive circuits, need to convert low-voltage signals into high-voltage signals to control high-side power transistors. However, existing level shifting circuits suffer from insufficient output voltage stability, which can easily lead to large output voltage deviations, resulting in power transistors being turned on incorrectly, causing short circuits between the upper and lower transistors, increased switching losses, and other faults. This seriously affects the reliability and performance of HVIC driver chips and makes it difficult to meet the stringent stability requirements of next-generation power modules. Summary of the Invention

[0003] The present invention aims to improve at least one technical problem in the prior art.

[0004] A first aspect of the present invention provides a level shifting circuit, comprising: a bias current unit, a first-level level shifting unit, a second-level level shifting unit, and a trigger unit; the bias current unit is electrically connected to the first-level level shifting unit, the first-level level shifting unit is electrically connected to the second-level level shifting unit, and the second-level level shifting unit is electrically connected to the trigger unit; the bias current unit is used to provide a bias current, the first-level level shifting unit is used to implement level shifting, the second-level level shifting unit is used to extend the output voltage range, and the trigger unit is used to restore the logic signal.

[0005] The beneficial effects of this invention are as follows: This invention includes a bias current unit that provides a fixed bias current, eliminating the dependence of the output voltage on the matching degree of the device's electrical parameters and fundamentally suppressing the impact of process and temperature fluctuations. Subsequently, a first-stage level shift unit is used to achieve basic level shifting, and a second-stage level shift unit is used to expand the output voltage range, ensuring the accuracy of signal conversion. Finally, a trigger unit restores the voltage signal to a logic signal, achieving reliable output of the drive pulse. Through the coordinated design of the bias current unit, the first-stage level shift unit, the second-stage level shift unit, and the trigger unit, this invention significantly improves the stability of the output voltage, effectively avoiding power transistor malfunctions and meeting the stringent stability requirements of next-generation power modules.

[0006] As some sub-solutions of the above technical solution, the bias current unit includes a voltage input terminal VCC, a bias current source IBIAS, and a nineteenth field-effect transistor M19; the voltage input terminal VCC is connected to one end of the bias current source IBIAS and the first-level level shift unit, the other end of the bias current source IBIAS is connected to the drain of the nineteenth field-effect transistor M19, the source of the nineteenth field-effect transistor M19 is grounded, and the gate of the nineteenth field-effect transistor M19 is connected to the first-level level shift unit.

[0007] As some sub-solutions of the above technical solution, the first-level level shifting unit includes a first input terminal SET, a second input terminal RESET, a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, a fourth field-effect transistor M4, a fifth field-effect transistor M5, a sixth field-effect transistor M6, a fifteenth field-effect transistor M15, a sixteenth field-effect transistor M16, a seventeenth field-effect transistor M17, and an eighteenth field-effect transistor M18;

[0008] The source of the third field-effect transistor M3 is connected to the source of the fourth field-effect transistor M4, the source of the fifth field-effect transistor M5, the source of the sixth field-effect transistor M6, and the second-level level shifting unit; the gate of the third field-effect transistor M3 is connected to the drain of the fourth field-effect transistor M4, the drain of the sixth field-effect transistor M6, the gate of the sixth field-effect transistor M6, the drain of the sixteenth field-effect transistor M16, and the second-level level shifting unit; the drain of the third field-effect transistor M3 is connected to the gate of the fourth field-effect transistor M4, the drain of the fifth field-effect transistor M5, the gate of the fifth field-effect transistor M5, the drain of the fifteenth field-effect transistor M15, and the second-level level shifting unit.

[0009] The gates of the fifteenth field-effect transistor M15 and the sixteenth field-effect transistor M16 are connected to the voltage input terminal VCC; the source of the fifteenth field-effect transistor M15 is connected to the drain of the first field-effect transistor M1, the gate of the first field-effect transistor M1 is connected to the first input terminal SET, the source of the first field-effect transistor M1 is connected to the drain of the seventeenth field-effect transistor M17, the gate of the seventeenth field-effect transistor M17 is connected to the gate of the nineteenth field-effect transistor M19, and the source of the seventeenth field-effect transistor M17 is grounded;

[0010] The source of the sixteenth field-effect transistor M16 is connected to the drain of the second field-effect transistor M2, the gate of the second field-effect transistor M2 is connected to the second input terminal RESET, the source of the second field-effect transistor M2 is connected to the drain of the eighteenth field-effect transistor M18, the gate of the eighteenth field-effect transistor M18 is connected to the gate of the nineteenth field-effect transistor M19, and the source of the eighteenth field-effect transistor M18 is grounded.

[0011] As some sub-solutions of the above technical solution, the first-level level shifting unit further includes a first capacitor C1 and a second capacitor C2; one end of the first capacitor C1 is connected to the drain of the seventeenth field-effect transistor M17, and the other end of the first capacitor C1 is grounded; one end of the second capacitor C2 is connected to the drain of the eighteenth field-effect transistor M18, and the other end of the second capacitor C2 is grounded.

[0012] As some sub-solutions of the above technical solution, the first input terminal SET and the second input terminal RESET respectively output complementary pulse signals with opposite polarities.

[0013] As some sub-solutions of the above technical solution, the fifth field-effect transistor M5 and the sixth field-effect transistor M6 have the same channel width-to-length ratio.

[0014] As some sub-solutions of the above technical solution, the secondary level shifting unit includes a high-voltage terminal VB, a low-voltage terminal VS, a seventh field-effect transistor M7, an eighth field-effect transistor M8, a ninth field-effect transistor M9, a tenth field-effect transistor M10, an eleventh field-effect transistor M11, a twelfth field-effect transistor M12, a thirteenth field-effect transistor M13, and a fourteenth field-effect transistor M14.

[0015] The source of the seventh field-effect transistor M7 is connected to the sources of the eighth field-effect transistor M8, the sixth field-effect transistor M6, the ninth field-effect transistor M9, the fourteenth field-effect transistor M14, and the high-voltage terminal VB. The gate of the seventh field-effect transistor M7 is connected to the gates of the eighth field-effect transistor M8 and the sixth field-effect transistor M6. The drain of the seventh field-effect transistor M7 is connected to the drain of the eleventh field-effect transistor M11 and the trigger unit. The gate of the ninth field-effect transistor M9 is connected to the gate of the fourteenth field-effect transistor M14 and the drain of the third field-effect transistor M3. The drain of the ninth field-effect transistor M9 is connected to... The gate and drain of the tenth field-effect transistor M10 and the gate of the eleventh field-effect transistor M11 are connected; the drain of the eighth field-effect transistor M8 is connected to the drain of the twelfth field-effect transistor M12; the drain of the fourteenth field-effect transistor M14 is connected to the gate of the twelfth field-effect transistor M12, the gate of the thirteenth field-effect transistor M13, the drain of the thirteenth field-effect transistor M13, and the trigger unit; the low-voltage terminal VS is connected to the source of the tenth field-effect transistor M10, the source of the eleventh field-effect transistor M11, the source of the twelfth field-effect transistor M12, and the source of the thirteenth field-effect transistor M13.

[0016] As some sub-solutions of the above technical solution, the trigger unit includes an RS trigger and an output terminal OUT; the R terminal of the RS trigger is connected to the drain of the fourteenth field-effect transistor M14, the S terminal of the RS trigger is connected to the drain of the seventh field-effect transistor M7, and the Q terminal of the RS trigger is connected to the output terminal OUT.

[0017] A second aspect of the present invention provides a PCB board on which the level shifting circuit described above is printed.

[0018] The PCB board according to the second aspect embodiment of the present invention also has corresponding beneficial effects because it includes the level shifting circuit of the above-described technical solution.

[0019] A third aspect of the present invention provides a chip, wherein the chip employs a level shifting circuit as described above to achieve operational control.

[0020] The chip according to the third aspect embodiment of the present invention, since it includes the level shifting circuit of the above-described technical solution, also has corresponding beneficial effects. Attached Figure Description

[0021] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0022] Figure 1 A circuit block diagram of the level shifting circuit provided by the present invention;

[0023] Figure 2 The application circuit diagram of the level shifting circuit provided by the present invention.

[0024] In the attached diagram: 1-Bias current unit; 2-First-level level shift unit; 3-Second-level level shift unit; 4-Flip-flop unit. Detailed Implementation

[0025] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0026] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0027] In the description of this invention, "several" means an indefinite quantity, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features. The use of "and / or" throughout the text indicates three parallel solutions; for example, A and / or B indicates a solution satisfied by A, a solution satisfied by B, or a solution satisfied by both A and B.

[0028] In the description of this invention, if there is a short phrase containing multiple parallel features, the modifier in the phrase defines the closest feature. For example, "B, C, and E connected to D are set on A" means that B is set on A, E is connected to D, and C is not defined. However, modifiers indicating the relationship between features, such as "interval setting" or "circular arrangement," do not fall into this category. Modifiers preceded by "all" define all features in the short phrase. For example, "B, C, and D are all set on A" means that B, C, and D are all set on A. In statements where the subject is omitted, the omitted subject is the subject of the preceding statement; that is, "A has B and includes C" means that A has B and A includes C.

[0029] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0030] The following is combined Figures 1 to 2 Embodiments of the present invention will be described.

[0031] A level shifting circuit according to a first aspect embodiment of the present invention includes: a bias current unit 1, a first-level level shifting unit 2, a second-level level shifting unit 3, and a trigger unit 4; the bias current unit 1 is electrically connected to the first-level level shifting unit 2, the first-level level shifting unit 2 is electrically connected to the second-level level shifting unit 3, and the second-level level shifting unit 3 is electrically connected to the trigger unit 4; the bias current unit 1 is used to provide bias current, the first-level level shifting unit 2 is used to implement level shifting, the second-level level shifting unit 3 is used to expand the output voltage range, and the trigger unit 4 is used to restore the logic signal.

[0032] In this invention, a bias current unit 1 is provided to provide a fixed bias current, eliminating the dependence of the output voltage on the matching degree of the device's electrical parameters and suppressing the impact of process and temperature fluctuations at the source. Subsequently, a first-level level shift unit 2 is used to achieve basic level shifting, and a second-level level shift unit 3 is used to expand the output voltage range, ensuring the accuracy of signal conversion. Finally, a trigger unit 4 restores the voltage signal to a logic signal, realizing the reliable output of the drive pulse. Through the collaborative design of the bias current unit 1, the first-level level shift unit 2, the second-level level shift unit 3, and the trigger unit 4, this invention significantly improves the stability of the output voltage, effectively avoids power transistor malfunctions, and meets the stringent stability requirements of next-generation power modules.

[0033] The bias current unit 1 includes a voltage input terminal VCC, a bias current source IBIAS, and a nineteenth field-effect transistor M19; the voltage input terminal VCC is connected to one end of the bias current source IBIAS and the first-level level shift unit 2, the other end of the bias current source IBIAS is connected to the drain of the nineteenth field-effect transistor M19, the source of the nineteenth field-effect transistor M19 is grounded, and the gate of the nineteenth field-effect transistor M19 is connected to the first-level level shift unit 2.

[0034] In this embodiment, the voltage input terminal VCC serves as the energy input node of the bias current unit 1, directly connected to one end of the bias current source IBIAS, and simultaneously connected to the gates of the fifteenth field-effect transistor M15 and the sixteenth field-effect transistor M16 in the first-stage level shift unit 2, providing the operating voltage for the first-stage level shift unit 2. The bias current source IBIAS adopts a constant current source design, with one end connected to the voltage input terminal VCC and the other end connected to the drain of the nineteenth field-effect transistor M19. The bias current source IBIAS is used to generate a stable reference current, the value of which is determined by the circuit design requirements. The source of the nineteenth field-effect transistor M19 is grounded, and its gate is connected to the gates of the seventeenth field-effect transistor M17 and the eighteenth field-effect transistor M18 in the first-stage level shift unit 2. The gate voltage of the nineteenth field-effect transistor M19 is controlled by the operating state feedback of the first-stage level shift unit 2, forming a current mirror reference node.

[0035] The bias current source IBIAS draws energy from the voltage input terminal VCC to generate a constant current I_BIAS. This current flows through the drain and source of the nineteenth field-effect transistor M19, forming a reference voltage V_G0 ​​at the gate of M19. Since the bias current source IBIAS is a constant current source, the reference voltage V_G0 ​​is determined only by the device parameters of the nineteenth field-effect transistor M19 and is not affected by process corners or temperature fluctuations. The seventeenth and eighteenth field-effect transistors M17 and M18 use the same device parameters as the nineteenth field-effect transistor M19. According to the current mirror principle of MOSFETs, current flows through the seventeenth and eighteenth field-effect transistors M17 and M18. The current of M18 will be strictly matched with I_BIAS. This current provides bias for the first field-effect transistor M1 and the second field-effect transistor M2 in the first-level level shift unit 2, ensuring that the conduction current of the first field-effect transistor M1 and the second field-effect transistor M2 is limited within the range of I_BIAS, avoiding voltage instability caused by current fluctuations. If the device parameters of the first-level level shift unit 2 change due to temperature rise, the gate voltage of the nineteenth field-effect transistor M19 will automatically adjust the conduction state of the seventeenth field-effect transistor M17 and the eighteenth field-effect transistor M18 through current mirroring, maintaining the bias current unchanged, forming a self-stabilizing mechanism of "parameter fluctuation - current feedback - dynamic compensation".

[0036] Specifically, the first-level level shift unit 2 includes a first input terminal SET, a second input terminal RESET, a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, a fourth field-effect transistor M4, a fifth field-effect transistor M5, a sixth field-effect transistor M6, a fifteenth field-effect transistor M15, a sixteenth field-effect transistor M16, a seventeenth field-effect transistor M17, and an eighteenth field-effect transistor M18;

[0037] The source of the third field-effect transistor M3 is connected to the source of the fourth field-effect transistor M4, the source of the fifth field-effect transistor M5, the source of the sixth field-effect transistor M6, and the second-level level shifting unit 3; the gate of the third field-effect transistor M3 is connected to the drain of the fourth field-effect transistor M4, the drain of the sixth field-effect transistor M6, the gate of the sixth field-effect transistor M6, the drain of the sixteenth field-effect transistor M16, and the second-level level shifting unit 3; the drain of the third field-effect transistor M3 is connected to the gate of the fourth field-effect transistor M4, the drain of the fifth field-effect transistor M5, the gate of the fifth field-effect transistor M5, the drain of the fifteenth field-effect transistor M15, and the second-level level shifting unit 3.

[0038] The gates of the fifteenth field-effect transistor M15 and the sixteenth field-effect transistor M16 are connected to the voltage input terminal VCC; the source of the fifteenth field-effect transistor M15 is connected to the drain of the first field-effect transistor M1, the gate of the first field-effect transistor M1 is connected to the first input terminal SET, the source of the first field-effect transistor M1 is connected to the drain of the seventeenth field-effect transistor M17, the gate of the seventeenth field-effect transistor M17 is connected to the gate of the nineteenth field-effect transistor M19, and the source of the seventeenth field-effect transistor M17 is grounded;

[0039] The source of the sixteenth field-effect transistor M16 is connected to the drain of the second field-effect transistor M2, the gate of the second field-effect transistor M2 is connected to the second input terminal RESET, the source of the second field-effect transistor M2 is connected to the drain of the eighteenth field-effect transistor M18, the gate of the eighteenth field-effect transistor M18 is connected to the gate of the nineteenth field-effect transistor M19, and the source of the eighteenth field-effect transistor M18 is grounded.

[0040] Specifically, the first-level level shifting unit 2 further includes a first capacitor C1 and a second capacitor C2; one end of the first capacitor C1 is connected to the drain of the seventeenth field-effect transistor M17, and the other end of the first capacitor C1 is grounded; one end of the second capacitor C2 is connected to the drain of the eighteenth field-effect transistor M18, and the other end of the second capacitor C2 is grounded.

[0041] Specifically, the first input terminal SET and the second input terminal RESET output complementary pulse signals with opposite polarities.

[0042] Specifically, the fifth field-effect transistor M5 and the sixth field-effect transistor M6 have the same channel width-to-length ratio.

[0043] In this embodiment, the first field-effect transistor M1 and the second field-effect transistor M2 serve as signal input stages and are connected to the first input terminal SET and the second input terminal RESET, respectively. The first input terminal SET and the second input terminal RESET are complementary pulse signals with opposite polarities, which control the alternating conduction of the first field-effect transistor M1 and the second field-effect transistor M2 to form a pulse triggering mechanism.

[0044] The fifteenth MOSFET M15 and the sixteenth MOSFET are high-voltage transistors. The characteristics of high-voltage transistors are used to isolate the low-voltage control signal from the high-voltage operating area, ensuring that the low-voltage side MOSFETs can work safely in a high-voltage environment and avoiding the risk of breakdown.

[0045] The seventeenth field-effect transistor M17 and the eighteenth field-effect transistor M18 serve as current bias stages, providing constant bias current to the first field-effect transistor M1 and the second field-effect transistor M2, ensuring that the current when they are turned on is stable at the microampere level, and avoiding node voltage drift caused by current fluctuations.

[0046] The third field-effect transistor (FET) M3, the fourth field-effect transistor (FET) M4, the fifth field-effect transistor (FET) M5, and the sixth field-effect transistor (FET) M6 serve as the node control stage; the gates and drains of the third and fourth FETs M3 and M4 are cross-connected to form an interlocking structure; the drains of the third FET M3, the gates of the fourth FET M4, the drains of the fifth FET M5, and the drains of the fifteenth FET M15 are interconnected, and their connection points can be equivalent to... Figure 2 Node X in the diagram; the drain of the fourth field-effect transistor M4, the gate of the third field-effect transistor M3, the drain of the sixth field-effect transistor M6, and the drain of the sixteenth field-effect transistor M16 are interconnected, and their connection points can be equivalent to... Figure 2 Node Y in;

[0047] The operation of the first-level level shift unit 2 can be divided into three stages: "pulse triggering - current discharge - node level flipping". Taking the case where the first input terminal SET is high and the second input terminal RESET is low as an example:

[0048] Pulse triggering stage: When the first input terminal SET is high, the first field-effect transistor M1 is turned on, and the bias current I_BIAS of the seventeenth field-effect transistor M17 flows through the first field-effect transistor M1 to the source of the fifteenth field-effect transistor M15. Since the gate of the fifteenth field-effect transistor M15 is connected to the voltage input terminal VCC, its source voltage is pulled high, the fifteenth field-effect transistor M15 is turned on, and the current flows from the drain of the fifteenth field-effect transistor M15 to node X, causing the potential of node X to drop instantaneously.

[0049] Current discharge and node switching stage: When the potential of node X drops below VB-|VTHP|, the third field-effect transistor M3 turns on, and the drain current of the third field-effect transistor M3 flows to node Y, causing the potential of node Y to rise to VB; the high level of node Y causes the fourth field-effect transistor M4 to turn off, and at the same time the sixth field-effect transistor M6 turns off, forming a stable state of "X low-Y high".

[0050] Complementary pulse response: When the second input terminal RESET is high, the second field-effect transistor M2 is turned on, and the bias current I_BIAS of the eighteenth field-effect transistor M18 flows through the second field-effect transistor M2 to the source of the sixteenth field-effect transistor M16. The sixteenth field-effect transistor M16 is turned on, and the current flows to node Y, causing the potential of node Y to drop. The low level of node Y triggers the fourth field-effect transistor M4 to turn on, and the drain current of node Y flows to node X, causing the potential of node X to rise to VB, forming a "X high - Y low" state, completing the level flip.

[0051] The node X and node Y levels output by the first-level level shifting unit 2 are used as the inputs of the second-level level shifting unit 3;

[0052] The first capacitor C1 and the second capacitor C2 are used to achieve transient acceleration; taking the first capacitor C1 as an example:

[0053] When the first input terminal SET transitions from low to high, the first capacitor C1 begins to charge. Since the voltage across the first capacitor C1 cannot change abruptly, the first capacitor C1 is equivalent to a short circuit at the initial instant. At this time, the current flowing through the first field-effect transistor M1 includes the constant current provided by the bias current source and the spike current generated by the charging of the first capacitor C1. The spike current can significantly accelerate the pull-down speed of the potential of node X. When the first capacitor C1 has finished charging, its charging current gradually decays to zero. At this time, the first capacitor C1 is equivalent to an open circuit, and the current flowing through the first field-effect transistor M1 falls back to the constant bias current. Since the current flowing through the first field-effect transistor M1 decreases, the charge injection effect when the first field-effect transistor M1 is turned off is weakened, thus improving the stability of the circuit.

[0054] By using a two-stage current regulation system involving the charging and discharging of the first capacitor C1 and the second capacitor C2, the transmission speed and reliability can be optimized in a coordinated manner without increasing the average power consumption.

[0055] Specifically, the secondary level shifting unit 3 includes a high-voltage terminal VB, a low-voltage terminal VS, a seventh field-effect transistor M7, an eighth field-effect transistor M8, a ninth field-effect transistor M9, a tenth field-effect transistor M10, an eleventh field-effect transistor M11, a twelfth field-effect transistor M12, a thirteenth field-effect transistor M13, and a fourteenth field-effect transistor M14;

[0056] The source of the seventh field-effect transistor M7 is connected to the sources of the eighth field-effect transistor M8, the sixth field-effect transistor M6, the ninth field-effect transistor M9, the fourteenth field-effect transistor M14, and the high-voltage terminal VB. The gate of the seventh field-effect transistor M7 is connected to the gates of the eighth field-effect transistor M8 and the sixth field-effect transistor M6. The drain of the seventh field-effect transistor M7 is connected to the drain of the eleventh field-effect transistor M11 and the trigger unit 4. The gate of the ninth field-effect transistor M9 is connected to the gate of the fourteenth field-effect transistor M14 and the drain of the third field-effect transistor M3. The drain of the ninth field-effect transistor M9 is connected to... The gate and drain of the tenth field-effect transistor M10 and the gate of the eleventh field-effect transistor M11 are connected; the drain of the eighth field-effect transistor M8 is connected to the drain of the twelfth field-effect transistor M12; the drain of the fourteenth field-effect transistor M14 is connected to the gate of the twelfth field-effect transistor M12, the gate of the thirteenth field-effect transistor M13, the drain of the thirteenth field-effect transistor M13, and the trigger unit 4; the low-voltage terminal VS is connected to the source of the tenth field-effect transistor M10, the source of the eleventh field-effect transistor M11, the source of the twelfth field-effect transistor M12, and the source of the thirteenth field-effect transistor M13.

[0057] In this embodiment, since the first-level level shifting unit 2 needs to reduce static power consumption, its bias current is relatively small. However, if the current is too small, the output voltage of the circuit cannot be lower than VS+VTHN, causing the high-side MOSFET to be in the normally open state. The second-level level shifting unit 3 is a compensation design for the insufficient voltage range caused by the "low-power design" of the first-level circuit. Through additional circuit structure, the output voltage is extended to the level of the high-voltage side VB or the low-voltage side VS without increasing static power consumption, which ensures the normal switching of the power transistor and maintains the low-power advantage.

[0058] The working principles of each component in the second-level level shift unit 3 are as follows:

[0059] The seventh field-effect transistor (FET) M7, the eighth field-effect transistor (FET) M8, and the fourteenth field-effect transistor (FET) M14 serve as the high-voltage input stage. The gates of FETs M7 and M8 receive the level signal from node Y of the first-stage level shift unit 2, while the gate of FET M14 receives the level signal from node X, forming complementary inputs. When node Y of the first-stage level shift unit 2 is high, the gates of FETs M7 and M8 are connected to a high level and are cut off, while the gate of FET M14 is connected to a low level and is turned on. At this time, FET M14 pulls its drain to the low-voltage terminal VS. Conversely, when node Y of the first-stage level shift unit 2 is low, the gates of FETs M7 and M8 are connected to a low level and are turned on, and their drains are pulled to the high-voltage terminal VB.

[0060] The twelfth field-effect transistor M12 and the thirteenth field-effect transistor M13 serve as level conversion stages. They switch the conduction state according to the input level, converting the high-voltage signal into the logic level of the low-voltage terminal VS or the high-voltage terminal VB.

[0061] The ninth field-effect transistor M9, the tenth field-effect transistor M10, and the eleventh field-effect transistor M11 serve as a current mirror stage. The drain current of the ninth field-effect transistor M9 is mirrored to the eleventh field-effect transistor M11 through the tenth field-effect transistor M10, forming a current mirror structure. The current amplification factor is determined by the width-to-length ratio of the tenth field-effect transistor M10 and the eleventh field-effect transistor M11. The nineth field-effect transistor M9, the tenth field-effect transistor M10, and the eleventh field-effect transistor M11 work together to amplify the weak signal output from the first-stage level shift unit 2.

[0062] The high-voltage terminal VB provides the operating voltage for the seventh field-effect transistor M7, the eighth field-effect transistor M8, the ninth field-effect transistor M9, and the fourteenth field-effect transistor M14; the low-voltage terminal VS serves as a logic low-level reference.

[0063] The operation of the second-level level shift unit 3 is based on the output state of the first-level level shift unit 2. It realizes rail-to-rail output in two working conditions. Taking the output of the first-level level shift unit 2 as "X low Y high" as an example: when the potential of node X is low, the potential of node Y is high. At this time, the seventh field-effect transistor M7 and the eighth field-effect transistor M8 are cut off, and the fourteenth field-effect transistor M14 is turned on. Its drain potential is approximately equal to the low-voltage terminal VS potential. The R terminal of the trigger unit 4 is connected to the drain of the fourteenth field-effect transistor M14, and the S terminal is connected to the drain of the seventh field-effect transistor M7. Therefore, the RS trigger output OUT is high.

[0064] Specifically, the trigger unit 4 includes an RS trigger and an output terminal OUT; the R terminal of the RS trigger is connected to the drain of the fourteenth field-effect transistor M14, the S terminal of the RS trigger is connected to the drain of the seventh field-effect transistor M7, and the Q terminal of the RS trigger is connected to the output terminal OUT.

[0065] In this embodiment, the output of the second-level level shift unit 3 is a voltage signal, which is converted into a logic signal by the RS flip-flop to realize the conversion from "analog voltage to digital logic" and adapt to the driving requirements of the subsequent power transistor.

[0066] A second aspect of the present invention provides a PCB board on which the level shifting circuit described above is printed.

[0067] A third aspect of the present invention provides a chip, wherein the chip employs a level shifting circuit as described above to achieve operational control.

[0068] The preferred embodiments of the present invention have been described in detail above, but the present disclosure is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and these equivalent modifications or substitutions are all included within the scope defined by the claims of the present disclosure.

Claims

1. A level shifting circuit, characterized in that, include: Bias current unit, first-level level shift unit, second-level level shift unit, and flip-flop unit; The bias current unit is electrically connected to the first-level level shift unit, the first-level level shift unit is electrically connected to the second-level level shift unit, and the second-level level shift unit is electrically connected to the trigger unit. The bias current unit is used to provide bias current, the first-level level shift unit is used to implement level shifting, the second-level level shift unit is used to extend the output voltage range, and the trigger unit is used to restore the logic signal.

2. The level shifting circuit according to claim 1, characterized in that: The bias current unit includes a voltage input terminal VCC, a bias current source IBIAS, and a nineteenth field-effect transistor M19; the voltage input terminal VCC is connected to one end of the bias current source IBIAS and the first-level level shift unit, the other end of the bias current source IBIAS is connected to the drain of the nineteenth field-effect transistor M19, the source of the nineteenth field-effect transistor M19 is grounded, and the gate of the nineteenth field-effect transistor M19 is connected to the first-level level shift unit.

3. The level shifting circuit according to claim 2, characterized in that: The first-level level shift unit includes a first input terminal SET, a second input terminal RESET, a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, a fourth field-effect transistor M4, a fifth field-effect transistor M5, a sixth field-effect transistor M6, a fifteenth field-effect transistor M15, a sixteenth field-effect transistor M16, a seventeenth field-effect transistor M17, and an eighteenth field-effect transistor M18; The source of the third field-effect transistor M3 is connected to the source of the fourth field-effect transistor M4, the source of the fifth field-effect transistor M5, the source of the sixth field-effect transistor M6, and the second-level level shifting unit; the gate of the third field-effect transistor M3 is connected to the drain of the fourth field-effect transistor M4, the drain of the sixth field-effect transistor M6, the gate of the sixth field-effect transistor M6, the drain of the sixteenth field-effect transistor M16, and the second-level level shifting unit; the drain of the third field-effect transistor M3 is connected to the gate of the fourth field-effect transistor M4, the drain of the fifth field-effect transistor M5, the gate of the fifth field-effect transistor M5, the drain of the fifteenth field-effect transistor M15, and the second-level level shifting unit. The gates of the fifteenth field-effect transistor M15 and the sixteenth field-effect transistor M16 are connected to the voltage input terminal VCC; the source of the fifteenth field-effect transistor M15 is connected to the drain of the first field-effect transistor M1, the gate of the first field-effect transistor M1 is connected to the first input terminal SET, the source of the first field-effect transistor M1 is connected to the drain of the seventeenth field-effect transistor M17, the gate of the seventeenth field-effect transistor M17 is connected to the gate of the nineteenth field-effect transistor M19, and the source of the seventeenth field-effect transistor M17 is grounded; The source of the sixteenth field-effect transistor M16 is connected to the drain of the second field-effect transistor M2, the gate of the second field-effect transistor M2 is connected to the second input terminal RESET, the source of the second field-effect transistor M2 is connected to the drain of the eighteenth field-effect transistor M18, the gate of the eighteenth field-effect transistor M18 is connected to the gate of the nineteenth field-effect transistor M19, and the source of the eighteenth field-effect transistor M18 is grounded.

4. The level shifting circuit according to claim 3, characterized in that: The first-level level shifting unit further includes a first capacitor C1 and a second capacitor C2; one end of the first capacitor C1 is connected to the drain of the seventeenth field-effect transistor M17, and the other end of the first capacitor C1 is grounded; one end of the second capacitor C2 is connected to the drain of the eighteenth field-effect transistor M18, and the other end of the second capacitor C2 is grounded.

5. The level shifting circuit according to claim 3, characterized in that: The first input terminal SET and the second input terminal RESET respectively output complementary pulse signals with opposite polarities.

6. The level shifting circuit according to claim 3, characterized in that: The fifth field-effect transistor M5 and the sixth field-effect transistor M6 have the same channel width-to-length ratio.

7. The level shifting circuit according to claim 3, characterized in that: The secondary level shifting unit includes a high-voltage terminal VB, a low-voltage terminal VS, a seventh field-effect transistor M7, an eighth field-effect transistor M8, a ninth field-effect transistor M9, a tenth field-effect transistor M10, an eleventh field-effect transistor M11, a twelfth field-effect transistor M12, a thirteenth field-effect transistor M13, and a fourteenth field-effect transistor M14. The source of the seventh field-effect transistor M7 is connected to the sources of the eighth field-effect transistor M8, the sixth field-effect transistor M6, the ninth field-effect transistor M9, the fourteenth field-effect transistor M14, and the high-voltage terminal VB. The gate of the seventh field-effect transistor M7 is connected to the gates of the eighth field-effect transistor M8 and the sixth field-effect transistor M6. The drain of the seventh field-effect transistor M7 is connected to the drain of the eleventh field-effect transistor M11 and the trigger unit. The gate of the ninth field-effect transistor M9 is connected to the gate of the fourteenth field-effect transistor M14 and the drain of the third field-effect transistor M3. The drain of the ninth field-effect transistor M9 is connected to... The gate and drain of the tenth field-effect transistor M10 and the gate of the eleventh field-effect transistor M11 are connected; the drain of the eighth field-effect transistor M8 is connected to the drain of the twelfth field-effect transistor M12; the drain of the fourteenth field-effect transistor M14 is connected to the gate of the twelfth field-effect transistor M12, the gate of the thirteenth field-effect transistor M13, the drain of the thirteenth field-effect transistor M13, and the trigger unit; the low-voltage terminal VS is connected to the source of the tenth field-effect transistor M10, the source of the eleventh field-effect transistor M11, the source of the twelfth field-effect transistor M12, and the source of the thirteenth field-effect transistor M13.

8. The level shifting circuit according to claim 7, characterized in that: The trigger unit includes an RS trigger and an output terminal OUT; the R terminal of the RS trigger is connected to the drain of the fourteenth field-effect transistor M14, the S terminal of the RS trigger is connected to the drain of the seventh field-effect transistor M7, and the Q terminal of the RS trigger is connected to the output terminal OUT.

9. A PCB board, characterized in that, The PCB board is printed with a level shifting circuit as described in any one of claims 1-8.

10. A chip, characterized in that, The chip employs a level shifting circuit as described in any one of claims 1-8 to achieve operational control.

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