Analog-to-digital conversion circuit, chip and electronic equipment
By coordinating the drive control module, common-mode voltage generation module, and pre-charge module, the voltage settling speed at the comparator input terminal in the analog-to-digital conversion circuit is improved, solving the problem of excessively long voltage settling time under high sampling rates.
Patent Information
- Application Number
- CN202511185848.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-22
- Publication Date
- 2025-11-18
AI Technical Summary
In analog-to-digital converter circuits, the voltage settling time at the input of the comparator is too long, which cannot meet the requirements of higher sampling rates.
The drive control module generates enable and control signals, the common-mode voltage generation module generates common-mode voltage, the switching module controls the transmission of common-mode voltage, and the pre-charge module performs pre-charging to improve the establishment speed of the comparator input voltage.
This reduces the settling time of the comparator input voltage, meeting the requirements for higher sampling rates.
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Figure CN120979445A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuit technology, specifically to an analog-to-digital converter circuit, a chip, and an electronic device. Background Technology
[0002] In some analog-to-digital converter (ADC) circuits, the voltage at the comparator's input is equivalent to the voltage on the upper plate of the switched capacitor array in the digital-to-analog converter (DAC). During the first sampling, the voltage at the comparator's input needs to build up from the initial voltage to the common-mode voltage. In subsequent sampling, the voltage at the comparator's input is very close to the common-mode voltage.
[0003] Therefore, during the first sampling, the voltage at the comparator's input takes longer to set up, which makes it impossible to meet the stringent requirements for this settling time at higher sampling rates. Summary of the Invention
[0004] In view of the above problems, embodiments of this application provide an analog-to-digital conversion circuit, a chip, and an electronic device to alleviate the aforementioned technical problems.
[0005] In a first aspect, embodiments of this application provide an analog-to-digital conversion circuit, which includes a drive control module, a common-mode voltage generation module, a switching module, and a pre-charge module. The drive control module is used to generate a first enable signal, a second enable signal, a third enable signal, a first control signal, and a second control signal. The common-mode voltage generation module is used to generate a common-mode voltage based on the first enable signal, the second enable signal, and the third enable signal. The switching module is used to control the transmission of the common-mode voltage to a first input terminal and a second input terminal of a comparator based on the first control signal. The pre-charge module is used to pre-charge the first input terminal and the second input terminal using the common-mode voltage based on the second control signal.
[0006] Secondly, embodiments of this application also provide a chip that includes the analog-to-digital conversion circuit described above.
[0007] Thirdly, embodiments of this application also provide an electronic device, which includes the analog-to-digital conversion circuit or chip described above.
[0008] The analog-to-digital conversion circuit, chip, and electronic device provided in this application embodiment generate a first enable signal, a second enable signal, a third enable signal, a first control signal, and a second control signal through a drive control module. A common-mode voltage generation module generates a common-mode voltage based on the first enable signal, the second enable signal, and the third enable signal. A switching module controls the transmission of the common-mode voltage to the first input terminal and the second input terminal of the comparator according to the first control signal. A pre-charge module pre-charges the first input terminal and the second input terminal through the common-mode voltage according to the second control signal. This can improve the voltage settling speed of the first input terminal and the second input terminal during sampling, thereby reducing the voltage settling time of the first input terminal and the second input terminal during sampling, and thus meeting the stringent requirements for the settling time under higher sampling rates.
[0009] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description
[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0011] Figure 1 A first schematic block diagram of the analog-to-digital conversion circuit provided in an embodiment of this application is shown.
[0012] Figure 2 A schematic diagram of the precharge module is shown.
[0013] Figure 3 The circuit diagram of the precharge unit is shown.
[0014] Figure 4 The circuit schematic of the balancing unit is shown.
[0015] Figure 5 A second schematic diagram of the analog-to-digital conversion circuit provided in an embodiment of this application is shown.
[0016] Figure 6 The circuit diagram of the voltage neutralization module is shown.
[0017] Figure 7 The circuit schematic of the switching module is shown.
[0018] Figure 8 A third block diagram of the analog-to-digital conversion circuit provided in an embodiment of this application is shown.
[0019] Figure 9 The circuit diagram of the reset leakage protection module is shown.
[0020] Figure 10 A block diagram of the common-mode voltage generation module is shown.
[0021] Figure 11 The circuit schematic of the initial voltage generation unit is shown.
[0022] Figure 12 The circuit diagram of the buffer unit is shown.
[0023] Figure 13 A schematic diagram of the drive control module is shown.
[0024] Figure 14 A schematic block diagram of the first control unit is shown.
[0025] Figure 15 The circuit schematic of the first logic subunit is shown.
[0026] Figure 16 The circuit schematic of the second logic subunit is shown.
[0027] Figure 17 A schematic block diagram of the second control unit is shown.
[0028] Figure 18 The circuit schematic of the third logic subunit is shown.
[0029] Figure 19 The circuit schematic of the fifth logic subunit is shown.
[0030] Figure 20 A block diagram of the second drive unit is shown.
[0031] Figure 21 The first timing diagram of the analog-to-digital converter circuit is shown.
[0032] Figure 22 A second timing diagram of the analog-to-digital converter circuit is shown.
[0033] Figure 23 A schematic diagram of the chip structure provided in an embodiment of this application is shown.
[0034] Figure 24 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation
[0035] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0036] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0037] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.
[0038] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0039] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.
[0040] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.
[0041] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.
[0042] In the embodiments of this application, the first terminal / first end of each transistor is one of the source and the drain, and the second terminal / second end of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first terminal / first end and the second terminal / second end of the transistor in the embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal / first end is the source, and the second terminal / second end is the drain; for example, when the transistor is an N-type transistor, the first terminal / first end is the drain, and the second terminal / second end is the source.
[0043] like Figure 1 As shown in the figure, this application embodiment provides an analog-to-digital converter circuit 100, which includes a drive control module 10, a common-mode voltage generation module 20, a switching module 30, and a pre-charge module 40. The drive control module 10 is used to generate a first enable signal SENB, a second enable signal SENA, a third enable signal ENA, a first control signal VCM_BS, and a second control signal Idleb. The common-mode voltage generation module 20 is used to generate a common-mode voltage VCM according to the first enable signal SENB, the second enable signal SENA, and the third enable signal ENA. The switching module 30 is used to control the transmission of the common-mode voltage VCM to the first input terminal VP and the second input terminal VN of the comparator according to the first control signal VCM_BS. The pre-charge module 40 is used to pre-charge the first input terminal VP and the second input terminal VN through the common-mode voltage VCM according to the second control signal Idleb.
[0044] It is understood that the analog-to-digital conversion circuit 100 provided in this application generates a first enable signal SENB, a second enable signal SENA, a third enable signal ENA, a first control signal VCM_BS, and a second control signal Idleb through the drive control module 10. The common-mode voltage generation module 20 generates a common-mode voltage VCM based on the first enable signal SENB, the second enable signal SENA, and the third enable signal ENA. The switching module 30 controls the common-mode voltage VCM to be transmitted to the first input terminal VP and the second input terminal VN of the comparator according to the first control signal VCM_BS. The pre-charge module 40 pre-charges the first input terminal VP and the second input terminal VN through the common-mode voltage VCM according to the second control signal Idleb. This can improve the voltage settling speed of the first input terminal VP and the second input terminal VN during sampling, thereby reducing the voltage settling time of the first input terminal VP and the second input terminal VN during sampling, and thus meeting the stringent requirements for the settling time under higher sampling rates.
[0045] It should be noted that this embodiment can not only reduce the voltage settling time of the first input terminal VP and the second input terminal VN during the first sampling in high-speed sampling mode, but also reduce the voltage settling time of the first input terminal VP and the second input terminal VN during each sampling in high-speed sampling mode.
[0046] In some embodiments, such as Figure 2 As shown, the pre-charge module 40 includes a pre-charge unit 41 and a balancing unit 42. The pre-charge unit 41 is used to pre-charge the first input terminal VP and the second input terminal VN through the common-mode voltage VCM according to the second control signal Idleb. The balancing unit 42 is used to balance the establishment speed of the common-mode voltage VCM on the first input terminal VP and the second input terminal VN according to the second control signal Idleb.
[0047] It should be noted that the pre-charge unit 41 and the balancing unit 42 can share the second control signal Idleb, thereby reducing the number of signals required. When the pre-charge path of the common-mode voltage VCM to the first input terminal VP or the second input terminal VN fails, such as being open-circuited, the pre-charge of the first input terminal VP and the second input terminal VN can still be achieved through the balancing unit 42.
[0048] In some embodiments, such as Figure 3 As shown, the precharge unit 41 includes a first transistor MP3 and a second transistor MP5. The first terminal of the first transistor MP3 is connected to the common-mode voltage VCM, the control terminal of the first transistor MP3 is connected to the second control signal Idleb, and the second terminal of the first transistor MP3 is connected to the first input terminal VP. The first terminal of the second transistor MP5 is connected to the second input terminal VN, the control terminal of the second transistor MP5 is connected to the second control signal Idleb, and the second terminal of the second transistor MP5 is connected to the common-mode voltage VCM.
[0049] It should be noted that each transistor in this application can be a field-effect transistor or a bipolar junction transistor (BJT), and the control electrode can be the gate or the base. The channel type of the first transistor MP3 is the same as that of the second transistor MP5, and they share the same second control signal Idleb, allowing for synchronous switching. When the first transistor MP3 and the second transistor MP5 are synchronously turned on, the first input terminal VP and the second input terminal VN can be synchronously pre-charged.
[0050] In some embodiments, such as Figure 4 As shown, the balancing unit 42 includes a third transistor MP4. The first terminal of the third transistor MP4 is connected to the second terminal and the first input terminal VP of the first transistor MP3. The control terminal of the third transistor MP4 is connected to the second control signal Idleb. The second terminal of the third transistor MP4 is connected to the first terminal and the second input terminal VN of the second transistor MP5.
[0051] It should be noted that the channel type of the third transistor MP4 is the same as that of the first transistor MP3 and the second transistor MP5, and they share the same second control signal Idleb, which allows them to switch synchronously.
[0052] In some embodiments, such as Figure 5 As shown, the drive control module 10 is also used to generate a third control signal Sampleb, and the analog-to-digital conversion circuit 100 also includes a voltage neutralization module 50, which is used to neutralize the feedthrough voltage on the first input terminal VP and the second input terminal VN according to the third control signal Sampleb.
[0053] It should be noted that, due to various reasons, the equivalent feedthrough voltages on the first input terminal VP and the second input terminal VN may be unbalanced, or even significantly deviate. This is detrimental to the comparator's offset voltage calibration, potentially resulting in a large residual voltage. In this embodiment, the voltage neutralization module 50 neutralizes the feedthrough voltages on the first input terminal VP and the second input terminal VN based on the third control signal Sampleb. This neutralization can occur at the rising or falling edge of the sampling signal Sampleb, thereby balancing the equivalent feedthrough voltages on the first input terminal VP and the second input terminal VN. This facilitates comparator offset voltage calibration and reduces residual voltage.
[0054] In some embodiments, such as Figure 6 As shown, the voltage neutralization module 50 includes a fourth transistor MP2. The first terminal of the fourth transistor MP2 is connected to the first input terminal VP and the first output terminal of the switching module 30. The control terminal of the fourth transistor MP2 is connected to the third control signal Sampleb. The second terminal of the fourth transistor MP2 is connected to the second input terminal VN and the second output terminal of the switching module 30.
[0055] It should be noted that when the third control signal Sampleb drives the fourth transistor MP2 to switch states, it can balance the equivalent feed-through voltage of the first input terminal VP and the equivalent feed-through voltage of the second input terminal VN, which is beneficial for the offset voltage calibration of the comparator and thus reduces the residual voltage.
[0056] In some embodiments, such as Figure 7As shown, the switching module 30 includes a fifth transistor MN3 and a sixth transistor MN4. The first terminal of the fifth transistor MN3 is connected to the first terminal and the first input terminal VP of the fourth transistor MP2. The control terminal of the fifth transistor MN3 is connected to the first control signal VCM_BS, and the second terminal of the fifth transistor MN3 is connected to the common-mode voltage VCM. The first terminal of the sixth transistor MN4 is connected to the second terminal and the second input terminal VN of the fourth transistor MP2. The control terminal of the sixth transistor MN4 is connected to the control terminal of the fifth transistor MN3, and the second terminal of the sixth transistor MN4 is connected to the second terminal of the fifth transistor MN3. The channel type of the fifth transistor MN3 is the same as that of the sixth transistor MN4, but the channel type of the fifth transistor MN3 is different from that of the fourth transistor MP2.
[0057] It should be noted that the channel type of the fifth transistor MN3 is the same as that of the sixth transistor MN4, and they are driven by the same first control signal VCM_BS, allowing for synchronous switching to achieve synchronous pre-charging of the first input terminal VP and the second input terminal VN. The channel type of the fourth transistor MP2 is opposite to that of the fifth transistor MN3 and the sixth transistor MN4. When the rising or falling edge of the sampling signal Sample arrives, the gate-source voltage difference of the fourth transistor MP2 approaches zero compared to the gate-drain voltage difference of the fifth transistor MN3, and the gate-drain voltage difference of the fourth transistor MP2 approaches zero compared to the gate-drain voltage difference of the sixth transistor MN4, thereby neutralizing the equivalent feedthrough voltage on the first input terminal VP and the second input terminal VN.
[0058] In some embodiments, such as Figure 8 As shown, the drive control module 10 is also used to generate a fourth enable signal ENB, and the analog-to-digital conversion circuit 100 also includes a reset and leakage protection module 60, which is used to reset the voltage of the first input terminal VP and the second input terminal VN according to the fourth enable signal ENB, and to prevent leakage of the first input terminal VP and the second input terminal VN.
[0059] It should be noted that the reset leakage protection module 60 can reset the voltage of the first input terminal VP and the second input terminal VN during the reset phase to improve the subsequent sampling accuracy; outside the reset phase, it can prevent the first input terminal VP and the second input terminal VN from leaking current through the reset leakage protection module 60, which can also improve the sampling accuracy.
[0060] In some embodiments, such as Figure 9As shown, the reset leakage protection module 60 includes a seventh transistor MN5, an eighth transistor MN6, a ninth transistor MP6, and a tenth transistor MN7. The first terminal of the seventh transistor MN5 is connected to the first input terminal VP, and the control terminal of the seventh transistor MN5 is connected to the fourth enable signal ENB. The first terminal of the eighth transistor MN6 is connected to the second input terminal VN. The first terminal of the ninth transistor MP6 is connected to the first power supply voltage VDD. The first terminal of the tenth transistor MN7 is connected to the second terminals of the seventh transistor MN5, the eighth transistor MN6, and the ninth transistor MP6. The control terminal of the tenth transistor MN7 is connected to the control terminals of the seventh transistor MN5, the eighth transistor MN6, and the ninth transistor MP6. The second terminal of the tenth transistor MN7 is connected to the second power supply voltage VSS.
[0061] It should be noted that the seventh transistor MN5, the eighth transistor MN6, the ninth transistor MP6, and the tenth transistor MN7 share the same fourth enable signal ENB, which reduces the number of signals required. When the seventh transistor MN5, the eighth transistor MN6, and the tenth transistor MN7 are synchronously turned on, the voltages at the first input terminal VP and the second input terminal VN can be reset using the second power supply voltage VSS. When the seventh transistor MN5, the eighth transistor MN6, and the tenth transistor MN7 are synchronously turned off, while the ninth transistor MP6 is turned on, the first power supply voltage VDD can be transmitted to the source of the seventh transistor MN5 and the source of the eighth transistor MN6, thereby increasing the gate-source voltage difference between the seventh transistor MN5 and the eighth transistor MN6, and thus reducing leakage current through the seventh transistor MN5 and the eighth transistor MN6.
[0062] In some embodiments, such as Figure 10 As shown, the common-mode voltage generation module 20 includes an initial voltage generation unit 21 and a buffer unit 22. The initial voltage generation unit 21 is used to generate an initial voltage VI according to a first enable signal SENB and a second enable signal SENA. The buffer unit 22 is used to control whether the initial voltage VI is buffered before generating the common-mode voltage VCM according to the first enable signal SENB and the third enable signal ENA.
[0063] It should be noted that, under the control of the first enable signal SENB and the second enable signal SENA, the initial voltage generation unit 21 can generate the required initial voltage VI. Based on this, the initial voltage VI is processed by the buffer unit 22 to generate the common-mode voltage VCM.
[0064] In some embodiments, such as Figure 11As shown, the initial voltage generation unit 21 includes an eleventh transistor MP1, a first resistor R1, a second resistor R2, and a twelfth transistor MN1. The first terminal of the eleventh transistor MP1 is connected to the first power supply voltage VDD, and the control terminal of the eleventh transistor MP1 is connected to the first enable signal SENB. The first terminal of the first resistor R1 is connected to the second terminal of the eleventh transistor MP1. The first terminal of the second resistor R2 is connected to the second terminal of the first resistor R1 and generates the initial voltage VI. The first terminal of the twelfth transistor MN1 is connected to the second terminal of the second resistor R2, the control terminal of the twelfth transistor MN1 is connected to the second enable signal SENA, and the second terminal of the twelfth transistor MN1 is connected to the second power supply voltage VSS.
[0065] It should be noted that the on-resistance of the eleventh transistor MP1 should be as close as possible to that of the twelfth transistor MN1. The first resistor R1 and the second resistor R2 can also be adjusted to make the equivalent impedances of the pull-up path and the pull-down path equal. In this way, the initial voltage VI can be approximately equal to or equal to half of the first power supply voltage VDD. Here, the first power supply voltage VDD is greater than the second power supply voltage VSS, and the second power supply voltage VSS can be ground voltage for example.
[0066] In some embodiments, such as Figure 12 As shown, the buffer unit 22 includes a thirteenth transistor MN2 and a buffer BUF. The control terminal of the thirteenth transistor MN2 is connected to the first enable signal SENB; the enable terminal of the buffer BUF is connected to the third enable signal ENA. The first input terminal of the buffer BUF is connected to the first terminal of the thirteenth transistor MN2 and connected to the initial voltage VI. The second input terminal of the buffer BUF is connected to the second terminal of the thirteenth transistor MN2 and the output terminal of the buffer BUF to generate a common-mode voltage VCM.
[0067] It should be noted that when the thirteenth transistor MN2 is off and the third enable signal ENA is at an active level (e.g., high), the buffer BUF replicates the initial voltage VI to its output terminal with unity gain, generating the common-mode voltage VCM. When the third enable signal ENA is at an inactive level (e.g., low), the buffer BUF does not operate (it does not buffer the initial voltage VI). When the thirteenth transistor MN2 is on, the two input terminals of the buffer BUF can be shorted.
[0068] In some embodiments, such as Figure 13As shown, the drive control module 10 includes a first control unit 11, a second control unit 12, a first drive unit 13, and a second drive unit 14. The first control unit 11 is used to generate a first enable signal SENB and a second enable signal SENA based on the sampled signal Sample, the common-mode configuration signal Vcm_cfg, and the system enable signal SAR_EN. The second control unit 12 is used to generate a second control signal Idleb, a third enable signal ENA, and a fourth enable signal ENB based on the system enable signal SAR_EN, the sampled signal Sample, the system clock signal sar_clk, and the fifth enable signal comp_en. The first drive unit 13 is used to generate a second control signal Idleb, a third enable signal ENA, and a fourth enable signal ENB based on the sampled signal Sample. The first power supply voltage VDD, the common-mode voltage VCM, and the second control signal Idleb generate a third control signal Sampleb, a first substrate voltage VB_Id, and a second substrate voltage VB_Vp. The first substrate voltage VB_Id is used to control the substrate voltage of the transistor in the precharge module 40, and the second substrate voltage VB_Vp is used to control the substrate voltage of the transistor in the voltage neutralization module 50. The second driving unit 14 generates a first control signal VCM_BS and a third substrate voltage Vbulk based on the voltage selection signal VSEL, the common-mode voltage VCM, the sampling signal Sample, and the first power supply voltage VDD. The third substrate voltage Vbulk is used to control the substrate voltage of the transistor in the switching module 30.
[0069] It should be noted that this embodiment can not only generate various dynamic enable signals and control signals to control the dynamic switching of the voltage of the first input terminal VP and the second input terminal VN and pre-charge, but also generate dynamic substrate voltage to ensure the voltage withstand capability of the corresponding transistor while minimizing the switching impedance.
[0070] In some embodiments, such as Figure 14 As shown, the first control unit 11 includes a first logic subunit 111 and a second logic subunit 112. The first logic subunit 111 is used to generate a first intermediate signal based on the sampled signal Sample, the common mode configuration signal Vcm_cfg and the system enable signal SAR_EN. The second logic subunit 112 is used to delay the first intermediate signal and invert it to generate a first enable signal SENB and a second enable signal SENA.
[0071] It should be noted that the common-mode configuration signal Vcm_cfg can configure the generation mode of the common-mode voltage VCM. When the common-mode configuration signal Vcm_cfg is low, the common-mode voltage VCM is always present when the system enable signal SAR_EN is high, which is used for applications with high sampling rates. When the common-mode configuration signal Vcm_cfg is high, the common-mode voltage VCM is generated periodically when the system enable signal SAR_EN is high, depending on the sampling signal Sample, which is used for applications with low sampling rates to save power.
[0072] In some embodiments, such as Figure 15 As shown, the first logic subunit 111 includes a first NOT gate N1, a first NAND gate AN1, and a second NAND gate AN2. The input terminal of the first NOT gate N1 is connected to the sampling signal Sample. The two input terminals of the first NAND gate AN1 are respectively connected to the common-mode configuration signal Vcm_cfg and the inverted sampling signal Sample. The first input terminal of the second NAND gate AN2 is connected to the output terminal of the first NAND gate AN1, the second input terminal of the second NAND gate AN2 is connected to the system enable signal SAR_EN, and the output terminal of the second NAND gate AN2 generates a first intermediate signal.
[0073] It should be noted that the first NOT gate N1 inverts the sampled signal Sample, the first NAND gate AN1 performs NAND operation on the common-mode configuration signal Vcm_cfg and the inverted sampled signal Sample, and the second NAND gate AN2 performs NAND operation on the output of the first NAND gate AN1 and the system enable signal SAR_EN to generate the first intermediate signal.
[0074] In some embodiments, such as Figure 16 As shown, the second logic subunit 112 includes a second NOT gate N2, a third NOT gate N3, and a fourth NOT gate N4. The input of the second NOT gate N2 is connected to the output of the second NAND gate AN2; the input of the third NOT gate N3 is connected to the output of the second NOT gate N2; the input of the fourth NOT gate N4 is connected to the output of the third NOT gate N3 and generates a first enable signal SENB; the output of the fourth NOT gate N4 generates a second enable signal SENA.
[0075] It should be noted that the second NOT gate N2 and the third NOT gate N3 perform delay processing on the first intermediate signal to generate the first enable signal SENB. The first enable signal SENB is inverted by the fourth NOT gate N4 to generate the second enable signal SENA.
[0076] In some embodiments, such as Figure 17As shown, the second control unit 12 includes a third logic subunit 121, a fourth logic subunit 122, and a fifth logic subunit 123. The third logic subunit 121 is used to generate a third enable signal ENA and a fourth enable signal ENB based on the system enable signal SAR_EN. The fourth logic subunit 122 is used to generate an idle indicator signal IDLE based on the system enable signal SAR_EN, the sampling signal Sample, the system clock signal sar_clk, and the fifth enable signal comp_en. The fifth logic subunit 123 is used to generate a second control signal Idleb based on the fourth enable signal ENB and the idle indicator signal IDLE.
[0077] It should be noted that the fourth logic subunit 122 can generate a high-level idle indicator signal IDLE at the beginning of the idle phase of the analog-to-digital conversion circuit 100, and set the idle indicator signal IDLE to a low level one cycle after the rising edge of the sampling signal Sample arrives. That is, before the rising edge of the sampling signal Sample arrives, the pre-charge module 40 can pre-charge the first input terminal VP and the second input terminal VN, thereby reducing the settling time of the common-mode voltage VCM on the first input terminal VP and the second input terminal VN.
[0078] In some embodiments, such as Figure 18 As shown, the third logic subunit 121 includes a fifth NOT gate N5 and a sixth NOT gate N6. The input of the fifth NOT gate N5 is connected to the system enable signal SAR_EN. The input of the sixth NOT gate N6 is connected to the output of the fifth NOT gate N5 and generates a fourth enable signal ENB. The output of the sixth NOT gate N6 generates a third enable signal ENA.
[0079] It should be noted that the fifth NOT gate N5 inverts the system enable signal SAR_EN to generate the fourth enable signal ENB, and the sixth NOT gate N6 inverts the fourth enable signal ENB to generate the third enable signal ENA.
[0080] In some embodiments, such as Figure 18 As shown, when the system enable signal SAR_EN is high, the sampling signal Sample is low, and the fifth enable signal comp_en is low, the rising edge of the system clock signal sar_clk triggers the generation of the rising edge of the idle indicator signal IDLE; and after the rising edge of the sampling signal Sample arrives and one cycle of the system clock signal sar_clk has elapsed, the falling edge of the idle indicator signal IDLE is generated.
[0081] It should be noted that this embodiment further explains the generation mechanism of the idle indicator signal IDLE to ensure that the first input terminal VP and the second input terminal VN are pre-charged at the appropriate time.
[0082] In some embodiments, such as Figure 19 As shown, the fifth logic sub-unit 123 includes a third NAND gate AN3, a seventh NOT gate N7, and an eighth NOT gate N8. The two inputs of the third NAND gate AN3 are respectively connected to the third enable signal ENA and the idle indicator signal IDLE. The input of the seventh NOT gate N7 is connected to the output of the third NAND gate AN3. The input of the eighth NOT gate N8 is connected to the output of the seventh NOT gate N7, and the output of the eighth NOT gate N8 generates the second control signal Idleb.
[0083] It should be noted that the third NAND gate AN3 performs a NAND operation on the third enable signal ENA and the idle indicator signal IDLE, and after being delayed by the seventh NOT gate N7 and the eighth NOT gate N8, generates the second control signal Idleb. Here, Idleb is the output signal of the seventh NOT gate N7.
[0084] In some embodiments, such as Figure 19 As shown, when the idle indicator signal IDLE is high, the first driving unit 13 controls the first substrate voltage VB_Id to be the common-mode voltage VCM; when the idle indicator signal IDLE is low, it controls the first substrate voltage VB_Id to be the first power supply voltage VDD; when the sampling signal Sample is high, it controls the second substrate voltage VB_Vp to be the common-mode voltage VCM; and when the sampling signal Sample is low, it controls the second substrate voltage VB_Vp to be the first power supply voltage VDD.
[0085] It should be noted that this embodiment further illustrates the switching mechanism of the first substrate voltage VB_Id and the second substrate voltage VB_Vp, which can ensure that the transistors connected to the first substrate voltage VB_Id and the second substrate voltage VB_Vp have the lowest possible switching impedance while ensuring voltage withstand capability.
[0086] In some embodiments, such as Figure 20 As shown, the second driving unit 14 includes a voltage selection subunit 141 and a bootstrap subunit 142. The voltage selection subunit 141 is used to generate a first intermediate voltage VCM_O based on the first power supply voltage VDD, the common mode voltage VCM, and the voltage selection signal VSEL. The bootstrap subunit 142 is used to generate a first control signal VCM_BS and a third substrate voltage Vbulk based on the first intermediate voltage VCM_O, the sampling signal Sample, and the common mode voltage VCM.
[0087] It should be noted that when the first power supply voltage VDD is high, the voltage selection signal VSEL is high, and the voltage selection subunit 141 controls the first intermediate voltage VCM_O to be the common-mode voltage VCM; when the first power supply voltage VDD is low, the voltage selection signal VSEL is low, and the voltage selection subunit 141 controls the first intermediate voltage VCM_O to be the first power supply voltage VDD.
[0088] When the sampling signal Sample is high, the bootstrap unit 142 controls the voltage of the first control signal VCM_BS to be the sum of the first intermediate voltage VCM_O and the first power supply voltage VDD, and the third substrate voltage Vbulk to be the common-mode voltage VCM; when the sampling signal Sample is low, the bootstrap unit 142 controls the voltage of the first control signal VCM_BS to be the second power supply voltage VSS, which is lower than the first power supply voltage VDD, and the third substrate voltage Vbulk to be the second power supply voltage VSS.
[0089] Figure 21 A first timing diagram of the analog-to-digital converter circuit 100 is shown. This first timing diagram shows that in the high-speed continuous sampling mode, the sampling time is short, the common-mode voltage generation module 20 is always working, continuously generating the common-mode voltage VCM. In this case, the pre-charging module 40 pre-charges the first input terminal VP and the second input terminal VN only during the first sampling.
[0090] Specifically, when the system enable signal SAR_EN is high, the sampling signal Sample is low, and the fifth enable signal comp_en is low, the rising edge of the system clock signal sar_clk triggers the generation of the rising edge of the idle indicator signal IDLE; and the falling edge of the idle indicator signal IDLE is generated after the rising edge of the sampling signal Sample arrives and one cycle of the system clock signal sar_clk has elapsed.
[0091] Specifically, the level of the second control signal Idleb changes in the opposite direction to the level of the idle indicator signal IDLE; the level of the first substrate voltage VB_Id changes in the same direction as the level of the second control signal Idleb; the level of the second substrate voltage VB_Vp changes in the opposite direction to the level of the sampling signal Sample; the level of the third control signal Sampleb changes in the same direction as the level of the second substrate voltage VB_Vp; the level of the first control signal VCM_BS changes in the opposite direction to the level of the third control signal Sampleb; and the level of the third substrate voltage Vbulk changes in the same direction as the level of the first control signal VCM_BS.
[0092] The high level of the first substrate voltage VB_Id is the first power supply voltage VDD, and the low level of the first substrate voltage VB_Id is the common-mode voltage VCM. The high level of the second substrate voltage VB_Vp is the first power supply voltage VDD, and the low level of the second substrate voltage VB_Vp is the common-mode voltage VCM. The high level of the third substrate voltage Vbulk is the common-mode voltage VCM, and the low level of the third substrate voltage Vbulk is the first power supply voltage VDD, for example, ground. The high level of the first control signal VCM_BS is the sum of the first intermediate voltage VCM_O and the first power supply voltage VDD.
[0093] Figure 22 A second timing diagram of the analog-to-digital converter circuit 100 is shown. Figure 21 The difference is that the second timing diagram shows that in the high-speed single-step sampling mode, the sampling time is short, and the pre-charging of the pre-charge module 40 to the first input terminal VP and the second input terminal VN is generally performed before each sampling.
[0094] like Figure 23 As shown, this application embodiment also provides a chip 200, which includes the analog-to-digital conversion circuit 100 described above. The chip 200 is also called an integrated circuit (IC), and the chip 200 may be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip.
[0095] It is understood that, since the chip 200 provided in this application embodiment includes the analog-to-digital conversion circuit 100 described above, it can also generate a first enable signal SENB, a second enable signal SENA, a third enable signal ENA, a first control signal VCM_BS, and a second control signal Idleb through the drive control module 10. The common-mode voltage generation module 20 generates a common-mode voltage VCM according to the first enable signal SENB, the second enable signal SENA, and the third enable signal ENA. The switching module 30 controls the common-mode voltage VCM to be transmitted to the first input terminal VP and the second input terminal VN of the comparator according to the first control signal VCM_BS. The pre-charge module 40 pre-charges the first input terminal VP and the second input terminal VN through the common-mode voltage VCM according to the second control signal Idleb. This can improve the voltage establishment speed of the first input terminal VP and the second input terminal VN during sampling, thereby reducing the voltage establishment time of the first input terminal VP and the second input terminal VN during sampling, and thus meeting the stringent requirements for the establishment time under higher sampling rates.
[0096] like Figure 24As shown in the illustration, this application also provides an electronic device 300, which includes a device body and the aforementioned analog-to-digital conversion circuit 100 or chip 200 disposed within the device body. The electronic device 300 may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car infotainment screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.
[0097] It is understood that since the electronic device 300 provided in this application embodiment includes the analog-to-digital conversion circuit 100 or chip 200 described above, it can also generate a first enable signal SENB, a second enable signal SENA, a third enable signal ENA, a first control signal VCM_BS, and a second control signal Idleb through the drive control module 10. The common-mode voltage generation module 20 generates a common-mode voltage VCM according to the first enable signal SENB, the second enable signal SENA, and the third enable signal ENA. The switching module 30 controls the common-mode voltage VCM to be transmitted to the first input terminal VP and the second input terminal VN of the comparator according to the first control signal VCM_BS. The pre-charge module 40 pre-charges the first input terminal VP and the second input terminal VN through the common-mode voltage VCM according to the second control signal Idleb. This can improve the voltage establishment speed of the first input terminal VP and the second input terminal VN during sampling, thereby reducing the voltage establishment time of the first input terminal VP and the second input terminal VN during sampling, and thus meeting the stringent requirements for the establishment time under higher sampling rates.
[0098] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. An analog-to-digital converter circuit, characterized in that, The analog-to-digital conversion circuit includes: The drive control module is used to generate a first enable signal, a second enable signal, a third enable signal, a first control signal, and a second control signal; A common-mode voltage generation module is used to generate a common-mode voltage based on the first enable signal, the second enable signal, and the third enable signal; A switching module is configured to control the transmission of the common-mode voltage to the first input terminal and the second input terminal of the comparator according to the first control signal; The pre-charge module is used to pre-charge the first input terminal and the second input terminal according to the second control signal and the common mode voltage.
2. The analog-to-digital converter circuit as described in claim 1, characterized in that, The pre-charge module includes: The pre-charge unit is used to pre-charge the first input terminal and the second input terminal according to the second control signal and the common mode voltage; A balancing unit is used to balance the build-up speed of the common-mode voltage on the first input terminal and the second input terminal according to the second control signal.
3. The analog-to-digital converter circuit as described in claim 2, characterized in that, The pre-charge unit includes: A first transistor, wherein the first terminal of the first transistor is connected to the common-mode voltage, the control terminal of the first transistor is connected to the second control signal, and the second terminal of the first transistor is connected to the first input terminal; The second transistor has its first terminal connected to the second input terminal, its control terminal connected to the second control signal, and its second terminal connected to the common-mode voltage.
4. The analog-to-digital converter circuit as described in claim 3, characterized in that, The balancing unit includes a third transistor, the first terminal of which is connected to the second terminal of the first transistor and the first input terminal, the control terminal of which is connected to the second control signal, and the second terminal of which is connected to the first terminal of the second transistor and the second input terminal.
5. The analog-to-digital converter circuit as described in claim 1, characterized in that, The drive control module is also used to generate a third control signal, and the analog-to-digital conversion circuit further includes a voltage neutralization module, which is used to neutralize the feedthrough voltage on the first input terminal and the second input terminal according to the third control signal.
6. The analog-to-digital converter circuit as described in claim 5, characterized in that, The voltage neutralization module includes a fourth transistor. The first terminal of the fourth transistor is connected to the first input terminal and the first output terminal of the switching module. The control terminal of the fourth transistor is connected to the third control signal. The second terminal of the fourth transistor is connected to the second input terminal and the second output terminal of the switching module.
7. The analog-to-digital converter circuit as described in claim 6, characterized in that, The switching module includes: The fifth transistor has its first terminal connected to the first terminal of the fourth transistor and the first input terminal, its control terminal connected to the first control signal, and its second terminal connected to the common-mode voltage. The sixth transistor has its first terminal connected to the second terminal of the fourth transistor and the second input terminal, its control terminal connected to the control terminal of the fifth transistor, and its second terminal connected to the second terminal of the fifth transistor. The fifth transistor has the same channel type as the sixth transistor, but the channel type of the fifth transistor is different from that of the fourth transistor.
8. The analog-to-digital converter circuit as described in claim 1, characterized in that, The drive control module is also used to generate a fourth enable signal. The analog-to-digital conversion circuit also includes a reset and leakage protection module, which is used to reset the voltage of the first input terminal and the second input terminal according to the fourth enable signal and prevent leakage at the first input terminal and the second input terminal.
9. The analog-to-digital converter circuit according to any one of claims 1 to 8, characterized in that, The drive control module includes: The first control unit is configured to generate the first enable signal and the second enable signal based on the sampled signal, the common-mode configuration signal, and the system enable signal; The second control unit is configured to generate the second control signal, the third enable signal, and the fourth enable signal based on the system enable signal, the sampling signal, the system clock signal, and the fifth enable signal; The first driving unit is configured to generate a third control signal, a first substrate voltage, and a second substrate voltage based on the sampling signal, the first power supply voltage, the common mode voltage, and the second control signal. The first substrate voltage is used to control the substrate voltage of the transistor in the precharge module, and the second substrate voltage is used to control the substrate voltage of the transistor in the voltage neutralization module. The second driving unit is used to generate the first control signal and the third substrate voltage based on the voltage selection signal, the common-mode voltage, the sampling signal and the first power supply voltage. The third substrate voltage is used to control the substrate voltage of the transistor in the switching module.
10. The analog-to-digital converter circuit as described in claim 9, characterized in that, When the idle indicator signal is high, the first driving unit controls the first substrate voltage to be the common-mode voltage; when the idle indicator signal is low, it controls the first substrate voltage to be the first power supply voltage. When the sampling signal is high, the second substrate voltage is controlled to be the common-mode voltage; and when the sampling signal is low, the second substrate voltage is controlled to be the first power supply voltage.
11. The analog-to-digital converter circuit as described in claim 9, characterized in that, The second drive unit includes: A voltage selection subunit is configured to generate a first intermediate voltage based on the first power supply voltage, the common-mode voltage, and the voltage selection signal. A bootstrap subunit is configured to generate the first control signal and the third substrate voltage based on the first intermediate voltage, the sampling signal, and the common-mode voltage.
12. The analog-to-digital converter circuit as described in claim 11, characterized in that, When the first power supply voltage is high, the voltage selection signal is high, and the voltage selection subunit controls the first intermediate voltage to be the common-mode voltage; When the first power supply voltage is low, the voltage selection signal is low, and the voltage selection subunit controls the first intermediate voltage to be the first power supply voltage.
13. The analog-to-digital converter circuit as described in claim 11, characterized in that, When the sampling signal is high, the bootstrap subunit controls the voltage of the first control signal to be the sum of the first intermediate voltage and the first power supply voltage, and the third substrate voltage is the common mode voltage; When the sampling signal is low, the bootstrap subunit controls the voltage of the first control signal to be a second power supply voltage lower than the first power supply voltage, and the third substrate voltage is the second power supply voltage.
14. A chip, characterized in that, The chip includes the analog-to-digital conversion circuit as described in any one of claims 1 to 13.
15. An electronic device, characterized in that, The electronic device includes a device body and a chip as described in claim 14 disposed on the device body.