PCB layout evaluation method, system and medium integrating layout optimization and resource evaluation

Abstract

This invention discloses a PCB layout evaluation method, system, and medium that integrates layout optimization and resource assessment; it relates to the field of electronic design automation technology; this solution is based on PCB layout design, layout resource assessment, and layout quality assessment; it combines the minimum area constraints of different component spacing constraints to place components on the PCB board, and analyzes and evaluates the actual effective area on the PCB board to reflect the effective utilization of the PCB board, assisting engineers in predicting the PCB layout design resource situation in advance, facilitating the optimization of PCB board utilization, thereby reducing PCB raw material costs and manufacturing costs; after the layout is completed, the layout is evaluated from the overall layout to the local layout, providing guidance for the optimization of the layout results and improving the quality and reliability of PCB layout design.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, specifically to a PCB layout evaluation method, system, and medium that integrates layout optimization and resource assessment. Background Technology

[0002] In the field of electronic design automation (EDA), the placement design of components on printed circuit boards (PCBs) is a crucial step, directly impacting product performance, reliability, manufacturability, and cost. As electronic products evolve towards miniaturization, high density, and complexity, the challenges of PCB design are increasing. However, current PCB placement design processes, especially in handling non-standard scenarios and optimizing efficiency, still exhibit significant technical bottlenecks and limitations, primarily in the following aspects:

[0003] Insufficiency in handling irregularly shaped boards and physical constraints: Traditional PCB layout design methods and mainstream EDA tools are inefficient and ineffective when dealing with non-rectangular or irregularly shaped PCB boards. Designers often struggle to efficiently and rationally plan component placement within complex boundary contours, easily leading to wasted layout resources in the board edge areas. More importantly, existing layout tools are weak in automating the handling of predefined holes (such as mounting holes and heat dissipation holes) and keep-out zones (KOZs) on the board.

[0004] Pre-layout assessment relies on inefficient manual estimation: Before proceeding with the actual layout, designers typically need to estimate whether the selected board size can accommodate all necessary components, i.e., assess "board utilization." Currently, this crucial assessment step heavily relies on the designer's experience and manual estimation. Designers need to manually analyze the component list, approximate dimensions and shapes, and combine this with the board outline and known holes or forbidden areas to perform rough area matching calculations. This method is extremely inefficient, time-consuming, and labor-intensive, and the estimation results are highly subjective and inaccurate. Incorrect underestimation may lead to insufficient board space being discovered only later in the layout process, requiring rework or even board replacement; incorrect overestimation may result in selecting oversized boards, causing cost waste.

[0005] Although modern EDA tools offer powerful interactive layout capabilities, allowing designers to place components manually or semi-automatically, their core value often remains at the level of "layout execution".

[0006] These tools generally lack real-time, intelligent, and comprehensive automatic evaluation capabilities, making it difficult to dynamically and accurately calculate and visualize the actual utilization rate of the current layout scheme on the board space (especially after considering irregular shapes and holes / no-wiring areas) during or after the layout process, and even more difficult to predict the overall density distribution after the final wiring is completed.

[0007] More importantly, existing tools are significantly inadequate in providing proactive optimization guidance. They typically cannot automatically analyze bottlenecks in the current layout based on preset goals (such as maximizing board utilization, minimizing dead zones, optimizing heat dissipation or signal paths), nor can they intelligently generate specific improvement suggestions (such as suggestions for fine-tuning, rotating, or replacing key components) to guide designers in optimization. Designers mainly rely on their own experience and repeated trial and error to improve the layout effect, resulting in an inefficient, time-consuming, and difficult-to-achieve optimal solution optimization process.

[0008] In summary, current PCB layout design processes have significant technical shortcomings in handling irregular board materials, effectively avoiding holes / no-go zones to prevent resource waste, improving the efficiency of board utilization assessment, and obtaining automated assessment and optimization guidance. These limitations restrict the improvement of design efficiency, increase design costs and risks, and may lead to suboptimal space utilization and cost-effectiveness in the final product. Therefore, a new technical solution that can effectively solve the above problems is urgently needed. Summary of the Invention

[0009] The technical problem this invention aims to solve is that current PCB layout design processes have significant technical shortcomings in dealing with irregular boards, effectively avoiding holes or restricted areas to prevent resource waste, improving the efficiency of board utilization assessment, and obtaining automated assessment and optimization guidance. This invention aims to provide a PCB layout assessment method, system, and medium that integrates layout optimization and resource assessment, focusing on PCB layout, layout resource assessment, and layout quality assessment. It combines minimum area constraints based on spacing constraints between different components to place components on the PCB board, while simultaneously analyzing and evaluating the actual effective area of ​​the PCB board to reflect the effective utilization of the PCB board. This assists engineers in anticipating PCB layout design resource conditions, facilitating optimization of PCB board utilization, and thereby reducing PCB raw material and manufacturing costs. After layout completion, the layout is evaluated from overall to partial layout, providing guidance for optimizing the layout results and improving the quality and reliability of PCB layout design.

[0010] This invention is achieved through the following technical solution:

[0011] This solution provides a PCB layout evaluation method that integrates layout optimization and resource assessment, including:

[0012] Obtain PCB board material data and component data; arrange the components in descending order according to their area size to construct a component placement sequence;

[0013] Based on the device placement sequence, considering device spacing constraints and minimum area constraints, the devices are dynamically laid out on the PCB board.

[0014] The layout of the PCB board is evaluated; the evaluation items include: board resource utilization, component placement evaluation, overall board uniformity, component group clustering degree, and flying wire evaluation; wherein, the board resource utilization evaluation is based on the dynamic layout results.

[0015] Adjust the placement of components on the PCB board based on the layout evaluation results.

[0016] A further optimization scheme involves dynamically arranging each component on the PCB board based on the component placement sequence, considering both component spacing constraints and minimum area constraints; including the following methods:

[0017] Components are placed onto the PCB board sequentially according to their placement order:

[0018] Adjust the placement angle of the device i to be placed to obtain the inscribed critical polygon region IFP between the device i and the PCB board. board ;

[0019] Obtain the keep-out area of ​​the PCB board material, based on the inscribed critical polygon region IFP. board The candidate region (IFP) on the PCB board for placing device i was determined by the restricted area. final ;

[0020] Obtain the critical polygon region NFP between the device to be placed i and all already placed devices. placed ;

[0021] According to the critical polygon region NFP placed and candidate region IFP final Determine the candidate locations for placing device i;

[0022] Using a square with side length L as the evaluation square, traverse each vertex in the candidate positions, and calculate the total layout area occupied by the device i when placed at each vertex in combination with the evaluation square. The vertex corresponding to the minimum total layout area is taken as the target placement position. When there are multiple target placement positions, calculate the sum S of the x and y coordinates of each target position, and take the target position with the minimum sum S as the final target position of the device i.

[0023] A further optimized approach is to evaluate the method for determining the side length L of the square, which includes:

[0024] ;

[0025] Where N represents the total number of devices; dis ij This represents the spacing constraint between the device i to be placed and the device j already placed.

[0026] A further optimization scheme is to obtain the critical polygonal region NFP between the device to be placed i and all already placed devices. placed ;Including methods:

[0027] Obtain the spacing constraint dis between the device to be placed i and the already placed device j. ij ;

[0028] The device i to be placed and the device j already placed are expanded outwards respectively. Then, the critical polygon region NFP between the device i to be placed and the device j already placed is calculated after the expansion. ij ; External size is dis ij / 2;

[0029] Sum of all critical polygon regions NFP ij Obtain the critical polygonal region NFP placed .

[0030] A further optimized scheme is that the method for determining the candidate position of the device i to be placed includes: according to the formula DIF=IFP final -NFP placed Determine the candidate location DIF for the device i to be placed.

[0031] A further optimized solution is that the evaluation method for the utilization rate of the board material resources includes:

[0032] Calculate the NFP, the union of the evaluation square and the critical polygon regions of all placed devices. b And compute the union set NFP b Area max ;

[0033] The resource utilization rate index R of the board material is calculated according to the following formula:

[0034] ;

[0035] Among them, Area res This indicates the maximum usable area of ​​the PCB material, i.e., the candidate area IFP. final The area.

[0036] A further optimization scheme is that the evaluation method for the degree of aggregation of the device group includes:

[0037] Iterate through all devices and obtain the Manhattan distance d from device i to its nearest neighbor device. i1 ;

[0038] The average minimum boundary distance is calculated using the following formula: = ;

[0039] The clustering index C of the device group is obtained based on the average minimum boundary distance:

[0040] C=1- / D;

[0041] ;

[0042] Where D represents the diagonal length of the rectangle surrounding the device group, W represents the width of the rectangle surrounding the device group, and H represents the height of the rectangle surrounding the device group.

[0043] When the clustering index C of the device group is closer to 1, the clustering degree of the device group is higher; when the clustering index C of the device group is closer to 0, the clustering degree of the device group is lower.

[0044] A further optimization scheme is that the evaluation method for the overall uniformity of the board includes: obtaining the centroid of each device and calculating the nearest neighbor centroid distance d for each centroid. i2 ;

[0045] The uniformity index U of the entire plate is calculated according to the following formula:

[0046] ;

[0047] ;

[0048] ;

[0049] ;

[0050] Wherein, it represents; a i Represents the area of ​​device i; This represents the weighted average. Indicates the weighted standard deviation; The coefficient of variation represents the area-weighted nearest neighbor distance, reflecting the degree of dispersion in the distance between devices;

[0051] When the uniformity index U of the whole plate is closer to 1, the uniformity of the whole plate is higher; when the uniformity index U of the whole plate is closer to 0, the uniformity of the whole plate is lower.

[0052] This solution integrates a PCB layout evaluation system for layout optimization and resource assessment, used to implement the aforementioned PCB layout evaluation method that integrates layout optimization and resource assessment; the system includes:

[0053] The preprocessing module is used to acquire PCB board data and component data, and to preprocess the component data to obtain a component placement sequence;

[0054] The layout module is used to dynamically place each component on the PCB board based on the component placement sequence, taking into account component spacing constraints and minimum area constraints.

[0055] The evaluation module is used to evaluate the layout of PCB materials; the evaluation items of the layout evaluation include: material resource utilization rate, component placement evaluation, overall board uniformity, component group clustering degree and flying wire evaluation; among which, the material resource utilization rate evaluation is based on the dynamic layout results.

[0056] The adjustment module is used to adjust the layout position of components on the PCB board based on the layout evaluation results.

[0057] This solution also provides a computer-readable medium having a computer program stored thereon, the computer program being executed by a processor to implement a PCB layout evaluation method for integrated layout optimization and resource evaluation as described above.

[0058] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0059] 1. This invention provides a PCB layout evaluation method, system, and medium that integrates layout optimization and resource assessment; it is based on PCB layout design, layout resource assessment, and layout quality assessment; it combines the minimum area constraints of different component spacing constraints to place components on the PCB board, and analyzes and evaluates the actual effective area on the PCB board to reflect the effective utilization of the PCB board, assisting engineers in predicting the PCB layout design resource situation in advance, facilitating the optimization of PCB board utilization, thereby reducing PCB raw material costs and manufacturing costs; after the layout is completed, the layout is evaluated from the overall layout to the local layout, providing guidance for the optimization of the layout results and improving the quality and reliability of PCB layout design.

[0060] 2. The PCB layout evaluation method, system and medium integrating layout optimization and resource evaluation provided by this invention can perform self-verification based on the layout results after automatic PCB board layout, thereby improving the layout quality generated by automatic layout. Attached Figure Description

[0061] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:

[0062] Figure 1 A schematic diagram of a PCB layout evaluation system that integrates layout optimization and resource assessment.

[0063] Figure 2 A schematic diagram showing the evaluation results of the rationality assessment of PCB board layout and component placement;

[0064] Figure 3 A schematic diagram of the PCB board layout evaluation results interface A;

[0065] Figure 4 Schematic diagram of interface B for PCB board layout evaluation results;

[0066] Figure 5 A schematic diagram of interface A for evaluating the utilization rate of PCB board materials to be laid out.

[0067] Figure 6 This is a schematic diagram of interface B, used to evaluate the utilization rate of PCB board materials for layout. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0069] Current PCB layout design processes have significant technical shortcomings in dealing with irregular board materials, effectively avoiding holes / no-go zones to prevent resource waste, improving the efficiency of board utilization assessment, and obtaining automated assessment and optimization guidance. Therefore, this solution provides the following embodiments to address the aforementioned technical problems:

[0070] Example 1: This example provides a PCB layout evaluation method that integrates layout optimization and resource assessment, such as... Figure 1 As shown, it includes:

[0071] Acquire PCB board data and component data; arrange the components in descending order according to their area to construct a component placement sequence; the PCB board data mainly includes the overall area of ​​the PCB board, the holes or forbidden areas on the PCB board, etc.; the component data mainly includes component parameters and spacing constraints between components.

[0072] Based on the component placement sequence and considering component spacing constraints and minimum area constraints, dynamic placement of each component is performed on the PCB board. This step specifically includes: placing components sequentially onto the PCB board according to the component placement sequence.

[0073] a. Adjust the placement angle of the device i to be placed to obtain the inscribed critical polygon region IFP between the device i and the PCB board. boardThis scheme is based on the Minkowski method to calculate the critical polygon region (NFP) between graphics. Considering that this method is only applicable to convex polygons, for concave polygonal plates, it is necessary to decompose them into multiple convex polygons, calculate the critical polygons separately, and then take the union of the sets. The inscribed critical polygon region (IFP) is then calculated. board This is the complement of the union. The rotation angle of the device to be placed is 0 by default. If the current angle cannot be obtained, IFP will be used. board Try different angles; if none of the angles support placement, then the device cannot be placed.

[0074] b. Obtain the no-hatch zone of the PCB board material, based on the inscribed critical polygon region IFP. board The candidate region (IFP) on the PCB board for placing device i was determined by the restricted area. final (If there are holes or keep-out areas in the PCB board, the holes or keep-out areas need to be considered, and the critical polygon set NFP between the device to be placed and all holes or keep-out areas needs to be calculated.) hole Then IFP board With NFP hole The difference between the sets yields the final candidate region (IFP_final) on the board for the device to be placed, excluding any already placed devices.

[0075] c, Obtain the critical polygon region NFP between the device to be placed i and all already placed devices. placed This step specifically includes:

[0076] c1, obtain the spacing constraint between the device to be placed i and the already placed device j. ij ;

[0077] c2, expand the outer regions of both the device to be placed i and the already placed device j, and then calculate the critical polygon region NFP between the expanded device i and the already placed device j. ij ; External size is dis ij / 2;

[0078] c3, summing all critical polygon regions NFP ij Obtain the critical polygonal region NFP placed .

[0079] d, based on the critical polygon region NFP placed and candidate region IFP final Determine the candidate locations for placing device i; specifically, according to the formula DIF=IFP final -NFP placed Determine the candidate location DIF for the device i to be placed.

[0080] e. Using a square with side length L as the evaluation square, traverse each vertex in the candidate positions and calculate the total layout area occupied by the device i when placed at each vertex in combination with the evaluation square. The vertex corresponding to the minimum total layout area is taken as the target placement position. When there are multiple target placement positions, calculate the sum S of the x and y coordinates of each target position and take the target position with the minimum sum S as the final target position of the device i.

[0081] Considering that the spacing between components is also part of the resource usage of already placed components, this solution uses a fixed-size square to assess the layout resource usage during component placement, in order to better evaluate the current layout resource usage of the placed components. The method for determining the side length L of the assessment square includes:

[0082] ;

[0083] Where N represents the total number of devices; dis ij This represents the spacing constraint between the device i to be placed and the device j already placed.

[0084] This solution, based on the above method, lays out components on PCB boards by combining minimum area constraints and spacing constraints. During the layout process, the critical polygon method and the inscribed critical polygon method are combined to realize the layout of polygonal boards with holes or forbidden areas, thereby improving the resource utilization of PCB boards and facilitating the improvement of the accuracy of resource utilization assessment.

[0085] The layout of PCB materials is evaluated. The evaluation items include: material resource utilization, component placement evaluation, overall board uniformity, component clustering degree, and flying wire evaluation. Among them, the material resource utilization evaluation is based on the dynamic layout results. The material resource utilization evaluation includes two cases: one is to evaluate the material resource utilization of the already laid-out PCB materials to optimize the layout, and the other is to evaluate the material resource utilization of the PCB materials to be laid out in order to count the available layout resources.

[0086] The methods for evaluating the degree of clustering of device groups include:

[0087] Iterate through all devices and obtain the Manhattan distance d from device i to its nearest neighbor device. i1 ;

[0088] Because the component packages on the PCB vary in size, this solution uses the Manhattan distance, which takes into account the component size, to describe the distance between two components more accurately. If two components overlap, the distance is 0. The Manhattan distance d from component i to its nearest neighbor is... i1 for:

[0089] ;

[0090] in, This represents the width of device i in the two-dimensional coordinate system, parallel to the x-axis. This represents the height of device i in the two-dimensional coordinate system, parallel to the y-axis. This represents the width of the nearest neighboring device i in the two-dimensional coordinate system, parallel to the x-axis. This represents the height of the nearest neighboring device i in a two-dimensional coordinate system, parallel to the y-axis; x i ,y i x1 and y1 represent the x and y coordinates of device i; x1 and y1 represent the x and y coordinates of the nearest neighboring device to device i.

[0091] The average minimum boundary distance is calculated using the following formula: = ;

[0092] The clustering index C of the device group is obtained based on the average minimum boundary distance:

[0093] C=1- / D;

[0094] ;

[0095] Where D represents the diagonal length of the rectangle surrounding the device group, W represents the width of the rectangle surrounding the device group, and H represents the height of the rectangle surrounding the device group.

[0096] When the clustering index C of the device group is closer to 1, the clustering degree of the device group is higher; when the clustering index C of the device group is closer to 0, the clustering degree of the device group is lower. At this time, the devices in the device group are relatively dispersed.

[0097] Methods for evaluating the uniformity of the entire plate include:

[0098] Obtain the centroid of each device and calculate the nearest neighbor centroid distance d for each centroid. i2 ;

[0099] The nearest neighbor centroid of centroid i is d i2 for:

[0100] ;

[0101] Among them, X i ,Y i x1 and y1 represent the x and y coordinates of the centroid i; x1 and y1 represent the x and y coordinates of the nearest neighbor centroid i.

[0102] The uniformity index U of the entire plate is calculated according to the following formula:

[0103] ;

[0104] ;

[0105] ;

[0106] ;

[0107] Wherein, it represents; a i Represents the area of ​​device i; This represents the weighted average. Indicates the weighted standard deviation; The coefficient of variation represents the area-weighted nearest neighbor distance, reflecting the degree of dispersion in the distance between devices;

[0108] When the uniformity index U of the whole plate is closer to 1, the uniformity of the whole plate is higher; when the uniformity index U of the whole plate is closer to 0, the uniformity of the whole plate is lower.

[0109] The method of calculating the occupied layout area by taking the union of the evaluation square and the NFP of all placed devices is used to calculate the area of ​​each device group and sort them according to the area size to obtain the ranking of the impact on the overall board distribution.

[0110] Flywire evaluation involves splitting ordinary signal networks (excluding power and ground networks) into minimum spanning trees based on Manhattan distance, according to the PCB netlist and layout results, to obtain multiple flywires. The length of each flywire is counted, the number of flywire crossings is calculated, and the results are displayed.

[0111] The evaluation of device placement rationality includes two parts: evaluation of decoupling capacitor placement rationality and inspection and optimization suggestions for device spacing violations.

[0112] Decoupling capacitor placement rationality assessment: The placement of decoupling capacitors is evaluated by checking their distance from the IC power pins on the PCB layout. In engineering practice, a relatively simple formula for estimating the decoupling capacitor radius r, which only considers the capacitance value, is sometimes used. The unit is mm, where C represents the capacitance value of the decoupling capacitor in microfarads. If the pin on the decoupling capacitor connected to the power supply is located within a circle centered on the power supply pin and with the decoupling radius as the radius, then the decoupling capacitor is placed correctly; otherwise, it will be shown in the recommendations.

[0113] Component spacing violation check: Considering the spacing between components, traverse all components and check for overlap with other components in turn. The check method is as follows: Assume the spacing constraint between component i and component j is dis ij For device i and device j, expand dis ij / 2. Check if there are any overlaps between the expanded components. If overlaps are found, it indicates a violation of spacing rules, and the violating component pair is recorded. For all component pairs violating spacing rules, an optimization function based on simulated annealing is used sequentially to determine the new positions of the unoverlapping components. Methods for evaluating board material resource utilization include:

[0114] After all components have been successfully placed, the resource utilization rate is given by calculating the ratio of the layout space occupied by all components after placement to the available layout space before placement.

[0115] Calculate the NFP, the union of the evaluation square and the critical polygon regions of all placed devices. b And compute the union set NFP b Area max ;

[0116] The resource utilization rate index R of the board material is calculated according to the following formula:

[0117] ;

[0118] Among them, Area res This indicates the maximum usable area of ​​the PCB material, i.e., the candidate area IFP. final The area.

[0119] When calculating occupied layout resources, the NFP is calculated by taking the union of the evaluation square and the critical polygons of all placed devices. b This refers to the currently occupied layout area; before layout, obtain the inscribed critical polygon IFP between the evaluation square and the PCB board outline. pboard Then obtain the inscribed critical polygon IFP. pboard NFP (Network Plug-in) is the critical polygonal region of all keep-out areas (including vias) in the PCB board. hole and with critical polygonal region NFP hole The area is used as the largest available layout resource for current PCB materials. res Reserved for future use, to calculate resource utilization after all components have been placed.

[0120] Adjust the placement of components on the PCB board based on the layout evaluation results.

[0121] This embodiment evaluates the rationality of component placement on a completed PCB board layout, and the evaluation report is as follows: Figure 2As shown, the evaluation score for the rationality of decoupling capacitor placement is 70.5882. Based on the layout resource evaluation results, some suggestions are made. For example, decoupling capacitors C1, C11, C36, C44, and C46 have unreasonable placement issues and it is recommended that they be placed within the circular area formed by the corresponding decoupling capacitor radius r. Devices ANT2, C37, C44, C47, C48, and C70 have unreasonable placement issues and it is recommended that they be placed within the rectangular area. It is also recommended to check the pins of some decoupling capacitors and power supplies.

[0122] like Figure 3 and Figure 4 As shown, this embodiment evaluates the overall uniformity, flying wires, and component placement rationality of the completed PCB layout, and provides corresponding suggestions, such as... Figure 3 The impact levels of the regions containing device groups 13, 7, 5, 10, 4, 12, 14, 15, 6, 2, 3, and 1 on the uneven distribution of the entire board are given as Level 1, Level 2, Level 3, Level 4, Level 5, Level 6, Level 7, Level 8, Level 9, Level 10, and Level 11, respectively. The flying wire evaluation information given includes the flying wire evaluation score, the number of flying wire intersections, and the total length of the flying wires.

[0123] Example 2: The device placement evaluation, overall board uniformity, device group aggregation degree and flying wire evaluation in Example 1 are mainly for evaluating the PCB board that has been laid out; the evaluation of board resource utilization includes two cases: one is to evaluate the board resource utilization of the laid-out PCB board (as in Example 1), and the other is to evaluate the board resource utilization of the PCB board to be laid out, so as to make statistics on the available layout resources.

[0124] Specifically, when there are components to be placed on the PCB board, the proportion of PCB board resources still required for the components can be calculated using the board resource utilization assessment method. The user will then be notified that the current PCB board area cannot meet the layout requirements and that additional PCB board area is needed. The specific formula for calculating the proportion of PCB board resources required for the components is as follows:

[0125] ;

[0126] Where n is the number of devices to be placed, and m is the number of devices already placed; Area i Area represents the layout space occupied by the device i to be placed; j This indicates the layout space occupied by the placed device j.

[0127] Specifically, such as Figure 5 and Figure 6 As shown, this embodiment calculates the proportion of PCB board resources still required for the device to be placed using a board resource utilization evaluation method. Figure 5 As shown, the evaluation results of the board material resource utilization rate include information such as layout area utilization rate, effective layout area, device layout area, placed devices, unplaced devices, and suggestions for increasing layout resources.

[0128] Example 3: This example provides a PCB layout evaluation system integrating layout optimization and resource assessment, used to implement the PCB layout evaluation method integrating layout optimization and resource assessment in Example 1; the system includes:

[0129] The preprocessing module is used to acquire PCB board data and component data, and to preprocess the component data to obtain a component placement sequence;

[0130] The layout module is used to dynamically place each component on the PCB board based on the component placement sequence, taking into account component spacing constraints and minimum area constraints.

[0131] The evaluation module is used to evaluate the layout of the laid-out PCB materials. The evaluation items include: material resource utilization, component placement evaluation, overall board uniformity, component group clustering degree, and flying wire evaluation. Among them, the material resource utilization evaluation is based on the dynamic layout results. The material resource utilization evaluation includes two cases: one is to evaluate the material resource utilization of the already laid-out PCB materials to optimize the layout, and the other is to evaluate the material resource utilization of the PCB materials to be laid out in order to count the available layout resources.

[0132] The adjustment module is used to adjust the layout position of components on the PCB board based on the layout evaluation results.

[0133] Example 4: This example also provides a PCB layout evaluation system integrating layout optimization and resource assessment, used to implement the PCB layout evaluation method integrating layout optimization and resource assessment in Example 1; such as Figure 1 As shown, the system includes:

[0134] The system includes a display module, a layout resource assessment module, and a layout analysis module. The layout resource assessment module includes a data preprocessing unit, a cyclic placement of components unit, and a board material resource utilization assessment module. The layout analysis module includes a flying wire assessment unit, a component group aggregation assessment unit, a component placement assessment unit, a board uniformity assessment unit, and a layout resource utilization unit (i.e., the layout resource assessment module).

[0135] The display module showcases the layout evaluation results and optimization suggestions for easy viewing and analysis by users. The results displayed in the display unit mainly include a log or report display section, an optimization suggestion display section, and an evaluation report export section. Figure 3 The results shown present the display interface of the demonstration unit, which is divided into five parts: function operation buttons 1, total score display 2, optimization suggestion display 3, real-time log and evaluation report display 4, and evaluation progress bar 5. During the evaluation process, the real-time log will be displayed on the "Log" option page of section 4. The evaluation progress bar 5 shows the evaluation progress. When the evaluation is completed, the progress bar will reach 100%. All evaluation reports will be displayed on the "Report" option page of section 4, which shows the real-time log and evaluation report display. Section 3, the optimization suggestion display, shows the suggestions given, which are displayed by a tree control from "overall board suggestions", "module suggestions" and "component suggestions".

[0136] The layout resource assessment module has two working modes. When running the module alone, if the board resources are insufficient to accommodate all components, a pre-layout feasibility report will be generated, displaying the suggested increase in board area on the overall board recommendation, prompting the user to increase board resources. When assessing the board resource utilization of already laid-out PCB boards, the layout assessment results will be generated and displayed.

[0137] The modules are suggested to be sorted from high to low according to their impact on the uniformity of the overall board distribution. In the module suggestions, each branch represents a module circuit (component group). Clicking on a branch will highlight the corresponding components in the module circuit in the PCB design software and outline the scope of the module circuit with a polygon.

[0138] The component suggestions section displays improperly placed components / decoupling capacitors and provides placement recommendations. Each branch in the component suggestions section represents a component. Clicking on a branch will highlight the corresponding component in the PCB design software, and a rectangle / circle will be used to draw the suggested placement range.

[0139] Example 5: This example provides a computer-readable medium storing a computer program that, when executed by a processor, enables a PCB layout evaluation method that integrates layout optimization and resource evaluation as described in Example 1; specifically, it executes the following process:

[0140] Obtain PCB board material data and component data; arrange the components in descending order according to their area size to construct a component placement sequence;

[0141] Based on the device placement sequence, considering device spacing constraints and minimum area constraints, the devices are dynamically laid out on the PCB board.

[0142] Layout evaluation of PCB materials; the evaluation items include: material resource utilization, component placement evaluation, overall board uniformity, component group clustering degree, and flying wire evaluation; among them, material resource utilization evaluation is based on dynamic layout results; the material resource utilization evaluation includes two cases: one is to evaluate the material resource utilization of the already laid-out PCB materials to optimize the layout, and the other is to evaluate the material resource utilization of the PCB materials to be laid out in order to statistically analyze the available layout resources;

[0143] Adjust the placement of components on the PCB board based on the layout evaluation results.

[0144] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A PCB layout evaluation method integrating layout optimization and resource assessment, characterized in that, include: Obtain PCB board material data and component data; arrange the components in descending order according to their area size to construct a component placement sequence; Based on the device placement sequence, considering device spacing constraints and minimum area constraints, the devices are dynamically laid out on the PCB board. The layout of the PCB board is evaluated; the evaluation items include: board resource utilization, component placement evaluation, overall board uniformity, component group clustering degree, and flying wire evaluation; wherein, the board resource utilization evaluation is based on the dynamic layout results. Adjust the placement of components on the PCB board based on the layout evaluation results; The method involves dynamically laying out each component on a PCB board, considering both component spacing constraints and minimum area constraints, based on the component placement sequence. Components are placed onto the PCB board sequentially according to their placement order: Adjust the placement angle of the device i to be placed to obtain the inscribed critical polygon region IFP between the device i and the PCB board. board ; Obtain the keep-out area of ​​the PCB board material, based on the inscribed critical polygon region IFP. board The candidate region (IFP) on the PCB board for placing device i was determined by the restricted area. final ; Obtain the critical polygon region NFP between the device to be placed i and all already placed devices. placed ; According to the critical polygon region NFP placed and candidate region IFP final Determine the candidate locations for placing device i; Using a square with side length L as the evaluation square, traverse each vertex in the candidate positions, and calculate the total layout area occupied by the device i when placed at each vertex in combination with the evaluation square. The vertex corresponding to the minimum total layout area is taken as the target placement position. When there are multiple target placement positions, calculate the sum S of the x and y coordinates of each target position, and take the target position with the minimum sum S as the final target position of the device i. Methods for determining the side length L of a square include: ； Where N represents the total number of devices; dis ij This represents the spacing constraint between the device i to be placed and the device j already placed.

2. The PCB layout evaluation method integrating layout optimization and resource evaluation according to claim 1, characterized in that, The critical polygonal region NFP between the device to be placed i and all placed devices is obtained. placed ;include method: Obtain the spacing constraint dis between the device to be placed i and the already placed device j. ij ; The device i to be placed and the device j already placed are expanded outwards respectively. Then, the critical polygon region NFP between the device i to be placed and the device j already placed is calculated after the expansion. ij ; External size is dis ij / 2; Sum of all critical polygon regions NFP ij Obtain the critical polygonal region NFP placed .

3. The PCB layout evaluation method integrating layout optimization and resource evaluation according to claim 1, characterized in that, The method for determining the candidate position of the device i to be placed includes: according to the formula DIF=IFP final -NFP placed Determine the candidate location DIF for the device i to be placed.

4. The PCB layout evaluation method integrating layout optimization and resource evaluation according to claim 1, characterized in that, The evaluation method for the utilization rate of the board material resources includes: Calculate the NFP, the union of the evaluation square and the critical polygon regions of all placed devices. b And compute the union set NFP b Area max ; The resource utilization rate index R of the board material is calculated according to the following formula: ； Among them, Area res This indicates the maximum usable area of ​​the PCB material, i.e., the candidate area IFP. final The area.

5. The PCB layout evaluation method integrating layout optimization and resource evaluation according to claim 1, characterized in that, The methods for evaluating the degree of aggregation of the device group include: Iterate through all devices and obtain the Manhattan distance d from device i to its nearest neighbor device. i1 ; The average minimum boundary distance is calculated using the following formula: = ; The clustering index C of the device group is obtained based on the average minimum boundary distance: C=1- / D; ； Where D represents the diagonal length of the rectangle surrounding the device group, W represents the width of the rectangle surrounding the device group, and H represents the height of the rectangle surrounding the device group. When the clustering index C of the device group is closer to 1, the clustering degree of the device group is higher; when the clustering index C of the device group is closer to 0, the clustering degree of the device group is lower.

6. The PCB layout evaluation method integrating layout optimization and resource evaluation according to claim 1, characterized in that, The method for evaluating the uniformity of the entire plate includes: Obtain the centroid of each device and calculate the nearest neighbor centroid distance d for each centroid. i2 ; The uniformity index U of the entire plate is calculated according to the following formula: ； ； ； ； Wherein, it represents; a i Represents the area of ​​device i; This represents the weighted average. Indicates the weighted standard deviation; The coefficient of variation represents the area-weighted nearest neighbor distance, reflecting the degree of dispersion in the distance between devices; When the uniformity index U of the whole plate is closer to 1, the uniformity of the whole plate is higher; when the uniformity index U of the whole plate is closer to 0, the uniformity of the whole plate is lower.

7. A PCB layout evaluation system integrating layout optimization and resource assessment, characterized in that, A PCB layout evaluation method for implementing integrated layout optimization and resource evaluation as described in any one of claims 1-6; the system comprises: The preprocessing module is used to acquire PCB board data and component data, and to preprocess the component data to obtain a component placement sequence; The layout module is used to dynamically place each component on the PCB board based on the component placement sequence, taking into account component spacing constraints and minimum area constraints. Evaluation module, used for The layout of the PCB board is evaluated; the evaluation items include: board resource utilization, component placement evaluation, overall board uniformity, component group clustering degree, and flying wire evaluation; wherein, the board resource utilization evaluation is based on the dynamic layout results. The adjustment module is used to adjust the layout position of components on the PCB board based on the layout evaluation results.

8. A computer-readable medium having a computer program stored thereon, characterized in that, The computer program, when executed by a processor, can implement the PCB layout evaluation method that integrates layout optimization and resource evaluation as described in any one of claims 1-6.

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