Control method of cot conversion circuit, cot conversion circuit and chip

Abstract

The application provides a control method of a COT conversion circuit, the COT conversion circuit and a chip. The COT conversion circuit is used in connection with an output circuit. The method comprises the following steps: when it is detected that the output voltage of the COT conversion circuit is less than a preset first reference voltage, the COT conversion circuit is controlled to enter a pressure boosting state, and the pressure boosting state is reset through a reset signal; at the generation moment of the reset signal, if it is detected that the output voltage of the COT conversion circuit is still less than the preset first reference voltage, the reset signal is disabled, so that the COT conversion circuit remains in the pressure boosting state; and until it is detected that the output voltage of the COT conversion circuit is greater than a preset second reference voltage, the reset signal is enabled, so that the COT conversion circuit ends the pressure boosting state.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a control method for a COT conversion circuit, a COT conversion circuit, and a chip. Background Technology

[0002] Currently, the BUCK chip stabilizes the output voltage by real-time modulation of the duty cycle. Duty cycle modulation has several modes, such as Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), and Pulse Skipping Modulation (PSM). COT (Constant On Time) is a PFM scheme that keeps the upper power transistor on for a constant period, controlling the off-time by detecting the difference between the output voltage and the reference voltage to stabilize the output voltage. In the event of a sudden change in load current, the output voltage Vo drops significantly, causing VFB to drop as well. Therefore, in this situation, VFB may still be lower than VREF after the end of Ton. In this case, the upper transistor will be turned on again after a minimum off-time (Min Off-Time). Since the upper power transistor switch remains on for at least one constant period, voltage overshoot may occur, slowing down the system's response. Summary of the Invention

[0003] This application provides a control method, a COT conversion circuit, and a chip for accelerating system response and reducing voltage overshoot in the COT conversion circuit.

[0004] In a first aspect, embodiments of this application provide a control method for a COT conversion circuit, applied to a COT conversion circuit, wherein the COT conversion circuit is connected to another COT conversion circuit, the method comprising:

[0005] When the output voltage of the COT conversion circuit is detected to be less than a preset first reference voltage, the COT conversion circuit is controlled to enter a boost state, and the boost state is reset by a reset signal;

[0006] At the moment the reset signal is generated, if it is detected that the output voltage of the COT conversion circuit is still less than the preset first reference voltage, the reset signal is invalidated so that the COT conversion circuit maintains the boosted state.

[0007] The reset signal is activated when the output voltage of the COT conversion circuit is detected to be greater than the preset second reference voltage, so that the COT conversion circuit ends the boost state.

[0008] In some embodiments, if the output voltage of the COT conversion circuit is detected to be greater than a preset first reference voltage at the time the reset signal is generated, the reset signal is activated so that the COT conversion circuit ends the boost state.

[0009] In some embodiments, the COT conversion circuit includes: a first detection unit, a second detection unit, a timing unit, a reset control unit, and a switch control unit;

[0010] The first detection unit is used to detect the magnitude relationship between the output voltage of the output circuit and a preset first reference voltage;

[0011] The second detection unit is used to detect the magnitude relationship between the output voltage of the output circuit and the preset second reference voltage;

[0012] The timing unit is used to generate the reset signal when the duration of the COT conversion circuit in the boost state reaches the fixed period;

[0013] The reset control unit is used to determine whether the reset signal is invalid;

[0014] The switch control unit is used to increase the output voltage of the output circuit when entering the boost state.

[0015] In some embodiments, controlling the COT conversion circuit to enter a boost state includes:

[0016] The switch control unit sends a boost signal to the output circuit, thereby increasing the output voltage of the output circuit; or,

[0017] Increase the output voltage of the switch control unit to increase the output voltage of the output circuit.

[0018] In some embodiments, the first detection unit includes a first comparator, the second detection unit includes a second comparator, the reset control unit includes an AND gate and an SR flip-flop, and the switch control unit includes a logic converter; the positive input of the first comparator is connected to a preset first reference voltage, the negative input of the first comparator is connected to the output voltage of the output circuit, the output of the first comparator is connected to the logic converter, the input of the timing unit, and the first input of the AND gate, the second input of the AND gate is connected to the output of the timing unit, the output of the AND gate is connected to the set input of the SR flip-flop, the reset input of the SR flip-flop is connected to the output of the second comparator, the positive input of the second comparator is connected to the output voltage of the output circuit, the negative input of the second comparator is connected to a preset second reference voltage, the output of the second comparator is connected to the logic converter, and the signal output of the logic converter is connected to the output circuit; the method specifically includes:

[0019] When the first comparator detects that the output voltage of the output circuit is less than the preset first reference voltage, it sends start signals to the logic converter, the AND gate and the timing unit respectively, so as to control the logic converter to enter the boost state and send the boost signal to the output voltage, and control the timing unit to generate the reset signal when the timing duration reaches the fixed period.

[0020] At the moment the reset signal is generated, the AND gate controls the SR flip-flop to enter the set state according to the start signal and the reset signal, so that the SR flip-flop outputs a reset inhibit signal to the logic converter, thereby disabling the reset signal and keeping the logic converter in the boost state.

[0021] The second comparator controls the SR flip-flop to enter a reset state based on the output voltage of the output circuit and a preset second reference voltage, so that the SR flip-flop stops outputting a reset disable signal to the logic converter, thereby making the reset signal effective and causing the logic converter to end the boost state.

[0022] In some embodiments, the switch control unit includes: a logic converter, a higher-level power transistor, and a lower-level power transistor; the first detection unit includes: a first comparator; the second detection unit includes: a second comparator; the reset control unit includes: a first NOT gate, a second NOT gate, an AND gate, and a selector switch; the first control terminal of the logic converter is connected to the controlled terminal of the higher-level power transistor, the second control terminal of the logic converter is connected to the controlled terminal of the lower-level power transistor, the positive input of the first comparator is connected to a preset first reference voltage, the negative input of the first comparator is connected to the output voltage of the COT conversion circuit, and the output terminal of the first comparator is connected to the input terminal of the COT conversion circuit and the timing unit, respectively. The controlled terminal of the timing unit is connected to the second control terminal of the logic converter. The output terminal of the timing unit is connected to the first terminal of the selection switch. The second terminal of the selection switch is grounded. The selection terminal of the selection switch is connected to the output terminal of the AND gate. The two input terminals of the AND gate are respectively connected to the output terminals of the first NOT gate and the second NOT gate. The input terminal of the first NOT gate is connected to the output terminal of the second comparator. The positive input terminal of the second comparator is connected to a preset second reference voltage. The negative input terminal of the second comparator is connected to the output voltage of the COT conversion circuit. The input terminal of the second NOT gate is connected to the second control terminal of the logic converter. The selection terminal of the selection switch is also connected to the logic converter.

[0023] The method specifically includes:

[0024] When the first comparator detects that the output voltage of the COT conversion circuit is less than the preset first reference voltage, it sends start signals to the logic converter and the timing unit respectively to control the logic converter to enter the boost state. The logic converter sends a start signal to the upper power transistor to make the upper power transistor and the lower power transistor turn on at the same time, thereby increasing the output voltage of the output circuit. The timing unit controls the timing unit to generate the reset signal when the timing duration reaches the fixed period.

[0025] At the moment the reset signal is generated, the second comparator controls the AND gate to open based on the output voltage of the output circuit and the preset second reference voltage. The AND gate controls the selection switch to input the reset signal to the logic converter, making the reset signal effective and thus ending the boost state of the COT conversion circuit.

[0026] In some embodiments, the timing unit includes: a timing switch transistor, a clock element, a filter capacitor, and a third comparator. The second terminal of the clock element is connected to the first terminal of the timing switch transistor, the first terminal of the filter capacitor, and the positive input of the third comparator. The second terminals of the timing switch transistor and the filter capacitor are both grounded. The controlled terminal of the timing switch transistor is the controlled terminal of the timing unit. The negative input of the third comparator is connected to a preset third reference voltage. The output terminal of the third comparator is connected to the first terminal of the selection switch.

[0027] Secondly, embodiments of this application provide a COT conversion circuit, which is used to connect to a COT conversion circuit and to execute a control method for the COT conversion circuit as described in any of the embodiments of this application.

[0028] Thirdly, embodiments of this application provide a chip, the chip including any of the COT conversion circuits described in the embodiments of this application.

[0029] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to implement a control method for a COT conversion circuit as described in any of the embodiments of this application.

[0030] This application provides a control method for a COT conversion circuit connected to an output circuit. The method includes: when the output voltage of the output circuit is detected to be less than a preset first reference voltage, controlling the COT conversion circuit to enter a boost state, the boost state being reset by a reset signal generated after a fixed period; if, at the time the reset signal is generated, the output voltage of the output circuit is still detected to be less than the preset first reference voltage, the reset signal is disabled to keep the COT conversion circuit in the boost state; until the output voltage of the output circuit is detected to be greater than a preset second reference voltage, the reset signal is activated to end the boost state of the COT conversion circuit. Through this method, the activation time of the reset signal is managed by the first reference voltage, the second reference voltage, and the output voltage of the COT conversion circuit, thereby managing the duration of the COT conversion circuit entering the boost state. This avoids the boost state duration being proportional to the constant period, thus reducing output voltage overshoot and the response time of the COT conversion circuit. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A schematic flowchart illustrating a control method for a COT conversion circuit provided in an embodiment of this application;

[0033] Figure 2 A circuit diagram of the first COT conversion circuit provided in the embodiments of this application;

[0034] Figure 3 A schematic diagram of the signal response of a COT conversion circuit provided in an embodiment of this application;

[0035] Figure 4 A circuit diagram of the second COT conversion circuit provided in the embodiments of this application;

[0036] Figure 5 A rendering of a COT conversion circuit provided in an embodiment of this application;

[0037] Figure 6 This is an operation flowchart of a control method for a COT conversion circuit provided in an embodiment of this application.

[0038] Figure label:

[0039] 200. Output circuit; 100. COT conversion circuit; 11. First detection unit; 12. Second detection unit; 13. Timing unit; 14. Reset control unit; 15. Switch control unit; U1. First comparator; U2. Second comparator; U3. Third comparator; Y1. AND gate; T1. SR flip-flop; L1. Logic converter; Q. Upper power transistor; Q2. Lower power transistor; Q3. Timing switch transistor; F1. First NOT gate; F2. Second NOT gate; S1. Selector switch; Js1. Clock device; C1. Filter capacitor. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0042] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0043] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0044] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating a control method for a COT conversion circuit provided in an embodiment of this application. Figure 1 The control method shown is for a COT conversion circuit, which is used to connect to an output circuit. The specific steps of the method include: S101-S103.

[0045] S101. When the output voltage of the output circuit is detected to be less than the preset first reference voltage, the COT conversion circuit is controlled to enter the boost state. The boost state is reset by a reset signal generated after a fixed period.

[0046] For example, the COT conversion circuit is connected to the output circuit. The COT conversion circuit is used to change the output voltage of the output circuit, and it can also detect the output voltage of the output circuit. When the COT conversion circuit enters the boost state, it can increase the output voltage of the output circuit by: 1. sending a boost signal to the output circuit, causing the output circuit to increase the number of power transistors turned on; 2. increasing the supply voltage from the COT conversion circuit to the output circuit, thereby increasing the output voltage of the output circuit. The COT conversion circuit has an internal timing function. It starts timing when it enters the boost state and generates a reset signal when the timing reaches a fixed period. When the part of the COT conversion circuit that sends the boost signal receives the reset signal, it exits the boost state; that is, the reset signal resets the boost state of the COT conversion circuit.

[0047] S102. At the moment the reset signal is generated, if it is detected that the output voltage of the output circuit is still less than the preset first reference voltage, the reset signal is invalidated so that the COT conversion circuit remains in boosted state.

[0048] For example, in the embodiments of this application, the reset signal affects the duration of the COT conversion circuit and the output circuit entering the boost state. If the duration of the two entering the boost state is controlled only by a fixed period multiple, multiple boost states need to be activated, which is not conducive to fast voltage response. At the same time, in the last boost state, the output voltage of the output circuit may be greater than the preset rated output voltage, and it is necessary to wait for the output voltage of the output circuit to drop, which is also not conducive to voltage response.

[0049] It should be noted that, in this embodiment of the application, the effectiveness of the reset signal can be determined by detecting whether the corresponding unit in the COT conversion circuit receives a reset signal.

[0050] S103. When the output voltage of the output circuit is detected to be greater than the preset second reference voltage, the reset signal is activated so that the COT conversion circuit ends the boost state.

[0051] For example, in this embodiment of the application, when the output voltage of the output circuit is detected to be greater than a preset second reference voltage, a reset signal is activated in the COT conversion circuit, causing the COT conversion circuit to exit the boost state. The second reference voltage is slightly greater than the first reference voltage; for example, the first reference voltage is 0.8V and the second reference voltage is 0.804V. This reduces the rate at which the output voltage of the output circuit falls back down.

[0052] This application provides a control method for a COT conversion circuit connected to an output circuit. The method includes: when the output voltage of the output circuit is detected to be less than a preset first reference voltage, controlling the COT conversion circuit to enter a boost state, the boost state being reset by a reset signal generated after a fixed period; if, at the time the reset signal is generated, the output voltage of the output circuit is still detected to be less than the preset first reference voltage, the reset signal is disabled to keep the COT conversion circuit in the boost state; until the output voltage of the output circuit is detected to be greater than a preset second reference voltage, the reset signal is activated to end the boost state of the COT conversion circuit. Through this method, the activation time of the reset signal is managed by the first reference voltage, the second reference voltage, and the output voltage of the COT conversion circuit, thereby managing the duration of the COT conversion circuit entering the boost state. This avoids the boost state duration being proportional to the constant period, thus reducing output voltage overshoot and the response time of the COT conversion circuit.

[0053] To more clearly illustrate the technical solution of this application, the technical solution of this application will be described below through specific embodiments. It should be noted that the specific embodiments are used to expand the description of the technical solution of this application, and are not intended to limit this application.

[0054] In some embodiments, at the time the reset signal is generated, if it is detected that the output voltage of the COT conversion circuit is greater than a preset first reference voltage, the reset signal is activated so that the COT conversion circuit ends the boost state.

[0055] For example, the fixed period is the minimum existence period of the boost state. In response to a small drop in output voltage, the output voltage of the output circuit is restored to the first reference voltage within a fixed period of the boost state. Therefore, at the time of generating the reset signal, if the output voltage of the COT conversion circuit is detected to be greater than the preset first reference voltage, it means that continuous boosting is not required, and the reset signal is activated to end the boost state.

[0056] In some embodiments, please refer to Figure 2 , Figure 2 This is a circuit diagram of the first COT conversion circuit provided in the embodiments of this application. Figure 2 As shown, the COT conversion circuit 100 includes: a first detection unit 11, a second detection unit 12, a timing unit 13, a reset control unit 14, and a switch control unit 15.

[0057] The first detection unit 11 is used to detect the magnitude relationship between the output voltage of the output circuit 200 and the preset first reference voltage.

[0058] The second detection unit 12 is used to detect the magnitude relationship between the output voltage of the output circuit 200 and the preset second reference voltage.

[0059] The timing unit 13 is used to generate a reset signal when the duration of the COT conversion circuit 100 in the boost state reaches a fixed period.

[0060] The reset control unit 14 is used to determine whether the reset signal is invalid.

[0061] The switch control unit 15 is used to increase the output voltage of the output circuit 200 when entering the boost state.

[0062] In some embodiments, controlling the COT conversion circuit 100 to enter a boost state includes: sending a boost signal to the output circuit 200 through the switch control unit 15 to increase the output voltage of the output circuit 200; or increasing the output voltage of the switch control unit 15 to increase the output voltage of the output circuit 200.

[0063] In this embodiment, the switch control unit 15 and the output circuit 200 enter the boost state synchronously, that is, when the switch control unit 15 enters the boost state, the output circuit 200 will also enter the boost state.

[0064] In one embodiment, if the switch control unit 15 does not contain a power transistor, but the output circuit 200 does contain a power transistor, when the switch control unit 15 enters the boost state, it will send a boost signal to the output circuit 200. The boost signal is used to control the number of power transistors turned on. By controlling the number of power transistors turned on in the output circuit 200, the output voltage of the output circuit 200 is increased.

[0065] In another embodiment, if the switch control unit 15 includes a power transistor while the output circuit 200 does not include a power transistor, when the switch control unit 15 enters the boost state, it directly increases the number of power transistors turned on, thereby increasing the output voltage of the switch control unit 15. The input terminal of the output circuit 200 is connected to the output terminal of the switch control unit 15. By increasing the output voltage of the switch control unit 15, the input voltage of the output circuit 200 is increased, thereby increasing the output voltage of the output circuit 200.

[0066] In the embodiments of this application, whether the COT conversion circuit 100 includes a power transistor or not, it is within the protection scope of this application.

[0067] In one embodiment, such as Figure 2 As shown, the first detection unit 11 includes a first comparator U1, the second detection unit 12 includes a second comparator U2, the reset control unit 14 includes an AND gate Y1 and an SR flip-flop T1, and the switch control unit 15 includes a logic converter L1. The positive input of the first comparator U1 is connected to a preset first reference voltage, the negative input of the first comparator U1 is connected to the output voltage of the output circuit 200, the output of the first comparator U1 is connected to the logic converter L1, the input of the timing unit 13, and the first input of the AND gate Y1, the second input of the AND gate Y1 is connected to the output of the timing unit 13, the output of the AND gate Y1 is connected to the set terminal (S terminal) of the SR flip-flop T1, the reset terminal (R terminal) of the SR flip-flop T1 is connected to the output of the second comparator U2, the positive input of the second comparator U2 is connected to the output voltage of the output circuit 200, the negative input of the second comparator U2 is connected to a preset second reference voltage, the output of the second comparator U2 is connected to the logic converter L1, and the signal output of the logic converter L1 is connected to the output circuit 200. Figure 2 The COT conversion circuit 100 shown, and the specific steps of the control method of the COT conversion circuit 100 include: S201-S203.

[0068] S201. When the first comparator U1 detects that the output voltage Vfb of the output circuit 200 is less than the preset first reference voltage Vref, it sends a start signal Vcomp to the logic converter L1, the AND gate Y1 and the timing unit 13 respectively, so as to control the logic converter L1 to enter the boost state and send the boost signal Ton to the output voltage. When the timing unit 13 reaches the fixed period, it controls the timing unit 13 to generate a reset signal Ton_Reset.

[0069] For example, please refer to Figure 3 , Figure 3 This is a schematic diagram of the signal response of a COT conversion circuit provided in an embodiment of this application. Figure 3 As shown, at time t1, the first comparator U1 detects that the output voltage Vfb of the output circuit 200 is less than the first reference voltage Vref. The first comparator U1 outputs a high-level start signal Vcomp, which is received by the logic converter L1, the AND gate Y1, and the timing unit 13. The logic converter L1 enters the boost mode and outputs a boost signal Ton. The timing unit 13 starts timing synchronously and outputs a reset signal Ton_Reset when the timing duration reaches a fixed period (Ts). When the reset signal Ton_Reset is received by the logic converter L1, it can be determined that the reset signal Ton_Reset has started to take effect.

[0070] It should be noted that in this embodiment, the switch control unit 15 does not include a power transistor, which is located in the output circuit 200. Therefore, the boost signal Ton is used to control the output circuit 200 to increase the number of power transistors turned on, thereby increasing the output voltage of the output circuit 200.

[0071] S202. At the moment when the reset signal Ton_Reset is generated, the AND gate Y1 controls the SR flip-flop T1 to enter the set state according to the start signal Vcomp and the reset signal Ton_Reset, so that the SR flip-flop T1 outputs the reset prohibition signal Reset_forbid to the logic converter L1, thereby disabling the reset signal Ton_Reset, and thus keeping the logic converter L1 in the boost state.

[0072] For example, the reset signal Ton_Reset is ANDed with the start signal Vcomp via AND gate Y1. At time t2, the timing unit 13 reaches a fixed period and generates the reset signal Ton_Reset. If the output voltage Vfb of the output circuit 200 is still lower than the first reference voltage Vref (e.g., 0.8V), and the start signal Vcomp is still high, AND gate Y1 outputs a high level, the SR flip-flop T1 enters the set state, and the Q terminal of the SR flip-flop T1 outputs the reset inhibit signal Reset_forbid (high level). The logic converter L1 receives both the reset signal Ton_Reset and the reset inhibit signal Reset_forbid simultaneously. Therefore, the logic converter L1 remains in the boost state and continues to output the boost signal Ton.

[0073] At time t3, the first comparator U1 detects that the output voltage Vfb of the output circuit 200 is equal to the first reference voltage Vref. The first comparator U1 stops outputting the start signal Vcomp, and the AND gate Y1 outputs a low level. Meanwhile, the second comparator U2 detects that the output voltage Vfb of the output circuit 200 is less than the second reference voltage New_Vref. The second comparator U2 outputs a low level, and both the S and R terminals of the SR flip-flop T1 are low. The output state of the SR flip-flop T1 is maintained, that is, the Q terminal continues to output the reset disable signal Reset_forbid.

[0074] S203. The second comparator U2 controls the SR flip-flop T1 to enter the reset state according to the output voltage Vfb of the output circuit 200 and the preset second reference voltage New_Vref, so that the SR flip-flop T1 stops outputting the reset prohibition signal Reset_forbid to the logic converter L1, thereby making the reset signal Ton_Reset effective, and thus causing the logic converter L1 to end the boost state.

[0075] For example, at time t4, the second comparator U2 detects that the output voltage Vfb of the output circuit 200 is equal to the second reference voltage New_Vref. The second comparator U2 outputs a high level, the SR flip-flop T1 enters the set state, that is, the Q terminal outputs a low level, the reset prohibition signal Reset_forbid is canceled, the reset signal Ton_Reset takes effect in the logic converter L1, the logic converter L1 exits the boost state, stops outputting the boost signal Ton, and the output voltage Vfb of the output circuit 200 begins to decrease.

[0076] It should be noted that after the logic converter L1 exits the boost state, the control timing unit 13 resets the reset signal Ton_Reset.

[0077] The technical solution of this application enables a dynamic and longer boost signal Ton, allowing the output voltage Vfb of the output circuit 200 to rise rapidly until it exceeds the second reference voltage New_Vref, rather than extending the boost signal Ton by a fixed multiple of the period. This also suppresses overshoot. It achieves faster dynamic response and less overshoot based on the degree of load voltage change.

[0078] In another embodiment, please refer to Figure 4 , Figure 4 This is a circuit diagram of the second COT conversion circuit provided in the embodiments of this application. Figure 4 As shown, the switch control unit 15 includes: a logic converter L1, a higher-level power transistor Q, and a lower-level power transistor Q2. The first detection unit 11 includes: a first comparator U1. The second detection unit 12 includes: a second comparator U2. The reset control unit 14 includes: a first NOT gate F1, a second NOT gate F2, an AND gate Y1, and a selection switch S1. The first control terminal of the logic converter L1 is connected to the controlled terminal of the higher-level power transistor Q, and the second control terminal of the logic converter L1 is connected to the controlled terminal of the lower-level power transistor Q2. The positive input of the first comparator U1 is connected to a preset first reference voltage, and the negative input of the first comparator U1 is connected to the output voltage of the COT conversion circuit 100. The output terminal of the first comparator U1 is connected to the input terminals of the COT conversion circuit 100 and the timing unit 13, respectively. The controlled terminal of the timing unit 13 is connected to the second control terminal of the logic converter L1, and the output terminal of the timing unit 13 is connected to the first terminal of the selection switch S1. The second terminal of circuit 1 is grounded. The selection terminal of selector switch S1 is connected to the output terminal of AND gate Y1. The two input terminals of AND gate Y1 are connected to the output terminals of first NOT gate F1 and second NOT gate F2, respectively. The input terminal of first NOT gate F1 is connected to the output terminal of second comparator U2. The positive input terminal of second comparator U2 is connected to a preset second reference voltage, and the negative input terminal of second comparator U2 is connected to the output voltage of COT conversion circuit 100. The input terminal of second NOT gate F2 is connected to the second control terminal of logic converter L1. The selection terminal of selector switch S1 is also connected to logic converter L1. The specific steps of the control method for COT conversion circuit 100 include: S301-S302.

[0079] S301. When the first comparator U1 detects that the output voltage of the COT conversion circuit 100 is less than the preset first reference voltage, it sends start signals to the logic converter L1 and the timing unit 13 respectively to control the logic converter L1 to enter the boost state. The logic converter L1 sends a start signal to the upper power transistor Q so that the upper power transistor Q and the lower power transistor Q2 are turned on at the same time, thereby increasing the output voltage of the output circuit 200. The timing unit 13 is controlled to generate a reset signal when the timing duration reaches a fixed period.

[0080] S302. At the moment the reset signal is generated, the second comparator U2 controls the AND gate Y1 to open according to the output voltage of the output circuit 200 and the preset second reference voltage, so that the AND gate Y1 controls the selection switch S1 to input the reset signal to the logic converter L1, so that the reset signal takes effect, thereby causing the COT conversion circuit 100 to end the boost state.

[0081] In the above embodiment, the activation of the reset signal is controlled by a selection switch S1, which is controlled by the second reference voltage and the output voltage of the output circuit 200. Therefore, when the output voltage of the output circuit 200 equals the second reference voltage, the reset signal is activated, causing the logic converter L1 to stop outputting the start signal Ton at that moment.

[0082] In some embodiments, such as Figure 3 As shown, the timing unit 13 includes: a timing switch transistor Q3, a clock element Js1, a filter capacitor C1, and a third comparator U3. The second terminal of the clock element Js1 is connected to the first terminal of the timing switch transistor Q3, the first terminal of the filter capacitor C1, and the positive input of the third comparator U3. The second terminals of the timing switch transistor Q3 and the filter capacitor C1 are both grounded. The controlled terminal of the timing switch transistor Q3 is the controlled terminal of the timing unit 13. The negative input of the third comparator U3 is connected to a preset third reference voltage. The output terminal of the third comparator U3 is connected to the first terminal of the selection switch S1.

[0083] It should be noted that, as Figure 2 and Figure 4 The COT conversion circuit 100 shown has the same electronic components as the timing unit 13, the only difference being the controlled terminal of the timing switch Q3.

[0084] During normal operation, after the boost signal Ton is triggered, the clock device Js1 starts a countdown. After a certain period of time, its comparator output becomes 1. At this time, the output voltage Vfb of the output circuit is higher than the first reference voltage Vref, and the control signal DL of the lower power transistor Q2 is 0. The logic of the selection switch S1 is 1, the reset signal Ton_Reset is transmitted to the logic selection device L1, and the boost signal Ton is reset.

[0085] However, when the load current changes significantly, the output voltage Vfb of the output circuit drops below the first reference voltage Vref. At this time, the boost signal Ton still triggers normally, but the transmission of the reset signal Ton_Reset is restricted. After the boost signal Ton is triggered, the clock device Js1 counts down, and after a certain time, its comparator output becomes 1. However, because the output voltage Vfb of the output circuit is still lower than the first reference voltage Vref after being boosted by the boost signal Ton within a fixed cycle, the logic of the selection switch S1 is 10, the ground signal (0V) is transmitted to the logic selection device L1, and the boost signal Ton is not reset. Only when the output voltage Vfb of the output circuit is higher than the second reference voltage New_Vref, and the control signal DL of the lower-level power transistor Q2 is 0, the logic of the selection switch S1 is 1, the reset signal Ton_Reset is transmitted to the logic selection device L1, and the boost signal Ton is reset. This mechanism extends the boost signal Ton and, after the transient recovery, enters the next normal operating cycle.

[0086] Please refer to the technical effects of this application. Figure 5 , Figure 5 A schematic diagram of a COT conversion circuit provided in an embodiment of this application. Figure 5 As shown, under the same test requirements (Cout=330u, ESR=1m, ILoad switched from 10A to 50A), the transient response is improved when comparing the transient response with and without the fast response scheme (solid line represents the scheme with fast response, dashed line represents the scheme without fast response).

[0087] Please see Figure 6 , Figure 6 This document illustrates an operational flowchart of a control method for a COT conversion circuit provided in an embodiment of this application. Figure 6 As shown, the control method of this COT conversion circuit includes: S401-S416.

[0088] S401. Check if the load current change is normal. If yes, proceed to step S402; if no, proceed to step S406.

[0089] S402, the feedback voltage Vfb drops only slightly and does not fall below Vref.

[0090] S403: Ton is enabled, and the Ton_Reset countdown is in progress. After executing S402, if transient enhancement technology is not used, then S404 is executed; if transient enhancement technology is used, then S405 is executed.

[0091] S404, countdown ends, Ton resets normally, transient response is normal.

[0092] S405, the countdown ends, it is determined that Vfb is higher than Vref, Ton resets normally, and the transient response is normal.

[0093] S406, the feedback voltage Vfb drops significantly, falling below Vref.

[0094] S407: Ton is enabled, and the Ton_Reset countdown is waited for. After executing S407, if transient enhancement technology is not used, then S408, S409, S410, and S413 are executed; if transient enhancement technology is used, then S411, S412, and S413 are executed.

[0095] S408, Countdown ends, Ton is reset, waiting for Toff_min.

[0096] S409. Restart Ton and wait for the Ton_Reset countdown.

[0097] S410. If Vfb is still lower than Vref, repeat the first two steps.

[0098] S411, the countdown ends, it is determined that Vfb is higher than Vref, enter the Reset_forbid state, and Ton disables reset.

[0099] S412, Ton is extended until Vfb is greater than New_Vref, and the Reset_forbid state is lifted.

[0100] S413, Transient response returns to normal.

[0101] This application provides a COT conversion circuit, which is used to connect to a COT conversion circuit and to execute a control method for the COT conversion circuit as described in any of the embodiments of this application.

[0102] This application provides a chip that includes a COT conversion circuit as described in any one of the embodiments of this application.

[0103] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A control method for a COT conversion circuit, characterized in that, The COT conversion circuit is used to connect to the output circuit. The COT conversion circuit includes: a first detection unit, a second detection unit, a timing unit, a reset control unit, and a switch control unit. The first detection unit includes: a first comparator; the second detection unit includes: a second comparator; the reset control unit includes: an AND gate and an SR flip-flop; the switch control unit includes: a logic converter; the positive input of the first comparator is connected to a preset first reference voltage; the negative input of the first comparator is connected to the output voltage of the output circuit; the output of the first comparator is connected to the logic converter, the input of the timing unit, and the first input of the AND gate; the second input of the AND gate is connected to the output of the timing unit; the output of the AND gate is connected to the set input of the SR flip-flop; the reset input of the SR flip-flop is connected to the output of the second comparator; the positive input of the second comparator is connected to the output voltage of the output circuit; the negative input of the second comparator is connected to a preset second reference voltage; the output of the second comparator is connected to the logic converter; and the signal output of the logic converter is connected to the output circuit. The method includes: When the output voltage of the output circuit is detected to be less than the preset first reference voltage, the COT conversion circuit is controlled to enter the boost state, and the boost state is reset by a reset signal generated after a fixed period. At the moment the reset signal is generated, if it is detected that the output voltage of the output circuit is still less than the preset first reference voltage, the reset signal is invalidated so that the COT conversion circuit maintains the boosted state. The reset signal is activated when the output voltage of the output circuit is detected to be greater than the preset second reference voltage, so that the COT conversion circuit ends the boost state. The method specifically includes: When the first comparator detects that the output voltage of the output circuit is less than the preset first reference voltage, it sends start signals to the logic converter, the AND gate and the timing unit respectively, so as to control the logic converter to enter the boost state and send the boost signal to the output voltage, and control the timing unit to generate the reset signal when the timing duration reaches the fixed period. At the moment the reset signal is generated, the AND gate controls the SR flip-flop to enter the set state according to the start signal and the reset signal, so that the SR flip-flop outputs a reset inhibit signal to the logic converter, thereby disabling the reset signal and keeping the logic converter in the boost state. The second comparator controls the SR flip-flop to enter a reset state based on the output voltage of the output circuit and a preset second reference voltage, so that the SR flip-flop stops outputting a reset disable signal to the logic converter, thereby making the reset signal effective and causing the logic converter to end the boost state.

2. The control method for a COT conversion circuit as described in claim 1, characterized in that, At the time the reset signal is generated, if the output voltage of the COT conversion circuit is detected to be greater than the preset first reference voltage, the reset signal is activated, and the COT conversion circuit ends the boost state.

3. The control method for a COT conversion circuit as described in claim 1, characterized in that, The first detection unit is used to detect the magnitude relationship between the output voltage of the output circuit and a preset first reference voltage; The second detection unit is used to detect the magnitude relationship between the output voltage of the output circuit and the preset second reference voltage; The timing unit is used to generate the reset signal when the duration of the COT conversion circuit in the boost state reaches the fixed period; The reset control unit is used to determine whether the reset signal is invalid; The switch control unit is used to increase the output voltage of the output circuit when entering the boost state.

4. The control method for a COT conversion circuit as described in claim 3, characterized in that, The control of the COT conversion circuit to enter the boost state includes: The switch control unit sends a boost signal to the output circuit, thereby increasing the output voltage of the output circuit; or, Increase the output voltage of the switch control unit to increase the output voltage of the output circuit.

5. The control method for a COT conversion circuit as described in claim 3, characterized in that, The switch control unit includes a logic converter, a higher-level power transistor, and a lower-level power transistor. The first detection unit includes a first comparator, and the second detection unit includes a second comparator. The reset control unit includes a first NOT gate, a second NOT gate, an AND gate, and a selector switch. The first control terminal of the logic converter is connected to the controlled terminal of the higher-level power transistor, and the second control terminal of the logic converter is connected to the controlled terminal of the lower-level power transistor. The positive input of the first comparator is connected to a preset first reference voltage, and the negative input of the first comparator is connected to the output voltage of the COT conversion circuit. The output of the first comparator is connected to the COT conversion circuit and the input of the timing unit. The controlled terminal is connected to the second control terminal of the logic converter; the output terminal of the timing unit is connected to the first terminal of the selection switch; the second terminal of the selection switch is grounded; the selection terminal of the selection switch is connected to the output terminal of the AND gate; the two input terminals of the AND gate are respectively connected to the output terminals of the first NOT gate and the second NOT gate; the input terminal of the first NOT gate is connected to the output terminal of the second comparator; the positive input terminal of the second comparator is connected to a preset second reference voltage; the negative input terminal of the second comparator is connected to the output voltage of the COT conversion circuit; the input terminal of the second NOT gate is connected to the second control terminal of the logic converter; and the selection terminal of the selection switch is also connected to the logic converter. The method specifically includes: When the first comparator detects that the output voltage of the COT conversion circuit is less than the preset first reference voltage, it sends start signals to the logic converter and the timing unit respectively to control the logic converter to enter the boost state. The logic converter sends a start signal to the upper power transistor to make the upper power transistor and the lower power transistor turn on at the same time, thereby increasing the output voltage of the output circuit. The timing unit controls the timing unit to generate the reset signal when the timing duration reaches the fixed period. At the moment the reset signal is generated, the second comparator controls the AND gate to open based on the output voltage of the output circuit and the preset second reference voltage. The AND gate controls the selection switch to input the reset signal to the logic converter, making the reset signal effective and thus ending the boost state of the COT conversion circuit.

6. The control method for a COT conversion circuit as described in claim 5, characterized in that, The timing unit includes a timing switch transistor, a clock element, a filter capacitor, and a third comparator. The second terminal of the clock element is connected to the first terminal of the timing switch transistor, the first terminal of the filter capacitor, and the positive input of the third comparator. The second terminals of the timing switch transistor and the filter capacitor are both grounded. The controlled terminal of the timing switch transistor is the controlled terminal of the timing unit. The negative input of the third comparator is connected to a preset third reference voltage. The output terminal of the third comparator is connected to the first terminal of the selection switch.

7. A COT conversion circuit, characterized in that, The COT conversion circuit is used to connect to the COT conversion circuit, and the COT conversion circuit is used to execute the control method of the COT conversion circuit as described in any one of claims 1-6.

8. A chip, characterized in that, The chip includes the COT conversion circuit as described in claim 7.

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