Test data processing method and device, electronic equipment and storage medium

Abstract

The invention provides a test data processing method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining STDF (Standard Test Data Format) test data which at least comprises coordinates of a plurality of chips on a wafer and test values of each chip in a plurality of test items; according to the STDF test data and preset test item weight information, generating a test map of the wafer, the test map being used for indicating abnormal distribution characteristics of each chip on the wafer and test value deviation characteristics of the abnormal chip in each test item; according to the STDF test data and preset test item weight information, a root cause analysis report of the wafer is generated, and the root cause analysis report is used for indicating the test result of each chip on the wafer in each test item and the proportion of abnormal chips in each test item; and outputting a test map and a root cause analysis report, and improving the coupling sensitivity to abnormal test data through multi-modal statistics.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor testing, in particular to a test data processing method and device, an electronic device and a storage medium. BACKGROUND

[0002] In the field of semiconductor manufacturing and testing, yield management and defect diagnosis of integrated circuits are key links to ensure product quality and improve manufacturing efficiency. With the continuous miniaturization of integrated circuit technology and the increasing complexity of functions, the dimension and scale of test data are rapidly growing. In the wafer test and final test process, test equipment such as S100 test machines will generate a large amount of test data, which is stored in the standard test data format (STDF) and records the test results, test parameters, device information, test configuration, time stamp and other key information of the chip.

[0003] Currently, the analysis of STDF test data mainly relies on traditional single-mode statistical methods such as normal distribution statistics and 3σ principle. However, with the increase in the number of test items, single-mode statistical methods have the disadvantages of being insensitive to coupled anomalies, poor adaptability to non-normal distribution data, and lagging response to dynamic processes when facing high-dimensional STDF data, and have poor adaptability to high-dimensional, nonlinear and dynamically changing test data.

[0004] Therefore, the statistical analysis of integrated circuit test data in the prior art has certain limitations. SUMMARY

[0005] The present application aims to solve the problem of the limitations of the statistical analysis of integrated circuit test data in the prior art by providing a test data processing method and device, an electronic device and a storage medium.

[0006] To achieve the above-mentioned purpose, the technical solutions adopted by the embodiments of the present application are as follows:

[0007] In a first aspect, the embodiments of the present application provide a test data processing method, which comprises:

[0008] obtaining STDF test data, the STDF test data comprising at least the coordinates of a plurality of chips on a wafer and the test values of each chip in a plurality of test items;

[0009] generating a test map of the wafer according to the STDF test data and preset test item weight information, the test map being used to indicate the abnormal distribution characteristics of each chip on the wafer and the test value deviation characteristics of abnormal chips in each test item.

[0010] generate a root cause analysis report of the wafer according to the STDF test data and preset test item weight information, the root cause analysis report being used to indicate test results of each chip on the wafer in each test item and a proportion of abnormal chips in each test item;

[0011] output the test map and the root cause analysis report.

[0012] As an optional implementation manner, the generating the test map of the wafer according to the STDF test data and the preset test item weight information comprises:

[0013] determining interval color systems of each test item according to the test item weight information;

[0014] generating the test map of the wafer according to the STDF test data and the interval color systems of each test item.

[0015] As an optional implementation manner, the determining the interval color systems of each test item according to the test item weight information comprises:

[0016] allocating corresponding color systems to each test item according to the test item weight information;

[0017] determining first interval color systems, second interval color systems and third interval color systems of each test item according to the first test threshold value, the second test threshold value and the corresponding color system of each test item, wherein the second interval color systems of each test item are the same, and the second interval color systems are used to represent that a test value of a chip in a test item is qualified.

[0018] As an optional implementation manner, before the generating the test map of the wafer according to the STDF test data and the interval color systems of each test item, the method further comprises:

[0019] generating a spatial distribution map of the wafer according to coordinates of each chip on the wafer.

[0020] As an optional implementation manner, the generating the test map of the wafer according to the STDF test data and the interval color systems of each test item comprises:

[0021] determining whether a test value of each chip in each test item is qualified according to the STDF test data, the first test threshold value and the second test threshold value of each test item;

[0022] if yes, marking the chip on the spatial distribution map of the wafer by using the second interval color system;

[0023] Otherwise, the first interval color system or the third interval color system of the test item with the unqualified test value is used to mark the chip on the spatial distribution map of the wafer, and a test map of the wafer is generated.

[0024] As an optional implementation, the generating the root cause analysis report of the wafer according to the STDF test data and preset test item weight information comprises:

[0025] According to the test item weight information, a root cause analysis report template of the wafer is determined, and the order of arrangement of each test item in the root cause analysis report template of the wafer is the order of the weight of each test item.

[0026] According to the STDF test data, the first test threshold and the second test threshold of each test item, the test result of each chip in each test item is marked in the root cause analysis report template of the wafer, and the test result comprises being greater than the first test threshold or being less than the second test threshold.

[0027] According to the test result of each chip in each test item marked in the root cause analysis report template of the wafer, the proportion of abnormal chips in each test item is determined, and the proportion of abnormal chips in each test item is filled in the root cause analysis report template of the wafer, and the root cause analysis report of the wafer is generated.

[0028] As an optional implementation, the outputting the test map and the root cause analysis report comprises:

[0029] A test report containing the test map and the root cause analysis report is outputted.

[0030] In a second aspect, an embodiment of the present application provides a test data processing device, and the device comprises:

[0031] An acquisition module is configured to acquire STDF test data, wherein the STDF test data at least comprises coordinates of a plurality of chips on a wafer and test values of each chip in a plurality of test items;

[0032] A generation module is configured to generate a test map of the wafer according to the STDF test data and preset test item weight information, wherein the test map is used to indicate abnormal distribution characteristics of each chip on the wafer and test value deviation characteristics of abnormal chips in each test item.

[0033] The generation module is further configured to generate a root cause analysis report of the wafer according to the STDF test data and preset test item weight information, wherein the root cause analysis report is used to indicate test results of each chip in each test item on the wafer and a proportion of abnormal chips in each test item.

[0034] An output module is configured to output the test map and the root cause analysis report.

[0035] As an optional implementation, the generating module is specifically configured to:

[0036] According to the test item weight information, determine interval color systems of each test item;

[0037] According to the STDF test data and the interval color systems of each test item, generate a test map of the wafer.

[0038] As an optional implementation, the generating module is specifically configured to:

[0039] According to the test item weight information, assign a corresponding color system to each test item;

[0040] According to the first test threshold and the second test threshold of each test item and the color system corresponding to each test item, determine a first interval color system, a second interval color system and a third interval color system of each test item, wherein the second interval color systems of each test item are the same, and the second interval color system is used to represent that the test value of the chip at the test item is qualified.

[0041] As an optional implementation, the generating module is specifically configured to:

[0042] According to the coordinates of each chip on the wafer, generate a spatial distribution map of the wafer.

[0043] As an optional implementation, the generating module is specifically configured to:

[0044] According to the STDF test data, the first test threshold and the second test threshold of each test item, determine whether the test value of each chip at each test item is qualified;

[0045] If yes, mark the chip on the spatial distribution map of the wafer by using the second interval color system;

[0046] Otherwise, mark the chip on the spatial distribution map of the wafer by using the first interval color system or the third interval color system of the test item with unqualified test value, and generate a test map of the wafer.

[0047] As an optional implementation, the generating module is specifically configured to:

[0048] According to the test item weight information, determine a root cause analysis report template of the wafer, and the order of each test item in the root cause analysis report template of the wafer is the order of the weight of each test item;

[0049] According to the STDF test data, the first test threshold and the second test threshold of each test item, mark the test results of each chip in each test item in the root cause analysis report template of the wafer, and the test results include being greater than the first test threshold or less than the second test threshold;

[0050] According to the test results of each chip in each test item marked in the root cause analysis report template of the wafer, determine the proportion of abnormal chips in each test item, and fill the proportion of abnormal chips in each test item in the root cause analysis report template of the wafer to generate the root cause analysis report of the wafer.

[0051] As an optional implementation manner, the output module is specifically configured to:

[0052] Output a test report containing the test map and the root cause analysis report.

[0053] In a third aspect, an electronic device is provided, including a processor, a memory and a bus, the memory stores machine readable instructions executable by the processor, when the electronic device is running, the processor and the memory communicate through the bus, the processor executes the machine readable instructions, and the steps of the test data processing method in the first aspect are executed.

[0054] In a fourth aspect, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program, when the computer program is run by a processor, the steps of the test data processing method in the first aspect are executed.

[0055] The beneficial effects of the present application are:

[0056] This application provides a test data processing method, apparatus, electronic device, and storage medium. It acquires the coordinates of multiple chips on a wafer and the test values ​​of each chip in multiple test items from STDF test data. Based on the STDF test data and preset test item weight information, it generates a test map of the wafer to indicate the abnormal distribution characteristics of each chip on the wafer and the deviation characteristics of abnormal chips in each test item. Based on the STDF test data and preset test item weight information, it generates a root cause analysis report of the wafer to indicate the test results of each chip on the wafer in each test item and the proportion of abnormal chips in each test item. The test map and root cause analysis report are visualized to intuitively show the areas where abnormal chips are concentrated, the test items in which abnormal chips appear in clusters, and the deviation direction of the test values ​​of abnormal chips in each test item. The root cause analysis table provides a clear view of the test results for each chip in each test item, as well as the percentage of abnormal chips appearing in each test item. Combined with the test graph indicating the concentrated distribution areas of abnormal chips, the test items where they occur frequently, and the deviation direction of test values ​​for each item, the causes of anomalies can be further located and eliminated. Multimodal statistics, outputting test graphs and root cause analysis reports, improve the sensitivity to coupling abnormal test data and enhance the efficiency and accuracy of test data statistics. Attached Figure Description

[0057] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 A flowchart illustrating the test data processing method provided in the embodiments of this application. Figure One ;

[0059] Figure 2 This is a schematic diagram of the process trajectory of each test site provided in the embodiments of this application;

[0060] Figure 3 A flowchart illustrating the test data processing method provided in the embodiments of this application. Figure Two ;

[0061] Figure 4 A schematic diagram of the color scheme of each test item provided in the embodiments of this application;

[0062] Figure 5 A flowchart illustrating the test data processing method provided in the embodiments of this application. Figure Three ;

[0063] Figure 6 A spatial distribution map of a wafer provided by an embodiment of the present application

[0064] Figure 7 A flowchart of a test data processing method provided by an embodiment of the present application Figure Four ;

[0065] Figure 8 A test map of a wafer provided by an embodiment of the present application

[0066] Figure 9 A flowchart of a test data processing method provided by an embodiment of the present application Figure Five ;

[0067] Figure 10 A module structure diagram of a test data processing apparatus provided by an embodiment of the present application

[0068] Figure 11 A structural diagram of an electronic device provided by an embodiment of the present application DETAILED DESCRIPTION

[0069] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of description and illustration, and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn according to the actual proportions. The flowcharts in the present application show the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowcharts can not be implemented in sequence, and the steps without logical context relationship can be reversed in sequence or implemented simultaneously. In addition, one or more other operations can be added to the flowcharts or one or more operations can be removed from the flowcharts under the guidance of the content of the present application.

[0070] In addition, the described embodiments are only some of the embodiments of the present application, not all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0071] It should be noted that the term “comprising” will be used in the embodiments of the present application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0072] In the field of semiconductor manufacturing and testing, integrated circuits need to be tested for multiple tests to achieve yield management and defect diagnosis of integrated circuits. At present, STDF test data is analyzed by normal distribution statistics, 3σ principle and other single mode statistical methods. When facing high-dimensional STDF data, there are disadvantages of being insensitive to coupled abnormalities, poor adaptability to non-normal distribution data, and lag response to dynamic processes. The adaptability to high-dimensional, nonlinear and dynamic test data is poor. That is, the statistical analysis of integrated circuit test data in the prior art has certain limitations.

[0073] Based on the above problems, the embodiment of the present application provides a test data processing method, which improves the coupling sensitivity to abnormal test data through multi-modal statistics, wherein the test map of the wafer reflects the abnormal distribution characteristics of each chip on the wafer and the test value deviation characteristics of the abnormal chip in each test item. The root cause analysis report and test map of the wafer output by visualization can intuitively display the distribution of abnormal chips in the wafer and the abnormal reasons.

[0074] Figure 1 Process schematic of test data processing method provided by the embodiment of the present application Figure One The execution subject of the method can be any electronic device with computing processing capability. As shown in the figure, the method comprises the following steps. Figure 1

[0075] S101, acquiring STDF test data, the STDF test data at least comprising coordinates of a plurality of chips on a wafer and test values of each chip in a plurality of test items.

[0076] Optionally, in the test scene, a plurality of test stations (sites) are used to measure the chips on the wafer by the test machine table S100, Figure 2 The process trajectory of each test station provided by the embodiment of the present application is shown in the figure. The process trajectory of the site reflects the total chips measured by the site in the whole test process. Taking four sites as an example, the chips measured by each site in the test process are different, for example, Figure 2 The process trajectory of site1 comprises the first chip, the fifth chip, the ninth chip, etc., and the process trajectory of site2 comprises the second chip, the sixth chip, the tenth chip, etc. When a whole wafer test is completed, each site creates a process trajectory belonging to itself. The chips corresponding to the process trajectory form a group of process links, and the links of each site are completely different.

[0077] ​Each site records the coordinates of the measured chip on the wafer during the test process, and corresponds the coordinates of the chip on the wafer to the test values of the chip in multiple test items. For example, site 1 records the coordinates of the first chip on the wafer when measuring the first chip, and corresponds the test values of the first chip in multiple test items to the coordinates of the first chip on the wafer.

[0078] The STDF test data output by the test machine S100 after completing the test on each chip on the wafer is obtained, wherein the STDF test data at least includes the coordinates of the multiple chips on the wafer and the test values of each chip in multiple test items. The STDF test data can also include test configuration, test timestamp and other test information.

[0079] S102, according to the STDF test data and the preset test item weight information, a test map of the wafer is generated, and the test map is used to indicate the abnormal distribution characteristics of each chip on the wafer and the test value deviation characteristics of the abnormal chip in each test item.

[0080] Optionally, the STDF test data is parsed to obtain the coordinates of each chip on the wafer and the test values of each chip in multiple test items corresponding to the coordinates of each chip on the wafer. For example, the test items can be divided into electrical characteristic parameter test and functional test, wherein the electrical characteristic parameter test mainly tests whether the basic physical properties of the chip are normal, for example, through open / short test to detect the physical connection integrity inside the chip or between pins, through static power current test and leakage current test to measure the static current characteristics of the chip, through power voltage test and threshold voltage test to measure the direct current voltage characteristics of the chip. The functional test mainly tests whether the logic function of the chip can be realized, for example, tests the instruction execution capability of the chip.

[0081] According to the influence degree of each test item on the performance of the chip, the test item weight information is preset, wherein the priority of each test item in the electrical characteristic parameter test is higher than that in the functional test. In this way, the priority is divided, and the chip can be tested first to see if it can work normally, and then the functional logic of the chip can be tested to see if it can be realized normally. If the working voltage of the chip exceeds the design range, or the static power consumption is abnormal, the chip will be physically failed, at this time, no matter how perfect the functional design is, it cannot be realized normally; on the contrary, if the electrical parameters are normal, such as voltage, current and timing are within the standard range, the functional test has meaning. Through the preset test item weight information, abnormal chips that cannot work physically can be excluded first, so as to avoid meaningless functional test on such chips and improve the test efficiency.

[0082] Taking ten test items T1 to T10 as an example, T1 is an open circuit test, T2 is a short circuit test, T8 is a leakage current test, and the other test items are functional tests. The weights of T1 to T10 are ranked from high to low as T1>T2>T8>T3>T4>T5>T6>T7>T9>T10.

[0083] According to the test values of each chip in the STDF test data in multiple test items, an abnormal chip is detected, and a deviation direction of the test value of the abnormal chip in the corresponding test item is determined. According to the deviation direction of the test value of the abnormal chip in the corresponding test item, the preset test item weight information, and the coordinates of each chip on the wafer in the STDF test data, a test map of the wafer is drawn by different colors, so as to indicate the abnormal distribution characteristics of each chip on the wafer and the test value deviation characteristics of the abnormal chip in each test item through the test map.

[0084] S103, generating a root cause analysis report of the wafer according to the STDF test data and the preset test item weight information, the root cause analysis report being used to indicate the test results of each chip on the wafer in each test item and the proportion of abnormal chips in each test item.

[0085] Optionally, according to the test values of each chip in multiple test items in the STDF test data, the test results of each chip in each test item are counted, including test pass, test fail and deviation direction of test fail in each test item.

[0086] According to the test results of each chip in each test item, the proportion of abnormal chips in each test item is counted. For example, for the ten test items T1 to T10, the ratio of the number of abnormal chips appearing in the 10 test items to the total number of abnormal chips is calculated, and the proportion of abnormal chips in each test item is obtained. For example, the total number of abnormal chips is 210, and the number of abnormal chips in T1 test item is 53, so the proportion of abnormal chips in T1 test item is the ratio of 53 to 210, that is, 25.2%.

[0087] According to the test results of each chip in each test item, the proportion of abnormal chips in each test item, and the preset test item weight information, a root cause analysis report of the wafer is generated, so as to directly display whether each chip is qualified in each test item and the deviation direction when unqualified through the root cause analysis report of the wafer, and the test items with higher weights are sorted in the front row of the root cause analysis report, so as to preferentially display the test results of each test item in the electrical characteristic parameter test of the chip.

[0088] S104, outputting the test map and the root cause analysis report.

[0089] Optionally, the test map and the root cause analysis table of the output wafer are output, wherein by outputting the test map, the abnormal distribution characteristics of each chip on the wafer and the test value deviation characteristics of the abnormal chip in each test item are visually displayed, so that the user can intuitively see from the test map that the abnormal chip is concentrated in which area of the wafer, the abnormal chip is abnormal in which test item, and the test value deviation direction in each test item, and then analyze the reason why the abnormal chip is concentrated in a certain area or abnormal in a certain test item.

[0090] By outputting the root cause analysis table, the test results of each chip in each test item and the proportion of abnormal chips in each test item are visually displayed, so that the user can directly see from the root cause analysis table the details of whether each chip passes each test item, and see the proportion of abnormal chips in each test item. Combined with the test map, the abnormal reason such as process deviation can be further located, and the abnormality can be eliminated.

[0091] For example, the proportion of abnormal chips in T1, T2 and T8 test items is 25.2%, 37.6% and 18.6% respectively, indicating that the proportion of abnormal chips in the electrical characteristic parameter test is relatively large. Combined with the test map of the wafer, it can be located that the overall process level in the corresponding area is poor or a device failure occurs. By improving the process level or repairing the device failure, the test yield of the chips in the wafer can be improved.

[0092] In the embodiment, the coordinates of the plurality of chips on the wafer and the test values of each chip in the plurality of test items in the STDF test data are obtained, and according to the STDF test data and the preset test item weight information, a test map of the wafer is generated to indicate the abnormal distribution characteristics of each chip on the wafer and the test value deviation characteristics of the abnormal chip in each test item. According to the STDF test data and the preset test item weight information, a root cause analysis report of the wafer is generated to indicate the test results of each chip in each test item and the proportion of abnormal chips in each test item. The test map and the root cause analysis report are visually output, so that the area where the abnormal chips are concentrated, the test item where the abnormal chips are concentrated, and the test value deviation direction of each test item of the abnormal chips can be intuitively seen from the test map. The test results of each chip in each test item and the proportion of abnormal chips in each test item can be directly seen from the root cause analysis table. Combined with the area where the abnormal chips are concentrated, the test item where the abnormal chips are concentrated, and the test value deviation direction of each test item indicated by the test map, the abnormal reason can be further located, and the abnormality can be eliminated. By multi-modal statistics, the test map and the root cause analysis report are output, which improves the coupling sensitivity of the abnormal test data and improves the test data statistical efficiency and accuracy.

[0093] Figure 3 Flowchart of the test data processing method provided by the embodiment of the present applicationFigure Two As shown in Figure 3 The step S102 of generating the test map of the wafer according to the STDF test data and the preset test item weight information includes the following steps.

[0094] S201, determine the interval color system of each test item according to the test item weight information.

[0095] Optionally, the test item weight information reflects the influence degree of different test items on the quality of the chip, wherein the higher the weight of the test item is, the greater the contribution of the abnormality of the test item to the chip failure is. When determining the interval color system, differentiated interval color system allocation can be performed based on the test item weight information. Each test item is allocated with three interval color systems to indicate the deviation direction of the test value of the chip in this test item through the three interval color systems.

[0096] Figure 4 The interval color system of each test item provided by the embodiments of the present application is shown in the following table. Figure 4 According to the test item weight T1>T2>T8>T3>T4>T5>T6>T7>T9>T10, three interval color systems are allocated to the ten test items T1 to T10.

[0097] S202, generate the test map of the wafer according to the STDF test data and the interval color system of each test item.

[0098] Optionally, according to the test values of each chip in multiple test items in the STDF test data, the interval color system of each test item is matched, and according to the coordinates of each chip on the wafer in the STDF test data, the position of each chip is marked with the interval color system of each test item to generate the test map of the wafer.

[0099] The test map of the wafer binds the test result of the chip with the physical position of the chip on the wafer, and in combination with the interval division of the color system, the spatial distribution characteristics of the abnormal chip can be directly observed, and the deviation direction of the test value of the abnormal chip can be distinguished according to the interval color system, i.e. whether the test value of the abnormal chip in the test item is too high or too low.

[0100] In the embodiments, differentiated interval color system allocation is performed on each test item according to the test item weight information to determine the interval color system of each test item. According to the test values of each chip in multiple test items in the STDF test data, the interval color system of each test item is matched, and according to the coordinates of each chip on the wafer in the STDF test data, the position of each chip is marked with the interval color system of each test item to generate the test map of the wafer. The test map of the wafer binds the test result of the chip with the physical position of the chip on the wafer, and in combination with the interval division of the color system, the spatial distribution characteristics of the abnormal chip can be directly observed, and the deviation direction of the test value of the abnormal chip can be distinguished according to the interval color system.

[0101] Figure 5 A flowchart illustrating the test data processing method provided in the embodiments of this application. Figure Three ,like Figure 4 As shown, in step S201 above, the range color system for each test item is determined based on the test item weight information, including:

[0102] S301. Assign a corresponding color scheme to each test item based on the test item weight information.

[0103] Optionally, based on the test item weight information, different color schemes are assigned to each test item so as to intuitively reflect the differences in importance of each test item through the difference in the color schemes with different levels of prominence. The higher the weight of the test item, the higher the prominence of the corresponding color scheme assigned to the test item.

[0104] Continue to refer to Figure 4 The ten test items T1-T10 are each assigned a color scheme with different levels of visibility according to their respective weights. For example, if the weights of test items T1, T2, and T8 are higher, then test items T1, T2, and T8 are assigned red, orange, and yellow color schemes with higher visibility, respectively.

[0105] S302. Based on the first test threshold, the second test threshold, and the color system corresponding to each test item, determine the first interval color system, the second interval color system, and the third interval color system for each test item. The second interval color system is the same for all test items. The second interval color system is used to characterize the chip's test value in the test item as qualified.

[0106] Optionally, each test item has two preset test thresholds. The first test threshold can be the upper specification limit (USL) of the test value within the test pass range, and the second test threshold can be the lower specification limit (LSL) of the test value within the test pass range.

[0107] Based on the first test threshold, the second test threshold, and the color system corresponding to each test item, determine the first color system in each test item that is higher than the first test threshold (i.e., higher than USL), the second color system that is between the first test threshold and the second test threshold (i.e., between USL and LSL), and the third color system that is lower than the second test threshold (i.e., lower than LSL).

[0108] Among them, the first and third color intervals of the same test item can be different shades of the same color system. Figure 4 For example, the first color interval of the T8 test item is dark yellow, and the third color interval is light yellow; the first color interval of the T1 test item is bright red, and the third color interval is dark red.

[0109] The second color scheme of each test item is the same, with Figure 4 For example, the second interval color scheme for each test item is green, indicating that the chip's test value for that test item is within the acceptable range, that is, between the first test threshold and the second test threshold, neither higher than USL nor lower than LSL. This is used to indicate that the chip's test value for that test item is acceptable, that is, the test result is PASS.

[0110] The second interval for each test item uses the same color scheme, ensuring that qualified chips form a unified visual identity across all test item graphs. Regardless of the type or weight of the test item, qualified chips can be quickly identified solely by the uniform green color scheme of the second interval.

[0111] In this embodiment, based on the test item weight information, different color schemes with varying degrees of prominence are assigned to each test item to visually reflect the differences in importance of each test item through the distinction of color schemes. According to the first test threshold, the second test threshold, and the corresponding color scheme for each test item, a first color scheme interval higher than the first test threshold, a second color scheme interval between the first and second test thresholds, and a third color scheme interval lower than the second test threshold are determined for each test item. The second color scheme intervals for all test items are the same, ensuring that qualified chips form a unified visual identifier across all test item graphs. This improves the visual recognition efficiency of qualified chips and facilitates the rapid differentiation of abnormal chips where test values ​​are too low (unqualified) or too high (unqualified) in each test item.

[0112] As an optional implementation, before generating the wafer test pattern based on the STDF test data and the color range of each test item in step S202 above, the following steps are included:

[0113] A spatial distribution map of the wafer is generated based on the coordinates of each chip on the wafer.

[0114] Optionally, the X and Y coordinates of each chip on the wafer can represent the row and column numbers of the chip on the wafer, respectively. Based on the X and Y coordinates of each chip on the wafer, the physical location of each chip on the wafer can be determined.

[0115] Based on the actual physical shape of the wafer, the XY coordinates of each chip are mapped proportionally onto a two-dimensional plane to form a chip location grid. Each grid point corresponds to the physical location of a chip, and the relative position of the grid is consistent with the chip distribution on the actual wafer, thus obtaining a spatial distribution map of the wafer.

[0116] Figure 6 The spatial distribution diagram of the wafer provided in the embodiments of this application is as follows: Figure 6 As shown, each grid in the spatial distribution diagram of the wafer corresponds one-to-one with each chip on the wafer.

[0117] In this embodiment, the physical positions of the chips on the wafer are determined based on the coordinates of the chips on the wafer. The coordinates of the chips on the wafer are mapped to a two-dimensional plane in proportion to the actual physical form of the wafer, to form a chip position grid, each grid point corresponding to the physical position of a chip, and the relative positions of the grid are consistent with the distribution of the chips on the actual wafer, to obtain a spatial distribution map of the wafer. Each grid in the spatial distribution map of the wafer corresponds to each chip on the wafer, which facilitates subsequent labeling of each chip with a color on the spatial distribution map of the wafer, and finally generates a test map of the wafer.

[0118] Figure 7 Flowchart of the test data processing method provided by the embodiments of the present application Figure Four As shown in Figure 7 According to the STDF test data and the interval color system of each test item, the test map of the wafer is generated in step S202, which includes:

[0119] S401, according to the STDF test data, the first test threshold and the second test threshold of each test item, determine whether the test value of each chip at each test item is qualified.

[0120] Optionally, the test value of each chip at each test item in the STDF test data is compared with the first test threshold and the second test threshold of each test item, and whether the test value of each chip at each test item is qualified is determined according to the comparison result.

[0121] Taking T1 test item as an example, if the test value of the chip with wafer coordinates (9, 1) at T1 test item is higher than the first test threshold, i.e. higher than USL, it is determined that the test value of the chip with wafer coordinates (9, 1) at T1 test item is unqualified. At this time, the test of the abnormal chip with wafer coordinates (9, 1) is terminated at T1 test item, and there is no need to perform T2-T10 test items on the chip.

[0122] If the test value of the chip with wafer coordinates (2, 2) at T1 test item is between the first test threshold and the second test threshold, i.e. between USL and LSL, it is determined that the test value of the chip with wafer coordinates (2, 2) at T1 test item is qualified. Continue to perform T2-T10 test items on the chip with wafer coordinates (2, 2), until the chip is detected to be unqualified at a certain test item or all tests are qualified, and the test of the chip is terminated.

[0123] For example, if a chip with wafer coordinates (24,2) passes tests T1, T2, T8, and T3, but its test value in test T4 is below the second test threshold, then the chip with wafer coordinates (24,2) is determined to be unqualified in test T4. In this case, testing for the abnormal chip with wafer coordinates (24,2) terminates at test T4, and there is no need to perform tests T5, T6, T7, T9, and T10 on this chip.

[0124] S402. If so, the second color scheme is used to mark the chips on the wafer spatial distribution map.

[0125] Optionally, if it is determined that the chip passes all test values ​​in each test item, the chip is marked on the wafer spatial distribution map using the second color scheme. For example, the corresponding grid of the chip on the wafer spatial distribution map is marked in green, indicating that the chip passes all test values ​​in all test items.

[0126] For example, if the chip with wafer coordinates (1,1) passes all test values ​​in test items T1 to T10, the grid in the first row and first column of the wafer spatial distribution map is marked in green, indicating that the chip corresponding to that position has passed all test items.

[0127] S403. Otherwise, use the first or third color interval of the test item with the unqualified test value to mark the chip on the spatial distribution map of the wafer, and generate the test map of the wafer.

[0128] Optionally, if it is determined that the chip fails the test value of a certain test item, the chip is marked on the spatial distribution map of the wafer according to the offset direction of the chip's test value in that test item, using the first or third interval color system of the test item with the failed test value. After marking all the chips on the wafer in sequence, the test map of the wafer is generated.

[0129] For example, if the chip with wafer coordinates (24,2) has a test value in the T4 test item that is lower than the second test threshold of the T4 test item, then the grid in the 24th row and 2nd column of the wafer spatial distribution map will be marked using the third interval color system of the T4 test item.

[0130] Figure 8 The test pattern of the wafer provided in the embodiments of this application, such as Figure 8 As shown, the states of each chip in the wafer, including excessively high, qualified, and excessively low test values ​​for each test item, are marked in different colors on the test spectrum. Figure 8 The measurement results showed that the defective chips were concentrated in the three test items T1, T2 and T8, and the abnormal chips were relatively densely distributed in the upper left corner of the wafer.

[0131] In the embodiment, the test values of each chip in each test item in the STDF test data are compared with the first test threshold and the second test threshold of each test item respectively, and whether the test values of each chip in each test item are qualified is determined according to the comparison result. If it is determined that the test values of the chip in each test item are qualified, the second interval color system is used to mark the chip on the spatial distribution map of the wafer. If it is determined that the test value of the chip in a certain test item is unqualified, the first interval color system or the third interval color system of the test item with unqualified test value is used to mark the chip on the spatial distribution map of the wafer according to the test value deviation direction of the chip in the test item, and after all the chips on the wafer are marked in turn, the test map of the wafer is generated. The test results of the chip in each test item are bound with the spatial position of the chip on the wafer, and the test map of the wafer is generated by multi-modal statistics, so that the regional distribution of abnormal chips and the test value deviation direction can be directly observed.

[0132] Figure 9 Flowchart of the test data processing method provided by the embodiment Figure Five As shown in Figure 9 The root cause analysis report of the wafer is generated according to the STDF test data and the preset test item weight information in step S103, including:

[0133] S501, according to the test item weight information, determine the root cause analysis report template of the wafer, the order of each test item in the root cause analysis report template of the wafer is the order of the weight of each test item.

[0134] Optionally, according to the test item weight information, the weight order of each test item is determined, the order of each test item is determined according to the weight order of each test item, and the root cause analysis report template of the wafer is matched according to the order of each test item, so that the order of each test item in the root cause analysis report template of the wafer is consistent with the weight order of each test item.

[0135] If the test item weight order is T1>T2>T8>T3>T4>T5>T6>T7>T9>T10, the root cause analysis report template of the wafer is matched based on this order, so that the order of T1-T10 in the root cause analysis report template of the wafer is also T1, T2, T8, T3, T4, T5, T6, T7, T9, T10.

[0136] S502, according to the STDF test data, the first test threshold and the second test threshold of each test item, mark the test results of each chip in each test item in the root cause analysis report template of the wafer, and the test results include greater than the first test threshold or less than the second test threshold.

[0137] Optionally, the XY coordinates of each chip on the wafer in the STDF test data are filled into the wafer root cause analysis report template row by row, and the test values of each chip in each test item in the STDF test data are compared with the first test threshold and the second test threshold of each test item respectively to determine the test results of each chip in each test item. The test result of a chip in a test item includes that the test value of the chip in the test item is greater than the first test threshold, less than the second test threshold, or between the first test threshold and the second test threshold.

[0138] According to the XY coordinates of each chip on the wafer, the test results of each chip in each test item are filled in the table corresponding to the chip, the test item, and the deviation direction of the test value. Wherein, the test result of the chip in the test item is qualified when the test value of the chip in the test item is between the first test threshold and the second test threshold, and no mark is needed in the wafer root cause analysis report template.

[0139] For example, the test value of the chip with wafer coordinates (9, 1) in the T1 test item is higher than the first test threshold, i.e. higher than the USL, so a mark, such as ×, is marked in the table corresponding to the USL column of the T1 test item and the row corresponding to the wafer coordinates (9, 1), indicating that the test value of the chip with wafer coordinates (9, 1) in the T1 test item is higher than the USL.

[0140] S503, according to the test results of each chip in each test item marked in the wafer root cause analysis report template, determine the proportion of abnormal chips in each test item, and fill the proportion of abnormal chips in each test item in the wafer root cause analysis report template to generate the wafer root cause analysis report.

[0141] Optionally, according to the test results of each chip in each test item marked in the wafer root cause analysis report template, calculate the proportion of abnormal chips in each test item, and fill the proportion of abnormal chips in each test item in the last row of the wafer root cause analysis report template to generate the wafer root cause analysis report.

[0142] The wafer root cause analysis report generated indicates the XY coordinates of the chip, the deviation direction of the test of the chip in each test item, the test station to which the chip belongs, and whether the chip is PASS. For example, when the test values of the chip in each test item are all qualified, the PASS position of the chip is marked as √, indicating that the chip passes all test items. If the test value of the chip in any test item is unqualified, the PASS position of the chip is left blank, indicating that the chip does not pass all test items.

[0143] Table 1

[0144]

[0145] Table 1 is a root cause analysis report of the wafer provided by the embodiment of the present application. As shown in Table 1, the root cause analysis report of the wafer indicates the test results of each chip in the T1-T10 test items and the specific deviation direction of the test values. For example, the chip with wafer coordinates (1, 1) belongs to the test site site1, and the test values in the T1-T10 test items are all within the qualified range, and the PASS position is marked with √. The root cause analysis report of the wafer also marks the test value of the chip with wafer coordinates (9, 1) in the T1 test item is higher than the USL of the T1 test item, the test site is site1, and the PASS position is left blank. The root cause analysis report of the wafer also marks the test value of the chip with wafer coordinates (7, 4) in the T8 test item is higher than the USL of the T8 test item, the test site is site2, and the PASS position is left blank. The root cause analysis report of the wafer also marks the test value of the chip with wafer coordinates (4, 7) in the T2 test item is higher than the USL of the T2 test item, the test site is site3, and the PASS position is left blank. The root cause analysis report of the wafer also marks the test value of the chip with wafer coordinates (4, 1) in the T8 test item is lower than the LSL of the T8 test item, the test site is site4, and the PASS position is left blank.

[0146] The root cause analysis report of the wafer indicates the proportion of abnormal chips in each test item. For example, the proportion of abnormal chips in the T1 test item is 25.2%, the proportion of abnormal chips in the T2 test item is 37.6%, and the proportion of abnormal chips in the T8 test item is 18.6%. It can be seen that the proportion of abnormal chips in the electrical characteristic parameter test is large.

[0147] In the embodiment, according to the test item weight information, the root cause analysis report template of the wafer is determined, so that the order of arrangement of each test item in the determined root cause analysis report template of the wafer is consistent with the order of the weight of each test item. According to the STDF test data, the first test threshold and the second test threshold of each test item, the test result of each chip in each test item is marked in the root cause analysis report template of the wafer as being greater than the first test threshold or being less than the second test threshold, and the proportion of abnormal chips in each test item is determined according to the test result of each chip in each test item marked in the root cause analysis report template of the wafer. The proportion of abnormal chips in each test item is filled in the root cause analysis report template of the wafer to generate the root cause analysis report of the wafer. In order to visually see the test result of each chip in each test item, the deviation direction of the test value, and the proportion of abnormal chips appearing in each test item based on the root cause analysis report of the wafer.

[0148] As an optional implementation, the outputting of the test map and the root cause analysis report in the step S104 includes:

[0149] The test report includes a test map and a root cause analysis report.

[0150] Optionally, the test map of the wafer and the root cause analysis table are integrated into a test report of the wafer, the test report can further include a model of the wafer and the like, and the test report of the wafer is visually output.

[0151] The test map of the wafer is generated by mapping each test item to a corresponding color system according to the weight of each test item, comparing the test value of each chip in each test item with the USL and LSL of each test item, and marking the color of each chip on the spatial distribution map of the wafer according to the comparison result.

[0152] The root cause analysis table of the wafer is a structured table sorted according to the weight of each test item, and includes the XY coordinates of the chip on the wafer, the test item name, the test value deviation direction abnormal type (higher than the USL or lower than the LSL), the proportion of the abnormal chip in each test item, the qualified flag and the like, and quantitatively analyzes the test result of each chip in each test item.

[0153] In the embodiment, the test map of the wafer and the root cause analysis table are integrated into a test report of the wafer, and the test report of the wafer is visually output, so that the abnormal distribution of each chip on the wafer, the test value deviation direction of the abnormal chip in each test item and the test result of each chip in each test item can be directly observed based on the test map and the root cause analysis table of the wafer in the test report.

[0154] Based on the same inventive concept, the embodiments of the present application also provide a test data processing device corresponding to the test data processing method. Since the principle of solving problems of the device in the embodiments of the present application is similar to the test data processing method described above, the implementation of the device can be referred to the implementation of the method, and the repeated parts will not be described here.

[0155] Figure 10 The module structure diagram of the test data processing device provided in the embodiments of the present application is shown in Figure 10 The device includes:

[0156] The acquisition module 1001 is configured to acquire STDF test data, and the STDF test data at least includes the coordinates of a plurality of chips on a wafer and the test values of each chip in a plurality of test items.

[0157] The generation module 1002 is configured to generate a test map of the wafer according to the STDF test data and preset test item weight information, and the test map is used to indicate the abnormal distribution characteristics of each chip on the wafer and the test value deviation characteristics of the abnormal chip in each test item.

[0158] The generating module 1002 is further configured to generate a root cause analysis report of the wafer according to the STDF test data and preset test item weight information, and the root cause analysis report is used to indicate test results of each chip on the wafer in each test item and a proportion of abnormal chips in each test item.

[0159] The output module 1003 is configured to output the test map and the root cause analysis report.

[0160] As an optional implementation, the generating module 1002 is specifically configured to:

[0161] According to the test item weight information, interval color systems of each test item are determined.

[0162] According to the STDF test data and the interval color systems of each test item, a test map of the wafer is generated.

[0163] As an optional implementation, the generating module 1002 is specifically configured to:

[0164] According to the test item weight information, a corresponding color system is assigned to each test item.

[0165] According to the first test threshold, the second test threshold and the corresponding color system of each test item, a first interval color system, a second interval color system and a third interval color system of each test item are determined, wherein the second interval color systems of each test item are the same, and the second interval color system is used to represent that a test value of a chip in a test item is qualified.

[0166] As an optional implementation, the generating module 1002 is specifically configured to:

[0167] According to coordinates of each chip on the wafer, a spatial distribution map of the wafer is generated.

[0168] As an optional implementation, the generating module 1002 is specifically configured to:

[0169] According to the STDF test data, the first test threshold and the second test threshold of each test item, whether a test value of each chip in each test item is qualified is determined.

[0170] If yes, the second interval color system is used to mark the chip on the spatial distribution map of the wafer.

[0171] Otherwise, the first interval color system or the third interval color system of the test item with an unqualified test value is used to mark the chip on the spatial distribution map of the wafer, and a test map of the wafer is generated.

[0172] As an optional implementation, the generating module 1002 is specifically configured to:

[0173] Based on the test item weight information, the root cause analysis report template for the wafer is determined. The order of the test items in the root cause analysis report template is based on the order of their weights.

[0174] Based on the STDF test data, the first test threshold and the second test threshold for each test item, mark the test results of each chip in each test item in the wafer root cause analysis report template. The test results include those greater than the first test threshold or less than the second test threshold.

[0175] Based on the test results of each chip marked in the wafer root cause analysis report template for each test item, determine the percentage of abnormal chips in each test item, and fill the percentage of abnormal chips in each test item into the wafer root cause analysis report template to generate the wafer root cause analysis report.

[0176] As an optional implementation, the output module 1003 is specifically used for:

[0177] The output includes a test report containing test graphs and root cause analysis reports.

[0178] This application also provides an electronic device, such as... Figure 11 The diagram shown is a schematic representation of the structure of an electronic device provided in an embodiment of this application, including: a processor 111, a memory 112, and a bus 113. The memory 112 stores machine-readable instructions executable by the processor 111 (e.g., ...). Figure 10 The device in the embodiment acquires the execution instructions corresponding to the module 1001, the generation module 1002, and the output module 1003. When the electronic device is running, the processor 111 and the memory 112 communicate through the bus 113. When the machine-readable instructions are executed by the processor 111, the steps of the test data processing method in the above embodiment are executed.

[0179] This application also provides a computer-readable storage medium storing a computer program, which, when run by a processor, executes the steps of the test data processing method described above.

[0180] Those skilled in the art can clearly understand the specific working process of the system and the device described above for the convenience and brevity of description, which can refer to the corresponding process in the method embodiment, and will not be repeated in the present application. In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented by other ways. The device embodiments described above are only schematic, for example, the division of the modules is only a logical function division, and the actual implementation can have another division, for example, a plurality of modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed each other can be indirect coupling or communication connection through some communication interface, device or module, which can be electrical, mechanical or other forms.

[0181] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. When the functions are realized in the form of software functional units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or say the parts that make contributions to the prior art or parts of the technical solutions can be embodied in the form of software products, which are stored in a storage medium and include a plurality of instructions for making a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in each embodiment of the present application. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and various program code storage media.

[0182] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application.

Claims

1. A test data processing method, characterized by, The method comprises the following steps: acquiring standard test data format (STDF) test data, the STDF test data comprising at least coordinates of a plurality of chips on a wafer and test values of each chip on a plurality of test items; generating a test map of the wafer according to the STDF test data and preset test item weight information, the test map being used to indicate abnormal distribution characteristics of each chip on the wafer and test value deviation characteristics of abnormal chips on each test item; generating a root cause analysis report of the wafer according to the STDF test data and the preset test item weight information, the root cause analysis report being used to indicate test results of each chip on each test item on the wafer and an abnormal chip proportion in each test item; outputting the test map and the root cause analysis report.

2. The method of claim 1, wherein, The step of generating the test map of the wafer according to the STDF test data and the preset test item weight information comprises the following steps: determining interval color systems of each test item according to the test item weight information; generating the test map of the wafer according to the STDF test data and the interval color systems of each test item.

3. The method of claim 2, wherein, The step of determining the interval color systems of each test item according to the test item weight information comprises the following steps: allocating corresponding color systems to each test item according to the test item weight information; determining first interval color systems, second interval color systems and third interval color systems of each test item according to first test thresholds, second test thresholds of each test item and the corresponding color systems of each test item, wherein the second interval color systems of each test item are the same, and the second interval color systems are used to represent test values of chips on test items being qualified.

4. The method of claim 1, wherein, Before the step of generating the test map of the wafer according to the STDF test data and the interval color systems of each test item, the method further comprises the following step: generating a spatial distribution map of the wafer according to the coordinates of each chip on the wafer.

5. The method of claim 3, wherein, The step of generating the test map of the wafer according to the STDF test data and the interval color systems of each test item comprises the following steps: determining whether test values of each chip on each test item are qualified according to the STDF test data, the first test thresholds and the second test thresholds of each test item; if yes, marking the chip on the spatial distribution map of the wafer by using the second interval color system; otherwise, marking the chip on the spatial distribution map of the wafer by using the first interval color system or the third interval color system of the test item with unqualified test values, and generating the test map of the wafer.

6. The method of claim 1, wherein, The step of generating the root cause analysis report of the wafer according to the STDF test data and the preset test item weight information comprises the following steps: determining a root cause analysis report template of the wafer according to the test item weight information, wherein the order of each test item in the root cause analysis report template of the wafer is the order of the weight of each test item; marking test results of each chip on each test item in the root cause analysis report template of the wafer according to the STDF test data, the first test thresholds and the second test thresholds of each test item, wherein the test results comprise values greater than the first test thresholds or values smaller than the second test thresholds. According to the test results of each chip marked in the wafer root cause analysis report template in each test item, the proportion of abnormal chips in each test item is determined, and the proportion of abnormal chips in each test item is filled in the wafer root cause analysis report template to generate the wafer root cause analysis report.

7. The method of claim 1, wherein, The output of the test map and the root cause analysis report includes: Output a test report containing the test map and the root cause analysis report.

8. A test data processing apparatus, characterized by, The device includes: An acquisition module is configured to acquire standard test data format (STDF) test data, the STDF test data including at least coordinates of a plurality of chips on a wafer and test values of each chip in a plurality of test items; A generation module is configured to generate a test map of the wafer according to the STDF test data and preset test item weight information, the test map being used to indicate abnormal distribution characteristics of each chip on the wafer and test value deviation characteristics of abnormal chips in each test item; The generation module is further configured to generate a root cause analysis report of the wafer according to the STDF test data and preset test item weight information, the root cause analysis report being used to indicate test results of each chip on the wafer in each test item and a proportion of abnormal chips in each test item; An output module is configured to output the test map and the root cause analysis report.

9. An electronic device, comprising: It includes: A processor, a memory and a bus, the memory storing machine readable instructions executable by the processor, when the electronic device is running, the processor and the memory communicate through the bus, the processor executes the machine readable instructions, and the steps of the test data processing method in any one of claims 1 to 7 are executed.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to execute the steps of the test data processing method in any one of claims 1 to 7.

Images