Exposure method and system and semiconductor device

Abstract

The invention provides an exposure method and system and a semiconductor device, and relates to the technical field of semiconductors. Aiming at the crystal face height difference between the edge area and the central area of the wafer, when the second exposure process for eliminating the bridging defect is executed, the wafer is divided into a plurality of exposure blocks, and the appropriate exposure parameters of each exposure block are determined based on the first exposure process before the second exposure process is executed; therefore, the corresponding second exposure process can be carried out on the exposure blocks with different crystal face heights, so that the situation that the overall exposure parameters are difficult to adapt to the areas with different crystal face heights when the second exposure process is carried out on the whole wafer (especially the edge areas with lower heights) is avoided. Besides, when the exposure parameters are determined, the influence of different exposure parameters on the correction of the critical dimension under the crystal face height when the first exposure process parameter is fixed is determined through a simulation algorithm, so that the appropriate exposure parameters under each crystal face height are determined, and the accuracy of the critical dimension of the semiconductor device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to an exposure method, system and semiconductor device. BACKGROUND

[0002] The exposure process of photoresist is particularly important in the semiconductor manufacturing process. Specifically, when forming a specific semiconductor structure, the wafer can be coated with photoresist and then the local photoresist can be modified through the exposure process, so as to realize the patterning of the photoresist, and then the specific semiconductor structure can be prepared based on the patterned photoresist layer.

[0003] With the complication of semiconductor device structure, some structures (such as pixel layer of image sensor) often need to be coated with thick photoresist for preparation. In the exposure process of thick photoresist, only one exposure can only shape the bottom critical dimension, and form a bridging defect in the upper part of the photoresist. Therefore, how to optimize the exposure process and eliminate the bridging defect is a technical problem to be solved by those skilled in the art. SUMMARY

[0004] Therefore, the embodiments of the present application provide an exposure method, system and semiconductor device, which adopts two exposure processes for thick photoresist, and eliminates the bridging defect in the photoresist through the subsequently executed second exposure process, so as to improve the accuracy of the formed semiconductor structure.

[0005] In a first aspect, the present application provides an exposure method applied to a photoresist exposure system, the exposure method comprising: in response to a target wafer coated with photoresist being placed on a workpiece table, determining the crystal surface height of each exposure block of the target wafer; determining a first target exposure parameter of a first exposure process, wherein the exposure depth range of the focusing position in the first target exposure parameter covers the interface between the photoresist and the target wafer; determining a first correlation between the different crystal surface heights and the critical dimension deviation of the target wafer after executing the first exposure process; performing a second exposure simulation for the target exposure block based on the target crystal surface height after executing the first exposure process, and determining a second correlation between the second exposure parameter and the critical dimension compensation under the target crystal surface height, wherein the second exposure parameter at least includes the focusing position; based on the first correlation and the second correlation, determining a second target exposure parameter for eliminating the target crystal surface height, so as to determine the second target exposure parameter of each exposure block; executing the first exposure process based on the first target exposure parameter, and then executing the second exposure process for each exposure block based on the second target exposure parameter of each exposure block.

[0006] In a second aspect, the present application provides a photoresist exposure system, comprising: an exposure device configured to release an exposure beam; a workpiece table configured to carry a wafer; and a controller communicatively connected to the exposure device and the workpiece table, and configured to control the exposure device and the workpiece table based on the exposure method of the first aspect.

[0007] In a third aspect, the present application provides a semiconductor device, which is prepared based on the exposure method of the first aspect.

[0008] The exposure method, system and semiconductor device provided by the present application are capable of solving the problem of the difficulty of the exposure parameter of the whole wafer in adapting to the different crystal surface height regions (especially the edge region with lower height) when the second exposure process is performed to eliminate the bridging defects, by dividing the wafer into a plurality of exposure blocks when the second exposure process is performed to eliminate the bridging defects, and determining the appropriate exposure parameter of each exposure block based on the first exposure process performed before the second exposure process, so that the corresponding second exposure process can be performed on the exposure blocks with different crystal surface heights. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0010] Figure 1 is a structural schematic diagram of a photoresist exposure system provided by some embodiments of the present application.

[0011] Figure 2 is a schematic diagram of the crystal surface height distribution of a wafer provided by some embodiments of the present application.

[0012] Figure 3 is an exemplary flowchart of an exposure method provided by some embodiments of the present application.

[0013] Figure 4 is a fitting schematic diagram of a first correlation provided by some embodiments of the present application.

[0014] Figure 5 is a fitting schematic diagram of a second correlation provided by some embodiments of the present application.

[0015] Figure 6 is an exemplary flowchart of a second exposure process execution procedure provided by some embodiments of the present application.

[0016] Figure 7 is an exemplary flowchart of a second exposure parameter determination procedure provided by some embodiments of the present application.

[0017] Figure 8 is an exemplary flowchart of a second exposure parameter determination procedure provided by some embodiments of the present application. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0019] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concept of the present application, and therefore, in the diagrams, only the components related to the present application are shown, rather than the number, shape and size of the components when actually implemented. The shape, number and proportion of the components when actually implemented can be arbitrarily changed, and the layout form of the components can also be more complex.

[0020] In the present application, it should be noted that, if terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like appear, the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, if the terms "first" and "second" appear, they are only for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0021] SUMMARY To further illustrate the exposure process of the photoresist, the present application also provides a structural schematic diagram of a photoresist exposure system (100). Figure 1 ).

[0022] As shown in Figure 1 , the photoresist exposure system 100 of the wafer can include an exposure device 110 and a workpiece table 120. The exposure device 110 is used to release an exposure beam, which generally has an optical system 111, a mask system 112 and an auxiliary system (not shown in the figure).

[0023] The optical system 111 can be configured to generate an exposure beam, which can include a light source generating device (e.g., a laser) for generating the exposure beam and an optical projection device (typically a combination of optical elements) for spatially modulating the exposure beam. The mask system 112 is disposed between the optical system 111 and the worktable along the propagation direction of the exposure beam, and is configured to load and control a mask 220 for performing the exposure process. The mask 220 can selectively transmit the exposure beam, so that a pattern on the mask 220 can be transferred to a photoresist layer on the wafer 210. The auxiliary system can include other devices related to the exposure process. For example, an alignment system can be included for aligning the mask 220 with an existing pattern on the wafer 210.

[0024] The worktable 120 can be configured to support the wafer 210 to be exposed. The worktable 120 often has spatial movement capability to focus the exposure beam on the photoresist layer on the wafer 210 to perform the exposure of the photoresist layer. That is, when the wafer is placed on the worktable 120, the exposure device 110 can load the corresponding mask 220 and perform alignment, and after alignment, the exposure beam can be generated to perform the corresponding exposure process on the wafer 210 on the worktable 120.

[0025] Based on the modulation of the optical system 111, the exposure beam has a certain exposure depth of focus range (DOF) based on its focus position. The exposure depth of focus range refers to the defocus range that can maintain the clarity and quality of the image. It is generally symmetrically distributed along the longitudinal direction (i.e., the photoresist stacking direction) with the focus position as the center of symmetry. For example, if the exposure depth of focus range is 0.4 μm, it can be understood that within the range of ±0.2 μm from the focus position, the image on the photoresist formed based on the exposure process can continuously maintain clarity (i.e., meet the requirements of pattern resolution and topography).

[0026] In performing the exposure process, to shape the critical dimension of the bottom, the exposure process will preferentially focus near the interface between the photoresist and the substrate, so that the exposure focus range covers the interface. By precisely controlling the exposure dose, the photoresist bottom can obtain sufficient photochemical reaction, so that a clear and dimensionally accurate bottom pattern can be obtained after development, to ensure the stability of the semiconductor structure formed in subsequent preparation processes.

[0027] However, in the fabrication of some semiconductor devices, thicker photoresists are often required to create microstructures with high aspect ratios (for example, the fabrication of shallow trench isolation structures of 2500 Å in image sensors requires thicker photoresists). With thicker photoresists, prioritizing the shaping of the bottom critical dimension (CD) may result in the upper portion of the photoresist being outside the aforementioned depth of focus, leading to defocus defects. This can result in insufficient exposure of this portion of the photoresist, creating bridge defects.

[0028] To eliminate the aforementioned issues, compensatory exposure can be performed after the bottom critical dimensions have been shaped, based on the defects that have formed. This is achieved by supplementing the exposure of the upper portion of the photoresist, which is prone to bridging defects, to eliminate these defects. Therefore, to distinguish between the two types of exposure, the exposure process used to shape the bottom critical dimensions can be referred to as the first exposure process, and the exposure process used to eliminate bridging defects can be referred to as the second exposure process.

[0029] This application further discovers that before the exposure process, the wafer often exhibits significant differences in crystal plane height due to other processes. In particular, processes such as edge washing often result in a significant difference between the crystal plane height at the wafer edge and that at the wafer center.

[0030] To further illustrate this point, this application provides a schematic diagram of the crystal plane height distribution of a CMOS image sensor (CIS) wafer as an example. Figure 2 ).

[0031] exist Figure 2 In the height distribution diagram shown, a circular border represents a wafer, and the rectangular array on it reflects the various partitions. Wafer surface height can be represented by grayscale, where black indicates a higher crystal plane height, and white indicates a lower crystal plane height. Based on... Figure 2 It can be observed that the crystal plane height is higher in the central part of the wafer, while the crystal plane height is lower in the edge region of the wafer.

[0032] Specifically, in the fabrication process of CMOS image sensors (CIS), the height difference between the crystal planes on the wafer surface can reach 0.3 μm. This is generally not something that can be optimized through process optimization.

[0033] Based on the difference in the aforementioned crystal surface height, the first exposure process can be configured based on the crystal surface height, so as to cover the interface between the photoresist and the wafer as a whole. Based on the difference in the aforementioned crystal surface height, after the aforementioned first exposure process is performed, the different focusing depths of the first exposure process relative to the photoresist often lead to different critical dimension deviations of different crystal surface heights (for example, the critical dimensions at the surface of the photoresist away from the wafer are different). Even if the second lithography process is used for compensation, the second lithography process performed globally cannot adapt to the different critical dimension deviations caused by different crystal surface heights, and thus the photoresist after the compensation of the second lithography process (especially the part with a lower crystal surface height) still has defocus defects, which may further cause the continued existence of bridging defects.

[0034] To solve the aforementioned technical problem, the present application adjusts the execution method of the second exposure process and improves the parameter determination logic of the second parameter exposure process. For the difference in the crystal surface height of the wafer edge region and the center region, the present application divides the wafer into multiple exposure blocks when performing the second exposure process for eliminating the bridging defects, and determines the appropriate exposure parameters of each exposure block based on the first exposure process before the second exposure process is performed, so that the corresponding second exposure process can be performed in the exposure blocks with different crystal surface heights, to avoid the case that the overall exposure parameters of the wafer cannot adapt to the regions with different crystal surface heights (especially the edge regions with a lower height) when the second exposure process is performed on the wafer as a whole. In addition, when the exposure parameters are determined, the present application determines the influence of different exposure parameters on the critical dimension correction under the fixed first exposure process parameters through a simulation algorithm, so as to determine the appropriate exposure parameters under each crystal surface height, and improve the accuracy of the critical dimension of the semiconductor device.

[0035] The following will be described in detail Figures 3-8 The exposure method provided by the present application will be described in detail.

[0036] Exemplary exposure method: To further illustrate the exposure method provided by the present application, the present application also provides an exemplary flowchart of an exposure method (P300) Figure 3 ). Among them, Figure 3 The exposure method P300 shown in the figure can be executed by the controller in the aforementioned exposure system 100. Among them, the controller of the exposure system 100 can be in communication connection with the exposure device and the workpiece table and control the exposure device and the workpiece table based on the exposure method P300 provided by the present application.

[0037] As Figure 3 shown, P300 can include the following steps: S310, in response to the target wafer coated with photoresist being placed on the workpiece table, determining the crystal surface height of each exposure block of the target wafer.

[0038] S320, determine a first target exposure parameter of the first exposure process.

[0039] S330, determine a first correlation between different facet heights and critical dimension deviations in the target wafer after performing the first exposure process.

[0040] S340, perform a second exposure simulation for a target exposure block based on a target facet height after performing the first exposure process, to determine a second correlation between the second exposure parameter and the critical dimension compensation under the target facet height.

[0041] S350, based on the first correlation and the second correlation, determine a second target exposure parameter for eliminating the critical dimension deviation of the target facet height, to determine the second target exposure parameter of each exposure block.

[0042] S360, perform the first exposure process based on the first target exposure parameter, and then perform the second exposure process for each exposure block based on the second target exposure parameter of each exposure block.

[0043] In the foregoing S310, the target wafer can refer to the wafer currently undergoing the exposure process. That is, after the wafer is coated with photoresist, it can be placed on the workbench for subsequent exposure process, so as to realize pattern transfer from the mask to the photoresist.

[0044] The subsequent steps of the present application depend on the movement ability of the workbench, optimize the execution process of the second exposure process, and gradually expose each region of the target wafer in a partitioned form. Among them, the wafer region that can be exposed by the second exposure process at a time can be referred to as an exposure block. That is, the exposure block can be a virtual region defined on the wafer, which can reflect an exposure region of the exposure process when exposing in a partitioned form. Among them, the exposure block can be planned based on a preset rule. For example, the exposure block can be a plurality of rectangular regions as shown in the figure. Figure 2

[0045] The facet height can refer to the height of the wafer surface (i.e. the interface with the photoresist). It can be characterized as a relative height. For example, the plane height of the wafer surface can be determined, and the actual height of each position can be characterized as a value relative to the average height, and the sign of the value can represent high or low relative to the average height. In addition, other values (such as the lowest value or the highest value) can also be selected as the height reference.

[0046] In actual execution, the foregoing S310 can be determined by the related detection equipment of the exposure system. That is, the exposure system often has related sensors, which can measure the vertical height (Z direction) and inclination angle of each position on the wafer surface after the wafer is placed on the workbench, so as to ensure that the exposure block is always within the focal depth range of the projection objective. The test results can be visualized as Figure 2 ​The image shown. That is, in actual execution, the foregoing S310 can be placed on the workbench after the target wafer, by the sensor in the exposure device to determine the exposure of each block of the crystal surface height.

[0047] In the foregoing S320, as described above, the first exposure process is used to shape the photoresist bottom. Then the exposure depth range based on the focus position in the first target exposure parameter includes the interface between the photoresist and the target interface, so as to shape the critical dimension at the interface.

[0048] Considering that the present application does not make additional adjustments to the first exposure process under normal circumstances, the corresponding first target exposure parameter can be determined based on the traditional algorithm (such as Focus-Energy Matrix (FEM) analysis). Wherein, FEM is a key experimental method for determining the lithography process window, by systematically changing the focus and exposure energy parameters, the influence on the pattern line width (critical dimension) is evaluated, so as to optimize the exposure condition. Considering that the first exposure process is a relatively mature exposure process, its FEM analysis can be based on historical data to determine the optimal exposure parameter as the first target exposure parameter. Its specific determination process can refer to the related description of FEM.

[0049] Further, considering that in the actual device production process, the same process of semiconductor devices is often batch prepared. That is, the wafers in the same batch often have similar specifications. Only the crystal surface height and its distribution on each wafer are different. Then the foregoing first target exposure parameter can be determined based on the current matching wafer data. That is, the foregoing S320 can determine the wafer topography data of the wafer batch in which the target wafer is prepared when executed. Then the first target exposure parameter of the first exposure process is determined based on the wafer topography data through the Focus-Energy Matrix data analysis.

[0050] In some embodiments, considering that if you want to execute the first exposure process globally, you often need to meet the requirement that the crystal surface height range of the target wafer is less than the exposure focal depth range, at which time the first target exposure parameter of the first exposure process for simultaneously processing each exposure block can be determined based on the wafer data through the Focus-Energy Matrix data analysis. When the crystal surface height range is greater than or equal to the exposure focal depth range, the first exposure process can be executed in zones, so that the crystal surface height range in each zone is less than the exposure focal depth range. That is, the crystal surface height range of the target wafer can be determined first. Then in response to the crystal surface height range being greater than or equal to the exposure focal depth range, a plurality of first exposure regions are demarcated based on the crystal surface height of the target wafer, and the first target exposure parameter of each first exposure region is determined based on the wafer data through the Focus-Energy Matrix data analysis. Wherein, the first exposure region includes a plurality of exposure blocks with a crystal surface height range less than the exposure focal depth range.

[0051] Considering that there is also historical data for the second exposure process, the exposure parameters thereof can also be determined according to the foregoing process to obtain a candidate value. However, considering that the relationship between the parameters in the second exposure process and the CD will be determined based on the simulation process later to determine the appropriate process parameters, the process parameters of the first exposure process can be determined in S320 only.

[0052] In the foregoing S330, the first correlation relationship can refer to the relationship between the height of different crystal surfaces and the CD deviation after the first exposure process is performed. Considering that the first exposure process is used to shape the bottom CD, the region where the CD deviation exists is often in the middle and upper sections of the photoresist. Therefore, when the first correlation relationship is characterized, the CD deviation of one or more special points can be selected for description, or the CD deviation of each position can be described.

[0053] In particular, considering that the CD difference far from the surface of the bottom is often the largest when the bottom CD is formed, the foregoing key position deviation can be the CD deviation of the surface of the photoresist. Exemplarily, after the first exposure process is performed on the exposure block with a crystal surface height of 200 nm, the CD of the bottom edge can be simulated to be 163 nm, the CD of the middle region can be 232 nm, and the CD of the top region (i.e., the surface of the photoresist) can be 272 nm, and the CD deviation of the rest of the bottom CD is the largest.

[0054] In some embodiments, considering that the foregoing S320 can be determined based on historical data, the foregoing S330 can also be determined based on historical process data. That is, the first correlation relationship between the height of the crystal surface and the CD deviation of the photoresist after the first exposure process is performed can be determined based on the historical process data. In some embodiments, the first correlation relationship can also be further fitted with the height of the crystal surface and the CD deviation, so as to be characterized as a fitted relationship (such as a linear relationship) between the CD deviation and the height of the crystal surface.

[0055] In some embodiments, the foregoing CD deviation can reflect the influence of the height of the crystal surface on the CD when it is specifically characterized, that is, it can be characterized as the difference between the CD and the bottom CD, or it can be directly characterized by the CD value.

[0056] In some embodiments, in addition to the method of determining the first correlation relationship based on historical process data, considering that the second correlation relationship needs to be determined in the simulation environment later, the first correlation relationship can also be determined in the simulation environment. That is, the target wafer is loaded into the simulation environment and simulated based on the first exposure process, the CD deviation of the first exposure process after the height of different crystal surfaces is determined, so as to form the first correlation relationship.

[0057] In actual implementation, the two determination methods can be executed independently or fused with each other. For example, the first correlation can be determined by the historical process data, and the first correlation of the crystal surface height not covered by the historical process data can be determined by the simulation / fitting function.

[0058] In some embodiments, the positions corresponding to the aforementioned critical dimension deviations are mainly used to perform the second exposure process. If the critical dimension deviation compensation of each position cannot be completed by one second exposure process, the compensatory exposure can be performed multiple times. That is, the second exposure process can include at least one compensatory exposure process. The related configuration process of the at least one compensatory exposure process can be referred to Figure 7 、 8 and the related description thereof.

[0059] In the aforementioned S340, the second correlation can reflect the corresponding relationship between different second exposure parameters and critical dimension compensation at a specific crystal surface height.

[0060] The critical dimension compensation in the second correlation corresponds to the critical dimension deviation in the aforementioned first correlation, and both reflect the critical dimension of the same position. To correspond to the critical dimension deviation in the first correlation, when the critical dimension deviation in the first correlation is represented by a critical dimension value, the critical dimension compensation in the second correlation can be represented by the maximum critical dimension that can be corrected for the bottom critical dimension. When the critical dimension deviation in the first correlation is represented by the deviation of the critical dimension value relative to the bottom critical dimension, the critical dimension compensation in the second correlation can be represented by the deviation of the maximum critical dimension that can be corrected relative to the bottom critical dimension.

[0061] In actual implementation of the aforementioned S340, simulation can be performed based on each crystal surface height included in the target wafer, and each simulation is performed only for one crystal surface height. During the simulation, the first exposure process is performed based on the aforementioned first target exposure parameter to determine the corresponding relationship between different exposure parameters of the second exposure process and the critical dimension compensation (i.e., the second correlation). Similar to the aforementioned first correlation, the second correlation can also be fitted with the exposure parameter and the critical dimension compensation to determine the fitting relationship therebetween.

[0062] In the aforementioned S350, the second target exposure parameter can refer to a second exposure process execution parameter that can eliminate the critical size deviation formed after performing the first exposure process. Specifically, it can be determined based on the combined first and second correlation relationships. That is, for a crystal plane height, its corresponding critical size deviation can be determined from the first correlation relationship, and then the exposure parameter that can correct the critical size deviation (the critical size deviation is generally the same as the critical size compensation) can be determined based on the second correlation relationship of the crystal plane height, and used as the aforementioned second target exposure parameter. Thus, based on this process, the second target exposure parameter corresponding to each crystal plane height can be determined.

[0063] In some embodiments, considering that the aforementioned first correlation relationship and the second correlation relationship can be linearly fitted, the aforementioned S350 can also directly combine the two fitting relationships to directly parse the second target exposure parameters at each crystal plane height.

[0064] For example, assuming the exposure parameters only involve the focus position, the fitting relationship between the crystal plane height Z and the critical size deviation X can be Z = AX + B. At a specific crystal plane height z', the fitting relationship between the second exposure parameter P (e.g., exposure focal length) and the critical size compensation X' can be P = CX' + D. When the critical size deviation X and the critical size compensation X' adopt interchangeable correspondences, the two fitting relationships can be combined to obtain the second target exposure parameter P' = (C / A) * (z' - B) + D at a specific crystal plane height z'. Here, A, B, C, and D are constants determined based on testing and fitting.

[0065] To further illustrate this process, this application also provides a schematic diagram of fitting the first correlation relationship ( Figure 4 ) and a schematic diagram of the second correlation fitting at a specific crystal plane height (200nm) ( Figure 5 ).

[0066] exist Figure 4 In this model, the horizontal axis represents the critical dimension value of the wafer (typically in nm), and the vertical axis represents the crystal plane height (typically in nm). Based on different crystal plane heights, corresponding critical dimension values ​​can be collected as critical dimension deviations. Based on the collected data, a first correlation can be fitted. For example... Figure 4 As shown, the data generally exhibits linear regression, and the first correlation fitted based on this data is: Z = -4.0422X + 1337.7.

[0067] and Figure 4 resemblance, Figure 5 The horizontal axis can be the critical dimension value of the wafer (usually in nm), and the vertical axis can be the focus position of the second exposure process (usually in μm). Figure 5The shown data can be simulation data at a crystal height of 200 nm, which also presents a linear relationship. The second correlation relationship fitted based on the data is: P=-0.0025X-0.7741.

[0068] By combining the above two equations, the focus position of the second exposure process at a crystal height of 200 nm is-1.47774. That is, using the aforementioned focus position as the second target exposure parameter can eliminate the critical dimension deviation of the 200 nm crystal height.

[0069] In summary, when the second exposure parameter is mainly represented by the focus position, the target wafer after the first exposure process can be loaded in the simulation environment when the aforementioned S340 is executed. Then, different exposure focus positions are used to execute the second exposure simulation for the exposure blocks of the target crystal height, and the critical dimension compensation of different exposure focus positions is determined to construct the second correlation relationship of the target crystal height. When the aforementioned S350 is executed, the target critical dimension deviation of the target crystal height can be determined based on the first correlation relationship. The target focus position corresponding to the target critical dimension compensation matching the target critical dimension deviation in the second correlation relationship is determined as the second target exposure parameter.

[0070] Therefore, based on the aforementioned determined second target exposure parameter and the first target exposure parameter, the corresponding exposure process can be executed to execute the aforementioned S360.

[0071] When the aforementioned S360 is specifically executed, the first exposure process is generally a global process for the target wafer. That is, when the first exposure process is executed, the target wafer can be directly placed at a specific position in the exposure system according to the requirements of the first target exposure parameter, and the exposure device is controlled to perform exposure at the focus position and the focus energy specified by the first target exposure parameter to implement the first exposure process.

[0072] Considering that the present application configures different second target exposure parameters for each exposure block with different crystal heights, when the second exposure process is executed, each exposure block can be placed in the working range, and then the corresponding second target exposure parameter is called based on the crystal height of the exposure block located in the working range, and the exposure system is configured based on the second target exposure parameter to implement the second exposure process for the exposure block.

[0073] In some embodiments, the present application can control the exposure process through the workbench. That is, by controlling the position of the workbench in the longitudinal direction (in the same direction as the crystal height), the adjustment of the focus position can be realized, and then the aforementioned second exposure process can be executed.

[0074] Therefore, based on the aforementioned exposure method, in view of the difference in crystal plane height between the edge region and the center region of the wafer, the present application divides the wafer into multiple exposure blocks when performing the second exposure process for eliminating bridging defects, and determines appropriate exposure parameters for each exposure block based on the first exposure process performed before the second exposure process, so that the corresponding second exposure process can be performed on the exposure blocks with different crystal plane heights, thereby avoiding the case that the overall exposure parameters are difficult to adapt to the regions with different crystal plane heights (especially the edge region with lower height) when the second exposure process is performed on the whole wafer. In addition, when determining the exposure parameters, the present application determines the appropriate exposure parameters for each crystal plane height by simulating the influence of different exposure parameters on the critical dimension correction under the condition that the first exposure process parameters are fixed, thereby improving the accuracy of the critical dimension of the semiconductor device.

[0075] Exemplary process of the second exposure process: Based on the foregoing, in the second exposure process of the present application, the exposure blocks are often loaded into the working range of the exposure device by moving the plane of the workbench so that the exposure device can expose the exposure region. That is, for the exposure region (denoted as the target exposure region) that has been loaded into the working range, when the second exposure process is performed, the workpiece table can be controlled to move longitudinally in response to the workpiece table loading the target exposure block into the working range, so that the exposure beam of the exposure device is focused on the target focus position in the photoresist. Then the exposure device is controlled to perform the second exposure process.

[0076] In this process, considering that the crystal plane height distribution is often discrete, sequentially loading each exposure block into the working range may cause the workbench to move frequently. Therefore, the present application can plan each exposure block for performing the second exposure process, so that multiple exposure blocks with the same focus position are continuously loaded in a group, thereby reducing the longitudinal movement of the workbench.

[0077] To further illustrate the process, some embodiments of the present application also provide an exemplary flowchart of the second exposure process execution process (P600) Figure 6 ).

[0078] As shown in Figure 6 , the second exposure process execution process P600 can include the following steps: S610, dividing multiple second exposure regions based on the target focus positions of each exposure block.

[0079] S620, for a target second exposure region in the multiple second exposure regions, controlling the workpiece table to sequentially load each exposure block of the target second exposure region into the working range.

[0080] S630, performing the second exposure process based on the second target exposure parameters of the exposure blocks in the working range.

[0081] The second exposure area is similar to the first exposure area in that both are determined based on the crystal face height. Specifically, the second exposure area is a region formed by the exposure blocks having the same target focus position.

[0082] As described above, the focus position in the second target focus parameter generally corresponds to the crystal face height. The same crystal face height has the same focus position. Therefore, the second exposure area can be determined based on the crystal face height of each exposure area.

[0083] In the S620, one second exposure area can be understood as one continuous second exposure process, and the exposure parameter is fixed in this process. In actual implementation, the S620 can form a plane movement path based on the distribution of each exposure block in the second exposure area, so as to sequentially load each exposure area in the second exposure area into the working range based on the movement path.

[0084] As another implementation, when loading the exposure block, the exposure device can be controlled based on the block traversal control strategy and the enablement control of the exposure device, so that the exposure device performs work only when the exposure block in one second exposure area is loaded into the working range. At this time, although the exposure block outside the second exposure area is also loaded into the working range, the exposure device does not work when the exposure block is loaded into the working range. Therefore, the foregoing process can also be equivalent to sequentially loading each exposure block into the working range. Further, considering that the crystal face height is often distributed radially, the exposure block can be loaded in a circle-by-circle manner when traversing each exposure area.

[0085] In the S630, the focus position (i.e., the height of the worktable) of each second exposure area is maintained to be the same, so as to achieve exposure of each exposure block in the second exposure area. For details, refer to the foregoing description.

[0086] Therefore, based on the second exposure process execution flow, the exposure block with the same crystal face height can be continuously loaded to maintain the longitudinal height (focus position) of the worktable, reduce the change of the longitudinal height, and further reduce the fluctuation caused by the change of the longitudinal height, thereby improving the process stability.

[0087] Exemplary multi-round compensation exposure As described above, the actual role of the second exposure process is to perform compensatory exposure in the defocused area of the first exposure process. The number of exposure processes in the actual execution of the second exposure process can not be limited. That is, if the current compensatory exposure cannot eliminate the bridging defects caused by defocusing, one more exposure can be performed until the exposure is completed.

[0088] For the second exposure process performed multiple times as mentioned above, the exposure parameters can be determined in an overall planning, or based on the "performed" exposure process to determine the next compensation exposure process until the entire photoresist compensation exposure is completed.

[0089] For the foregoing case, the present application provides two methods for determining the second target exposure parameters based on multiple rounds of compensation exposure processes Figure 7 、 Figure 8 . The following will be described in turn.

[0090] As shown in Figure 7 , the flow P700 can include the following steps: S:710, determining at least one compensation exposure process in the second exposure process and its corresponding compensation position based on the first target exposure parameters and the exposure depth of focus range.

[0091] S720, for a target compensation exposure process in the at least one compensation exposure process, determining a first correlation between the critical dimension deviation of the target wafer different crystal surface height and the target compensation position after performing the first exposure process and the historical compensation exposure process, wherein the target compensation position corresponds to the target compensation exposure process, and the historical compensation exposure process is each compensation exposure process whose compensation position is below the target compensation position; S730, performing target compensation exposure process simulation for the target exposure block based on the target wafer surface height after performing the first exposure process and the historical compensation exposure process, and determining a second correlation between the second exposure parameters and the critical dimension compensation at the target compensation position under the target wafer surface height.

[0092] S740, based on the first correlation and the second correlation, determining the second target exposure parameters of the target compensation exposure process corresponding to the critical dimension deviation of the target compensation position of the target wafer surface height to determine the second target exposure parameters of the target compensation exposure process of each exposure block, and further determine the second target exposure parameters of each compensation exposure process in the second exposure process.

[0093] In the foregoing S710, the second exposure process can be composed of at least one compensation exposure process to eliminate the defocus defect of the first target exposure process. Then when determining the number and position of the compensation exposure process to be adopted, all the compensation exposure processes can be determined directly, or an iterative algorithm can be used to calculate the compensation exposure process. The specific content of the iterative calculation can be referred to in Figure 8 and its related description, which will be described here with the example of determining all the compensation exposure processes.

[0094] When performing the aforementioned S710, the approximate exposure range of each exposure process in the photoresist can be planned based on the exposure depth range of each exposure process, thereby ensuring that the overall depth of the photoresist has good critical dimensions. Generally, the planning can be based on the depth of the area to be compensated in the photoresist during the first exposure process and the depth range that a single compensation exposure process can compensate for, thereby determining the number of compensation exposure processes and the range that each compensation exposure process needs to compensate for.

[0095] The aforementioned S720-S740 can be described as a process for determining the second target exposure parameter of the target compensation exposure process in at least one compensation exposure process. The target compensation exposure process can be the compensation exposure process currently performing exposure parameter calculations. Considering that the exposure process in this application is executed from bottom to top, the target exposure process can also be selected from bottom to top. That is, the target exposure process can be the compensation exposure process that has not yet performed parameter calculations and is closest to the focus position of the first exposure process.

[0096] In the specific calculation process, the compensated exposure process with calculated parameters (referred to as the historical compensated exposure process) can be processed in a similar way to the first exposure process. That is, in the simulation environment, the critical dimension compensation after executing both the first exposure process and the historical compensated exposure process can be simulated to determine the specific exposure parameters of the target compensated exposure process. The specific execution process involves treating the historical compensated exposure process as part of the first exposure process, and using the parameter determination method for the aforementioned second exposure process to determine the process parameters of the target compensated exposure process. For details, please refer to the preceding content; further elaboration will not be repeated here.

[0097] Considering that the actual compensation position of each compensation exposure process may be adjusted based on the parameters of historical compensation exposure processes, the aforementioned process can be changed to an iterative process. That is, in response to the existence of out-of-focus defects, a compensation exposure process can be applied, and the process parameters of the compensation exposure process can be determined. Then, it is determined whether the out-of-focus defect still exists after executing the compensation exposure process. If yes, the aforementioned steps are repeated. If no, the loop ends.

[0098] The foregoing Figure 8 The process has been explained. For example... Figure 8 As shown, process P800 may include the following steps: S810. For the target exposure block with the target crystal plane height, determine the key dimensions of the target exposure block after performing the first exposure process and the historical compensation exposure process.

[0099] S820 determines whether to perform target compensation exposure process based on the key size of the target exposure block.

[0100] S830, if yes, determining a target compensation position corresponding to the target compensation exposure process based on the thickness of the photoresist, the critical dimension condition of the target exposure block and the depth of focus range of exposure.

[0101] S840, determining a second target compensation parameter of the target compensation process and taking the target compensation process as a historical compensation exposure process.

[0102] S850, if no, determining that the critical dimension condition meets the requirement.

[0103] In the foregoing P800, S820 can be a step of determining whether to perform a compensation exposure process. S830 and S840 can reflect subsequent conditions of performing the compensation exposure process. S850 can be a subsequent condition that the requirement has been met and no further exposure is needed. After S840 is performed, the foregoing S810 can be iteratively executed until S850.

[0104] In the foregoing S810, the historical compensation exposure can be processed similarly to the execution method of the first exposure process, so as to determine the critical dimension condition of the target exposure block after the first exposure process and the historical compensation exposure process are performed. The critical dimension condition herein can include the critical dimension condition of each depth of the photoresist.

[0105] The foregoing S820 can be performed based on whether the foregoing critical dimension condition meets the requirement. The requirement of the critical dimension condition can be directly or indirectly determined during semiconductor design. For example, the area where the photoresist is exposed can be used for a trench, and the requirement of the critical dimension of the exposure of the photoresist thereon can be determined based on the general preparation requirement of the trench.

[0106] The subsequent S830 and S840 can refer to the related description of the foregoing P700, and after S840 is completed, the target compensation exposure can be re-executed as the historical compensation exposure that has been determined to perform the foregoing S810 until the requirement of the critical dimension is met (i.e., jumping to S850 in the judgment of S820).

[0107] Unexpected technical effects: In summary, the semiconductor device and the manufacturing method provided by the application have the following unexpected effects: ①For the difference in crystal plane height between the edge region and the center region of the wafer, the application divides the wafer into a plurality of exposure blocks when performing the second exposure process for eliminating the bridging defect, and determines appropriate exposure parameters for each exposure block based on the first exposure process performed before the second exposure process, so that the corresponding second exposure process can be performed on the exposure blocks with different crystal plane heights, thereby avoiding the case that the overall exposure parameters are difficult to adapt to the regions with different crystal plane heights (especially the edge region with lower height) when the second exposure process is performed on the whole wafer.

[0108] ②In determining the exposure parameters, the application determines the influence of different exposure parameters on the critical dimension correction under the crystal plane height when the first exposure process parameters are fixed through a simulation algorithm, so as to determine the appropriate exposure parameters under each crystal plane height, and improve the accuracy of the critical dimension of the semiconductor device.

[0109] ③Considering that the crystal plane height distribution is often discrete, if each exposure block is sequentially loaded into the working range, the worktable may be frequently moved. Therefore, the application can plan each exposure block for performing the second exposure process, so that a plurality of exposure blocks with the same focus position are continuously loaded in one group, the longitudinal movement of the worktable is reduced, and the execution efficiency of the second exposure process is improved.

[0110] ④Considering that if the first exposure process is to be performed globally, the crystal plane height range of the target wafer often needs to be less than the exposure focal depth range, at which time the first target exposure parameters of the first exposure process for simultaneously processing each exposure block can be determined based on the wafer data through focus-energy matrix data analysis. When the crystal plane height range is greater than or equal to the exposure focal depth range, the first exposure process can be performed in zones so that the crystal plane height range in each zone is less than the exposure focal depth range. That is, the crystal plane height range of the target wafer can be determined first. Then, in response to the crystal plane height range being greater than or equal to the exposure focal depth range, a plurality of first exposure regions are demarcated based on the crystal plane height of the target wafer, and the first target exposure parameters of each first exposure region are determined based on the wafer data through focus-energy matrix data analysis. The first exposure region includes a plurality of exposure blocks with a crystal plane height range less than the exposure focal depth range. Thus, the problem of being unable to expose due to wafer edge abnormalities can be overcome, thereby improving the yield of the semiconductor.

[0111] ⑤Considering that the actual role of the second exposure process is to perform compensatory exposure in the defocused area of the first exposure process, the number of exposure processes in the actual execution of the second exposure process can not be limited. That is, if the current compensatory exposure cannot eliminate the bridging defects caused by defocusing, one more exposure can be added, until the exposure is completed. Thus, the thickness of the photoresist that the application can adapt to is further improved.

[0112] The above disclosed embodiments of the application are only used to help explain the application. The embodiments do not describe all the details, nor limit the application to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of the present application. The present application selects and specifically describes these embodiments in order to better explain the principles and practical applications of the application, so that those skilled in the art can well understand and utilize the application. The application is limited only by the claims and their full scope and equivalents.

Claims

1. An exposure method characterized by, The application is applied to a photoresist exposure system, and the exposure method comprises the following steps: In response to a target wafer coated with photoresist being placed on a workpiece table, the crystal plane height of each exposure block of the target wafer is determined; A first target exposure parameter of a first exposure process is determined, wherein the exposure depth range of the focus position in the first target exposure parameter covers the interface between the photoresist and the target wafer; A first correlation between different crystal plane heights and critical dimension deviations in the target wafer after the first exposure process is performed is determined; Second exposure simulation is performed on a target exposure block based on the target crystal plane height after the first exposure process, and a second correlation between a second exposure parameter and a critical dimension compensation under the target crystal plane height is determined, wherein the second exposure parameter at least includes a focus position; Based on the first correlation and the second correlation, a second target exposure parameter for eliminating the critical dimension deviation of the target crystal plane height is determined to determine the second target exposure parameter of each exposure block; The first exposure process is performed based on the first target exposure parameter, and then the second exposure process is sequentially performed on each exposure block based on the second target exposure parameter of each exposure block.

2. The exposure method according to claim 1, wherein The second exposure simulation on the exposure block of the target crystal plane height in the photoresist after the first exposure process comprises the following steps: The target wafer after the first exposure process is loaded in a simulation environment; Different exposure focus positions are used to perform second exposure simulation on the exposure block of the target crystal plane height, and the critical dimension compensation of different exposure focus positions is determined to construct the second correlation of the target crystal plane height; Based on the first correlation and the second correlation, a second target exposure parameter for eliminating the critical dimension deviation of the photoresist of the target crystal plane height is determined, comprising: The target critical dimension deviation of the target crystal plane height is determined based on the first correlation; The target critical dimension compensation matched with the target critical dimension deviation is determined at the corresponding target focus position in the second correlation as the second target exposure parameter.

3. The exposure method according to claim 2, wherein The second exposure process is sequentially performed on each exposure block based on the second target exposure parameter of each exposure block, comprising: In response to the workpiece table loading the target exposure block into the working range, the workpiece table is controlled to move longitudinally, so that the exposure beam of the exposure device is focused on the target focus position in the photoresist; The exposure device is controlled to perform the second exposure process.

4. The exposure method according to claim 2, wherein The second exposure process is sequentially performed on each exposure block based on the second target exposure parameter of each exposure block, comprising: A plurality of second exposure regions are demarcated based on the target focus position of each exposure block, wherein the second exposure region includes a plurality of exposure blocks with the same target focus position; For a target second exposure region in the plurality of second exposure regions, the workpiece table is controlled to sequentially load each exposure block of the target second exposure region into the working range; performing the second exposure process based on second target exposure parameters of exposure blocks in the job range.

5. The exposure method according to any one of claims 1, wherein The first target exposure parameters of the first exposure process of the photoresist based on the target wafer include: determining wafer data of a wafer batch in which the target wafer is located; determining the first target exposure parameters of the first exposure process based on the wafer data through focus-energy matrix data analysis.

6. The exposure method according to claim 5, wherein The first target exposure parameters of the first exposure process based on the wafer data through focus-energy matrix data analysis include: determining a range of facet heights of the target wafer; in response to the range of facet heights being less than an exposure focal depth range, determining the first target exposure parameters of the first exposure process based on the wafer data through focus-energy matrix data analysis; in response to the range of facet heights being greater than or equal to the exposure focal depth range, dividing a plurality of first exposure regions based on the range of facet heights of the target wafer, and determining first target exposure parameters of each first exposure region based on the wafer data through focus-energy matrix data analysis, wherein the first exposure region includes a plurality of exposure blocks with a range of facet heights less than the exposure focal depth range.

7. The exposure method according to any one of claims 1, wherein The exposure method further includes: determining at least one compensation exposure process in the second exposure process and a corresponding compensation position based on the first target exposure parameters and an exposure focal depth range; The determination of the first correlation between different facet heights of the target wafer and critical dimension deviations after the first exposure process includes: for a target compensation exposure process in the at least one compensation exposure process, determining a first correlation between different facet heights of the target wafer and critical dimension deviations at a target compensation position after the first exposure process and historical compensation exposure processes, wherein the target compensation position corresponds to the target compensation exposure process, and the historical compensation exposure processes are each a compensation exposure process with a compensation position below the target compensation position; The second exposure simulation for the target exposure block based on the target facet height after the first exposure process determines a second correlation between the second exposure parameters and the critical dimension compensation at the target facet height, including: The target compensation exposure process simulation for the target exposure block based on the target facet height after the first exposure process and the historical compensation exposure processes determines a second correlation between the second exposure parameters and the critical dimension compensation at the target compensation position at the target facet height.

8. The exposure method according to claim 7, wherein The determination of the at least one compensation exposure process in the second exposure process and the compensation position corresponding to the compensation exposure process based on the first target exposure parameters and the exposure focal depth range includes: for a target exposure block of a target facet height, determining a critical dimension condition of the target exposure block after the first exposure process and the historical compensation exposure processes; determining whether to perform the target compensation exposure process based on the critical dimension condition of the target exposure block; If yes, a target compensation position corresponding to a target compensation exposure process is determined based on a thickness of the photoresist, a critical dimension condition of the target exposure block, and an exposure depth of focus range.

9. A photoresist exposure system, characterized by, The photoresist exposure system comprises: an exposure device for releasing an exposure light beam; a workpiece table for carrying a wafer; and a controller in communication connection with the exposure device and the workpiece table, for controlling the exposure device and the workpiece table based on the exposure method in any one of claims 1-8.

10. A semiconductor device, characterized by comprising: The semiconductor device is prepared based on the exposure method in any one of claims 1-8.

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