Advanced process control method

Abstract

The invention discloses an advanced process control method, which comprises the following steps of: 1, carrying out set description to obtain a name wafer set, an available wafer boat slot position set and a batch wafer boat slot position set; step 2, carrying out set solving to obtain a product name wafer boat slot position set, compensating the wafer boat slot position set, and obtaining a first mapping between the product name wafer set and the product name wafer boat slot position set; and step 3, judging whether repair distribution can be carried out or not: if the number of the wafer boat slots in the set of the compensation wafer boat slot sets in the names and the number of the wafer boat slots in the intersection of the batch wafer boat slot sets is smaller than the number of the wafers in the wafer set of the names, judging that repair distribution cannot be carried out. And if the number of the wafer boat slots in the combination of the compensation wafer boat slot sets of all the names and the intersection of the batch wafer boat slot sets is smaller than the number of the wafers in the wafer sets of all the names, it is judged that repair distribution cannot be carried out. Otherwise, judging that repair distribution can be carried out. According to the method, the calculation efficiency and the operation flexibility can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to an advanced process control method. Background Technology

[0002] The large volume of the furnace tubes can cause temperature and airflow to be inconsistent in different locations, creating an inherent tendency that cannot be adjusted inside the furnace tubes.

[0003] In CMOS devices, key films such as gate oxide and silicon nitride for SONOS are usually grown in furnace tubes. This inherent trend inevitably leads to differences in film thickness / quality between the crystal boat slots in the furnace tube, ultimately resulting in significant fluctuations in product performance.

[0004] In theory, if the wafers placed in each crystal boat slot have undergone targeted dosage adjustments in the upstream ion implantation step, the inherent trends in film thickness and quality within the furnace tube can be corrected, ensuring that the final product performance meets requirements. For example... Figure 1 The table shown is a table of ion implantation doses for each wafer slot during existing furnace tube ion implantation compensation. The first column corresponds to the wafer slot and the second column corresponds to the implantation dose. The impact of the wafer slot on the furnace tube process is adjusted by the implantation dose. That is, before performing the furnace tube process, the wafer slot to be placed needs to be determined in advance. Then, according to the different wafer slots, the implantation dose of the wafer is set in advance and repaired by ion implantation.

[0005] The large volume of the furnace tubes can cause temperature and airflow to be inconsistent in different locations, creating an inherent tendency that cannot be adjusted inside the furnace tubes.

[0006] In CMOS devices, key films such as gate oxide and SONOS Nitride are usually grown in furnace tubes. This inherent trend inevitably leads to differences in film thickness / quality between the crystal boat slots in the furnace tube, ultimately resulting in significant fluctuations in product performance.

[0007] In theory, if the wafers placed in each crystal boat slot have undergone targeted dosage adjustments in the upstream ion implantation step, the inherent trends in film thickness and quality in the furnace tube can be repaired, ensuring that the final product performance meets the requirements.

[0008] The industry typically uses advanced process control methods based on path planning to solve the problem of repairing downstream processes with upstream processes.

[0009] A simpler application scenario is:

[0010] Each dry lithography chamber has its own unique non-uniform distribution of critical dimensions, and the upstream photolithography process requires tailor-made repair conditions.

[0011] Before the photolithography process, a dry etching cavity is designated as the destination for each wafer, and then the corresponding photolithography repair conditions are selected as the starting point.

[0012] Then work according to that path.

[0013] When this method is applied to ion implantation-furnace tubes, the situation becomes more complex.

[0014] First, the furnace tube is a batch operation process. Before the ion implantation process, a furnace tube batch needs to be formed. The batch contains several wafers to be assembled. The furnace tube will provide a batch of wafer boat slots for the batch according to the operation mode and the number of wafers to be assembled. According to certain rules, the wafer boat slots are selected as the destination for all wafers to be assembled, and then the corresponding ion implantation dose is selected as the starting point to form the repair plan for the furnace tube batch.

[0015] The above rules are as follows:

[0016] Different product names have varying degrees of sensitivity to differences in film thickness / film quality, and therefore the allowed wafer slots for each product name will also differ. For example, product name B is very sensitive and can only be placed in slots 1-25; product name A can be placed in slots 1-50. Therefore, the rule is: each wafer slot must allow the placement of the product name to which the selected wafer belongs.

[0017] According to existing classic path planning methods, it is necessary to continuously try possible combinations of destinations until a destination that meets the rules is planned for all wafers. If no compliant combination is found after trying all possibilities, it means that there is no patching solution and batching is not possible. The disadvantage of this method is its low computational efficiency.

[0018] For example, such as Figure 2 The table shown is a table of various attempts to allocate slots to wafers when the existing advanced process control method based on path planning determines whether the first group of wafers can be batched; the first group of wafers includes wafers of two products, product name A and product name B. Figure 2 In the diagram, product name A corresponds to 25 wafers of LOT07, designated as LOT07#01, LOT07#02 to LOT07#25 respectively. Product name B corresponds to 25 wafers of LOT08, designated as LOT08#01, LOT08#02 to LOT08#25 respectively.

[0019] There are 50 slots in total, numbered from 1 to 50.

[0020] Product A can be placed in slots 1-50, and product B can be placed in slots 1-25; the wafers to be batched are 25 pieces each of product A and product B, and the furnace tube provides wafer boat slots 1-50.

[0021] First, we tried placing wafers of product A from slots 1 to 25, and wafers of product B from slots 26 to 50, but this did not meet the requirements. Therefore, we proceeded with... Figure 2 The first attempt in the table shows that the slots corresponding to LOT08#01, LOT08#02 to LOT08#25 of product B do not meet the requirements. The crossed-out parts indicate that they do not meet the requirements.

[0022] Next, we tried placing wafers of product B from slots 1 to 25, and wafers of product A from slots 26 to 50, which met the requirements. This is the next step. Figure 2 The second attempt in the table.

[0023] There are repair solutions available, which can be batched.

[0024] For example, such as Figure 3 The table shown is a table of various attempts to allocate slots to wafers when using existing advanced process control methods based on path planning to determine whether the second group of wafers can be batched; the second group of wafers includes wafers of two products, product name C and product name D. Figure 3 In the diagram, product name C corresponds to batch LOT09, which contains 25 wafers. Product name D corresponds to batch LOT10, which contains 25 wafers.

[0025] Product C can be placed in slots 26-50, and product D can be placed in slots 26-50; each of products C and D requires 25 wafers, and the furnace tube provides slots 1-50 for the crystal boat.

[0026] First, we tried placing wafers of product C, numbered 1 to 25, in slots 1-25 respectively, and wafers of product D, numbered 1 to 25, in slots 26-50 respectively. This did not meet the requirements. Figure 3 The first attempt in the process.

[0027] Next, we tried placing wafers of product D from slots 1 to 25, and wafers of product C from slots 26 to 50, but this did not meet the requirements. Figure 3 This is the second attempt.

[0028] Further attempts were made to place wafers 2 through 24 of product C and wafer 1 of product D in slots 1-25 respectively, and wafers 2 through 24 of product D and wafer 1 of product C in slots 26-50 respectively. These methods did not meet the requirements. Figure 3 This is the third attempt.

[0029] ...

[0030] None of the possibilities meet the requirements, there is no solution, and batching is not possible.

[0031] Secondly, unlike dry etching, which can assign a cavity to each wafer according to the path when issuing a work instruction, the wafer boat slot of the furnace tube is not an independent work unit and cannot be directly assigned when issuing a work instruction. Instead, it is indirectly determined by the sorting of the wafer pods (FOUP) to be batched and the order of the wafers in the FOUP.

[0032] For example, such as Figure 4 The image shows a sorting table of wafers to be batched within a FOUP and a sorting table of various FOUPs within the furnace tube, based on existing advanced process control methods using path planning. Figure 4 It can be seen that the first 25 pieces of LOT1 are placed in FOUP1 in sequence, and the first 25 pieces of LOT2 are placed in FOUP2 in sequence;

[0033] If the furnace tubes operate in the order of FOUP1+FOUP2, then... Figure 4 In the FOUP sequence 1 operation, the first 25 wafers of LOT1 are placed in slots 1-25 of the crystal boat, and the first 25 wafers of LOT2 are placed in slots 26-50 of the crystal boat.

[0034] If the furnace tubes operate in the order of FOUP2+FOUP1, then... Figure 4 In the FOUP sequence 2 operation, the first 25 wafers of LOT1 are placed in slots 26-50 of the crystal boat, and the first 25 wafers of LOT2 are placed in slots 1-25 of the crystal boat.

[0035] According to the classic path planning method, before furnace tube operation, it is necessary to calculate whether the actual destination of all wafers strictly meets the path requirements.

[0036] For example, such as Figure 5 The table shown is a sorting table of various FOUPs in a furnace tube that meet the path requirements under the condition that the slots allocated to the wafers are determined, in the existing advanced process control method based on path planning. Wafers 1-25 of LOT3 are placed in FOUP3 in sequence, and their destinations are slots 26-50 of the wafer boat. Wafers 1-25 of LOT4 are placed in FOUP4 in sequence, and their destinations are slots 1-25 of the wafer boat.

[0037] First, we tried working in the order of FOUP3+FOUP4, i.e., FOUP sequence 1. The calculation showed that the destination of LOT3's 1-25 pieces was crystal boat slot 1-25, and the destination of LOT4's 1-25 pieces was crystal boat slot 26-50, which did not meet the path requirements.

[0038] Then, we tried the FOUP4+FOUP3 sequence, i.e., FOUP sequence 2. We calculated that the destination of LOT3's 1-25 pieces is crystal boat slot 26-50, and the destination of LOT4's 1-25 pieces is crystal boat slot 1-25, which meets the path requirements.

[0039] Therefore, homework is possible.

[0040] For example, such as Figure 6 The table shown is a sorting table of various FOUPs in the furnace tube that do not meet the path requirements under the condition that the slots allocated to the wafers are determined in the existing advanced process control method based on path planning. Wafers 1-25 of LOT5 are placed in FOUP5 in sequence, and their destinations are slots 2-25 and 1 of the wafer boat, respectively. Wafers 1-25 of LOT6 are placed in FOUP6 ​​in sequence, and their destinations are slots 27-50 and 26 of the wafer boat, respectively.

[0041] First, we tried working in the order of FOUP5+FOUP6, i.e., FOUP sequence 1. The calculation showed that the destination of LOT5's 1-25 pieces was crystal boat slot 1-25, and the destination of LOT6's 1-25 pieces was crystal boat slot 26-50, which did not meet the path requirements.

[0042] Trying to work in the order of FOUP6+FOUP5, i.e. FOUP sequence 2, we calculated that the destination of LOT5's 1-25 pieces is crystal boat slot 26-50, and the destination of LOT6's 1-25 pieces is crystal boat slot 1-25, which does not meet the path requirements;

[0043] Therefore, homework is not allowed.

[0044] The existing path planning method introduces the problem that wafers of the same product name and with the same ion implantation dose cannot be swapped between wafer boat slots, even though theoretically they could be swapped. This reduces the flexibility of furnace tube operations. Therefore, a new advanced process control method for ion implantation-furnace tube is needed to solve the existing technical problems. Summary of the Invention

[0045] The technical problem to be solved by the present invention is to provide an advanced process control method that can determine whether repair allocation and batching can be performed through set calculations during the process control of the process of the previous layer site compensating the next layer site, thereby improving the calculation efficiency; it can also realize the swapping of wafers of the same name and the same compensation process between the various wafer slots of the next layer site, thereby improving the flexibility of the operation of the next layer site.

[0046] To address the aforementioned technical problems, the present invention provides an advanced process control method for compensating a subsequent layer of a previous layer of a crystal boat, wherein the subsequent layer of a crystal boat comprises multiple crystal boat slots. Before performing compensation at the previous layer of the crystal boat, the method includes the following steps:

[0047] Step 1: Describe the set, including:

[0048] The wafers of products requiring compensation are described in a set, including: classifying the wafers according to the product name, and grouping the wafers of the products of each product name into a set of wafers of the same product name.

[0049] The available wafer slots are described as sets, including: each wafer corresponding to each product name has multiple sets of available wafer slots, and each set of available wafer slots shares the compensation process conditions of the previous layer station.

[0050] The set description of the wafer boat slots provided by the next layer station includes: forming a batch wafer boat slot set according to the operation mode of the next layer station and the total number of wafers.

[0051] Step 2: Perform set solving, including:

[0052] According to the product name, the wafers are allocated to the slots of the wafers to obtain a product name wafer slot set. The allocation of the product name wafer slot set satisfies the following conditions: the intersection between any two product name wafer slot sets is an empty set, and the union of all product name wafer slot sets is the batch wafer slot set.

[0053] The wafers are allocated the slots according to the product name and the compensation process conditions to obtain a set of compensation slots. The allocation of the set of compensation slots satisfies the following conditions: the intersection of any two sets of compensation slots is an empty set, and the union of all sets of compensation slots corresponding to the same product name is the set of product name slots.

[0054] Solve for the first mapping of one-to-one correspondence between the wafer set and the slot set corresponding to each product name.

[0055] The first mapping corresponding to each product name further yields the overall first mapping, which provides a one-to-one correspondence between the wafer set corresponding to each product name and the slot set corresponding to each product name.

[0056] Step 3: Perform set operations to determine whether patching allocation is possible, including:

[0057] Step 31: For a given product name, if the number of ...

[0058] Step 32: For all product names, if the number of the crystal boat slots in the intersection of the set of each compensation crystal boat slot for all product names and the set of the batch crystal boat slots is less than the number of the wafers in the set of all product names wafers, then it is determined that the repair allocation cannot be performed and batching is not possible; otherwise, proceed to the subsequent step 33.

[0059] Step 33: Determine whether the repair allocation can be performed and whether batch processing can be performed.

[0060] A further improvement is that, when step 33 determines that the repair allocation can be performed, the following steps are also included:

[0061] Step 4: Perform the repair allocation. In the repair allocation, the allocation priority of each wafer corresponding to each product name is set according to the number of available wafer slots included in the set of available wafer slots corresponding to each product name. The smaller the number of available wafer slots included in the set of available wafer slots corresponding to each product name, the higher the allocation priority. During the repair allocation, the wafers corresponding to the product name with higher allocation priority are allocated first.

[0062] A further improvement is that step four includes the following sub-steps:

[0063] Step 41: Set the set of wafer slots to be allocated, including: setting the set of wafer slots in the batch of wafer slots that have not yet been allocated to the wafer as the set of wafer slots to be allocated.

[0064] Step 42: Determine whether each product name has formed a mapping, including: determining whether the set of product name slots corresponding to each product name is an empty set. If it is an empty set, it means that the corresponding product name has not yet formed a mapping; otherwise, it means that the corresponding product name has already formed a mapping.

[0065] Step 43: Find the product name with the fewest slot positions, including:

[0066] Among the product names that have not formed a mapping, find the product name that has the smallest number of available slots in the corresponding set of available slots. Product names that have already formed a mapping are not included in the search. The product name found is named as the product name with the smallest number of slots.

[0067] Step 44: Forming the mapping corresponding to the product name with the minimum number of slots, including:

[0068] Set the set of available crystal boat slots corresponding to the product name with the minimum number of slots as the intersection of the set of available crystal boat slots corresponding to the product name with the minimum number of slots and the set of crystal boat slots to be allocated.

[0069] The set of compensated crystal boat slots corresponding to the minimum number of slots and the compensated process conditions is set as the intersection of the set of available crystal boat slots and the set of crystal boat slots to be allocated.

[0070] The elements in the wafer set and the slot set of the product name corresponding to the product name with the minimum number of slots are arranged in order to form the first mapping with a one-to-one correspondence.

[0071] Step 45: Mark the product name with the minimum number of slots as the product name that has been mapped; subtract the product name crystal boat slot set corresponding to the product name with the minimum number of slots from the crystal boat slot set to be allocated; then repeat steps 41 to 45 until the repair allocation is completed.

[0072] A further improvement is that, after the repair allocation is completed, a compensation process is also included at the previous layer site, the steps of which include:

[0073] Step 5: Assemble all the wafers in the batch to be processed into a wafer set for the previous layer site.

[0074] Step 6: Traverse all the sets of compensation boat slots; for each compensation process condition corresponding to each product name, intersect the inverse mapping set of the first mapping of the compensation boat slot set with the wafer set of the previous layer station to form a compensation wafer intersection; if the compensation wafer intersection is not empty, then all the wafers in the compensation wafer intersection are subjected to the compensation process according to the corresponding compensation process condition.

[0075] A further improvement is that, after the compensation process is completed and before proceeding to the operation at the next-level station, the following steps are also included:

[0076] Step 7: Perform crystal boat slot verification, including: determining whether the wafer placed in each crystal boat slot is correct. When the wafer placed in the corresponding crystal boat slot belongs to the inverse mapping set of the first mapping of the compensation crystal boat slot set to which the crystal boat slot belongs in the compensation process, the wafer position is correct; otherwise, the wafer position is incorrect.

[0077] A further improvement is that step seven includes the following sub-steps:

[0078] All the wafers in the batch to be processed are combined into a next-layer site wafer set.

[0079] Iterate through and sort all the wafer boxes.

[0080] Under the sorting of each wafer box, a second mapping from the set of wafer slots in the batch to the set of wafers at the next layer site is calculated.

[0081] Traverse each of the compensation boat slot sets. Under the corresponding compensation boat slot set, if the set of the second mapping of the compensation boat slot set is not equal to the set of the inverse mapping of the first mapping of the compensation boat slot set, it indicates that the wafer has a positional error; otherwise, the wafer is in the correct position.

[0082] If, after traversing each set of compensated wafer boat slots under the corresponding wafer box sorting, the wafer position remains correct, then the wafer boat slot verification is successful, and the wafer box sorting is subsequently used to perform the operation of the next layer station.

[0083] A further improvement is that the first front-layer site includes: an ion implantation site;

[0084] The first rear-layer site includes the furnace tube site.

[0085] A further improvement is that the operation mode of the next layer station is either bottom priority mode or top priority mode.

[0086] A further improvement is that, in step 44, when forming the first mapping, the following steps are included:

[0087] The elements in the wafer set of the product name are arranged in ascending order, and the elements in the slot set of the wafer name are arranged in ascending order. Then, the first mapping is formed in a one-to-one correspondence in sequence.

[0088] A further improvement is that, in step 41, the initial value of the set of crystal boat slots to be allocated is the set of crystal boat slots in the batch.

[0089] This invention describes known conditions using sets before compensation at the previous site, including a set description of the wafers and wafer slots of each product name requiring compensation (repair). Then, to determine whether repair allocation is possible, a set solution is performed, including allocating wafer slots based on product name and compensation process conditions, and forming a one-to-one first mapping between the sets of wafers and wafer slots corresponding to each product name. Operations are performed on the sets describing known conditions and the allocated sets, including union and intersection, and the number of elements is counted and compared. This allows for rapid determination of whether each product name requiring compensation can be repaired, thus forming suitable batches for repair. Compared to existing traditional methods that require traversing all path combinations to determine if batching is not possible, this invention significantly improves computational efficiency.

[0090] After determining that a repair batch can be formed, this invention allocates wafer slots based on the product name with the fewest available wafer slots during the repair allocation process. The product name with the fewest available wafer slots can be obtained through set operations, and the allocation of wafer slots can be achieved using a one-to-one mapping relationship between sets. Therefore, after determining that a repair batch can be formed, this invention uses a one-to-one mapping method to prioritize allocating wafer slots to the product name with the fewest available wafer slots until wafer slots and compensation process conditions such as repair dosage are allocated to all wafers. Compared with existing traditional methods that require traversing path combinations to find a suitable repair solution, this invention significantly improves computational efficiency.

[0091] Furthermore, in this invention, after the compensation process is completed and before proceeding to the next station, under various wafer cassette arrangements, any wafer placed in the inverse mapping set of the first mapping of the compensation wafer cassette set corresponding to the wafer cassette slot is correctly positioned when placed in the wafer cassette slot. Therefore, the wafer placed in the wafer cassette slot of this invention does not correspond to just one wafer, but to wafers in a wafer set using the same compensation process conditions. Thus, the wafers in the wafer cassette slot are replaceable, and all replacement wafers are correctly placed. In this way, the wafer cassette arrangement in which the wafers in each wafer cassette slot are correctly placed can be quickly found, and then the next station operation can proceed. That is, in this invention, during the operation of the next station, the wafers set in each wafer cassette slot do not need to be the same as the wafers corresponding to the wafer cassette slots when the compensation process was performed in the previous station. The wafers corresponding to the wafer cassette slots with the same compensation process in the previous station can be interchanged during the operation of the next station, which increases the flexibility of the operation of the next station. Therefore, the operation of the next layer of the present invention, such as furnace tube operation, only requires that the wafer actually placed in the crystal boat slot and the wafer corresponding to the slot in the repair scheme belong to the same set of wafers using the same repair dose. This effectively avoids the drawback of the existing traditional method where the actual crystal boat slot of the wafer must be equal to the crystal boat slot in the repair scheme, and improves the flexibility of furnace tube operation. Attached Figure Description

[0092] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0093] Figure 1 This is a table showing the ion implantation doses used for compensation for each crystal boat slot when performing ion implantation compensation on existing furnace tubes;

[0094] Figure 2 It is a table of various attempts to allocate slots to wafers when existing advanced process control methods based on path planning determine whether the first group of wafers can be batched;

[0095] Figure 3This is a table of various attempts to allocate slots to wafers when existing advanced process control methods based on path planning determine whether the second group of wafers can be batched;

[0096] Figure 4 It is a sorting table of wafers to be batched in the FOUP and a sorting table of various different FOUPs in the furnace tube in the existing advanced process control method based on path planning.

[0097] Figure 5 It is a sorting table of various FOUPs in the furnace tube that meet the path requirements under the condition that the slots allocated to the wafer are determined in the existing advanced process control methods based on path planning.

[0098] Figure 6 It is a sorting table of all different FOUPs in the furnace tube that do not meet the path requirements under the condition that the slots allocated to the wafer are determined in the existing advanced process control methods based on path planning.

[0099] Figure 7 This is a flowchart of an advanced process control method according to an embodiment of the present invention. Detailed Implementation

[0100] like Figure 7 The diagram shows a flowchart of an advanced process control method according to an embodiment of the present invention. This method is used to compensate a subsequent layer of a previous layer of a process station, where the subsequent layer includes multiple crystal boat slots. Before compensating the previous layer, the method includes the following steps:

[0101] Step 1: Describe the set, including:

[0102] The wafers of products requiring compensation are described in a set, including: classifying the wafers according to the product name, and grouping the wafers of the products of each product name into a set of wafers of the same product name.

[0103] The available wafer slots are described as sets, including: each wafer corresponding to each product name has multiple sets of available wafer slots, and each set of available wafer slots shares the compensation process conditions of the previous layer station.

[0104] The set description of the wafer boat slots provided by the next layer station includes: forming a batch wafer boat slot set according to the operation mode of the next layer station and the total number of wafers.

[0105] In this embodiment of the invention, the first front-layer site includes: an ion implantation site;

[0106] The first rear-layer site includes the furnace tube site.

[0107] The operation mode of the next layer station is either bottom priority mode or top priority mode.

[0108] The following description, using the formula, further illustrates the set from step one:

[0109] The first step is to describe the known conditions using sets:

[0110] For example, if there are p products with different names, a repair plan needs to be developed. Here, p is an integer greater than or equal to 1.

[0111] The product with the i-th name has w i A wafer, i∈[1,p], is the set of wafers of a product, denoted as WafersOfProduct. i . i is the product name number.

[0112] The product with the i-th name has d. i A set of accessible boat slots can be called a boat slot set. Each boat slot in the set shares a single ion implantation dose. This set of boat slots can be denoted as AvailableBoatSlots. i,j , i∈[1,p], j∈[1,d] i The wafers corresponding to the i-th product name are not repaired or compensated using the same ion implantation dose. Instead, they need to be repaired using the ion implantation dose of di. That is, some wafers will be repaired using one ion implantation dose, while others will be repaired using a different ion implantation dose, until the di-th wafers are repaired using the di-th ion implantation dose. Different types of wafers, i.e., different types of ion implantation doses, correspond to different boat slots. The set of boat slots corresponding to various ion implantation doses is the set of available boat slots.

[0113] Based on the furnace tube operation mode and the total number of wafers, the furnace tube can be defined as the set of boat slots provided for this batch, i.e., the batch boat slot set, denoted as BoatSlotsOfBatch.

[0114] For example, assuming the furnace tube can process a maximum of MaxBoatSlot wafers in a single batch, and if the furnace tube's processing mode is bottom-first, then:

[0115]

[0116] For example, assuming the furnace tube can process a maximum of MaxBoatSlot wafers per batch, and if the furnace tube's processing mode is top-first, then:

[0117]

[0118] Step 2: Perform set solving, including:

[0119] According to the product name, the wafers are allocated to the slots of the wafers to obtain a product name wafer slot set. The allocation of the product name wafer slot set satisfies the following conditions: the intersection between any two product name wafer slot sets is an empty set, and the union of all product name wafer slot sets is the batch wafer slot set.

[0120] The wafers are allocated the slots according to the product name and the compensation process conditions to obtain a set of compensation slots. The allocation of the set of compensation slots satisfies the following conditions: the intersection of any two sets of compensation slots is an empty set, and the union of all sets of compensation slots corresponding to the same product name is the set of product name slots.

[0121] Solve for the first mapping of one-to-one correspondence between the wafer set and the slot set corresponding to each product name.

[0122] The first mapping corresponding to each product name further yields the overall first mapping, which provides a one-to-one correspondence between the wafer set corresponding to each product name and the slot set corresponding to each product name.

[0123] The following is a further description of step two using the formula:

[0124] In this embodiment of the invention, to achieve advanced process control for repairing differences in the ion implantation dose in the furnace tube and crystal boat slots, the following set needs to be determined:

[0125] The set of boat slots allocated to each product name on a wafer is the boat slot set for that product name, denoted as BoatSlotsOfProduct. i For any two sets i∈[1,p], the intersection of any two sets must be empty, and the formula is:

[0126]

[0127] The set of boat slots allocated to each product name and each ion implantation dose wafer is the compensation boat slot set, denoted as BoatSlotsOfDosage. i,j For any two sets i∈[1,p], j∈[1,di], the intersection of any two sets must be empty, and the formula is:

[0128]

[0129] Find WafersOfProduct i To BoatSlotsOfProducti The one-to-one correspondence mapping is the first mapping, denoted as Assign. i A one-to-one mapping means that each wafer corresponds to only one wafer slot, and each wafer slot corresponds to only one wafer; thus, arrive The one-to-one mapping is denoted as Assign.

[0130] Assign -1 for arrive The one-to-one correspondence mapping is the inverse mapping of the first mapping.

[0131] Step 3: Perform set operations to determine whether patching allocation is possible, including:

[0132] Step 31: For a given product name, if the number of ...

[0133] Step 32: For all product names, if the number of the crystal boat slots in the intersection of the set of each compensation crystal boat slot for all product names and the set of the batch crystal boat slots is less than the number of the wafers in the set of all product names wafers, then it is determined that the repair allocation cannot be performed and batching is not possible; otherwise, proceed to the subsequent step 33.

[0134] Step 33: Determine whether the repair allocation can be performed and whether batch processing can be performed.

[0135] The following is a further description of step three, using the formula as an example:

[0136] Determine if a repair solution exists:

[0137] If there exists an i∈[1,p] such that the following expression holds:

[0138]

[0139] In formula (5) The corresponding set is the intersection of the set of compensation boat slots in the product name and the set of batch boat slots, as expressed in formula (5).

[0140] The number of elements in the set is less than WafersOfProduct iThe set refers to the number of elements in the set of wafers of the product name. When formula (5) is true, there is no repair scheme and batching is not possible. The above steps correspond to step 31.

[0141] Otherwise, if there exists an i∈[1,p] such that the following expression holds:

[0142] The set of each of the compensation crystal boat slots.

[0143] Formula (6) means The number of elements in the set is less than the total number of WafersOfProduct. i The sum of the number of elements in the set. When formula (6) holds true, there is no repair scheme and batching is not possible. The above steps correspond to step 32.

[0144] Otherwise, there are remedial solutions that can be implemented in batches.

[0145] In this embodiment of the invention, when step 33 determines that the repair allocation can be performed, the subsequent steps also include:

[0146] Step 4: Perform the repair allocation. In the repair allocation, the allocation priority of each wafer corresponding to each product name is set according to the number of available wafer slots included in the set of available wafer slots corresponding to each product name. The smaller the number of available wafer slots included in the set of available wafer slots corresponding to each product name, the higher the allocation priority. During the repair allocation, the wafers corresponding to the product name with higher allocation priority are allocated first.

[0147] Step four includes the following sub-steps:

[0148] Step 41: Set the set of wafer slots to be allocated, including: setting the set of wafer slots in the batch of wafer slots that have not yet been allocated to the wafer as the set of wafer slots to be allocated.

[0149] In this embodiment of the invention, the initial value of the set of crystal boat slots to be allocated is the set of crystal boat slots in the batch.

[0150] Step 42: Determine whether each product name has formed a mapping, including: determining whether the set of product name slots corresponding to each product name is an empty set. If it is an empty set, it means that the corresponding product name has not yet formed a mapping; otherwise, it means that the corresponding product name has already formed a mapping.

[0151] Step 43: Find the product name with the fewest slot positions, including:

[0152] Among the product names that have not formed a mapping, find the product name that has the smallest number of available slots in the corresponding set of available slots. Product names that have already formed a mapping are not included in the search. The product name found is named as the product name with the smallest number of slots.

[0153] Step 44: Forming the mapping corresponding to the product name with the minimum number of slots, including:

[0154] Set the set of available crystal boat slots corresponding to the product name with the minimum number of slots as the intersection of the set of available crystal boat slots corresponding to the product name with the minimum number of slots and the set of crystal boat slots to be allocated.

[0155] The set of compensated crystal boat slots corresponding to the minimum number of slots and the compensated process conditions is set as the intersection of the set of available crystal boat slots and the set of crystal boat slots to be allocated.

[0156] The elements in the set of wafers and the set of wafer slots corresponding to the product name with the minimum number of slots are sequentially arranged to form a one-to-one first mapping. In this embodiment of the invention, forming the first mapping includes:

[0157] The elements in the wafer set of the product name are arranged in ascending order, and the elements in the slot set of the wafer name are arranged in ascending order. Then, the first mapping is formed in a one-to-one correspondence in sequence.

[0158] Step 45: Mark the product name with the minimum number of slots as the product name that has been mapped; subtract the product name crystal boat slot set corresponding to the product name with the minimum number of slots from the crystal boat slot set to be allocated; then repeat steps 41 to 45 until the repair allocation is completed.

[0159] The following is a further description of step four, using the formula as an example:

[0160] Develop a repair plan:

[0161] The core idea is to continuously allocate wafer slots to the product name with the fewest available wafer slots until wafer slots and repair doses are allocated to all wafers.

[0162] Let the set of unassigned boat slots, BoatSlots, be the set of BoatSlotsOfBatch. That is, let BoatSlots represent the set of unassigned boat slots. The initial value is set of BoatSlotsOfBatch, indicating that initially, none of the boat slots in the set of BoatSlotsOfBatch have been assigned, so they all belong to the set of unassigned boat slots. This step corresponds to step 41.

[0163] Traverse k∈[1,p](7);

[0164] Let min_i be the number of the product name with the fewest workable crystal boat slots;

[0165] Traverse i∈[1,p](8);

[0166] If BoatSlotsOfProduct i The set is empty, indicating that the product name has not yet been mapped.

[0167] Searching for To reach the minimum value of i;

[0168]

[0169] Let i be min_i, which represents the product name with the fewest workable crystal boat slots;

[0170] Otherwise, it means that the product name has already been mapped and will no longer be included in the search.

[0171] End the traversal (9).

[0172] Let BoatSlotsOfProduct min_i for:

[0173] BoatSlotsOfDosage min_i,j For: AvailableBoatSlots min_i,j ∩BoatSlots;

[0174] WafersOfProduct min_i The elements in the list are arranged from smallest to largest, similar to BoatSlotsOfProduct. min_i The elements are arranged from smallest to largest, forming a one-to-one correspondence in sequence.

[0175] Let BoatSlots=BoatSlots\BoatSlotsOfProduct min_i This means removing the mapped boat slots from BoatSlots.

[0176] End traversal (10).

[0177] The above uses a loop block representation: where lines (8) to (9) correspond to step 43, i.e., finding the product name with the minimum number of slots; after finding the product name with the minimum number of slots, the steps between lines (9) and (10) are performed, which correspond to steps 44 and 45. One loop of the loop block between lines (7) and (10) represents the completion of the repair allocation of one product name; then the repair allocation of the next product name is performed, and the number of loops is controlled by k.

[0178] In this embodiment of the invention, after the repair allocation is completed, a compensation process is further performed at the previous layer site. The steps of the compensation process include:

[0179] Step 5: Assemble all the wafers in the batch to be processed into a wafer set for the previous layer site.

[0180] Step 6: Traverse all the sets of compensation boat slots; for each compensation process condition corresponding to each product name, intersect the inverse mapping set of the first mapping of the compensation boat slot set with the wafer set of the previous layer station to form a compensation wafer intersection; if the compensation wafer intersection is not empty, then all the wafers in the compensation wafer intersection are subjected to the compensation process according to the corresponding compensation process condition.

[0181] The following is a further description of steps five and six, using the formula as an example:

[0182] Ion implantation control:

[0183] The set of all wafers in the Lot to be processed, i.e., the set of wafers from the previous layer site, is denoted as CurrentWafersAtImplantStep set; this step corresponds to step five.

[0184] Iterate through all BoatSlotsOfDosage collections

[0185] if

[0186] Assign -1 (BoatSlotsOfDosage i,j )∩CurrentWafersAtImplantStep is not empty;

[0187] Assign -1 (BoatSlotsOfDosage i,j In CurrentWafersAtImplantStep, all wafers are processed according to the Dosage. i,j repair;

[0188] Finish

[0189] End of traversal

[0190] In this embodiment of the invention, after the compensation process is completed and before proceeding to the operation at the next-layer station, the following steps are also included:

[0191] Step 7: Perform crystal boat slot verification, including: determining whether the wafer placed in each crystal boat slot is correct. When the wafer placed in the corresponding crystal boat slot belongs to the inverse mapping set of the first mapping of the compensation crystal boat slot set to which the crystal boat slot belongs in the compensation process, the wafer position is correct; otherwise, the wafer position is incorrect.

[0192] Step seven includes the following sub-steps:

[0193] All the wafers in the batch to be processed are combined into a next-layer site wafer set.

[0194] Iterate through and sort all the wafer boxes.

[0195] Under the sorting of each wafer box, a second mapping from the set of wafer slots in the batch to the set of wafers at the next layer site is calculated.

[0196] Traverse each of the compensation boat slot sets. Under the corresponding compensation boat slot set, if the set of the second mapping of the compensation boat slot set is not equal to the set of the inverse mapping of the first mapping of the compensation boat slot set, it indicates that the wafer has a positional error; otherwise, the wafer is in the correct position.

[0197] If, after traversing each set of compensated wafer boat slots under the corresponding wafer box sorting, the wafer position remains correct, then the wafer boat slot verification is successful, and the wafer box sorting is subsequently used to perform the operation of the next layer station.

[0198] The following is a further description of step seven, using the formula as an example:

[0199] Crystal boat slot verification before furnace tube operation:

[0200] The core idea is that it is only required that the wafer actually placed in the wafer slot and the wafer corresponding to that slot in the repair plan belong to the same set of wafers using the same repair dose, and it is not required that the wafer corresponding to that slot be placed in the plan.

[0201] The set of all wafers in the Lot to be processed, i.e., the set of wafers in the next layer site, is denoted as CurrentWafersAtIFurnaceStep set;

[0202] The mapping Result from the set BoatSlots to the set CurrentWafersAtIFurnaceStep is calculated under various FOUP sorting conditions, which is the second mapping (11).

[0203] The wafer positions are marked correctly;

[0204] Iterate through all BoatSlotsOfDosage sets (12);

[0205] If the collection Result(BoatSlotsOfDocument) i,j ) is not equal to set

[0206] Assign -1 (BoatSlotsOfDosage i,j This indicates that BoatSlotsOfDosage i,j The crystal boat slots in the middle were not placed according to the Dosage i,j Repaired wafer.

[0207] The wafer position is incorrect; exit the loop.

[0208] Finish;

[0209] End traversal (13);

[0210] If the wafer position is correct;

[0211] Perform furnace tube operations according to the current FOUP sorting, then exit the loop;

[0212] Finish;

[0213] End the traversal (14).

[0214] The above description includes two loop modules. Lines (12) to (13) correspond to traversing each set of compensation boat slots under the wafer box sorting, and using set operations to determine whether there is an error in the wafer position.

[0215] The line between lines (11) and (14) corresponds to the loop under the sorting of each wafer box. That is, when the wafer box sorting in a loop, i.e. the FOUP sorting, detects an error in the wafer position, the loop check of the next FOUP sorting is performed; otherwise, if the FOUP sorting is correct, the loop ends.

[0216] This invention describes known conditions using sets before compensation at the previous site, including a set description of the wafers and wafer slots of each product name requiring compensation (repair). Then, a set solution is performed to determine whether repair allocation is possible. This includes allocating wafer slots based on product name and compensation process conditions, and forming a one-to-one first mapping between the sets of wafers and wafer slots corresponding to each product name based on the allocation results. Operations are performed on the set describing the known conditions and the set obtained from the allocation solution, including union and intersection, and the number of elements is counted and compared. This allows for rapid determination of whether each product name requiring compensation can be repaired, thus forming suitable batches for repair. Compared to existing traditional methods that require traversing all path combinations to determine if batching is not possible, this invention significantly improves computational efficiency.

[0217] In this embodiment of the invention, after determining that a repair batch can be formed, the repair allocation is performed by prioritizing the allocation of wafer slots to the product name with the fewest available wafer slots. The product name with the fewest available wafer slots can be obtained through set operations, and the allocation of wafer slots can be achieved using a one-to-one mapping relationship between sets. Therefore, after determining that a repair batch can be formed, this embodiment of the invention uses a one-to-one mapping method to prioritize allocating wafer slots to the product name with the fewest available wafer slots until wafer slots and compensation process conditions such as repair dosage are allocated to all wafers. Compared with existing traditional methods that require traversing path combinations to find a suitable repair solution, this embodiment of the invention significantly improves computational efficiency.

[0218] Furthermore, in this embodiment of the invention, after the compensation process is completed and before proceeding to the next station, under various wafer cassette arrangements, any wafer in the inverse mapping set of the first mapping of the compensation wafer cassette set corresponding to the wafer cassette slot is correctly positioned when placed in the wafer cassette slot. Therefore, the wafer placed in the wafer cassette slot in this embodiment of the invention does not correspond to only one wafer, but to wafers in a wafer set using the same compensation process conditions. Thus, the wafers in the wafer cassette slot are replaceable, and all replacement wafers are correctly placed. In this way, the wafer cassette arrangement in which the wafers in each wafer cassette slot are correctly placed can be quickly found, and then the next station operation can proceed. That is, in this embodiment of the invention, during the operation of the next station, the wafers set in each wafer cassette slot do not need to be the same as the wafers corresponding to the wafer cassette slots when the compensation process was performed in the previous station. The wafers corresponding to the wafer cassette slots with the same compensation process in the previous station can be interchanged during the operation of the next station, which increases the flexibility of the operation of the next station. Therefore, in the subsequent layer station operations of the present invention, such as furnace tube operations, it is only required that the wafer actually placed in the crystal boat slot and the wafer corresponding to that slot in the repair scheme belong to the same set of wafers using the same repair dose. This effectively avoids the drawback of the existing traditional method where the actual crystal boat slot of the wafer must be equal to the crystal boat slot in the repair scheme, and improves the flexibility of furnace tube operations.

[0219] In this embodiment of the invention, firstly, a set theory method is used. By performing union and intersection operations on the set and then counting the number of elements, it can be determined whether a suitable batch of furnace tubes for repair can be formed. Compared with the existing traditional method of traversing all path combinations before determining that a batch cannot be formed, the computational efficiency is greatly improved.

[0220] Secondly, after determining that a repair batch can be formed, the embodiments of the present invention use a one-to-one mapping method to prioritize the allocation of wafer slots to the product name with the fewest available wafer slots, until wafer slots and repair doses are allocated to all wafers. Compared with the existing traditional method of traversing path combinations to find a suitable repair scheme, the computational efficiency is greatly improved.

[0221] Finally, during furnace tube operation, it is only required that the wafer actually placed in the wafer boat slot and the wafer corresponding to that slot in the repair plan belong to the same set of wafers using the same repair dose. This effectively avoids the drawback of the existing traditional method where the actual wafer boat slot must be equal to the wafer boat slot in the repair plan, and improves the flexibility of furnace tube operation.

[0222] The embodiments of the present invention will be further described below with reference to specific applications:

[0223] Application of the present invention embodiment 1:

[0224] SONOS devices are extremely sensitive to the properties of the ONO thin film grown in SONOS furnace tubes. Even minute differences between different crystal boat slots can affect device performance, and these minute differences cannot be adjusted using the SONOS furnace tube process.

[0225] The differences between different crystal boat slots can be compensated by adjusting the cell tunneling ion implantation dose under the ONO thin film in the SONOS device.

[0226] The advanced process control method based on set theory, as described in this invention, enables the realization of differences between different crystal boat slots in the furnace tube process of Cell Tunnel Implant ONO thin film dose compensation.

[0227] Application 2 of the present invention:

[0228] Low-power CMOS devices are extremely sensitive to the thickness of the gate oxide film grown in the furnace tube. There is an inherent S-shaped curve inside the furnace tube, which is the film thickness versus the position of the crystal boat. Even if the temperature is simply increased to force the S-shaped curve of film thickness to be flattened, the temperature-induced changes in film quality will still lead to differences in device performance between crystal boat positions.

[0229] By adjusting the well threshold voltage (Well Vt Adjust Implant) dose under the Gate Oxide film in Low-Power CMOS devices, differences in film thickness and quality between different crystal boat slots can be compensated.

[0230] The advanced process control method based on set theory in this invention can realize the differences in film thickness and quality between different crystal boat slots in the furnace tube process of Well Vt AdjustImplant Gate Oxide thin film.

[0231] In this embodiment of the invention, a set theory approach is adopted to achieve advanced process control for repairing differences in the crystal boat slots of the furnace tube by means of steps such as determining the existence of repair schemes, generating repair schemes, controlling ion implantation, and verifying the crystal boat slot positions in the furnace tube operation.

[0232] By using set theory, we can determine whether a repair solution can be formed by performing union and intersection operations on the sets and then counting the number of elements.

[0233] Using a one-to-one mapping method, crystal boat slots are continuously allocated to the product name with the fewest available crystal boat slots until crystal boat slots and repair doses are allocated to all wafers, and a repair plan is generated.

[0234] During ion implantation, the repair dose for each wafer is determined by performing inverse mapping and intersection operations on the set.

[0235] During furnace tube operation, it is only necessary to verify that the wafers actually placed in the crystal boat slot and the wafers corresponding to that slot in the repair plan belong to the same set of wafers using the same repair dose.

[0236] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. An advanced process control method, characterized by, The front layer site compensates for the back layer site, and the back layer site includes a plurality of wafer boat slots; Before the front layer site compensates, the following steps are included: Step one, performing set description, including: Performing set description on the wafers of products of each product name that needs to be compensated, including: classifying the wafers according to the product name, and each wafer of the product of each class of the product name belongs to the same product name wafer set; Performing set description on the available wafer boat slots, including: each wafer of the wafer set corresponding to each product name corresponds to a plurality of available wafer boat slot sets, and each wafer boat slot set shares a compensation process condition of the front layer site; Performing set description on the wafer boat slots provided by the back layer site, including: forming a batch wafer boat slot set according to the operation mode of the back layer site and the total number of wafers; Step two, performing set solving, including: Allocating the wafer boat slots to each wafer according to the product name to obtain a product name wafer boat slot set, and the allocation of the product name wafer boat slot set satisfies: the intersection between any two product name wafer boat slot sets is an empty set, and the union of all product name wafer boat slot sets is the batch wafer boat slot set; Allocating the wafer boat slots to each wafer according to the product name and the compensation process condition to obtain a compensation wafer boat slot set, and the allocation of the compensation wafer boat slot set satisfies: the intersection between any two compensation wafer boat slot sets is an empty set, and the union of all compensation wafer boat slot sets corresponding to the same product name is the product name wafer boat slot set; Solving the one-to-one correspondence of the wafers and the wafer boat slots between the product name wafer set corresponding to each product name and the product name wafer boat slot set; Further obtaining the one-to-one correspondence of the wafers and the wafer boat slots between the product name wafer set corresponding to all product names and all product name wafer boat slot sets from the first mapping corresponding to each product name; Step three, performing set operation to determine whether the repair allocation can be performed, including: Step 31, for a product name, if the number of wafer boat slots in the intersection between the union of the compensation wafer boat slot set in the product name and the batch wafer boat slot set is less than the number of wafers in the product name wafer set, it is determined that the repair allocation cannot be performed, and batch cannot be formed; otherwise, further step 32 is performed; Step 32, for all product names, if the number of wafer boat slots in the intersection between the union of the compensation wafer boat slot set of all product names and the batch wafer boat slot set is less than the number of wafers in all product name wafer sets, it is determined that the repair allocation cannot be performed, and batch cannot be formed; otherwise, further step 33 is performed; Step 33, it is determined that the repair allocation can be performed, and batch can be formed.

2. The advanced process control method of claim 1, wherein: When step 33 determines that the repair allocation can be performed, the following steps are further included: Step four, performing the repair allocation, in which the allocation priority of each wafer corresponding to each product name is set according to the number of the available boat slots corresponding to the product name wafer set of each product name, and the smaller the number of the available boat slots corresponding to the product name wafer set of each product name, the higher the allocation priority, and in the repair allocation, the wafers corresponding to the product name with the higher allocation priority are allocated first.

3. The advanced process control method of claim 2, wherein: In step four, the following sub-steps are included: Step 41, setting a set of available boat slots, including: setting the set of boat slots that have not been allocated wafers in the set of batch boat slots as the set of available boat slots; Step 42, determining whether each product name forms a mapping, including: determining whether the product name wafer set corresponding to each product name is an empty set, if it is an empty set, it means that the corresponding product name has not formed a mapping, otherwise, it means that the corresponding product name has already formed a mapping; Step 43, finding the product name with the smallest number of slots, including: finding the product name with the smallest number of slots in the set of available boat slots among the product names that have not formed a mapping, the product names that have formed a mapping do not participate in the finding, and the product name found in the finding is the product name with the smallest number of slots; Step 44, forming a mapping corresponding to the product name with the smallest number of slots, including: setting the product name wafer set corresponding to the product name with the smallest number of slots as the intersection between the union of the set of available boat slots corresponding to the product name with the smallest number of slots and the set of available boat slots corresponding to the compensation process condition and the set of available boat slots corresponding to the product name with the smallest number of slots and the set of available boat slots corresponding to the compensation process condition; forming a one-to-one first mapping between the product name wafer set corresponding to the product name with the smallest number of slots and each element in the product name wafer set in order; Step 45, marking the product name with the smallest number of slots as the product name that has formed a mapping; and subtracting the product name wafer set corresponding to the product name with the smallest number of slots from the set of available boat slots, and then repeating steps 41 to 45 until the repair allocation is completed. After the repair allocation is completed, a compensation process is also performed at the previous layer site, and the steps of the compensation process include:

4. The advanced process control method of claim 3, wherein: Step five, forming a set of wafers at the previous layer site from all the wafers in the batch to be processed; ​ Step six, traversing all the compensation wafer boat slot sets; for each of the compensation wafer boat slot sets corresponding to each of the compensation process conditions of each of the product names, intersecting the inverse mapping set of the first mapping of the compensation wafer boat slot set and the wafer set of the previous layer station to form a compensation wafer intersection; if the compensation wafer intersection is not empty, all the wafers in the compensation wafer intersection are subjected to the compensation process according to the corresponding compensation process condition.

5. The advanced process control method of claim 4, wherein: After the compensation process is completed, before entering the operation of the next layer station, further comprising: Step seven, wafer boat slot verification, including: judging whether the wafer placed in each wafer boat slot is correct, when the wafer placed in the corresponding wafer boat slot belongs to the inverse mapping set of the first mapping of the compensation wafer boat slot set to which the wafer boat slot belongs in the compensation process, the wafer position is correct, otherwise the wafer position is incorrect.

6. The advanced process control method of claim 5, wherein: Step seven includes the following sub-steps: Forming a wafer set of the next layer station by all the wafers of the batch to be operated; Traversing various wafer cassette orders; Under each wafer cassette order, calculating a second mapping from the wafer boat slot set of the batch to the wafer set of the next layer station; Traversing each of the compensation wafer boat slot sets, if the second mapping set of the compensation wafer boat slot set is not equal to the inverse mapping set of the first mapping of the compensation wafer boat slot set under the corresponding compensation wafer boat slot set, it indicates that the wafer with position error; otherwise, the wafer position is correct; If the wafer position remains correct after traversing each of the compensation wafer boat slot sets under the corresponding wafer cassette order, the wafer boat slot verification is successful, and the wafer cassette order is used for subsequent operation of the next layer station.

7. The advanced process control method of claim 1, wherein: The first previous layer station includes an ion implantation station. The first next layer station includes a furnace tube station.

8. The advanced process control method of claim 7, wherein: The operation mode of the next layer station is a bottom-first mode or a top-first mode.

9. The advanced process control method of claim 3, wherein: In step 44, when forming the first mapping, it includes: Arranging the elements in the wafer set of the product name from small to large and arranging the elements in the wafer boat slot set of the product name from small to large, and then forming a one-to-one correspondence of the first mapping in order.

10. The advanced process control method of claim 3, wherein: In step 41, the initial value of the wafer boat slot set to be allocated is the wafer boat slot set of the batch.

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