SiC-based electronic device with improved electrical performance and method of manufacture

Abstract

The invention relates to a SiC-based electronic device with improved electrical performance and a method of manufacture. An electronic device is provided. An example electronic device has a semiconductor body of silicon carbide having a front surface, a first conductivity type and housing an active region and an edge region laterally to the active region along a first direction. The first terminal doped region extends at least partially in the edge region from the front surface into the semiconductor body, wherein the first terminal doped region has a second conductivity type different from the first conductivity type. A first metal region extends on the front surface over the active region and the first termination doped region, wherein the first metal region has a first thickness and interrupts over the first termination doped region along a first direction. The second metal region extends laterally to the first metal region along the first direction at a distance from the front surface over the edge region.

Description

[0001] Cross-references to (one or more) related applications

[0002] This application claims priority to Italian patent application No. 102024000014086, filed on June 19, 2024, entitled “ELECTRONIC DEVICE BASED ON SiCHAVING IMPROVED ELECTRICAL PERFORMANCES AND MANUFACTURING METHOD”, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure relates to a SiC-based electronic device with improved electrical performance and a method for manufacturing the electronic device. Background Technology

[0004] Silicon carbide (SiC) is gaining increasing attention in the semiconductor industry, particularly for the manufacture of electronic components such as diodes or transistors, especially for power applications.

[0005] Electronic devices formed in silicon carbide substrates of different polymorphisms (e.g., 3C-SiC, 4H-SiC, 6H-SiC) have various advantages, such as low on-resistance, low leakage current, high operating temperature and high operating frequency.

[0006] Figure 1 A section of a known type of electronic device (here exemplarily a JBS, "junction barrier Schottky" diode)1 is shown in a Cartesian (triaxial) reference frame with axes X, Y, and Z.

[0007] JBS device 1 includes an N-type SiC semiconductor body 3 having an upper surface 3A and a lower surface 3B. The semiconductor body 3 includes, for example, a substrate and one or more regions epitaxially grown on the substrate, the regions being N-type and having corresponding doping concentration values.

[0008] JBS device 1 also includes a plurality of junction barrier elements 9 (hereinafter also referred to as JB (junction-barrier) elements 9) in semiconductor body 3, which face the upper surface 3A and each element includes a corresponding P-type injection region in semiconductor body 3 and an ohmic contact (not shown) on the injection region at the level of the upper surface 3A of semiconductor body 3.

[0009] JBS device 1 also includes a first metallization portion 8, which extends on the upper surface 3A and is in electrical contact with JB element 9 via a corresponding ohmic contact (not shown).

[0010] The JBS device 1 further comprises an edge termination region 10 (or guard ring) entirely surrounding the JB element 9, in particular a P-type implanted region.

[0011] The edge termination region 10 has a doping level comprised between 10 15 and 10 18 atoms / cm2. 3

[0012] The Schottky diode 12 is formed at the interface between the first metallization 8 and the semiconductor body 3, where a semiconductor-metal Schottky junction is formed. The region of the JBS device 1 comprising the JB element 9 and the Schottky diode 12, i.e. the region comprised within the guard ring 10, is the active zone 4 of the JBS device 1.

[0013] The JBS device 1 further comprises a second metallization 6 extending on the lower surface 3B. The first metallization 8 and the second metallization 6 form respectively an anode and a cathode electrical terminal, which can be biased during the use of the JBS device 1.

[0014] The electrically passive region 16 extends outwardly towards the edge termination region 10.

[0015] The insulating layer 18, in particular silicon oxide (SiO2), extends partially over the edge termination region 10.

[0016] The first metallization 8 is in electrical contact with a portion of the edge termination region 10 not covered by the insulating layer 18, and also extends partially over the insulating layer 18.

[0017] The first metallization 8 has the same thickness above the active zone 4, where it serves as an anode metallization, and above the insulating layer 18, where it serves as a field plate region.

[0018] An interface layer 20, here made of silicon nitride (SiN), extends over the first metallization 8 and the insulating layer 18.

[0019] Furthermore, the JBS device 1 comprises a passivation layer 22, in particular polyimide, extending over the interface layer 20. In other words, the interface layer 20 acts as an interface between the passivation layer 22 and the underlying layers, here the first metallization 8 and the insulating layer 18.

[0020] Here, a protective layer 24, made of a resin such as for example phenoplast, extends over the passivation layer 22 to protect the JBS device 1 and form a package.

[0021] For example compared to the case where the passivation layer 22 extends directly on the upper surface 3A of the semiconductor body 3, the interface layer 20 ensures a good adhesion of the passivation layer 22.

[0022] ​However, the applicant has verified that certain critical conditions of use, thermal testing, or thermo-mechanical testing of JBS device 1 may cause the passivation layer 22 to peel off or partially separate from the interface layer 20 due to generated stress. This is particularly likely to occur at high operating temperatures (e.g., above 150°C). In addition to making JBS device 1 structurally vulnerable, this effect may also trigger unwanted discharges, rendering JBS device 1 inoperable or completely damaging its function.

[0023] In fact, the applicant has verified that under certain thermo-mechanical or mechanical stress conditions following the assembly process, one or more localized cracks appear across the entire thickness of the interface layer 20, which cause the generation of such discharges at the first metallization portion 8. This problem occurs particularly when the JBS device 1 is subjected to high thermal drift and high voltage difference under reverse bias conditions.

[0024] Therefore, we feel it is necessary to overcome the problems mentioned above. Summary of the Invention

[0025] According to this disclosure, a SiC-based electronic device and a method for manufacturing the same are provided, as defined in the appended claims. Attached Figure Description

[0026] To better understand this disclosure, embodiments will now be described by way of non-limiting example only with reference to the accompanying drawings, in which:

[0027] Figure 1 A cross-sectional view illustrates an electronic device of a known type;

[0028] Figure 2 An electronic device according to one embodiment is illustrated in a cross-sectional view; and

[0029] Figures 3A-3F A cross-sectional view is shown according to one embodiment. Figure 2 The manufacturing steps of electronic devices. Detailed Implementation

[0030] Figure 2 Electronic device 50 is shown. Electronic device 50 is a Schottky diode, particularly a JBS type Schottky diode; however, this description is not limited to this device and is also applicable to other types of electronic devices, particularly different types of Schottky diodes (e.g., MPS type), and even other electronic devices such as, for example, MOSFETs, IGBTs, PN diodes, PiN diodes, etc., especially vertical conduction type electronic devices for power applications.

[0031] In particular, Figure 2An end portion of an electronic device 50 is shown in a Cartesian reference system XYZ with orthogonal axes X, Y, and Z, which is arranged around a die in which the semiconductor material of the electronic device 50 is integrated.

[0032] The device 50 includes a semiconductor body 53 having a front surface 53a and a rear surface 53b that are spaced apart from each other along the Z-axis.

[0033] The semiconductor body 53 also includes a lateral surface 53c that is transverse to the front surface 53a, and particularly substantially orthogonal to the front surface 53a.

[0034] In detail, the lateral surface 53c laterally defines the semiconductor body 53 at one end along the X-axis.

[0035] The lateral surface 53c can be formed, for example, during the manufacturing process of the electronic device 50 after the step of cutting a wafer of semiconductor material.

[0036] The semiconductor body 53 is N-type or P-type silicon carbide (SiC) (hereinafter, N-type will be referred to only without limitation). In particular, the semiconductor body 53 is 4H-SiC type, but other polytypes such as 2H-SiC, 3C-SiC and 6H-SiC can be used.

[0037] exist Figure 2 In one embodiment, the semiconductor body 53 includes a substrate 53' and a drift region 53', the drift region 53' extending on the substrate 53' and formed, for example, by one or more epitaxial layers grown on the substrate 53'.

[0038] For example, substrate 53' may have a 1.10 18 atoms / cm 3 With 1.10 22 atoms / cm 3 The dopant concentration of the drift region 53” is between 100 μm and 450 μm, and the thickness along the Z-axis is between approximately 360 μm. The dopant concentration of the drift region 53” may be less than that of the substrate 53’, and the thickness along the Z-axis is between 5 and 20 μm.

[0039] The semiconductor body 53 includes an active region 54 and an edge region 55 extending laterally along the X-axis to the active region 54, particularly the edge region 55 monolithically connected to the active region 54.

[0040] exist Figure 2 In the diagram, for clarity, a dashed line parallel to the Z-axis separates the active region 54 from the edge region 55 in an indicative and non-restrictive manner.

[0041] The edge region 55 can extend around the active region 54, thus surrounding the active region 54.

[0042] In particular, Figure 2 In one embodiment, the edge region 55 may extend along the X-axis to the lateral surface 53c of the semiconductor body 53.

[0043] In this example, the metallization portion 57, forming the cathode metallization portion, is made of, for example, Ti / NiV / Ag or Ti / NiV / Au, and extends on the rear surface 53b. The metallization portion 57 may also include an ohmic contact layer (e.g., nickel silicide or titanium) extending in contact with the rear surface 53b.

[0044] Multiple barrier-doped regions 59' having conductivity opposite to that of the semiconductor body 53 (i.e., P-type here) extend from the front surface 53a into the semiconductor body 53 (particularly in the drift region 53") at a distance from each other along the X-axis.

[0045] The barrier doped region 59' along the X-axis may have a width, for example, between 0.5 μm and 10 μm.

[0046] In this embodiment, the electronic device 50 may optionally also include a corresponding ohmic contact region 59” for each barrier doped region 59’, which is accommodated in the barrier doped region 59’ at the front surface 53a.

[0047] Each doped region 59' and the corresponding ohmic contact region 59″ form a junction-barrier element 59, also referred to below as a JB (junction-barrier) element 59.

[0048] In embodiments where the electronic device 50 is a JBS or MPS type Schottky diode, the active region 54 can be defined as the portion of the semiconductor body 53 in which the JB element 59 is housed.

[0049] The electronic device 50 also includes an anode terminal region 62 with conductivity opposite to that of the semiconductor body 53 (i.e., P-type in this case), which extends into the semiconductor body 53 in the edge region 55, particularly in the drift region 53”.

[0050] The anode terminal region 62 can have a high dopant concentration, for example, including 10 17 With 10 21 atoms / cm 3 Between these regions, particularly in areas such as the formation of degraded semiconductor regions. In practice, from an electrical perspective, the anode terminal region 62 can exhibit metallic or quasi-metallic behavior.

[0051] The anode termination region 62 extends from the front surface 53a into the epitaxial region 53” at a certain distance from the barrier doped region 59’ along the X-axis. In particular, the anode termination region 62 extends between the barrier doped region 59’ and the lateral surface 53c of the semiconductor body 53 along a direction parallel to the X-axis.

[0052] exist Figure 2 In one embodiment, the anode terminal region 62 extends entirely within the edge region 55; in practice, the anode terminal region 62 laterally defines the active region 54.

[0053] However, the anode terminal region 62 may also extend partially into the active region 54, depending on the specific structure of the electronic device 50.

[0054] The anode terminal region 62 may have a width along the X-axis greater than that of the barrier doped region 59'; for example, it may be between 10 μm and 100 μm.

[0055] Electronic device 50 also includes an edge terminal area or a protective ring 63.

[0056] The edge terminal region 63 is formed by an additional doped region of type P, which extends from the front surface 53a into the drift region 53” in the edge region 55.

[0057] The dopant concentration in the edge termination region 63 can be lower than that in the anode termination region 62, for example, including 10. 15 With 10 18 atoms / cm 3 between.

[0058] In the plan view, on the XY plane, the edge terminal region 63 extends around the active region 54.

[0059] The edge terminal region 63 may partially cover the anode terminal region 62.

[0060] However, edge terminal region 63 is not required and can be omitted.

[0061] The electronic device 50 also includes a metal contact area 65 and a (metal) field plate area 72.

[0062] The metal contact region 65 extends and contacts the front surface 53a, extends both on the active region 54 and partially on the anode terminal region 62, and terminates above the anode terminal region 62.

[0063] In practice, the metal contact area 65 also extends partially above the edge area 55.

[0064] In detail, the metal contact area 65 includes an interface portion 66 extending directly on the front surface 53a and an upper portion 70 extending on the interface portion 66. The interface portion 66 is formed of a metal layer 67, such as titanium, nickel, Mo, TiN, MoN, V, Ta, W, WC, and the upper portion 70 is made of, for example, AlSiCu, AlCu, Al, or more generally an aluminum-based alloy.

[0065] The thickness of the interface portion 66 is less than the thickness of the upper portion 70.

[0066] The interface portion 66 may have a thickness (measured along the Z-axis) between, for example, 10 nm and 200 nm.

[0067] The upper portion 70 has a greater thickness than the interface portion 66, for example, between 2 μm and 10 μm. This ensures a reliable and robust electrical connection in the metal contact area 65.

[0068] Overall, the metal contact area 65 can have a thickness greater than or equal to 2 μm measured along the Z-axis.

[0069] The upper portion 70 extends from the active region 54 toward the outside of the electronic device 50 (i.e., toward the lateral surface 53c) in a direction parallel to the X-axis and terminates along the Z-axis toward the anode terminal region 62.

[0070] In particular, Figure 2 In one embodiment, the interface portion 66 moves away from the active region 54 in a direction parallel to the X-axis, extending beyond the upper portion 70; this feature is optional and can simplify obtaining the physical and electrical continuity between the metal contact region 65 and the metal field plate region 72 during manufacturing.

[0071] Multiple Schottky diodes 71 are formed at the interface between the semiconductor body 53 and the metal contact region 65, laterally positioned between the barrier doped regions 59'. Specifically, the Schottky diodes are formed from a semiconductor-metal junction formed by the portion of the semiconductor body 53 that is in direct contact with the metal contact region 65.

[0072] In practice, the metal contact area 65 forms the anode metallization part of the electronic device 50.

[0073] In addition, the metal contact area 65 is also in direct electrical contact with the JB element 59; in particular, it is in ohmic contact with the corresponding ohmic contact area 59”.

[0074] The field plate region 72 is made of metal and extends above the edge region 55 at a certain distance from the front surface 53a along the Z-axis.

[0075] In the illustrated embodiment, the field plate region 72 is formed by a raised portion of the metal layer 67 and is continuous with the interface portion 66. The fact that the field plate region 72 and the metal contact region 65 are formed by the same layer simplifies the manufacture of the electronic device 50.

[0076] The thickness of the field plate region 72 is less than the thickness of the metal contact region 65. Specifically, in this embodiment, the field plate region 72 has the same thickness as the interface portion 66. This thickness allows region 72 to effectively function as a field plate.

[0077] The interface 66 between the field plate region 72 and the metal layer is continuous, and therefore it is in direct electrical contact with the metal contact region 65.

[0078] The field plate region 72 extends beyond the anode terminal region 62 in a direction parallel to the X-axis. Specifically, in Figure 2 In one embodiment, the field plate region 72 terminates above the edge terminal region 63 and faces the edge terminal region 63 at a certain distance along the Z-axis.

[0079] The field plate region 72 can extend toward the lateral surface 53c in a direction parallel to the X-axis, and the width of the extension can be adjusted during the design process depending on the specific application.

[0080] For example, the field plate region 72 may terminate above (parallel to the Z-axis) the edge termination region 63, and the edge termination region 63 may extend beyond the field plate region 72 toward the lateral surface 53c (parallel to the X-axis). Specifically, the edge termination region 63 may extend beyond the field plate region 72 by a width measured along the X-axis in the direction of the lateral surface 53c, a width ranging from 0 μm (i.e., the outer boundary of the field plate region 72 may be aligned with the outer boundary of the edge termination region 63) to 50 μm, depending on the voltage level of the electronic device 50.

[0081] The electronic device 50 also includes multiple insulating layers 80, 81, 82, and 83.

[0082] An insulating layer 80 made of an electrically insulating or dielectric material (e.g., silicon oxide or TEOS-tetraethyl orthosilicate) extends directly over the front surface 53a of the semiconductor body 53 above the edge region 55.

[0083] The insulating layer 80 may have a thickness along the Z-axis, for example, between 0.1 μm and 5 μm.

[0084] In detail, the insulating layer 80 includes a portion 80A extending below the field plate region 72 and separating the field plate region 72 from the front surface 53a, and a portion 80B extending laterally to and continuously from the portion 80A on the edge region 55 in a direction parallel to the X-axis.

[0085] An insulating layer 81 of an electrically insulating or dielectric material (e.g., silicon oxide or TEOS-tetraethyl orthosilicate) extends over the front surface 53a of the semiconductor body 53.

[0086] The insulating layer 81 may have a thickness along the Z-axis ranging from, for example, 0.01 μm to 5 μm.

[0087] In detail, the insulating layer 81 includes a portion 81A extending over at least a portion of the metal contact region 65 above the active region 54 on the field plate region 72, and a portion 81B extending laterally to and continuously from portion 81A on a portion 80B of the insulating layer 80 in a direction parallel to the X-axis.

[0088] Since insulating layer 81 can be made of the same material as insulating layer 80, it may not be distinguishable from insulating layer 80 in the covered area; therefore, in Figure 2 The boundary between insulation layers 80 and 81 is indicated by a dashed line.

[0089] Insulating layer 82, also known as interface layer, is made of an electrically insulating or dielectric material different from insulating layer 81, such as nitride or oxynitride, especially silicon nitride, or aluminum oxide, hafnium oxide, etc.

[0090] The insulating layer 82 may have a thickness ranging from, for example, 0.01 μm to 5 μm.

[0091] Insulating layer 82 extends over insulating layer 81, particularly conformally over insulating layer 81.

[0092] In this embodiment, the insulating layer 82 also extends partly directly on the upper portion 70 of the metal contact area 65 and partly on the front surface 53a, next to the outer peripheral edges of the insulating layers 80, 81.

[0093] In detail, the insulating layer 82 includes a portion 82A extending over the metal regions 65, 72 and at a distance along the Z-axis toward the metal regions 65, 72, and a portion 82B extending laterally toward and continuous with portion 82A on a portion 81B of the insulating layer 81.

[0094] The insulating layer 83, also known as the passivation layer, is made of an electrically insulating or dielectric material, particularly an organic material, and even more particularly a polymeric material, such as, for example, polyimide (e.g., PIX).

[0095] The insulating layer 83 may have a flattened upper surface.

[0096] The insulating layer 83 may have a thickness ranging from, for example, 1 μm to 20 μm.

[0097] The insulating layer 83 includes portions 83A and 83B that completely cover the insulating layer 82, particularly those covering the corresponding portions 82A and 82B.

[0098] The insulating layer 83 may also extend partly over the active region 54 directly over the upper portion 70 of the metal contact region 65 and partly over the edge region 55 directly over the front surface 53a.

[0099] In practice, the insulating layer 82 extends between the passivation layer 83 and the underlying insulating layer (80, 81), and facilitates the adhesion of the overlying passivation layer 83.

[0100] One or more additional protective insulating layers (not shown here) may extend over the passivation layer 83 for encapsulating the electronic device 50. These protective insulating layers may be made of, for example, a resin such as bakelite.

[0101] In electronic device 50, the presence of a metal field plate region 72 that is thinner than the metal contact region 65 allows for a reduction in the risk of cracks in the insulation layers 80-83, particularly the insulation layer 82.

[0102] In fact, the thickness of the field plate region 72 forms a step within the insulating region formed by the insulating layers 80-83, particularly at the boundaries between the corresponding portions 81A and 82A facing the metal field plate region 72 and their corresponding adjacent portions 81B and 82B. The fact that the thickness of the field plate region 72 is lower than the thickness of the metal contact region 65 reduces the height of the step and thus reduces the risk of cracking.

[0103] This risk can be particularly reduced if the overlying insulation area includes a thin nitride layer that conforms to the contour of the underlying layer (e.g., insulation layer 82).

[0104] Even after multiple thermal cycles and / or harsh environmental conditions, the risk of cracking can remain low.

[0105] The absence of cracks ensures high electrical stability of the electronic device 50 during use; in fact, even in the presence of high voltage and possible delamination in the peripheral portion of the insulation layer 80-83, the metal regions 65 and 72 are still protected from discharges that could cause malfunction or damage to the electronic device 50.

[0106] Furthermore, the anode terminal region 62 can at least partially shield the overlying metal contact region 65 from the high electric field that may be generated by the semiconductor body 53 during use, especially under reverse bias. This helps to improve the electrical stability of the electronic device 50 during use.

[0107] If the anode terminal region 62 has a high doping level (e.g., including 10), 17 With 1021 atoms / cm 3 If the time frame is between (the two points), then this effect can be even more beneficial.

[0108] The presence of three insulating layers (insulation layers 80-83) further protects the electronic device 50 from the influence of the external environment, and in particular prevents moisture from reaching the high-voltage structure and metallized parts (65, 72).

[0109] This protection is likely to be more evident when the insulating layer 81 seals and covers the periphery of the metallized portion 65; when the insulating layer 82 seals and covers the top of the insulating layer 81 and its lateral edges; and, in particular, when the insulating layer 83 seals and covers the top of the insulating layer 82 and its lateral edges.

[0110] The following text is for reference only. Figure 3A-3F The manufacturing steps of the electronic device 50 are described, but are limited to those useful for understanding this disclosure.

[0111] refer to Figure 3A The wafer 100 has been pre-processed to form JB element 59, anode terminal region 62 and edge terminal region 63 in the semiconductor body 53 of SiC in a manner known per se.

[0112] Subsequently, Figure 3B An insulating layer 80 is formed on the front surface 53a.

[0113] The insulating layer 80 can be formed by blanket deposition of insulating or dielectric materials, for example by CVD (chemical vapor deposition) or LPCVD (low-pressure chemical vapor deposition) and subsequent patterning (e.g., photolithography and etching).

[0114] refer to Figure 3C A metal layer 67, such as titanium or nickel, is deposited on wafer 100. This metal layer 67 covers the front surface 53a and the insulating layer 80. An upper metal layer 105 is then deposited on the metal layer 67 (this layer will form...). Figure 1 The upper portion 70 of the metal contact area 65.

[0115] In detail, metal layers 67 and 105 are deposited in a blanket manner by evaporation or sputtering.

[0116] Then, Figure 3D The upper metal layer 105 is patterned by photolithography and etching steps in such a way that the upper portion 70 of the metal contact region 65 formed above the active region 54 and partially extending over the anode terminal region 62 is patterned.

[0117] Partial removal of the upper metal layer 105 exposes the underlying metal layer 67 above the edge region 55.

[0118] existFigure 3E In this process, the metal layer 67 is patterned by photolithography and etching steps in order to form the field plate region 72.

[0119] Subsequently, Figure 3F Insulating layers 81, 82, and 83 are formed, for example, by deposition and subsequent patterning.

[0120] The manufacturing process then continues with subsequent steps to form additional components of the electronic device 50 (not described in detail here) (e.g., forming an ohmic contact layer 56 and a cathode metallization portion 57) and to cut the wafer 100 to form the electronic device 50.

[0121] This manufacturing process allows for the production of electronic devices 50 in a simple and cost-effective manner.

[0122] In particular, the fact that the field plate region 72 is formed starting from the same metal layer 67 used for the metal contact region 65 allows for the easy acquisition of a metal field plate region that is thinner than the metal contact region 65.

[0123] In fact, maintaining a thickness greater than that of the metal contact area 65 can facilitate the electrical connection operation of the electronic device 50 (e.g., via wire bonding).

[0124] Finally, it is clear that modifications and variations may be made to the electronic devices described and illustrated herein and their manufacturing processes without departing from the scope of this disclosure as defined by the appended claims.

[0125] For example, the insulating region above the front surface 53a may include different numbers of insulating layers made of different materials, particularly two insulating layers (e.g., layers 82 and 83 only) above the metal regions 65 and 82. For example, layer 81 may be absent; in this case, layer 82 (e.g., nitride or oxynitride) may extend directly over the metal regions 65 and 72 and over the portion 80B of the metal layer 80.

Claims

1. An electronic device, comprising: A silicon carbide semiconductor body having a front surface and a first conductivity type, the semiconductor body accommodating an active region and an edge region laterally directed toward the active region along a first direction; A first terminal doped region extends at least partially from the front surface into the semiconductor body within the edge region, and the first terminal doped region has a second conductivity type different from the first conductivity type; A first metal region extends over the front surface of the semiconductor body, over the active region and the first terminal doped region, wherein the first metal region has a first thickness and is interrupted over the first terminal doped region along the first direction. The second metal region extends laterally toward the first metal region along the first direction at a certain distance above the edge region from the front surface. as well as The second metal region has a second thickness that is less than the first thickness.

2. The electronic device of claim 1, further comprising an insulating region having a first portion extending over the first metal region and the second metal region, and a second portion extending laterally to the first portion along the first direction and over the edge region on the front surface.

3. The electronic device according to claim 1, wherein, The first metal region has a thickness of 2 μm or more.

4. The electronic device according to claim 1, wherein, The second metal region has a thickness between 10 nm and 200 nm.

5. The electronic device according to claim 1, wherein, The second metal region is in electrical contact with the first metal region.

6. The electronic device according to claim 1, wherein, The first metal region includes a first metal layer and a second metal layer on the first metal layer, and the second metal region includes a third metal layer adjacent to the first metal layer and made of the same material as the first metal layer.

7. The electronic device according to claim 1, wherein, The first terminal doped region has a value greater than 10 17 atoms / cm 3 The doping level.

8. The electronic device according to claim 1, wherein, The electronic device is a JBS or MPS type Schottky diode.

9. The electronic device according to claim 1, wherein, The first metal region is in contact with the semiconductor host Schottky in the active region.

10. The electronic device of claim 1, further comprising a plurality of barrier-doped regions extending from the front surface into the active region of the semiconductor body, spaced apart from each other along the first direction, the barrier-doped regions having the second conductivity type.

11. A method of manufacturing an electronic device, comprising: Starting with a silicon carbide semiconductor body having a front surface and a first conductivity type, wherein the semiconductor body contains an active region and an edge region laterally directed toward the active region along a first direction; A first terminal doped region is formed, extending at least partially from the front surface into the semiconductor body within the edge region, the first terminal doped region having a second conductivity type different from the first conductivity type; A first metal region is formed on the front surface of the semiconductor body, extending over the active region and the first terminal doped region, wherein the first metal region has a first thickness and is interrupted over the first terminal doped region along the first direction; as well as A second metal region is formed, which extends laterally toward the first metal region along the first direction above the edge region at a certain distance from the front surface; as well as The second metal region has a second thickness that is less than the first thickness.

12. The manufacturing method according to claim 11, wherein, The formation of the first metallic region includes: A first metal layer is deposited on the front surface of the semiconductor body; and A second metal layer having a thickness greater than that of the first metal layer is deposited on the first metal layer.

13. The manufacturing method according to claim 12, wherein, The second metal region is formed from a portion of the first metal layer through patterning of the first metal layer.

14. The manufacturing method according to claim 12, wherein, The formation of the second metallic region includes: Before depositing the first metal layer, a first insulating layer is formed on the front surface; and The first metal layer is also deposited on a portion of the first insulating layer.

15. The manufacturing method according to claim 12, wherein, Forming the first metal region and the second metal region includes: Perform blanket deposition of the first metal layer; Perform blanket deposition of the second metal layer on the first metal layer; Etching the second metal layer; and After etching the second metal layer, the first metal layer is etched such that the first metal region includes a first portion of the first metal layer extending on the front surface and a portion of the second metal layer extending over the first portion of the first metal layer, and the second metal region includes a second portion of the first metal layer extending at a distance from the front surface.

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