Level shift circuit

Abstract

The level shift circuit includes a first P-type transistor to a sixth P-type transistor, a first N-type transistor, a second N-type transistor, a first resistor, and a second resistor. The first P-type transistor and the first N-type transistor are disposed between the input node and the output node. The second P-type transistor is disposed between the third power supply and the output node. The third P-type transistor is disposed between the first power supply and the output node. The first resistor is disposed between the third node and the output node. The fourth P-type transistor and the second N-type transistor are disposed between the inverting input node and the inverting output node. A fifth P-type transistor is disposed between the third power supply and the inverted output node. The sixth P-type transistor is disposed between the first power supply and the inverted output node. The second resistor is arranged between the sixth node and the inverted output node.

Description

TECHNICAL FIELD

[0001] The present application relates to a level shift circuit that converts the voltage of a signal to a desired level when transmitting the signal between circuits supplied with different power supply voltages. BACKGROUND

[0002] A level shift circuit is provided, for example, in an interface section that transmits a signal from a circuit operating at a relatively low voltage inside an LSI to a circuit operating at a relatively high voltage outside the LSI, which level shift circuit is used when converting the voltage of the signal.

[0003] In recent years, as transistors are increasingly miniaturized, the voltage stress (voltage resistance) that transistors can tolerate has decreased. In this background, as a prior art document, a level shift circuit that performs voltage conversion within a prescribed voltage resistance range is disclosed.

[0004] The level shift circuit of Patent Document 1 is configured to perform step-up conversion on a low-level voltage in addition to a high-level voltage. In this way, by lowering the voltage between the low and high levels, the voltage applied between the terminals of a transistor (for example, between the gate and source, or between the source and drain) is lowered, and the voltage stress on the transistor is alleviated.

[0005] PRIOR ART DOCUMENT

[0006] PATENT DOCUMENT

[0007] Patent Document 1: U.S. Patent No. 7151391 SUMMARY

[0008] PROBLEMS TO BE SOLVED BY THE INVENTION

[0009] However, in the case of the configuration of Patent Document 1, Figure 1 the following technical problem arises, that is, the operation of the level shift circuit cannot keep up with the decrease in the operating voltage accompanying the demand for low power consumption and / or the increase in the speed of circuit operation accompanying the demand for high functionality.

[0010] An object of the present disclosure is to solve the above technical problem.

[0011] TECHNICAL SOLUTION TO THE PROBLEM

[0012] The level shift circuit according to the present disclosure is configured to perform voltage conversion on a high-level voltage and a low-level voltage.The level shift circuit of one aspect of the present disclosure includes: an input node that receives an input signal that is switched between a first power supply and a second power supply that is lower in potential than the first power supply; a first N-type transistor provided between the input node and an output node, a gate of the first N-type transistor being connected to the first power supply; a first P-type transistor provided in parallel with the first N-type transistor between the input node and the output node, a gate of the first P-type transistor being connected to the input node via a first node; a first resistor provided between the first node and the output node; a second P-type transistor provided between a third power supply that is higher in potential than the first power supply and the output node, a gate of the second P-type transistor being connected to an inverted output node; a third P-type transistor provided between the first power supply and the output node, a gate of the third P-type transistor being connected to the output node via a second node; an inverted input node that receives an inverted input signal that is inverted from the input signal; a second N-type transistor provided between the inverted input node and the inverted output node, a gate of the second N-type transistor being connected to the first power supply; a fourth P-type transistor provided in parallel with the second N-type transistor between the inverted input node and the inverted output node, a gate of the fourth P-type transistor being connected to the inverted input node via a third node; a second resistor provided between the third node and the inverted output node; a fifth P-type transistor provided between the third power supply and the inverted output node, a gate of the fifth P-type transistor being connected to the output node; and a sixth P-type transistor provided between the first power supply and the inverted output node, a gate of the sixth P-type transistor being connected to the inverted output node via a fourth node.

[0013] In the level shift circuit of the present aspect, in operation in which the input signal changes from low to high, the fourth P-type transistor is turned on together with the second N-type transistor when the input signal changes from low to high, and thus the falling speed of the signal at the inverted output node becomes fast. Thus, the second P-type transistor is turned on early, and the rising speed of the output signal becomes fast. In addition, since the gate-source voltage (Vgs) of the second P-type transistor when it is turned on is higher than that of the patent document 1, the switching operation becomes fast, and the rising speed of the output signal becomes fast. At this time, since the first P-type transistor is turned off, the rising of the output signal is not hindered.

[0014] Because the circuit connected to the input node and the circuit connected to the inverting input node are symmetrical, the level shifting circuit in this aspect works in the same way when the input signal changes from high level to low level, and the output signal drops faster.

[0015] Furthermore, the level shifting circuit of this aspect consists of two power supplies, a first power supply and a third power supply, and does not use a bias voltage (equivalent to VBIAS in Patent Document 1). In other words, there is no need for a circuit to generate a bias voltage.

[0016] -The effects of the invention-

[0017] In this disclosure, the operating voltage is reduced and / or the circuit operation is accelerated in the level shifting circuit. Attached Figure Description

[0018] Figure 1 This is a circuit diagram illustrating one example of the structure of the level shifting circuit according to the first embodiment.

[0019] Figure 2 This is a diagram showing one example of the voltage waveforms at various nodes of a level shifting circuit.

[0020] Figure 3 This is a circuit diagram illustrating one example of the structure of the level shifting circuit according to the second embodiment.

[0021] Figure 4 This is a circuit diagram illustrating one example of the structure of the level shifting circuit according to the third embodiment.

[0022] Figure 5 This is a circuit diagram illustrating one example of the structure of the level shifting circuit according to the fourth embodiment.

[0023] Figure 6 This is a circuit diagram showing a modified example of the level shifting circuit according to the fourth embodiment.

[0024] Figure 7 This is a circuit diagram illustrating one example of the structure of the level shifting circuit according to the fifth embodiment.

[0025] Figure 8 This is a circuit diagram illustrating one example of the structure of a selector circuit.

[0026] Figure 9 This is a circuit diagram showing a modified example of the level shifting circuit according to the fifth embodiment. Detailed Implementation

[0027] The implementation methods will now be described. It should be noted that the specific numerical values ​​shown in the following embodiments are merely examples for easy understanding of the invention and are not intended to limit the scope of the invention. It should also be noted that in the following description, sometimes the nodes of the circuit and the signals passing through those nodes are described with the same name. Sometimes the power supply name and the power supply voltage are described with the same symbol.

[0028] <First Implementation>

[0029] Level shifting circuit 1 is a circuit consisting of a first power supply VDD and a third power supply VDDIO. It boosts the high-level voltage from VDD to VDDIO and boosts the low-level voltage from VSS to VDD. The third power supply VDDIO has a higher voltage than the first power supply VDD. It should be noted that in the following description, low level may sometimes be abbreviated as 'L' and high level as 'H'.

[0030] The level shifting circuit 1 receives the input signal IN, which is converted between the first power supply VDD and ground VSS (equivalent to the second power supply), from the input terminal IN (input node in), and outputs the received signal OUT, which is converted between the third power supply VDDIO and the first power supply VDD, from the output terminal OUT (output node out). In other words, the input signal IN is a signal with an amplitude of VDD, and the output signal OUT is a signal with an amplitude of (VDDIO - VDD).

[0031] Figure 1 An example of a circuit diagram of the level shifting circuit 1 according to the first embodiment is shown.

[0032] The level shifting circuit 1 includes a first circuit 10, a second circuit 20, and an inverter 3 that inverts the input signal IN to generate an inverted input signal NIN.

[0033] Inverter 3 receives the input signal IN as input and outputs the inverted input signal NIN to the second circuit 20. The power supply terminal of inverter 3 is connected to the first power supply VDD, and the ground terminal of inverter 3 is connected to ground VSS. It should be noted that it can also be obtained from... Figure 1 Inverter 3 is omitted. For example, it can also be configured such that the input signal IN and the inverted input signal NIN are generated in the pre-stage circuit (not shown) of the level shift circuit 1, and the input signal IN and the inverted input signal NIN are input to the level shift circuit 1. The same applies in other figures (other embodiments).

[0034] The first circuit 10 and the second circuit 20 are symmetrical to each other. The circuits will now be described with reference to the accompanying drawings.

[0035] - First Circuit -

[0036] The first circuit 10 includes N-type transistors N11 and N12, P-type transistors P11 to P15, and resistor R11.

[0037] The N-type transistor N11 (equivalent to the first N-type transistor) and the P-type transistor P11 (equivalent to the first P-type transistor) are located between the input node in and the output node out.

[0038] N-type transistor N11 and P-type transistor P11 share a common drain and source. Specifically, the source of N-type transistor N11 and the drain of P-type transistor P11 are shared and connected to the input node in. The drain of N-type transistor N11 and the source of P-type transistor P11 are shared and connected to node n2 (equivalent to the second node). The gate of N-type transistor N11 is connected to the first power supply VDD. The gate of P-type transistor P11 is connected to node n1 (equivalent to the first node).

[0039] It should be noted that in this disclosure, "connection" broadly encompasses the concept of electrical connection, including not only direct connections but also indirect electrical connections via passive components. For example, such as... Figure 1 As shown, “node n2 is connected to output node out” includes the structure in which node n2 is connected to output node out via P-type transistor P14.

[0040] P-type transistor P12 (equivalent to the second P-type transistor) is located between the third power supply VDDIO and the output node out. The gate of P-type transistor P12 is connected to the inverting output node outb.

[0041] P-type transistor P13 (equivalent to the third P-type transistor) is located between the first power supply VDD and the output node out, and the gate of P-type transistor P13 is connected to node n2.

[0042] P-type transistor P14 (equivalent to the seventh P-type transistor) is located between node n2 and output node out. The gate of P-type transistor P14 is connected to the first power supply VDD. It should be noted that P-type transistor P14 can also be omitted, but by setting P-type transistor P14, the electrical connection between the first power supply VDD and input node in via P-type transistor P13 and N-type transistor N11 is cut off.

[0043] An N-type transistor N12, a P-type transistor P15, and a resistor R11 are connected in series between the input node in and the node n2.

[0044] An N-type transistor N12 (equivalent to the third N-type transistor) is positioned between the input node in and node n4 (equivalent to the fifth node), with its gate connected to the first power supply VDD. A P-type transistor P15 (equivalent to the eighth P-type transistor) is positioned between node n4 and node n1, with its gate connected to the first power supply VDD. It should be noted that N-type transistor N12 and P-type transistor P15 can be omitted, but their inclusion accelerates the voltage drop at node n1.

[0045] Resistor R11 (equivalent to the first resistor) is placed between nodes n1 and n2. Resistor R11 is connected to the output node out via node n2 and P-type transistor P14. In other words, resistor R11 is placed between node n1 and the output node out. Resistor R11 can be any element that functions as a resistor and is not particularly limited. For example, in addition to a resistive element, a conducting resistor or diode that keeps the transistor always conducting can also be used as resistor R11. The same applies to resistor R21, which will be described later.

[0046] -Second Circuit-

[0047] As described above, the second circuit 20 has a structure symmetrical to the first circuit 10. The second circuit 20 includes N-type transistors N21 and N22, P-type transistors P21 to P25, and resistor R21.

[0048] The N-type transistor N21 (equivalent to the second N-type transistor) and the P-type transistor P21 (equivalent to the fourth P-type transistor) are located between the inverting input node inb and the inverting output node outb.

[0049] N-type transistor N21 and P-type transistor P21 share a common drain and source. Specifically, the source of N-type transistor N21 and the drain of P-type transistor P21 are shared and connected to the inverting input node inb. The drain of N-type transistor N21 and the source of P-type transistor P21 are shared and connected to node n2b (equivalent to the fourth node). The gate of N-type transistor N21 is connected to the first power supply VDD. The gate of P-type transistor P21 is connected to node n1b (equivalent to the third node).

[0050] P-type transistor P22 (equivalent to the fifth P-type transistor) is located between the third power supply VDDIO and the inverting output node outb. The gate of P-type transistor P22 is connected to the output node out.

[0051] P-type transistor P23 (equivalent to the sixth P-type transistor) is located between the first power supply VDD and the inverting output node outb, and the gate of P-type transistor P23 is connected to node n2b.

[0052] P-type transistor P24 (equivalent to the ninth P-type transistor) is located between node n2b and the inverting output node outb. The gate of P-type transistor P24 is connected to the first power supply VDD. It should be noted that P-type transistor P24 can also be omitted, but by setting P-type transistor P24, the electrical connection between the first power supply VDD and the inverting input node inb via P-type transistor P23 and N-type transistor N21 is broken.

[0053] An N-type transistor N22, a P-type transistor P25, and a resistor R21 are connected in series between the inverting input node inb and node n2b.

[0054] An N-type transistor N22 (equivalent to the fourth N-type transistor) is positioned between the inverting input node inb and node n4b (equivalent to the sixth node), with its gate connected to the first power supply VDD. A P-type transistor P25 (equivalent to the tenth P-type transistor) is positioned between node n4b and node n1b, with its gate connected to the first power supply VDD. It should be noted that both N-type transistor N22 and P-type transistor P25 can be omitted, but their inclusion accelerates the voltage drop at node n1b.

[0055] Resistor R21 (equivalent to a second resistor) is placed between nodes n1b and n2b. Resistor R21 is connected to the inverting output node outb via node n2b and P-type transistor P24. In other words, resistor R21 is placed between node n1b and the inverting output node outb.

[0056] [Operation of the level shifting circuit]

[0057] Next, the operation of the level shifting circuit 1 involved in this embodiment will be explained.

[0058] -Work Example (1-1)-

[0059] The operation will be explained when the input 'L' is used as the input signal IN and the output 'L' is used as the output signal OUT, that is, when the input signal voltage is VSS and the output signal voltage is VDD. In the following explanation, the gate-source voltage Vgs of the transistor will be simply referred to as "Vgs".

[0060] In the first circuit 10, since the input signal IN is 'L', N-type transistors N11 and N12 are turned on, and nodes n1, n2, and n4 become 'L' (voltage VSS), while P-type transistor P13 is turned on. Therefore, the voltage at the output node OUT becomes VDD. That is, 'L' (voltage VDD) is output from the output terminal OUT.

[0061] In the second circuit 20, since the voltage at the output node out is VDD, P-type transistors P22, P24, and P25 are turned on. Therefore, the voltages at nodes n1b, n2b, n4b, and the inverting output node outb become VDDIO. Additionally, the inverting input signal NIN is 'H', and the voltage at the inverting input node inb is VDD.

[0062] -Work Example (1-2)-

[0063] The operation is explained when the input signal 'H' is used as the input signal IN and the output signal 'H' is used as the output signal OUT, that is, when the input signal voltage is VDD and the output signal voltage is VDDIO.

[0064] In the second circuit 20, since the inverting input signal NIN is 'L', N-type transistors N21 and N22 are turned on, and nodes n1b, n2b, and n4b become 'L' (voltage VSS), while P-type transistor P23 is turned on. Therefore, the voltage at the inverting output node outb becomes VDD.

[0065] In the first circuit 10, since the voltage at the inverting output node outb is VDD, P-type transistors P12, P14, and P15 are turned on. Therefore, the voltages at nodes n1, n2, n4, and the output node out become VDDIO. In other words, 'H' (VDDIO) is output from the output terminal OUT.

[0066] -Work Examples (1-3)-

[0067] Reference Figure 2 The solid-line waveform illustrates the operation when the input signal IN changes from 'L' to 'H' and the output signal OUT changes from 'L' to 'H'. In this case, the input signal voltage changes from VSS to VDD, and the output signal voltage changes from VDD to VDDIO.

[0068] In the first circuit 10, when the input signal IN begins to rise from 'L' to 'H', the voltages at nodes n1, n2, and n4 begin to rise along with the input signal IN (see time t1). Consequently, the Vgs (Vgs = VDD - VIN) of N-type transistors N11 and N12 begins to decrease. Here, VIN is the voltage of the input signal IN. When the Vgs of N-type transistors N11 and N12 is less than the threshold, N-type transistors N11 and N12 are turned off, and therefore the voltage rise at nodes n1, n2, and n4 temporarily stops (see times t2 to t3).

[0069] In the second circuit 20, when the inverting input signal NIN starts to decrease from 'H' to 'L', the voltages at nodes n1b, n2b, n4b, and the inverting output node outb begin to decrease along with the inverting input signal NIN (refer to time t2). Furthermore, when the Vgs of the P-type transistor P22 is less than the threshold, the P-type transistor P22 is turned off.

[0070] In the first circuit 10, when the voltage at the inverting output node outb drops, causing Vgs of P-type transistor P12 to exceed the threshold, P-type transistor P12 turns on. As a result, the output signal OUT begins to rise from 'L' to 'H' (refer to time t1 to time t2). When the output signal OUT rises, causing Vgs of P-type transistor P14 to exceed the threshold, P-type transistor P14 turns on. As a result, the voltage rise at the previously stagnant nodes n1 and n2 accelerates (refer to time t3). When the voltage at node n2 rises, causing Vgs of transistor P13 to fall below the threshold, transistor P13 turns off. As a result, the connection between the third power supply VDDIO and the first power supply VDD via P-type transistors P12 and P13 becomes non-conductive, and the voltage of the output signal OUT rises to VDDIO. That is, the output signal OUT becomes 'H'.

[0071] Here, in the first circuit 10, the voltage at node n1 rises along with the voltage at node n4, so the Vgs of the P-type transistor P11 is less than the threshold, causing the P-type transistor P11 to be turned off. As a result, VDDIO becomes non-conductive with the input node in, and the voltage rise of the output signal OUT is not hindered and delayed (refer to time t3 to time t4).

[0072] In the second circuit 20, as described above, the voltages at nodes n1b, n4b, and the inverting output node outb decrease. When the Vgs of P-type transistors P24 and P25 is less than the threshold, P-type transistors P24 and P25 are turned off. On the other hand, since N-type transistor N21 is turned on, the voltages at nodes n1b and n2b decrease to VSS (reference time t4). When the voltage at node n2b decreases, causing the Vgs of P-type transistor P23 to exceed the threshold, P-type transistor P23 is turned on. Therefore, the voltage at the inverting output node outb decreases to VDD (reference time t4).

[0073] Here, because there is a resistor R21 between nodes n2b and n1b, a voltage drop is generated across resistor R21 due to the discharge current flowing from node n2b to the inverting input node inb (VSS). Therefore, the resistance value of resistor R21 is set such that the potential difference between nodes n1b and n2b exceeds the threshold value of Vgs of the P-type transistor P21. This turns on the P-type transistor P21, and the N-type transistor N21 conducts in parallel with the P-type transistor P21. As a result, the voltage drop rate at node n2b increases, and in conjunction with the conduction of the P-type transistor P23, it accelerates the voltage drop at the inverting output node outb (refer to times t2 to t4).

[0074] It should be noted that, as mentioned above, since P-type transistors P24 and P25 are turned off as the voltage at the inverting output node outb decreases, the connection between the first power supply VDD and the inverting input node inb via P-type transistor P23 becomes non-conductive.

[0075] -Work Examples (1-4)-

[0076] The operation is explained when the input signal IN changes from 'H' to 'L' and the output signal OUT changes from 'H' to 'L'. In this case, the voltage of the input signal changes from VDD to VSS, and the voltage of the output signal changes from VDDIO to VDD.

[0077] As described above, the first circuit 10 and the second circuit 20 are structurally symmetrical. Furthermore, when the input signal IN changes from 'H' to 'L', the inverting input signal NIN changes from 'L' to 'H'. Therefore, compared to operating examples (1-3), in this operating example, the first circuit 10 and the second circuit 20 perform opposite operations. That is, in Figure 2Although there is a deviation in the input timing between the input node in and the inverting input node inb in the voltage waveform, the work of swapping the input node in and the inverting input node inb, swapping the node n4 and the node n4b, swapping the node n1 and the node n1b, swapping the node n2 and the node n2b, and swapping the output node out and the inverting output node outb is carried out.

[0078] - Functions and effects of the first embodiment -

[0079] As described above, according to this embodiment, high-speed operation of the level shifting circuit 1 can be achieved.

[0080] Specifically, in the operating examples (1-3), when the N-type transistor N21 is turned on, the P-type transistor P21 is turned on in parallel, thus the signal at the inverting output node outb falls faster, and the P-type transistor P12 turns on earlier. Therefore, the rise speed of the output signal OUT is faster. Furthermore, since Vgs(VDDIO - VDD) when the P-type transistor P12 is turned on is higher than the Vgs(VDDIO - VBIAS) of the transistor in Patent Document 1, the switching operation is faster. Therefore, the rise speed of the output signal OUT is even faster. Additionally, when the output signal OUT rises, the P-type transistor P11 is turned off, so VDDIO and the input node in (voltage VDD) become non-conductive, and the rise of the output signal OUT is not hindered.

[0081] Similarly, in operating examples (1-4), when the N-type transistor N11 is turned on, the P-type transistor P11 is turned on in parallel, thus the signal at node n2 falls faster, and the P-type transistor P13 turns on earlier. Therefore, the output signal OUT falls faster. Furthermore, since Vgs(VDDIO - VDD) when the P-type transistor P22 is turned on is higher than the Vgs(VDDIO - VBIAS) of the transistor in Patent Document 1, the switching operation is faster. Therefore, the voltage at the inverting output node outb rises faster. Additionally, when the inverting output signal outb rises, the P-type transistor P21 is turned off, so VDDIO and the inverting input node inb (voltage VDD) become non-conductive, and the rise of the signal at the inverting output node outb is not hindered.

[0082] Furthermore, the level shifting circuit 1 in this embodiment is composed of two power supplies: a first power supply VDD and a third power supply VDDIO. That is, since a bias voltage (VBIAS) is not used as in Patent Document 1, there is no need to design and install a bias generation circuit inside the LSI to generate the bias voltage.

[0083] <Second Implementation>

[0084] Figure 3 An example circuit diagram of the level shifting circuit 1 according to the second embodiment is shown. Figure 3 In the middle, to and Figure 1 The corresponding structures are labeled with the same symbols. The following description focuses on the differences from the first embodiment. It should be noted that regarding the... Figure 1 and Figure 3 The use of the same symbols for components (e.g., transistors, inverters) does not imply that they must be identical in various design / process parameters. In other words, the scope of this disclosure includes configurations where... Figure 1 and Figure 3 The various parameters of components marked with the same symbol in Figure 1 and Figure 3 They are all different from each other. The relationships between the other attached figures are also the same.

[0085] Compared to the first embodiment, the level shifting circuit 1 in this embodiment is configured to make the output signal OUT rise faster from 'L' to 'H'.

[0086] In the structure of the first embodiment, when the signal rises at nodes n1 and n2, the Vgs of P-type transistor P11 exceeds the threshold due to the voltage drop across resistor R11, resulting in a period during which P-type transistor P11 is turned on. When P-type transistor P11 is turned on, node n2 and input node in are also turned on. Therefore, during this period, the voltage rise at node n2 becomes slow, and the turn-off of P-type transistor P13 is sometimes delayed. This creates a period during which the third power supply VDDIO and the first power supply VDD are turned on via P-type transistors P12 and P13, which can sometimes affect the increase in the rise rate of the output signal OUT.

[0087] Therefore, in this embodiment, from the viewpoint of accelerating the rise of the output signal OUT, a short-circuit circuit of resistors R11 and R21 is added to the structure of the first embodiment.

[0088] Specifically, in this embodiment, based on the structure of the first embodiment, a short-circuit circuit consisting of a P-type transistor P16 and a buffer B11 is added to the first circuit 10. Similarly, in the second circuit 20, a short-circuit circuit consisting of a P-type transistor P26 and a buffer B21 is added.

[0089] - First Circuit -

[0090] The P-type transistor P16 (equivalent to the eleventh P-type transistor) is connected in parallel with the resistor R11. In other words, the resistor R11 and the P-type transistor P16 are connected in parallel between node n1 and node n2.

[0091] Buffer B11 (equivalent to the first buffer) is located between the output node out and the gate of P-type transistor P16. The power supply terminal of buffer B11 is connected to the third power supply VDDIO, and the ground terminal of buffer B11 is connected to the first power supply VDD.

[0092] -Second Circuit-

[0093] P-type transistor P26 (equivalent to the twelfth P-type transistor) is connected in parallel with resistor R21. In other words, resistor R21 and P-type transistor P26 are connected in parallel between node n1b and node n2b.

[0094] Buffer B21 (equivalent to a second buffer) is positioned between the inverting output node outb and the gate of the P-type transistor P26. The power supply terminal of buffer B21 is connected to the third power supply VDDIO, and the ground terminal of buffer B21 is connected to the first power supply VDD.

[0095] [Operation of the level shifting circuit]

[0096] Next, refer to Figure 2 The operation of the level shifting circuit 1 involved in this embodiment will be explained. Figure 2 From time t1 to time t4, the characteristics of the voltage waveform involved in this embodiment are shown using dashed lines. Here, the description will focus on the differences in operation between this embodiment and the level shifting circuit 1 involved in the first embodiment.

[0097] -Work Example (2-1)-

[0098] The operation is the same as the operation example (1-1) of the first embodiment when 'L' is input as the input signal IN.

[0099] At this time, since the output signal OUT is 'L' (voltage VDD) and the voltage at nodes n2 and n1 is VSS, the P-type transistor P16 is turned off. Furthermore, since the voltage at the inverting output node outb and nodes n2b and n1b is VDDIO, the P-type transistor P26 does not function.

[0100] - Work Example (2-2) -

[0101] The operation is the same as the operation example (1-2) of the first embodiment when 'H' is input as the input signal IN.

[0102] At this time, since the output signal OUT is 'H' (voltage VDDIO), and the voltages at nodes n2 and n1 are VDDIO, the P-type transistor P16 does not function. Additionally, since the voltage at the inverting output node outb is VDD, and the voltages at nodes n2b and n1b are VSS, the P-type transistor P26 is turned off.

[0103] - Work Example (2-3) -

[0104] The operation will be explained when the input signal IN changes from 'L' to 'H'. Here, the explanation will focus on the differences from the first embodiment.

[0105] In the first circuit 10, the voltage of the output signal OUT is input to the gate of the P-type transistor P16 after a delay of the buffer B11. That is, after the output signal OUT begins to rise (referring to time t2), during a predetermined period, the input 'L' (voltage VDD) turns on the P-type transistor P16, thus short-circuiting the two ends of resistor R11. Thus, as... Figure 2 As shown by the dashed line, the voltage rise at node n1 becomes faster than in the first embodiment's operating example (1-3). Consequently, the P-type transistor P11 is turned off without a potential difference between nodes n1 and n2, thus the voltage rise at node n2 is faster. As a result, the P-type transistor P13 turns off earlier, and the output signal OUT rises faster.

[0106] In the second circuit 20, the voltage at the inverting output node outb is input to the gate of the P-type transistor P26 after a delay of the buffer B21. That is, during a predetermined period after the voltage at the inverting output node outb begins to drop, 'H' (voltage VDDIO) is input, and the P-type transistor P26 is turned off, thus preventing a short circuit across resistor R21. Therefore, the effect of the first embodiment is maintained when the voltage at the inverting output node outb drops. It should be noted that, as described above, because the rise of the output signal OUT is faster, the turn-off of the P-type transistor P22 is advanced, and compared to the first embodiment, the voltage drop at the inverting output node outb and nodes n2b and n1b is faster (see reference). Figure 2 (The dashed line in the middle).

[0107] - Work Example (2-4) -

[0108] The operation is explained when the input signal IN changes from 'H' to 'L'.

[0109] Similar to the above-mentioned working examples (1-4), compared with working examples (2-3), the first circuit 10 and the second circuit 20 of this working example perform opposite operations.

[0110] - The function and effects of the second embodiment -

[0111] As described above, according to this embodiment, in the first circuit 10, the P-type transistor P16 is turned on when the output signal OUT and the signal at node n1 rise, thereby short-circuiting the two ends of resistor R11. Therefore, since no voltage drop occurs at resistor R11, the period during which the third power supply VDDIO and the first power supply VDD are turned on can be suppressed, thereby accelerating the rise speed of the output signal OUT. Furthermore, when the output signal OUT falls, the P-type transistor P16 is turned off, thus preventing a short circuit across resistor R11. Therefore, the effect of resistor R11 in the first embodiment is maintained. The second circuit 20 operates in the same manner through the reverse operation.

[0112] <Third Implementation Method>

[0113] Figure 4 An example circuit diagram of the level shifting circuit 1 according to the third embodiment is shown. Figure 4 In the middle, to and Figure 1 The corresponding structures are labeled with the same symbols. The following description focuses on the differences from the first embodiment.

[0114] Compared to the first embodiment, the level shifting circuit 1 in this embodiment is configured to make the output signal OUT decrease from 'H' to 'L' faster.

[0115] In the structure of the first embodiment, since the signals at nodes n1 and n2 also decrease when the output signal OUT decreases, the Vgs of P-type transistors P14 and P15 decreases, and the source-drain current gradually decreases. Thus, the discharge current from the output signal OUT to the input node in (voltage VSS) via P-type transistors P14 and P15 decreases. Consequently, the voltage drop at nodes n1 and n2 becomes slow, and therefore the turn-on of P-type transistor P11 sometimes does not occur prematurely. As a result, the voltage at node n2 continues to decrease slowly, P-type transistor P13 does not conduct, and the decrease in the output signal OUT does not become faster, which can sometimes affect high-speed operation.

[0116] Therefore, in this embodiment, from the viewpoint of accelerating the descent of the output signal OUT, a P-type transistor P17 is added to the first circuit 10 and a P-type transistor P27 is added to the second circuit 20, based on the structure of the first embodiment.

[0117] - First Circuit -

[0118] P-type transistor P17 (equivalent to the thirteenth P-type transistor) is located between node n1 and the first power supply VDD, and the gate of P-type transistor P17 is connected to node n4.

[0119] -Second Circuit-

[0120] P-type transistor P27 (equivalent to the fourteenth P-type transistor) is located between node n1b and the first power supply VDD, and the gate of P-type transistor P27 is connected to node n4b.

[0121] [Operation of the level shifting circuit]

[0122] Next, refer to Figure 2 The operation of the level shifting circuit 1 involved in this embodiment will be explained. Figure 2 From time t5 to time t8, the characteristics of the voltage waveform involved in this embodiment are shown using dashed lines. Here, the description will focus on the differences in operation between this embodiment and the level shifting circuit 1 involved in the first embodiment.

[0123] -Work Example (3-1)-

[0124] The operation is the same as the operation example (1-1) of the first embodiment when 'L' is input as the input signal IN.

[0125] At this point, since the voltage at node n4 is VSS, P-type transistor P17 is turned on. Conversely, since the voltage at node n4b is VDDIO, P-type transistor P27 is turned off.

[0126] - Work Example (3-2) -

[0127] The operation is the same as the operation example (1-2) of the first embodiment when 'H' is input as the input signal IN.

[0128] It should be noted that since the voltage at node n4 is VDDIO, the P-type transistor P17 is turned off. Conversely, since the voltage at node n4b is VSS, the P-type transistor P27 is turned on.

[0129] - Work Example (3-3) -

[0130] The operation will be explained when the input signal IN changes from 'H' to 'L'. Here, the explanation will focus on the differences from the first embodiment.

[0131] In the first circuit 10, at time t5, the voltage at node n4 begins to decrease. Furthermore, when Vgs of the P-type transistor P17 exceeds the threshold, the P-type transistor P17 turns on. Thus, as... Figure 2As shown by the dashed lines in t5 to t7, because the voltage at node n1 drops faster than in the first embodiment, the P-type transistor P11 turns on earlier, and the voltage at node n2 drops faster. Therefore, compared to the first embodiment, the P-type transistor P13 turns on earlier, and the output signal OUT drops faster.

[0132] At this point, in the second circuit 20, the voltage at node n4b begins to rise. Furthermore, when Vgs of the P-type transistor P27 is less than the threshold, P-type transistor P27 is turned off. Therefore, in the second circuit 20, P-type transistor P27 does not impede the voltage rise at the inverting output node outb and at nodes n1b, n2b, and n4b.

[0133] It should be noted that, since the output signal OUT decreases faster, the P-type transistor P22 turns on earlier. Compared with the first embodiment, the voltage rises faster at the inverted output node outb and nodes n1b, n2b, and n4b (refer to the dashed lines from time t6 to t8).

[0134] - Work Example (3-4) -

[0135] As described above, the first circuit 10 and the second circuit 20 are structurally symmetrical. Furthermore, when the input signal IN changes from 'L' to 'H', the inverting input signal NIN changes from 'H' to 'L'. Therefore, compared to the operating example (3-3), in this operating example, the first circuit 10 and the second circuit 20 perform opposite operations.

[0136] - The function and effects of the third embodiment -

[0137] As described above, according to this embodiment, the configuration is such that when the output signal OUT decreases, the P-type transistor P17 turns on, accelerating the rate of voltage decrease at nodes n1 and n2, thus causing the P-type transistor P11 to turn on earlier. Therefore, compared to the first embodiment, the P-type transistor P13 turns on earlier, and the rate of decrease of the output signal OUT becomes faster.

[0138] Furthermore, when the output signal OUT rises, the P-type transistor P17 is turned off, thus maintaining the effect of the first embodiment. In the second circuit 20, it operates in the same way through the reverse process.

[0139] <Fourth Implementation>

[0140] Figure 5 An example circuit diagram of the level shifting circuit 1 according to the fourth embodiment is shown. Figure 5As shown, the structure of this embodiment is based on the structure of the first embodiment, with the circuitry added in the second and third embodiments added as well. Figure 5 In the middle, to and Figure 1 , Figure 3 as well as Figure 4 The corresponding structural labels use the same symbols.

[0141] By configuring the structure in this way, the rise and fall of the output signal OUT are accelerated, thereby achieving further high speed.

[0142] like Figure 5 As shown, the level shifting circuit 1 includes a first circuit 10, a second circuit 20, and an inverter 3 that inverts the input signal IN to generate an inverted input signal NIN.

[0143] - First Circuit -

[0144] The first circuit includes N-type transistors N11 and N12, P-type transistors P11 to P17, resistor R11, and buffer B11.

[0145] An N-type transistor N11 (equivalent to the first N-type transistor) is positioned between input node in and node n2 (equivalent to the first node), with its gate connected to the first power supply VDD. A P-type transistor P11 (equivalent to the first P-type transistor) is positioned between input node in and node n2, with its gate connected to node n1 (equivalent to the second node). A P-type transistor P14 (equivalent to the second P-type transistor) is positioned between node n2 and output node out, with its gate connected to the first power supply VDD. A P-type transistor P12 (equivalent to the third P-type transistor) is positioned between the third power supply VDDIO and output node out, with its gate connected to the inverting output node outb. A P-type transistor P13 (equivalent to the fourth P-type transistor) is positioned between the first power supply VDD and output node out, with its gate connected to node n2. An N-type transistor N12 (equivalent to the second N-type transistor) is positioned between input node in and node n4 (equivalent to the third node), with its gate connected to the first power supply VDD. P-type transistor P15 (equivalent to the fifth P-type transistor) is located between nodes n4 and n1, and its gate is connected to the first power supply VDD. Resistor R11 (equivalent to the first resistor) is located between nodes n1 and n2. P-type transistor P16 (equivalent to the sixth P-type transistor) is connected in parallel with resistor R11. Here, P-type transistor P16 is located between nodes n1 and n2. Buffer B11 (equivalent to the first buffer) is located between the output node out and the gate of P-type transistor P16. P-type transistor P17 (equivalent to the seventh P-type transistor) is located between node n1 and the first power supply VDD, and its gate is connected to node n4.

[0146] -Second Circuit-

[0147] The second circuit includes N-type transistors N21 and N22, P-type transistors P21 to P27, resistor R21, and buffer B21.

[0148] N-type transistor N21 (equivalent to the third N-type transistor) is positioned between the inverting input node inb and node n2b (equivalent to the fourth node), with its gate connected to the first power supply VDD. P-type transistor P21 (equivalent to the eighth P-type transistor) is positioned between the inverting input node inb and node n2b, with its gate connected to node n1b (equivalent to the fifth node). P-type transistor P24 (equivalent to the ninth P-type transistor) is positioned between node n2b and the inverting output node outb, with its gate connected to the first power supply VDD. P-type transistor P22 (equivalent to the tenth P-type transistor) is positioned between the third power supply VDDIO and the inverting output node outb, with its gate connected to the output node out. P-type transistor P23 (equivalent to the eleventh P-type transistor) is positioned between the first power supply VDD and the inverting output node outb, with its gate connected to node n2b. An N-type transistor N22 (equivalent to the fourth N-type transistor) is positioned between the inverting input node inb and node n4b (equivalent to the sixth node), with its gate connected to the first power supply VDD. A P-type transistor P25 (equivalent to the twelfth P-type transistor) is positioned between node n4b and node n1b, with its gate connected to the first power supply VDD. A resistor R21 (equivalent to the second resistor) is positioned between node n1b and node n2b. A P-type transistor P26 (equivalent to the thirteenth P-type transistor) is connected in parallel with resistor R21. Here, P-type transistor P26 is positioned between node n1b and node n2b. A buffer B21 (equivalent to the second buffer) is positioned between the inverting output node outb and the gate of P-type transistor P26. A P-type transistor P27 (equivalent to the fourteenth P-type transistor) is positioned between node n1b and the first power supply VDD, with its gate connected to node n4b.

[0149] [Operation of the level shifting circuit]

[0150] Next, refer to Figure 2 The operation of the level shifting circuit 1 according to this embodiment will be described. In this embodiment, the effects obtained by combining the second and third embodiments can be achieved. Figure 2 From time t1 to time t8, the characteristics of the voltage waveform involved in this embodiment are shown using dashed lines.

[0151] - Work Example (4-1) -

[0152] The operation is the same as the operation example (1-1) of the first embodiment when 'L' is input as the input signal IN.

[0153] It should be noted that, as shown in working example (2-1), P-type transistor P16 is cut off, and P-type transistor P26 does not function. Additionally, as shown in working example (3-1), P-type transistor P17 is turned on, and P-type transistor P27 is cut off.

[0154] - Work Example (4-2) -

[0155] The operation is the same as the operation example (1-2) of the first embodiment when 'H' is input as the input signal IN.

[0156] It should be noted that, as shown in working example (2-2), P-type transistor P16 is not functional, and P-type transistor P26 is turned off. Additionally, as shown in working example (3-2), P-type transistor P17 is turned off, and P-type transistor P27 is turned on.

[0157] - Work Example (4-3) -

[0158] The operation when the input signal IN changes from 'L' to 'H' is the same as the operation example (2-3) of the second embodiment.

[0159] - Work Example (4-4) -

[0160] The operation when the input signal IN changes from 'H' to 'L' is the same as the operation example (3-3) of the third embodiment.

[0161] (Modified example)

[0162] Figure 6 A modified example of the level shifting circuit 1 according to the fourth embodiment is shown. Figure 6 In the middle, to and Figure 5 The corresponding structures are labeled with the same symbols. The following description focuses on the differences from the fourth embodiment.

[0163] In this variation, compared to the fourth embodiment, the connection point of one end of resistor R11 is changed from node n2 to output node out. Similarly, the connection point of one end of resistor R21 is changed from node n2b to inverting output node outb. All other structures are the same as in the fourth embodiment.

[0164] It should be noted that in each of the first to third embodiments, the relationship with... Figure 6 Similarly, the connection object of one end of resistor R11 can be changed from node n2 to output node out, and the connection object of one end of resistor R21 can be changed from node n2b to inverting output node outb, achieving the same effect as in the various implementation methods.

[0165] [Operation of the level shifting circuit]

[0166] Next, regarding Figure 6 The operation of the level shifting circuit 1 will be explained.

[0167] - Work Example (4-5) -

[0168] The operation is explained when the input signal IN changes from 'L' to 'H'.

[0169] First, the operation of applying this modified example to the second and fourth embodiments will be explained. In this modified example, a P-type transistor P16 is provided in parallel with the resistor R11 in the first circuit 10. Therefore, the P-type transistor P16 is turned on at the same time as in each embodiment, thereby short-circuiting the two ends of the resistor R11. As a result, the same characteristics as in each embodiment can be obtained.

[0170] Next, the operation of applying this modified example to the first and third embodiments will be described. Here, in this modified example, the 'L' voltage is VSS at node n2 and VDD at node n1. This provides the following advantages: it is easy to achieve a design where the Vgs of the P-type transistor P11 does not exceed the threshold when the signal rises at nodes n1 and n2. Furthermore, if the P-type transistor P11 is turned off, the rise of the output signal OUT can be accelerated compared to the first and third embodiments.

[0171] - Work Example (4-6) -

[0172] The operation when the input signal IN changes from 'H' to 'L' will be explained. Here, the operation when this modified example is applied to the first to fourth embodiments will be explained.

[0173] In this modified structure, node n1 is connected from the output node out via resistor R11, resulting in a corresponding voltage drop. At node n2, since it is connected from the output node out via P-type transistor P14, there is a voltage drop caused by the on-resistance of P-type transistor P14. Therefore, the resistance value of resistor R11 is designed considering the potential difference between nodes n2 and n1 (n1 < n2). Specifically, by designing the resistance value of resistor R11 such that the Vgs of transistor P11 exceeds a threshold, characteristics equivalent to those in the first to fourth embodiments are obtained.

[0174] <Fifth Implementation>

[0175] Figure 7 An example of a circuit diagram of the level shifting circuit 1 according to the fifth embodiment is shown.

[0176] exist Figure 7 In the middle, to and Figure 5(Fourth Embodiment) The corresponding structures are labeled with the same symbols. In the following description, the differences from the fourth embodiment will be the focus.

[0177] The level shifting circuit 1 in this embodiment is configured to suppress the increase in circuit area compared to the fourth embodiment. Specifically, based on the structure of the fourth embodiment, the level shifting circuit 1 in this embodiment adds a voltage comparison circuit S11 to the first circuit 10 and a voltage comparison circuit S21 to the second circuit 20.

[0178] - First Circuit -

[0179] Voltage comparator circuit S11 is a dual-input, single-output comparator circuit, located between resistor R11 and output node out. Specifically, one input terminal of voltage comparator circuit S11 is connected to the first power supply VDD. The other input terminal of voltage comparator circuit S11 is connected to node n2. That is, the other input terminal of voltage comparator circuit S11 is connected to output node out via node n2 and P-type transistor P14. The output terminal of voltage comparator circuit S11 is connected to node n5, which is connected with resistor R11 and P-type transistor P16. In other words, resistor R11 and P-type transistor P16 are connected in parallel between nodes n1 and n5.

[0180] Figure 8 An example of the structure of the voltage comparator circuit S11 is shown. Figure 8 In the example, the voltage comparison circuit S11 includes P-type transistors P18 and P19. P-type transistor P18 is positioned between the first power supply VDD and node n5, and its gate is connected to node n2. P-type transistor P19 is positioned between node n5 and node n2, and its gate is connected to the first power supply VDD. Furthermore, when the voltage at node n2 is below VDD, P-type transistor P18 is turned on, and the first power supply VDD and node n5 are connected. Conversely, when the voltage at node n2 exceeds VDD, P-type transistor P19 is turned on, and nodes n5 and n2 are connected. It should be noted that in... Figure 8 In the diagram, parentheses are used to represent an example of the structure of voltage comparator circuit S21. Furthermore, the structures of voltage comparator circuits S11 and S21 are not limited to... Figure 8 The structure can also be used with other voltage comparator circuits that have the same function.

[0181] -Second Circuit-

[0182] The voltage comparator circuit S21 is a dual-input, single-output comparator circuit, located between resistor R21 and the inverting output node outb. Specifically, one input terminal of the voltage comparator circuit S21 is connected to the first power supply VDD. The other input terminal of the voltage comparator circuit S21 is connected to node n2b. That is, the other input terminal of the voltage comparator circuit S21 is connected to the inverting output node outb via node n2b and P-type transistor P24. The output terminal of the voltage comparator circuit S21 is connected to node n5b, which is connected to resistor R21 and P-type transistor P26. In other words, in this embodiment, resistor R21 and P-type transistor P26 are arranged in parallel between nodes n1b and n5b.

[0183] [Operation of the level shifting circuit]

[0184] Next, refer to Figure 2 The operation of the level shifting circuit 1 according to this embodiment will be described. In this embodiment, the same effects as in the fourth embodiment can be obtained. That is, in Figure 2 From time t1 to time t8, the characteristics of the voltage waveform involved in this embodiment are shown using dashed lines.

[0185] -Work Example (5-1)-

[0186] The operation when 'L' is input as the input signal IN is the same as the operation example (4-1) of the fourth embodiment.

[0187] - Work Example (5-2) -

[0188] The operation when 'H' is input as the input signal IN is the same as the operation example (4-2) of the fourth embodiment.

[0189] - Work Example (5-3) -

[0190] The operation will be explained when the input signal IN changes from 'L' to 'H'. Here, the explanation will focus on the differences from the operating example (4-3) of the fourth embodiment.

[0191] In the first circuit 10, when the voltage at node n2 is below VDD, the P-type transistor P18 is turned on, and the first power supply VDD is connected to node n5. Furthermore, when the voltage at node n2 rises above VDD, node n5 is connected to node n2. At this time, because the P-type transistor P16 short-circuits the two ends of resistor R11, the operation of the fourth embodiment is maintained.

[0192] In the second circuit 20, during the period when the voltage at node n2b is higher than VDD, nodes n5b and n2b are turned on. At this time, due to the on-resistance of P-type transistor P29 and the voltage drop caused by resistor R21, Vgs of P-type transistor P21 exceeds the threshold, thereby turning on P-type transistor P21. Thus, the operation of the fourth embodiment is maintained.

[0193] - Work Example (5-4) -

[0194] Regarding the operation when the input signal IN changes from 'H' to 'L', compared with the operating example (5-3), the first circuit 10 and the second circuit 20 perform opposite operations.

[0195] - The function and effects of the fifth embodiment -

[0196] As described above, according to this embodiment, in the first circuit 10, the resistance value obtained by adding the resistance of resistor R11 and the on-resistance of P-type transistor P19 can be designed to be the same as that of resistor R11 in the fourth embodiment, thus reducing the resistance value of resistor R11. Therefore, it is possible to obtain characteristics equivalent to those in the fourth embodiment while reducing the component area of ​​resistor R11 and the dedicated area of ​​level shift circuit 1. The same applies to the second circuit 20.

[0197] Furthermore, in this embodiment, when the input signal IN is 'L', the voltage at node n2 is VSS, and the voltage at node n1 is VDD. Therefore, it has the following characteristic: it is easy to achieve a design where the Vgs of the P-type transistor P11 does not exceed a threshold when the signal rises at nodes n1 and n2.

[0198] (Modified example)

[0199] Figure 9 A modified example of the level shifting circuit 1 according to the fifth embodiment is shown. Figure 9 In the middle, to and Figure 7 The corresponding structures are labeled with the same symbols. The following description focuses on the differences from the fifth embodiment.

[0200] In this modified example, compared to the fifth embodiment, the connection object of one input of the voltage comparator circuit S11 is changed from node n2 to the output node out. Similarly, the connection object of one input of the voltage comparator circuit S21 is changed from node n2b to the inverting output node outb. All other structures are the same as in the fifth embodiment.

[0201] [Operation of the level shifting circuit]

[0202] Next, regarding Figure 9 The operation of the level shifting circuit 1 will be explained.

[0203] - Work Example (5-5) -

[0204] The operation is explained when the input signal IN changes from 'L' to 'H'.

[0205] In the first circuit 10, a P-type transistor P16 is provided in parallel with the resistor R11. The P-type transistor P16 is turned on at the same time as in the fifth embodiment, and the resistor R11 is short-circuited. As a result, the same characteristics as in the fifth embodiment can be obtained.

[0206] - Work Example (5-6) -

[0207] The operation is explained when the input signal IN changes from 'H' to 'L'.

[0208] In this modified example, resistor R11 is connected in parallel with P-type transistor P14. Therefore, when designing the resistance value of resistor R11, by adding the on-resistance of P-type transistor P14, the Vgs of P-type transistor P11 is made to exceed the threshold, thereby obtaining the same characteristics as in the fifth embodiment.

[0209] It should be noted that the technology in this disclosure is not limited to the structures described in the above embodiments, and can also be applied to embodiments obtained by appropriate changes, substitutions, additions, omissions, etc. In addition, the constituent elements described in the above embodiments can also be combined to form new embodiments.

[0210] -Industry Applicability-

[0211] The level shifting circuit disclosed herein is extremely useful due to the lower voltage corresponding to the operating voltage and / or the higher speed of circuit operation.

[0212] - Symbol Explanation -

[0213] 1 level shift circuit

[0214] n1 nodes (first node, second node)

[0215] n1b nodes (third node, fifth node)

[0216] n2 nodes (second node, first node)

[0217] n2b node (fourth node)

[0218] n4 nodes (fifth node, third node)

[0219] n4b node (sixth node)

[0220] B11 buffer (first buffer)

[0221] B21 buffer (second buffer)

[0222] N11N-type transistor (first N-type transistor)

[0223] N12N type transistor (third N-type transistor, second N-type transistor)

[0224] N21N type transistor (second N-type transistor, third N-type transistor)

[0225] N22N type transistor (fourth type N transistor)

[0226] P11P-type transistor (first P-type transistor)

[0227] P12P type transistor (second P type transistor, third P type transistor)

[0228] P13P type transistor (third P-type transistor, fourth P-type transistor)

[0229] P14P type transistor (seventh P-type transistor, second P-type transistor)

[0230] P15P type transistor (eighth P-type transistor, fifth P-type transistor)

[0231] P16P type transistor (eleventh P-type transistor, sixth P-type transistor)

[0232] P17P type transistor (thirteenth P-type transistor, seventh P-type transistor)

[0233] P21P type transistor (fourth P-type transistor, eighth P-type transistor)

[0234] P22P type transistor (fifth P-type transistor, tenth P-type transistor)

[0235] P23P type transistor (sixth P-type transistor, eleventh P-type transistor)

[0236] P24P type transistor (ninth type P transistor)

[0237] P25P type transistor (tenth P type transistor, twelfth P type transistor)

[0238] P26P type transistor (twelfth P type transistor, thirteenth P type transistor)

[0239] P27P type transistor (fourteenth type P transistor)

[0240] R11 resistor (first resistor)

[0241] R21 resistor (second resistor)

[0242] VDD first power supply

[0243] VDDIO Third Power Supply

[0244] VSS is grounded (second power supply).

Claims

1. A level shifting circuit, characterized in that: The level shifting circuit includes: An input node receives an input signal that is switched between a first power source and a second power source with a potential lower than the first power source. A first N-type transistor is disposed between the input node and the output node, and the gate of the first N-type transistor is connected to the first power supply. A first P-type transistor is disposed in parallel with a first N-type transistor between the input node and the output node, and the gate of the first P-type transistor is connected to the first node. A first resistor is disposed between the first node and the output node; The second P-type transistor is disposed between the third power supply, which has a higher potential than the first power supply, and the output node. The gate of the second P-type transistor is connected to the inverting output node. A third P-type transistor is disposed between the first power supply and the output node, and the gate of the third P-type transistor is connected to the output node via a second node; An inverting input node receives an inverted input signal obtained by inverting the input signal; The second N-type transistor is disposed between the inverting input node and the inverting output node, and the gate of the second N-type transistor is connected to the first power supply. A fourth P-type transistor is provided, which is connected in parallel with the second N-type transistor between the inverting input node and the inverting output node, and the gate of the fourth P-type transistor is connected to the third node; A second resistor is disposed between the third node and the inverting output node; A fifth P-type transistor, wherein the fifth P-type transistor is disposed between the third power supply and the inverting output node, and the gate of the fifth P-type transistor is connected to the output node; and A sixth P-type transistor is disposed between the first power supply and the inverting output node, and the gate of the sixth P-type transistor is connected to the inverting output node via a fourth node.

2. The level shifting circuit according to claim 1, characterized in that: The level shifting circuit includes: A seventh P-type transistor is disposed between the output node and the second node, and the gate of the seventh P-type transistor is connected to the first power supply. A third N-type transistor is disposed between the input node and the fifth node, and the gate of the third N-type transistor is connected to the first power supply. An eighth P-type transistor is disposed between the fifth node and the first node, and the gate of the eighth P-type transistor is connected to the first power supply. A ninth P-type transistor is disposed between the inverting output node and the fourth node, and the gate of the ninth P-type transistor is connected to the first power supply. A fourth N-type transistor, disposed between the inverting input node and the sixth node, wherein the gate of the fourth N-type transistor is connected to the first power supply; and A tenth P-type transistor is disposed between the sixth node and the third node, and the gate of the tenth P-type transistor is connected to the first power supply.

3. The level shifting circuit according to claim 1, characterized in that: The level shifting circuit includes: The eleventh P-type transistor is arranged in parallel with the first resistor; A first buffer is disposed between the output node and the gate of the eleventh P-type transistor; A twelfth P-type transistor, wherein the twelfth P-type transistor is disposed in parallel with the second resistor; and The second buffer is disposed between the inverting output node and the gate of the twelfth P-type transistor.

4. The level shifting circuit according to claim 2, characterized in that: The level shifting circuit includes: A thirteenth P-type transistor, wherein the thirteenth P-type transistor is disposed between the first node and the first power supply, and the gate of the thirteenth P-type transistor is connected to the fifth node; and The fourteenth P-type transistor is disposed between the third node and the first power supply, and its gate is connected to the sixth node.

5. The level shifting circuit according to claim 4, characterized in that: The level shifting circuit includes: The eleventh P-type transistor is arranged in parallel with the first resistor; A first buffer is disposed between the output node and the gate of the eleventh P-type transistor; A twelfth P-type transistor, wherein the twelfth P-type transistor is disposed in parallel with the second resistor; and The second buffer is disposed between the inverting output node and the gate of the twelfth P-type transistor.

6. The level shifting circuit according to claim 1, characterized in that: The level shifting circuit includes: A first voltage comparator circuit is located between the first resistor and the output node; A second voltage comparator circuit is located between the second resistor and the inverting output node; A seventh P-type transistor, wherein the seventh P-type transistor is disposed between the output node and the second node, and the gate of the seventh P-type transistor is connected to the first power supply; and A ninth P-type transistor is disposed between the inverting output node and the fourth node, and the gate of the ninth P-type transistor is connected to the first power supply. One input of the first voltage comparator circuit is connected to the first power supply, the other input of the first voltage comparator circuit is connected to the second node or the output node, and the output of the first voltage comparator circuit is connected to the first resistor. One input of the second voltage comparator circuit is connected to the first power supply, the other input of the second voltage comparator circuit is connected to the fourth node or the inverting output node, and the output of the second voltage comparator circuit is connected to the second resistor.

7. The level shifting circuit according to claim 4, characterized in that: The level shifting circuit includes: A first voltage comparator circuit, the first voltage comparator circuit being located between the first resistor and the output node; and A second voltage comparator circuit is located between the second resistor and the inverting output node. One input of the first voltage comparator circuit is connected to the first power supply, the other input of the first voltage comparator circuit is connected to the second node or the output node, and the output of the first voltage comparator circuit is connected to the first resistor. One input of the second voltage comparator circuit is connected to the first power supply, the other input of the second voltage comparator circuit is connected to the fourth node or the inverting output node, and the output of the second voltage comparator circuit is connected to the second resistor.

8. A level shifting circuit, characterized in that: The level shifting circuit includes: An input node receives an input signal that is switched between a first power source and a second power source with a potential lower than the first power source. A first N-type transistor is disposed between the input node and the first node, and the gate of the first N-type transistor is connected to the first power supply. A first P-type transistor is disposed between the input node and the first node, and the gate of the first P-type transistor is connected to the second node. The second P-type transistor is disposed between the first node and the output node, and the gate of the second P-type transistor is connected to the first power supply. The third P-type transistor is disposed between the third power supply, which has a higher potential than the first power supply, and the output node. The gate of the third P-type transistor is connected to the inverting output node. A fourth P-type transistor is disposed between the first power supply and the output node, and the gate of the fourth P-type transistor is connected to the first node; The second N-type transistor is disposed between the input node and the third node, and the gate of the second N-type transistor is connected to the first power supply. A fifth P-type transistor is disposed between the third node and the second node, and the gate of the fifth P-type transistor is connected to the first power supply. A first resistor is disposed between the second node and the first node or the output node; A sixth P-type transistor, wherein the sixth P-type transistor is connected in parallel with the first resistor; A first buffer is disposed between the output node and the gate of the sixth P-type transistor; A seventh P-type transistor is disposed between the second node and the first power supply, and the gate of the seventh P-type transistor is connected to the third node; An inverting input node receives an inverted input signal obtained by inverting the input signal; A third N-type transistor is disposed between the inverting input node and the fourth node, and the gate of the third N-type transistor is connected to the first power supply. An eighth P-type transistor is disposed between the inverting input node and the fourth node, and the gate of the eighth P-type transistor is connected to the fifth node; A ninth P-type transistor is disposed between the fourth node and the inverting output node, and the gate of the ninth P-type transistor is connected to the first power supply. The tenth P-type transistor is disposed between the third power supply, which has a higher potential than the first power supply, and the inverting output node. The gate of the tenth P-type transistor is connected to the output node. The eleventh P-type transistor is disposed between the first power supply and the inverting output node, and the gate of the eleventh P-type transistor is connected to the fourth node. A fourth N-type transistor is disposed between the inverting input node and the sixth node, and the gate of the fourth N-type transistor is connected to the first power supply. The twelfth P-type transistor is disposed between the sixth node and the fifth node, and the gate of the twelfth P-type transistor is connected to the first power supply. A second resistor is disposed between the fifth node and the fourth node or the inverting output node; The thirteenth P-type transistor is arranged in parallel with the second resistor; A second buffer, disposed between the inverting output node and the gate of the thirteenth P-type transistor; and The fourteenth P-type transistor is disposed between the fifth node and the first power supply, and its gate is connected to the sixth node.

9. The level shifting circuit according to claim 8, characterized in that: The level shifting circuit includes: A first voltage comparator circuit, the first voltage comparator circuit being located between the first resistor and the output node; and A second voltage comparator circuit is located between the second resistor and the inverting output node. One input of the first voltage comparator circuit is connected to the first power supply, the other input of the first voltage comparator circuit is connected to the second node or the output node, and the output of the first voltage comparator circuit is connected to the first resistor. One input of the second voltage comparator circuit is connected to the first power supply, the other input of the second voltage comparator circuit is connected to the fourth node or the inverting output node, and the output of the second voltage comparator circuit is connected to the second resistor.

Images