Exception handling circuit and exception handling method for clock data recovery

Abstract

The application relates to an abnormality processing circuit and an abnormality processing method for clock data recovery. The application can support a data sender to implement data scrambling on target data to be transmitted aiming at direct current balance, so that a data receiver can receive the scrambled data with the characteristic of direct current balance through a physical channel. On this basis, the application can obtain periodic samples of sampling data obtained by sampling the scrambled data by the data receiver, and when it is determined according to the periodic direct current unbalance deviation of the continuous multiple periodic samples that the sampling clock phase of the scrambled data is locked in a false eye position in the eye diagram of the scrambled data, the sampling clock phase can be made to deviate from the false eye position by implementing unlocking phase adjustment on the sampling clock phase, so that the dynamic calibration of the sampling clock phase can be recovered in time, and then the failure risk of clock data recovery can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of AI (Artificial Intelligence) chips, in particular to an abnormality processing circuit for CDR (Clock and Data Recovery) and an abnormality processing method for CDR suitable for AI chips. BACKGROUND

[0002] An AI chip usually involves data transmission based on a physical channel. For example, an AI chip using Chiplet technology can include multiple Dies, and data transmission between different Dies can be implemented based on a physical channel of a UCIe (Universal chiplet interconnect express) protocol. For another example, data transmission between an AI chip and a processing chip such as a CPU (Central Processing Unit) can be implemented based on a physical channel of a PCIe (Peripheral Component Interconnect Express) protocol.

[0003] In order to improve the sampling accuracy of a data receiver (for example, a Die of an AI chip or an AI chip) on data received through a physical channel, a CDR technology can be used in the data receiver. The CDR technology can dynamically calibrate the sampling clock phase using an eye diagram generated by periodically superimposing the transmitted data, so that the data receiver can perform a sampling operation on the received data at the dynamically calibrated sampling clock phase.

[0004] However, in actual applications, there can be an abnormal situation in which the sampling clock phase is locked at a false eye position in the eye diagram, and at this time, it will be difficult to implement correct and effective dynamic calibration of the sampling clock phase, that is, the CDR fails.

[0005] As can be seen from the above, how to reduce the risk of CDR failure by releasing the abnormal lock of the sampling clock phase at the false eye position has become a technical problem to be solved in the related art. SUMMARY

[0006] The present application provides an abnormality processing circuit for CDR and an abnormality processing method for CDR, which helps to reduce the risk of CDR failure.

[0007] In an embodiment of the present application, an abnormality processing circuit for clock data recovery includes:

[0008] The sample acquisition module is configured to acquire periodic samples of sampling data of a data receiver, wherein the sampling data is obtained by sampling scrambled data transmitted by a data transmitter through a physical channel, the scrambled data is generated by the data transmitter by performing data scrambling on target data to be transmitted with a direct current balance as a target, the direct current balance is used to balance the number ratio of a first logic level and a second logic level in the scrambled data, the sampling operation of the data receiver on the scrambled data is performed based on a sampling reference voltage at a sampling clock phase, and the clock data recovery is used to dynamically calibrate the sampling clock phase by using an eye diagram of the scrambled data.

[0009] The sample detection module is configured to detect a periodic direct current imbalance deviation of the periodic samples, wherein the periodic direct current imbalance deviation is used to represent a deviation determination result of the number ratio of the first logic level and the second logic level in the periodic samples compared with a balance standard of the direct current balance.

[0010] The false eye decision module is configured to determine whether the sampling clock phase is currently locked at a false eye position in the eye diagram due to the voltage offset based on the periodic direct current imbalance deviations of the continuous multiple periodic samples, wherein the false eye position includes a cross point formed by a rising edge and a falling edge in the eye diagram.

[0011] The response adjustment module is configured to perform an unlocking phase adjustment on the sampling clock phase in response to a determination result that the sampling clock phase is currently locked at the false eye position due to the voltage offset, wherein the unlocking phase adjustment is used to make the sampling clock phase deviate from the false eye position.

[0012] In some examples, optionally, the sample acquisition module is specifically configured to periodically sample the sampling data according to a preset periodic bit width.

[0013] In some examples, optionally, the sample acquisition module includes a sampling register sequence, wherein the periodic bit width is determined by a sequence length of the sampling register sequence, and the periodic samples obtained by the periodic sampling each time are stored in the sampling register sequence, and the sample detection module is specifically configured to periodically acquire the periodic samples from the sampling register sequence.

[0014] In some examples, optionally, the sample detection module is specifically configured to determine the periodic direct current imbalance deviation of the periodic samples according to a number deviation of a single value number of the first logic level in the periodic samples compared with a preset threshold number, wherein the threshold number is half of a periodic bit width of the periodic samples.

[0015] In some examples, the sample detection module is optionally specifically configured to: perform a corresponding number of accumulation operations according to the number of single values of the first logic level in the periodic sample; wherein the operation result of the accumulation operation is used to represent the number of single values of the first logic level in the periodic sample; compare the operation result of the accumulation operation with the threshold number; wherein the comparison result of the operation result of the accumulation operation and the threshold number is used to represent the periodic DC imbalance deviation of the periodic sample.

[0016] In some examples, the sample detection module includes: a statistical register; an accumulation adder configured to perform a corresponding number of accumulation operations on the register value of the statistical register according to the number of single values of the first logic level in the periodic sample; wherein the register value of the statistical register is used to represent the number of single values of the first logic level in the periodic sample; and a threshold comparator configured to generate a comparison result of the register value of the statistical register and the threshold number; wherein the comparison result generated by the threshold comparator is used to represent the periodic DC imbalance deviation of the periodic sample.

[0017] In some examples, the false eye decision module is optionally specifically configured to: determine an estimated imbalance deviation of the sampling data according to the periodic DC imbalance deviations of a plurality of consecutive periodic samples; wherein the estimated imbalance deviation is used to represent the deviation of the proportion of the number of the first logic level and the second logic level in the sampling data from the DC balance; and determine whether the sampling clock phase is currently locked at the false eye position due to the voltage offset according to the estimated imbalance deviation.

[0018] In some examples, the deviation determination result of the proportion of the number of the first logic level and the second logic level in the periodic sample from the balance standard of the DC balance includes one of: a first determination result indicating that the proportion of the number of the first logic level is too high, a second determination result indicating that the proportion of the number of the second logic level is too high, and a third determination result indicating that the proportions of the number of the first logic level and the second logic level are balanced; and the false eye decision module is specifically configured to determine the estimated imbalance deviation according to the number of occurrences of the first determination result, the second determination result and the third determination result in the periodic DC imbalance deviations of a plurality of consecutive periodic samples.

[0019] In some examples, optionally, the false eye decision module is specifically configured to: in response to the occurrence of the first decision result in the periodic DC imbalance deviation of any one of the periodic samples, perform a plus 1 operation on a dynamic monitoring value; wherein the dynamic monitoring value is used to represent a deviation degree of a number ratio of the first logic level and the second logic level in the sampling data compared with a balance standard of the DC balance; in response to the occurrence of the second decision result in the periodic DC imbalance deviation of any one of the periodic samples, perform a minus 1 operation on the dynamic monitoring value; in response to the occurrence of the third decision result in the periodic DC imbalance deviation of any one of the periodic samples, perform a plus 0 or minus 0 operation on the dynamic monitoring value; in response to a positive overflow in a plus direction or a negative overflow in a minus direction of the dynamic monitoring value, generate a decision result indicating that the sampling clock phase is currently locked at the false eye position due to the voltage offset.

[0020] In some examples, optionally, the false eye decision module comprises: a decision register; wherein the dynamic monitoring value is a register value of the decision register; a sign adder, configured to perform a plus 1 operation on the register value of the decision register in response to the occurrence of the first decision result in the periodic DC imbalance deviation of any one of the periodic samples, perform a minus 1 operation on the register value of the decision register in response to the occurrence of the second decision result in the periodic DC imbalance deviation of any one of the periodic samples, and perform a plus 0 or minus 0 operation on the register value of the decision register in response to the occurrence of the third decision result in the periodic DC imbalance deviation of any one of the periodic samples; a signal generator, configured to generate a decision result indicating that the sampling clock phase is currently locked at the false eye position due to the voltage offset in response to a positive overflow in a plus direction or a negative overflow in a minus direction of the register value of the decision register.

[0021] In some examples, optionally, the eye diagram comprises a plurality of eye units, and the unlocking phase adjustment is performed by causing the sampling clock phase to produce a phase offset of a half eye width of one of the eye units, so as to make the sampling clock phase deviate from the false eye position.

[0022] In some examples, optionally, the false eye position further comprises: a neighborhood position of the sampling reference voltage where the voltage offset occurs, which is extended from the intersection point along the rising edge and the falling edge; and the response adjustment module is further configured to: implement a voltage correction adjustment on the sampling reference voltage; wherein the voltage correction adjustment is used to cause the sampling reference voltage to produce a reset offset of a reduced voltage offset.

[0023] Optionally, in some examples, the fake eye decision module is further configured to: determine, based on the periodic DC imbalance deviation of a plurality of consecutive periodic samples, the offset direction that causes the voltage offset that currently locks the sampling clock phase at the fake eye position; wherein the voltage correction adjustment is configured to cause the sampling reference voltage to generate the reset offset in a direction opposite to the offset direction.

[0024] In some examples, optionally, the deviation determination result of the quantity ratio of the first logic level and the second logic level in the periodic sample compared with the DC balance standard includes one of the following: a first determination result indicating that the quantity ratio of the first logic level is too high, a second determination result indicating that the quantity ratio of the second logic level is too high, and a third determination result indicating that the quantity ratios of the first logic level and the second logic level are balanced; the fake eye decision module is specifically configured to: in response to the occurrence of the first determination result in the periodic DC imbalance deviation of any periodic sample, perform an increment operation on the dynamic monitoring value; wherein, the dynamic monitoring value is used to characterize the degree of deviation of the quantity ratio of the first logic level and the second logic level in the sampled data compared with the DC balance standard; in response to the second determination result If the occurrence of the periodic DC imbalance deviation in any of the periodic samples occurs, the dynamic monitoring value is decremented by 1; in response to the occurrence of the third determination result in the periodic DC imbalance deviation in any of the periodic samples, the dynamic monitoring value is incremented or decremented by 0; in response to the overflow of the dynamic monitoring value in the increment or decrement direction, a determination result indicating that the sampling clock phase is currently locked at the dummy eye position due to the voltage offset, and the offset direction of the voltage offset are generated; wherein: the negative overflow of the dynamic monitoring value in the decrement direction is used to characterize the offset direction of the voltage offset as a first offset direction relative to the crossover point and closer to the first logic level; the positive overflow of the dynamic monitoring value in the increment direction is used to characterize the offset direction of the voltage offset as a second offset direction relative to the crossover point and closer to the second logic level.

[0025] In another embodiment of this application, an anomaly handling method for clock data recovery includes:

[0026] A periodic sample of the sampling data of the data receiver is obtained; wherein the sampling data is obtained by the data receiver sampling the scrambled data transmitted by the data sender through a physical channel, the scrambled data is generated by the data sender by performing data scrambling on the target data to be transmitted with DC balance as the target, the DC balance is used to make the proportion of the first logic level and the second logic level in the scrambled data tend to be balanced, the sampling operation of the data receiver on the scrambled data is performed on the sampling clock phase based on the sampling reference voltage, and the clock data recovery is used to dynamically calibrate the sampling clock phase using the eye diagram of the scrambled data;

[0027] The periodic DC imbalance deviation of the periodic sample is detected; wherein, the periodic DC imbalance deviation is used to characterize the deviation judgment result of the ratio of the number of the first logic level and the second logic level in the periodic sample compared with the balance standard of the DC balance;

[0028] Based on the periodic DC imbalance deviation of multiple consecutive periodic samples, it is determined whether the sampling clock phase is currently locked at the false eye position in the eye diagram due to the voltage offset of the sampling reference voltage; wherein, the false eye position includes the intersection point formed by the rising edge and falling edge in the eye diagram;

[0029] In response to a determination that the sampling clock phase is currently locked at the position of the artificial eye due to the voltage offset, an unlocking phase adjustment is performed on the sampling clock phase; wherein the unlocking phase adjustment is used to remove the sampling clock phase from the position of the artificial eye.

[0030] In some examples, optionally, the acquisition of periodic samples of eye diagram sampling data includes: periodically sampling the sampling data according to a preset periodic bit width.

[0031] In some examples, optionally, detecting the periodic DC imbalance deviation of the periodic sample includes: determining the periodic DC imbalance deviation of the periodic sample based on the number deviation of the number of single values ​​of the first logic level in the periodic sample compared to a preset threshold number; wherein the threshold number is half of the periodic bit width of the periodic sample.

[0032] In some examples, optionally, determining the periodic DC imbalance deviation of the periodic sample based on the deviation of the number of single values ​​of the first logic level in the periodic sample from a preset threshold number includes: performing an accumulation operation a corresponding number of times based on the number of single values ​​of the first logic level in the periodic sample; wherein the operation result of the accumulation operation is used to characterize the number of single values ​​of the first logic level in the periodic sample; comparing the operation result of the accumulation operation with the threshold number; wherein the comparison result of the operation result of the accumulation operation with the threshold number is used to characterize the periodic DC imbalance deviation of the periodic sample.

[0033] Optionally, in some examples, determining whether the sampling clock phase is currently locked at the dummy eye position in the eye diagram due to the voltage offset based on the periodic DC imbalance deviation of a plurality of consecutive periodic samples includes: determining an estimated imbalance deviation of the sampling data based on the periodic DC imbalance deviation of a plurality of consecutive periodic samples; wherein the estimated imbalance deviation is used to characterize the deviation of the proportion of the first logic level and the second logic level in the sampling data relative to the DC balance; and determining whether the sampling clock phase is currently locked at the dummy eye position due to the voltage offset based on the estimated imbalance deviation.

[0034] In some examples, optionally, the deviation determination result of the quantity ratio of the first logic level and the second logic level in the periodic sample compared with the DC balance standard includes one of the following: a first determination result indicating that the quantity ratio of the first logic level is too high, a second determination result indicating that the quantity ratio of the second logic level is too high, and a third determination result indicating that the quantity ratios of the first logic level and the second logic level are balanced; the step of determining the estimated imbalance deviation of the sampled data based on the periodic DC imbalance deviation of a consecutive plurality of periodic samples includes: determining the estimated imbalance deviation based on the number of times the first determination result, the second determination result, and the third determination result appear in the periodic DC imbalance deviation of a consecutive plurality of periodic samples.

[0035] In some examples, optionally, determining the estimated imbalance deviation based on the number of occurrences of the first determination result, the second determination result, and the third determination result in the periodic DC imbalance deviations of a series of consecutive periodic samples includes: in response to the occurrence of the first determination result in the periodic DC imbalance deviation of any one of the periodic samples, incrementing the dynamic monitoring value by 1; wherein the dynamic monitoring value is used to characterize the degree of deviation between the proportion of the first logic level and the second logic level in the sampled data and the balance standard of the DC balance; in response to the occurrence of the second determination result in ... The occurrence of the periodic DC imbalance deviation in the periodic sample triggers a decrement operation of 1 on the dynamic monitoring value; in response to the occurrence of the third determination result in the periodic DC imbalance deviation of any of the periodic samples, the dynamic monitoring value triggers an increment or decrement operation of 0; determining whether the sampling clock phase is currently locked at the dummy eye position due to the voltage offset based on the estimated imbalance deviation includes: generating a determination result indicating that the sampling clock phase is currently locked at the dummy eye position due to the voltage offset in response to a positive overflow of the dynamic monitoring value in the increment direction or a negative overflow in the decrement direction.

[0036] In some examples, the eye diagram may optionally include multiple eye units, and the unlock phase adjustment removes the sampling clock phase from the dummy eye position by causing the sampling clock phase to produce a phase shift of half the width of one eye unit.

[0037] In some examples, optionally, the fake eye location further includes: extending from the intersection along the rising edge and the falling edge to a neighborhood location of the sampled reference voltage where the voltage offset occurs; the anomaly handling method further includes: performing voltage correction adjustment on the sampled reference voltage; wherein the voltage correction adjustment is used to cause the sampled reference voltage to generate a reset offset that reduces the voltage offset.

[0038] In some examples, the anomaly handling method may optionally further include: determining, based on the periodic DC imbalance deviation of a plurality of consecutive periodic samples, the offset direction that causes the voltage offset that currently locks the sampling clock phase at the dummy eye position; wherein the voltage correction adjustment is used to generate the reset offset in the direction opposite to the offset direction of the sampling reference voltage.

[0039] In some examples, optionally, the deviation determination result of the quantity ratio of the first logic level and the second logic level in the periodic sample compared with the DC balance standard includes one of the following: a first determination result indicating that the quantity ratio of the first logic level is too high, a second determination result indicating that the quantity ratio of the second logic level is too high, and a third determination result indicating that the quantity ratios of the first logic level and the second logic level are balanced; the determination of the estimated imbalance deviation based on the occurrence frequency of the first determination result, the second determination result, and the third determination result in the periodic DC imbalance deviation of a series of consecutive periodic samples includes: in response to the occurrence of the first determination result in the periodic DC imbalance deviation of any one periodic sample, performing an increment operation on the dynamic monitoring value; wherein, the dynamic monitoring value is used to characterize the degree of deviation of the quantity ratio of the first logic level and the second logic level in the sampled data compared with the DC balance standard; in response to the occurrence of the second determination result in the occurrence frequency of the first determination result in the periodic DC imbalance deviation of any one periodic sample, the dynamic monitoring value is used to characterize the degree of deviation of the quantity ratio of the first logic level and the second logic level in the sampled data compared with the DC balance standard; in response to the occurrence of the second determination result in the occurrence frequency of the first logic level and the second logic level in ... frequency of the In response to the occurrence of the periodic DC imbalance deviation, the dynamic monitoring value is decremented by 1; in response to the occurrence of the third determination result in the periodic DC imbalance deviation of any of the periodic samples, the dynamic monitoring value is incremented or decremented by 0; the anomaly handling method simultaneously determines whether the sampling clock phase is currently locked at the dummy position due to the voltage offset, and the offset direction of the voltage offset that causes the sampling clock phase to be currently locked at the dummy position: in response to the overflow of the dynamic monitoring value in the increment or decrement direction, a determination result indicating that the sampling clock phase is currently locked at the dummy position due to the voltage offset, and the offset direction of the voltage offset are generated; wherein: the negative overflow of the dynamic monitoring value in the decrement direction is used to characterize the offset direction of the voltage offset as: a first offset direction relative to the crossover point and closer to the first logic level; the positive overflow of the dynamic monitoring value in the increment direction is used to characterize the offset direction of the voltage offset as: a second offset direction relative to the crossover point and closer to the second logic level.

[0040] As can be seen above, embodiments of this application can support the data sender in performing data scrambling with DC balance as the target data to be transmitted, so that the data receiver can receive scrambled data with DC balance characteristics through a physical channel. Based on this, embodiments of this application can obtain periodic samples of the sampled data obtained by the data receiver from sampling the scrambled data. Furthermore, when it is determined, based on the periodic DC imbalance deviation of multiple consecutive periodic samples, that the sampling clock phase of the scrambled data is locked at the false eye position in the eye diagram of the scrambled data, the sampling clock phase can be unlocked and adjusted to remove it from the false eye position. This allows for timely restoration of dynamic calibration of the sampling clock phase, thereby reducing the risk of CDR failure. Attached Figure Description

[0041] The following figures are for illustrative purposes only and do not limit the scope of this application:

[0042] Figure 1 This is a schematic diagram illustrating the principle of CDR technology used in the embodiments of this application;

[0043] Figure 2 This is a schematic diagram illustrating an abnormal example of the sampling clock phase at the location of the artificial eye in an embodiment of this application.

[0044] Figure 3 This is an exemplary structural diagram of the exception handling circuit for CDR in the embodiments of this application;

[0045] Figure 4 This is an exemplary structural diagram of the sample detection module of the anomaly handling circuit for CDR in an embodiment of this application;

[0046] Figure 5 This is an exemplary structural diagram of the fake eye decision module of the anomaly handling circuit for CDR in an embodiment of this application;

[0047] Figure 6 This is a schematic diagram of the state transition of the response adjustment module of the exception handling circuit used for CDR in the embodiments of this application. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.

[0049] Figure 1 This is a schematic diagram illustrating the principle of CDR technology used in the embodiments of this application. Please refer to... Figure 1In the embodiments of this application, the data receiver (e.g., a die of an AI chip or an AI chip) of the physical channel (e.g., based on the UCIE protocol or PCIe protocol) samples the scrambled data transmitted by the data sender (e.g., a die of an AI chip or an AI chip) through the physical channel. The scrambled data described herein is generated by the data sender through data scrambling with DC balance as the target data to be transmitted. Data scrambling is a data processing method that performs randomization-like processing on the data sequence of the target data to be transmitted, in order to break the regular continuous single-value distribution (e.g., a continuous distribution of a large number of first logic levels or a large number of second logic levels) in the target data to be transmitted. Furthermore, DC balance, as the target of data scrambling, can be used to balance the proportion of first logic levels (e.g., "1") and second logic levels (e.g., "0") in the scrambled data, that is, the proportion of both first logic levels (e.g., "1") and second logic levels (e.g., "0") in the scrambled data approaches 50%, thereby optimizing the data transmission characteristics in the physical channel.

[0050] For example, see still Figure 1 In the embodiments of this application, the sampling operation of the scrambled data by the data receiver can be performed based on the sampling reference voltage V_ref at the sampling clock phase I_clk. The data receiver can obtain the sampled data I_data by sampling the scrambled data transmitted in the physical channel. Furthermore, the data receiver can obtain the target data from the data sender by performing data descrambling on the sampled data I_data (i.e., the reverse processing of data scrambling). The scrambled data is transmitted in the physical channel in the form of a data signal, and the signal voltage of the data signal is determined by the logic level of the scrambled data. In this case, data signals with a signal voltage higher than the sampling reference voltage V_ref in the physical channel can be sampled as a first logic level (e.g., "1") in the sampled data I_data, and data signals with a signal voltage lower than or equal to the sampling reference voltage V_ref in the physical channel can be sampled as a second logic level (e.g., "0") in the sampled data I_data. Thus, sampled data I_data including the first logic level and the second logic level can be obtained. Furthermore, if the sampling clock phase I_clk is accurate, the logic level sequence of the first logic level and the second logic level in the sampled data I_data corresponds to the logic level sequence of the scrambled data.

[0051] For example, please see again Figure 1In embodiments of this application, CDR can be used at the data receiver to dynamically calibrate the sampling clock phase I_clk using the eye diagram of scrambled data. The eye diagram of the scrambled data can be generated based on the scrambled data, for example, by superimposing segments of the scrambled data. The eye diagram of the scrambled data can include multiple eye units, and the eye width of each eye unit can correspond to one UI (Unit Interval) of data transmission. It is understood that... Figure 1 The intention is to express the relationship between scrambled data and eye diagrams, therefore, Figure 1 The text merely provides an illustrative representation of the waveform morphology of scrambled data and eye diagrams, and is not intended to utilize... Figure 1 The graphic shape representing the scrambled data and eye diagram defines the waveform shape of the scrambled data and eye diagram.

[0052] For example, in embodiments of this application, the data receiver may include a CDR module, which can perform CDR-based dynamic calibration of the sampled clock phase I_clk using an eye diagram of the scrambled data. Specifically, the CDR module can determine the leading-edge clock phase Q_clk before the sampled clock phase I_clk and the trailing-edge clock phase Q1_clk after the sampled clock phase I_clk based on the phase position of the sampled clock phase I_clk in the eye diagram. The phase intervals between the leading-edge clock phase Q_clk and the trailing-edge clock phase Q1_clk and the sampled clock phase I_clk are equal (e.g., half an eye width or 0.5 UI). Furthermore, the CDR module can dynamically calibrate the current phase position of the sampled clock phase I_clk using the sampled data I_data and the leading-edge data Q_data and trailing-edge data Q1_data obtained by sampling the scrambled data at the leading-edge clock phase Q_clk and the trailing-edge clock phase Q1_clk, respectively.

[0053] For example, in an embodiment of this application, the CDR module can dynamically calibrate the current phase position of the sampling clock phase I_clk based on the first XOR result D_lead of the sampled data I_data and the leading edge data Q_data, and the second XOR result D_lag of the sampled data I_data and the trailing edge data Q1_data. For example, dynamic calibration can cause the sampling clock phase I_clk to be maintained at a phase position that satisfies the following target condition: the first XOR result D_lead and the second XOR result D_lag are at the same or substantially the same number of times the first logic level (e.g., "1") within a preset duration (i.e., the difference in the number of times is less than a preset tolerance value). The phase position of the sampling clock phase I_clk that satisfies the above target condition can typically be the center position of the eye unit in the eye diagram, at which point the sampling accuracy of the scrambled data is highest.

[0054] For example, in an embodiment of this application, when the sampling clock phase I_clk is maintained at the center of the eye unit, the leading edge clock phase Q_clk and the trailing edge clock phase Q1_clk can both be located at the intersection point formed by the rising edge and falling edge in the eye diagram.

[0055] For example, in the embodiments of this application, the calibrated value of the sampling reference voltage V_ref is usually the voltage value at the crossover point. Therefore, when the leading edge clock phase Q_clk and the trailing edge clock phase Q1_clk can both be at the crossover point in the eye diagram, the leading edge data Q_data and the trailing edge data Q1_data may fluctuate between the first logic level and the second logic level. However, the probability that the fluctuating leading edge data Q_data and trailing edge data Q1_data are at the first logic level or the second logic level is the same or substantially the same. Thus, the number of times the first XOR result D_lead and the second XOR result D_lag are at the first logic level (e.g., "1") within a preset time period is the same or substantially the same (i.e., the difference in the number of times is less than a preset tolerance value), thereby maintaining the sampling clock phase I_clk at the center position of the eye unit.

[0056] For example, in the embodiments of this application, if the sampling reference voltage V_ref deviates from the calibration value (i.e., deviates from the crossover point in the eye diagram), when the CDR module determines that the phase position of the sampling clock phase I_clk meets the aforementioned target condition, there may be an ideal situation where the sampling clock phase I_clk is located at the center of the eye unit, or there may be an abnormal situation where the sampling clock phase I_clk is locked at the fake eye position in the eye diagram.

[0057] Figure 2 This is a schematic diagram illustrating an abnormal example of the sampling clock phase at the location of the artificial eye in an embodiment of this application. Please refer to... Figure 2If the sampling reference voltage V_ref experiences a voltage offset relative to the calibration value (i.e., deviating from the crossover point in the eye diagram) that is close to the second logic level (e.g., "0"), and the phase position of the sampling clock phase I_clk in the eye diagram is exactly at (e.g., at the initial state or at the eye diagram crossover point due to waveform changes), then the sampling data I_data will remain at the first logic level (e.g., "1") for a period of time due to the voltage offset of the sampling reference voltage V_ref. Furthermore, since the leading edge clock phase Q_clk and the trailing edge clock phase Q1_clk are both at the center of the eye unit at this time, the leading edge data Q_data and the trailing edge data Q1_data may both remain at the second logic level (e.g., "0") for a period of time. This results in the first XOR result D_lead and the second XOR result D_lag being at the first logic level (e.g., "1") the same number of times within a preset duration. Consequently, the sampling clock phase I_clk will be locked at the eye diagram crossover point for a period of time, causing CDR to fail. That is, the fake eye position for the sampling clock phase I_clk includes the intersection point formed by the rising and falling edges in the eye diagram, and the neighborhood position extending from the intersection point along the rising and falling edges to the sampling reference voltage V_ref where the voltage shift occurs. Furthermore, the embodiments of this application attempt to reduce the failure risk of CDR by releasing the abnormal lock-up of the sampling clock phase I_clk at the fake eye position.

[0058] Figure 3 This is an exemplary structural diagram of the exception handling circuit used for CDR in an embodiment of this application. Please refer to... Figure 3 In the embodiments of this application, the anomaly handling circuit for CDR may include a sample acquisition module 31, a sample detection module 33, a fake eye decision module 35, and a response adjustment module 37.

[0059] For example, in an embodiment of this application, the sample acquisition module 31 can be used to acquire periodic samples of the sampled data I_data from the data receiver. For instance, the sample acquisition module 31 can be specifically configured to periodically sample the sampled data I_data according to a pre-set periodic bit width.

[0060] For example, in an embodiment of this application, the sample acquisition module 31 may include a sampling register sequence. The periodic bit width of the periodic sampling (i.e., a single periodic sample) performed by the sample acquisition module 31 on the sampled data I_data can be determined by the sequence length of the sampling register sequence (e.g., 16 bits, 32 bits, or 64 bits), and the periodic sample (i.e., a single periodic sample) obtained by the sample acquisition module 31 each time through periodic sampling can be stored in the sampling register sequence.

[0061] For example, in an embodiment of this application, the sample detection module 33 can be used to: detect the periodic DC imbalance deviation of the periodic samples of the sampled data I_data; wherein, the periodic DC imbalance deviation of the periodic samples of the sampled data I_data can be used to characterize the deviation judgment result of the ratio of the number of the first logic level and the second logic level in the periodic samples (i.e., a single periodic sample) of the sampled data I_data compared with the balance standard of DC balance.

[0062] For example, in an embodiment of this application, the sample detection module 33 can be specifically configured to periodically obtain periodic samples of sampled data I_data from the sampling register sequence of the sample acquisition module 31.

[0063] For example, in an embodiment of this application, the sample detection module 33 can be specifically configured to: determine the periodic DC imbalance deviation of the periodic samples of the sampled data I_data based on the deviation of the number of single values ​​of the first logic level in the periodic samples of the sampled data I_data from a preset threshold number; wherein, the threshold number can be half of the periodic bit width of the periodic samples of the sampled data I_data.

[0064] For example, in an embodiment of this application, the sample detection module 33 can be specifically configured to: perform an accumulation operation a corresponding number of times based on the number of single values ​​of the first logic level in the periodic samples of the sampled data I_data; wherein the operation result of the accumulation operation is used to characterize the number of single values ​​of the first logic level in the periodic samples of the sampled data I_data; and compare the operation result of the accumulation operation with the aforementioned threshold number; wherein the comparison result of the operation result of the accumulation operation and the threshold number is used to characterize the periodic DC imbalance deviation of the periodic samples of the sampled data I_data.

[0065] For example, if the comparison result generated by the sample detection module 33 is the binary number "2'b00", then the periodic DC imbalance deviation represented by the comparison result at this time is: the operation result of the accumulation operation (i.e., the number of single values ​​of the first logic level in the periodic sample of the sampled data I_data) is equal to the aforementioned threshold number (i.e., half of the periodic bit width of the periodic sample of the sampled data I_data). That is, the ratio of the number of the first logic level and the second logic level in the periodic sample of the sampled data I_data meets the balance standard of DC balance.

[0066] For example, if the comparison result generated by the sample detection module 33 is the binary number "2'b01", then the periodic DC imbalance deviation represented by the comparison result at this time is: the operation result of the accumulation operation (i.e., the number of single values ​​of the first logic level in the periodic sample of the sampled data I_data) is greater than the aforementioned threshold number (i.e., half of the periodic bit width of the periodic sample of the sampled data I_data). That is, the proportion of the number of the first logic level in the periodic sample of the sampled data I_data is higher than the DC balance standard, and the proportion of the number of the second logic level in the periodic sample of the sampled data I_data is lower than the DC balance standard.

[0067] For example, if the comparison result generated by the sample detection module 33 is the binary number "2'b11", then the periodic DC imbalance deviation represented by the comparison result at this time is: the operation result of the accumulation operation (i.e., the number of single values ​​of the first logic level in the periodic sample of the sampled data I_data) is less than the aforementioned threshold number (i.e., half of the periodic bit width of the periodic sample of the sampled data I_data). That is, the proportion of the number of the first logic level in the periodic sample of the sampled data I_data is lower than the DC balance standard, and the proportion of the number of the second logic level in the periodic sample of the sampled data I_data is higher than the DC balance standard.

[0068] Figure 4 This is an exemplary structural diagram of the sample detection module of the anomaly handling circuit used in CDR in an embodiment of this application. Please refer to... Figure 4 In the embodiments of this application, the sample detection module 33 may include a statistics register 331, an accumulator adder 333, and a threshold comparator 335.

[0069] For example, in an embodiment of this application, the accumulator adder 333 can be used to perform an accumulation operation on the register value of the statistics register 331 a corresponding number of times based on the number of single values ​​of the first logic level in the periodic samples of the sampled data I_data; wherein, the register value of the statistics register 331, as the result of the accumulation operation, can be used to characterize the number of single values ​​of the first logic level in the periodic samples of the sampled data I_data.

[0070] For example, in an embodiment of this application, the threshold comparator 335 can be used to generate a comparison result between the register value of the statistics register 331 (i.e., the result of the accumulation operation) and the aforementioned threshold number; wherein, the comparison result generated by the threshold comparator 335 is the aforementioned comparison result generated by the sample detection module 33, and can be used to characterize the periodic DC imbalance deviation of the periodic samples of the sampled data I_data.

[0071] For example, in an embodiment of this application, the fake eye decision module 35 can be used to: determine whether the sampling clock phase I_clk is currently locked in the fake eye position in the eye diagram of the scrambled data due to the voltage offset of the sampling reference voltage V_ref, based on the periodic DC imbalance deviation of multiple consecutive periodic samples of the sampling data I_data.

[0072] For example, in an embodiment of this application, the fake eye decision module 35 can be specifically configured to: determine the estimated imbalance deviation of the sampled data I_data based on the periodic DC imbalance deviation of multiple consecutive periodic samples of the sampled data I_data; wherein, the estimated imbalance deviation of the sampled data I_data is used to characterize the deviation of the proportion of the first logic level and the second logic level in the sampled data I_data relative to the DC balance; and, based on the estimated imbalance deviation of the sampled data I_data, determine whether the sampling clock phase I_clk is currently locked in the fake eye position in the eye diagram of the scrambled data due to the voltage offset of the sampling reference voltage V_ref.

[0073] For example, in an embodiment of this application, the deviation determination result characterized by the periodic DC imbalance deviation of the periodic samples (i.e., a single periodic sample) of the sampled data I_data may include one of the following: a first determination result indicating that the proportion of the number of first logic levels in the periodic samples (i.e., a single periodic sample) of the sampled data I_data is too high; a second determination result indicating that the proportion of the number of second logic levels in the periodic samples (i.e., a single periodic sample) of the sampled data I_data is too high; and a third determination result indicating that the proportions of the number of first logic levels and second logic levels in the periodic samples (i.e., a single periodic sample) of the sampled data I_data are balanced. In this case, the fake eye decision module 35 may be specifically configured to: determine the estimated imbalance deviation of the sampled data I_data based on the number of times the first determination result, the second determination result, and the third determination result appear in the periodic DC imbalance deviation of multiple periodic samples of the continuous sampled data I_data.

[0074] For example, in an embodiment of this application, the fake eye decision module 35 can be specifically configured as follows:

[0075] In response to the occurrence of the first determination result in the periodic DC imbalance deviation of any periodic sample of the sampled data I_data, the dynamic monitoring value is incremented by 1; wherein, the dynamic monitoring value is used to characterize the degree of deviation between the proportion of the first logic level and the second logic level in the sampled data I_data and the balance standard of DC balance.

[0076] In response to the occurrence of the second determination result in the periodic DC imbalance deviation of any periodic sample of the sampled data I_data, a decrement operation of 1 is performed on the dynamic monitoring value;

[0077] In response to the occurrence of the third determination result in the periodic DC imbalance deviation of any periodic sample of the sampled data I_data, perform a plus or minus operation on the dynamic monitoring value.

[0078] In response to a positive overflow of the dynamic monitoring value in the addition direction or a negative overflow in the subtraction direction, a determination result is generated indicating the position of the spurious eye in the eye diagram of the scrambled data, which is currently locked due to the voltage offset of the sampling reference voltage V_ref.

[0079] Figure 5 This is an exemplary structural diagram of the fake eye decision module of the anomaly handling circuit for CDR in an embodiment of this application. Please refer to... Figure 5 In the embodiments of this application, the fake eye decision module 35 may include: a decision register 351, a sign adder 353, and a signal generator 355.

[0080] For example, in an embodiment of this application, the dynamic monitoring value maintained by the fake eye decision module 35 can be the register value of the decision register 351.

[0081] For example, in an embodiment of this application, the symbolic adder 353 can be used to:

[0082] In response to the occurrence of the first determination result in the periodic DC imbalance deviation of any periodic sample of the sampled data I_data, the register value (i.e. the dynamic monitoring value) of the decision register 351 is incremented by 1.

[0083] In response to the occurrence of the second determination result in the periodic DC imbalance deviation of any periodic sample of the sampled data I_data, the register value (i.e. the dynamic monitoring value) of the decision register 351 is decremented by 1.

[0084] In response to the occurrence of the third determination result in the periodic DC imbalance deviation of any periodic sample of the sampled data I_data, the register value (i.e., the dynamic monitoring value) of the decision register 351 is incremented or decremented by 0.

[0085] For example, in an embodiment of this application, the signal generator 355 may be used to generate a determination result indicating the position of the fake eye in the eye diagram of the scrambled data that is currently locked due to the voltage offset of the sampling reference voltage V_ref, in response to a positive overflow of the register value (i.e., the dynamic monitoring value) of the decision register 351 in the addition direction or a negative overflow in the subtraction direction.

[0086] For example, in an embodiment of this application, the response adjustment module 37 can be used to: in response to a determination result indicating that the sampling clock phase I_clk is currently locked in the false eye position in the eye diagram of the scrambled data due to the voltage offset of the sampling reference voltage V_ref, perform unlock phase adjustment on the sampling clock phase I_clk; wherein, the unlock phase adjustment is used to remove the sampling clock phase I_clk from the false eye position in the eye diagram of the scrambled data.

[0087] For example, in an embodiment of this application, the response adjustment module 37 can perform unlocked phase adjustment on the sampling clock phase I_clk by controlling the CDR module of the data receiver.

[0088] Figure 6 This is a schematic diagram of the state transition of the response adjustment module of the exception handling circuit used for CDR in an embodiment of this application. Please refer to... Figure 6 In the embodiments of this application:

[0089] The response adjustment module 37 can be in an idle state S371 during the period when the sampling clock phase I_clk is not locked at the fake eye position in the eye diagram of the scrambled data, so as to reduce the circuit power consumption of the abnormal handling circuit for CDR.

[0090] The response adjustment module 37 can respond to the determination result that the fake eye position in the eye diagram of the scrambled data is currently locked due to the voltage offset of the sampling reference voltage V_ref, and transition from the idle state S371 to the fake eye state S373 to realize the wake-up operation with the determination result as the enable signal.

[0091] The response adjustment module 37 can transition from the fake eye state S373 to the adjustment state S375 after wake-up is completed, so as to implement phase adjustment on the sampling clock phase I_clk in the adjustment state S375 (or implement it by controlling the sampling clock phase I_clk through the CDR module) and then transition back to the idle state S371 after the phase adjustment is completed.

[0092] For example, in an embodiment of this application, the unlocking phase adjustment implemented by the response adjustment module 37 on the sampling clock phase I_clk (or implemented by controlling the CDR module on the sampling clock phase I_clk) can cause the sampling clock phase I_clk to be removed from the fake eye position in the eye diagram of the scrambled data by causing the sampling clock phase I_clk to produce a phase offset of half an eye width (e.g., 0.5 UI) of one eye unit.

[0093] Based on embodiments of this application, the data sender can scramble the target data to be transmitted with DC balance as the objective, so that the data receiver can receive scrambled data with DC balance characteristics through a physical channel. Furthermore, the anomaly handling circuit for CDR can acquire periodic samples of the sampled data obtained by the data receiver from sampling the scrambled data. When it is determined, based on the periodic DC imbalance deviation of multiple consecutive periodic samples, that the sampling clock phase I_clk of the scrambled data is locked at a false eye position in the eye diagram of the scrambled data, the sampling clock phase I_clk can be unlocked by performing phase adjustment, causing it to move away from the false eye position in the eye diagram of the scrambled data. This allows for timely restoration of dynamic calibration of the sampling clock phase I_clk, thereby reducing the risk of CDR failure.

[0094] For example, in an embodiment of this application, the response adjustment module 37 may further be used to: perform voltage correction adjustment on the sampling reference voltage V_ref; wherein the voltage correction adjustment is used to make the sampling reference voltage V_ref generate a reset offset that reduces the voltage offset, so as to reduce the neighborhood position in the false eye position in the eye diagram of the scrambled data, thereby reducing the risk that the sampling clock phase I_clk will be locked again.

[0095] For example, in an embodiment of this application, the response adjustment module 37 can perform voltage correction adjustment on the sampled reference voltage V_ref by controlling the CDR module of the data receiver.

[0096] Exemplary, in an embodiment of this application, the response adjustment module 37 can... Figure 6 In the adjustment state S375, voltage correction adjustment is performed on the sampled reference voltage V_ref (e.g., controlled by the CDR module), and the response adjustment module 37 can transition from the adjustment state S375 back to the idle state S371 in response to the completion of both the unlocking phase adjustment and the voltage correction adjustment.

[0097] For example, in an embodiment of this application, the fake eye decision module 35 can be further configured to: determine the offset direction of the voltage offset of the sampling reference voltage V_ref that causes the sampling clock phase I_clk to be currently locked at the fake eye position, based on the periodic DC imbalance deviation of multiple consecutive periodic samples of the sampling data I_data. In this case, the voltage correction adjustment implemented by the response adjustment module 37 on the sampling reference voltage V_ref (or implemented by controlling the CDR module on the sampling reference voltage V_ref) is used to make the sampling reference voltage V_ref generate a reset offset in the direction opposite to the offset direction of the voltage offset of the sampling reference voltage V_ref.

[0098] For example, in an embodiment of this application, the fake eye decision module 35 (e.g., signal generator 355) can be specifically configured to: in response to the overflow of a dynamic monitoring value (e.g., the register value of decision register 351) in the addition or subtraction direction, generate a decision result indicating that the sampling clock phase I_clk is currently locked at the fake eye position due to the voltage offset of the sampling reference voltage V_ref, and the offset direction of the voltage offset of the sampling reference voltage V_ref. Specifically, the negative overflow of the dynamic monitoring value (e.g., the register value of decision register 351) in the subtraction direction can be used to characterize the voltage offset direction of the sampling reference voltage V_ref as a first offset direction relative to the crossover point in the eye diagram, closer to the first logic level; and the positive overflow of the dynamic monitoring value (e.g., the register value of decision register 351) in the addition direction can be used to characterize the voltage offset direction of the sampling reference voltage V_ref as a second offset direction relative to the crossover point in the eye diagram, closer to the second logic level.

[0099] In another embodiment of this application, an AI chip is provided, which may include a CDR module and an exception handling circuit for CDR in the embodiment.

[0100] For example, in the embodiments of this application, the AI ​​chip can be any one of the following integrated circuit chips suitable for artificial intelligence: GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Units).

[0101] For example, in an embodiment of this application, if the AI ​​chip uses Chiplet technology, each die of the AI ​​chip can include a CDR module and an exception handling circuit for CDR as described in the embodiment. Alternatively, the PCIe controller of the AI ​​chip can include a CDR module and an exception handling circuit for CDR as described in the embodiment.

[0102] In another embodiment of this application, an exception handling method for CDR is provided, and the exception handling method may include the following steps executed concurrently in a pipelined manner:

[0103] Sample acquisition steps: Acquire periodic samples of the sampled data I_data from the data receiver; wherein, the sampled data I_data can be obtained by the data receiver sampling the scrambled data transmitted by the data sender through the physical channel. The scrambled data can be generated by the data sender by performing data scrambling on the target data to be transmitted with the goal of DC balance. The DC balance is used to make the proportion of the first logic level and the second logic level in the scrambled data tend to be balanced. The sampling operation of the scrambled data by the data receiver is performed based on the sampling reference voltage on the sampling clock phase. Furthermore, the CDR applied to the data receiver (e.g., the CDR module of the data receiver) can be used to dynamically calibrate the sampling clock phase I_clk using the eye diagram of the scrambled data.

[0104] Sample detection steps: Detect the periodic DC imbalance deviation of the periodic samples of the sampled data I_data; wherein, the periodic DC imbalance deviation of the periodic samples of the sampled data I_data can be used to characterize the deviation judgment result of the ratio of the first logic level and the second logic level in the periodic samples (i.e., a single periodic sample) of the sampled data I_data compared with the DC balance standard.

[0105] False eye detection steps: Based on the periodic DC imbalance deviation of multiple consecutive periodic samples of the sampled data I_data, determine whether the current sampling clock phase I_clk is locked in the false eye position in the eye diagram of the scrambled data due to the voltage offset of the sampling reference voltage V_ref;

[0106] Response adjustment step: In response to the determination result indicating that the sampling clock phase I_clk is currently locked in the false eye position in the eye diagram of the scrambled data due to the voltage offset of the sampling reference voltage V_ref, unlock phase adjustment is performed on the sampling clock phase I_clk; wherein, unlock phase adjustment is used to remove the sampling clock phase I_clk from the false eye position in the eye diagram of the scrambled data.

[0107] Based on embodiments of this application, the data sender can scramble the target data to be transmitted with DC balance as the objective, so that the data receiver can receive scrambled data with DC balance characteristics through a physical channel. Furthermore, the anomaly handling method for CDR can obtain periodic samples of the sampled data obtained by the data receiver from sampling the scrambled data. When it is determined, based on the periodic DC imbalance deviation of multiple consecutive periodic samples, that the sampling clock phase I_clk of the scrambled data is locked at a false eye position in the eye diagram of the scrambled data, the sampling clock phase I_clk can be unlocked by performing phase adjustment, causing it to move away from the false eye position in the eye diagram of the scrambled data. This allows for timely restoration of dynamic calibration of the sampling clock phase I_clk, thereby reducing the risk of CDR failure.

[0108] For example, in an embodiment of this application, the sample acquisition step may specifically include: periodically sampling the sampled data I_data according to a pre-set periodic bit width.

[0109] For example, in an embodiment of this application, the sample detection step may specifically include: determining the periodic DC imbalance deviation of the periodic sample of the sampled data I_data based on the deviation of the number of single values ​​of the first logic level in the periodic sample of the sampled data I_data from a preset threshold number; wherein, the threshold number may be half of the periodic bit width of the periodic sample of the sampled data I_data.

[0110] For example, in an embodiment of this application, the process of determining the periodic DC imbalance deviation of the periodic samples of the sampled data I_data based on the number deviation of the number of single values ​​of the first logic level in the periodic samples of the sampled data I_data compared to a preset threshold number in the sample detection step may specifically include:

[0111] Based on the number of single values ​​of the first logic level in the periodic samples of the sampled data I_data, an accumulation operation is performed a corresponding number of times; wherein, the result of the accumulation operation is used to characterize the number of single values ​​of the first logic level in the periodic samples of the sampled data I_data;

[0112] The result of the accumulation operation is compared with the aforementioned threshold number; wherein, the comparison result of the accumulation operation and the threshold number is used to characterize the periodic DC imbalance deviation of the periodic samples of the sampled data I_data.

[0113] For example, in an embodiment of this application, the fake eye determination step may specifically include:

[0114] Based on the periodic DC imbalance deviation of multiple consecutive periodic samples of the sampled data I_data, the estimated imbalance deviation of the sampled data I_data is determined; wherein, the estimated imbalance deviation of the sampled data I_data is used to characterize the deviation of the proportion of the first logic level and the second logic level in the sampled data I_data from the DC balance.

[0115] Based on the estimated imbalance deviation of the sampled data I_data, determine whether the current sampling clock phase I_clk is locked at the false eye position in the eye diagram of the scrambled data due to the voltage offset of the sampling reference voltage V_ref.

[0116] For example, in an embodiment of this application, the deviation determination result characterized by the periodic DC imbalance deviation of the periodic samples (i.e., a single periodic sample) of the sampled data I_data may include one of the following: a first determination result indicating that the proportion of the number of first logic levels in the periodic samples (i.e., a single periodic sample) of the sampled data I_data is too high; a second determination result indicating that the proportion of the number of second logic levels in the periodic samples (i.e., a single periodic sample) of the sampled data I_data is too high; and a third determination result indicating that the proportions of the number of first logic levels and second logic levels in the periodic samples (i.e., a single periodic sample) of the sampled data I_data are balanced. In this case, the process of determining the estimated imbalance deviation of the sampled data I_data based on the periodic DC imbalance deviation of multiple consecutive periodic samples of the sampled data I_data in the fake eye decision step may specifically include: determining the estimated imbalance deviation of the sampled data I_data based on the number of times the first determination result, the second determination result, and the third determination result appear in the periodic DC imbalance deviation of multiple consecutive periodic samples of the sampled data I_data.

[0117] For example, in an embodiment of this application, the process of determining the estimated imbalance deviation of the sampled data I_data based on the frequency of occurrence of the first determination result, the second determination result, and the third determination result in the periodic DC imbalance deviation of multiple periodic samples of the continuously sampled data I_data in the fake eye determination step may specifically include:

[0118] In response to the occurrence of the first determination result in the periodic DC imbalance deviation of any periodic sample of the sampled data I_data, the dynamic monitoring value is incremented by 1; wherein, the dynamic monitoring value is used to characterize the degree of deviation between the proportion of the first logic level and the second logic level in the sampled data I_data and the balance standard of DC balance.

[0119] In response to the occurrence of the second determination result in the periodic DC imbalance deviation of any periodic sample of the sampled data I_data, a decrement operation of 1 is performed on the dynamic monitoring value;

[0120] In response to the occurrence of the third determination result in the periodic DC imbalance deviation of any periodic sample of the sampled data I_data, a zero-addition or zero-subtraction operation is performed on the dynamic monitoring value.

[0121] For example, in an embodiment of this application, the process of determining whether the sampling clock phase I_clk is currently locked in the false eye position in the eye diagram of the scrambled data due to the voltage offset of the sampling reference voltage V_ref in the false eye determination step based on the estimation imbalance deviation of the sampling data I_data may specifically include: in response to a positive overflow of the dynamic monitoring value in the addition direction or a negative overflow in the subtraction direction, generating a determination result indicating that the sampling clock phase I_clk is currently locked in the false eye position in the eye diagram of the scrambled data due to the voltage offset of the sampling reference voltage V_ref.

[0122] For example, in an embodiment of this application, the response adjustment step can implement unlock phase adjustment of the sampling clock phase I_clk by controlling the CDR module of the data receiver.

[0123] For example, in an embodiment of this application, the unlocking phase adjustment implemented by the response adjustment step on the sampling clock phase I_clk (or implemented by controlling the sampling clock phase I_clk via the CDR module) can cause the sampling clock phase I_clk to be removed from the pseudo-eye position in the eye diagram of the scrambled data by causing the sampling clock phase I_clk to produce a phase offset of half an eye width (e.g., 0.5 UI) of one eye unit.

[0124] For example, in an embodiment of this application, the response adjustment step may further include: performing voltage correction adjustment on the sampling reference voltage V_ref; wherein the voltage correction adjustment is used to cause the sampling reference voltage V_ref to generate a reset offset that reduces voltage offset, so as to reduce the neighborhood position in the false eye position in the eye diagram of the scrambled data, thereby reducing the risk that the sampling clock phase I_clk will be locked again.

[0125] For example, in an embodiment of this application, the response adjustment step can perform voltage correction adjustment on the sampled reference voltage V_ref by controlling the CDR module of the data receiver.

[0126] For example, in an embodiment of this application, the fake eye decision step may further include: determining the offset direction of the voltage offset of the sampling reference voltage V_ref that causes the sampling clock phase I_clk to be currently locked at the fake eye position, based on the periodic DC imbalance deviation of multiple consecutive periodic samples of the sampling data I_data. In this case, the voltage correction adjustment implemented by the response adjustment step on the sampling reference voltage V_ref (or implemented by controlling the sampling reference voltage V_ref through the CDR module) is used to cause the sampling reference voltage V_ref to generate a reset offset in the direction opposite to the offset direction of the voltage offset of the sampling reference voltage V_ref.

[0127] For example, in an embodiment of this application, the fake eye decision step can be specifically configured to: in response to the overflow of the dynamic monitoring value in the addition or subtraction direction, generate a determination result indicating that the sampling clock phase I_clk is currently locked at the fake eye position due to the voltage offset of the sampling reference voltage V_ref, and the offset direction of the voltage offset of the sampling reference voltage V_ref. Specifically, the negative overflow of the dynamic monitoring value in the subtraction direction can be used to characterize the voltage offset direction of the sampling reference voltage V_ref as a first offset direction relative to the crossover point in the eye diagram, closer to the first logic level; and the positive overflow of the dynamic monitoring value in the addition direction is used to characterize the voltage offset direction of the sampling reference voltage V_ref as a second offset direction relative to the crossover point in the eye diagram, closer to the second logic level.

[0128] It is understood that, in the embodiments of this application, the various parts described by example may be related by an "and / or" relationship. In this document, "and / or" means that the contexts connected by it may be a common "and" relationship or an alternative "or" relationship. Therefore, the various parts having an "and / or" relationship can be understood to include different combinations of situations where the "and / or" between each pair of parts represents a common "and" relationship or an alternative "or" relationship, and such combinations of different situations can be considered substantially equivalent to the scope of "at least one of the parts".

[0129] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An anomaly handling circuit for clock data recovery, characterized in that, include: The sample acquisition module is used to: acquire periodic samples of the sampled data of the data receiver; wherein the sampled data is obtained by the data receiver sampling scrambled data transmitted by the data sender through a physical channel, the scrambled data is generated by the data sender by performing data scrambling on the target data to be transmitted with DC balance as the target, the DC balance is used to make the proportion of the first logic level and the second logic level in the scrambled data tend to be balanced, the sampling operation of the data receiver on the scrambled data is performed based on the sampling reference voltage on the sampling clock phase, and the clock data recovery is used to dynamically calibrate the sampling clock phase using the eye diagram of the scrambled data; The sample detection module is used to: detect the periodic DC imbalance deviation of the periodic sample; wherein, the periodic DC imbalance deviation is used to characterize the deviation judgment result of the ratio of the number of the first logic level and the second logic level in the periodic sample compared with the balance standard of the DC balance; The fake eye decision module is used to: determine whether the sampling clock phase is currently locked at the fake eye position in the eye diagram due to the voltage offset based on the periodic DC imbalance deviation of multiple consecutive periodic samples; wherein, the fake eye position includes the intersection point formed by the rising edge and falling edge in the eye diagram; A response adjustment module is configured to: in response to a determination that the sampling clock phase is currently locked at the position of the artificial eye due to the voltage offset, perform unlock phase adjustment on the sampling clock phase; wherein the unlock phase adjustment is used to disengage the sampling clock phase from the position of the artificial eye.

2. The exception handling circuit according to claim 1, characterized in that, The sample acquisition module is specifically configured as follows: The sampled data is periodically sampled according to a pre-set periodic bit width.

3. The exception handling circuit according to claim 2, characterized in that, The sample acquisition module includes a sampling register sequence; wherein the periodic bit width is determined by the sequence length of the sampling register sequence, and the periodic sample obtained each time through the periodic sampling is stored in the sampling register sequence; The sample detection module is specifically configured to periodically obtain the periodic samples from the sampling register sequence.

4. The exception handling circuit according to claim 1, characterized in that, The sample detection module is specifically configured as follows: The periodic DC imbalance deviation of the periodic sample is determined based on the deviation of the number of single values ​​of the first logic level in the periodic sample from a preset threshold number; wherein the threshold number is half of the periodic bit width of the periodic sample.

5. The exception handling circuit according to claim 4, characterized in that, The sample detection module is specifically configured as follows: Based on the number of single values ​​of the first logic level in the periodic sample, an accumulation operation is performed a corresponding number of times; wherein, the result of the accumulation operation is used to characterize the number of single values ​​of the first logic level in the periodic sample; The result of the accumulation operation is compared with the threshold number; wherein, the comparison result of the accumulation operation and the threshold number is used to characterize the periodic DC imbalance deviation of the periodic sample.

6. The exception handling circuit according to claim 5, characterized in that, The sample detection module includes: Statistical register; An accumulator adder is used to perform an accumulation operation on the register value of the statistics register a corresponding number of times based on the number of single values ​​of the first logic level in the periodic sample; wherein, the register value of the statistics register is used to represent the number of single values ​​of the first logic level in the periodic sample. A threshold comparator is used to generate a comparison result between the register value of the statistical register and the threshold number; wherein the comparison result generated by the threshold comparator is used to characterize the periodic DC imbalance deviation of the periodic sample.

7. The exception handling circuit according to claim 1, characterized in that, The fake eye decision module is specifically configured as follows: Based on the periodic DC imbalance deviation of multiple consecutive periodic samples, an estimated imbalance deviation of the sampled data is determined; wherein, the estimated imbalance deviation is used to characterize the deviation of the proportion of the first logic level and the second logic level in the sampled data compared with the DC balance; Based on the estimated imbalance deviation, it is determined whether the sampling clock phase is currently locked at the position of the artificial eye due to the voltage offset.

8. The exception handling circuit according to claim 7, characterized in that, The deviation determination result of the ratio of the first logic level and the second logic level in the periodic sample compared with the balance standard of the DC balance includes one of the following: a first determination result indicating that the ratio of the first logic level is too high, a second determination result indicating that the ratio of the second logic level is too high, and a third determination result indicating that the ratios of the first logic level and the second logic level are balanced. The fake eye decision module is specifically configured as follows: The estimated imbalance deviation is determined based on the number of times the first determination result, the second determination result, and the third determination result appear in the periodic DC imbalance deviation of a series of consecutive periodic samples.

9. The exception handling circuit according to claim 8, characterized in that, The fake eye decision module is specifically configured as follows: In response to the occurrence of the first determination result in the periodic DC imbalance deviation of any of the periodic samples, the dynamic monitoring value is incremented by 1; wherein the dynamic monitoring value is used to characterize the degree of deviation between the proportion of the first logic level and the second logic level in the sampled data and the balance standard of the DC balance; In response to the occurrence of the second determination result in the periodic DC imbalance deviation of any of the periodic samples, the dynamic monitoring value is decremented by 1. In response to the occurrence of the third determination result in the periodic DC imbalance deviation of any of the periodic samples, the dynamic monitoring value is incremented or decremented by 0 once; In response to a positive overflow of the dynamic monitoring value in the addition direction or a negative overflow in the subtraction direction, a determination result is generated indicating that the sampling clock phase is currently locked at the position of the artificial eye due to the voltage offset.

10. The exception handling circuit according to claim 9, characterized in that, The fake eye decision module includes: Decision register; wherein the dynamic monitoring value is the register value of the decision register; A sign adder is configured to increment the register value of the decision register by 1 in response to the occurrence of the first determination result in the periodic DC imbalance deviation of any of the periodic samples, decrement the register value of the decision register by 1 in response to the occurrence of the second determination result in the periodic DC imbalance deviation of any of the periodic samples, and increment or decrement the register value of the decision register by 0 in response to the occurrence of the third determination result in the periodic DC imbalance deviation of any of the periodic samples. A signal generator is used to generate a determination result indicating that the sampling clock phase is currently locked at the position of the artificial eye due to the voltage offset, in response to a positive overflow of the register value of the decision register in the addition direction or a negative overflow in the subtraction direction.

11. The exception handling circuit according to any one of claims 1 to 10, characterized in that, The eye diagram includes multiple eye units, and the unlock phase adjustment removes the sampling clock phase from the dummy eye position by causing a phase shift of half the width of one eye unit in the sampling clock phase.

12. The exception handling circuit according to any one of claims 1 to 10, characterized in that, The location of the artificial eye further includes: extending from the intersection along the rising edge and the falling edge to a neighborhood location of the sampling reference voltage where the voltage shift occurs; The response adjustment module is further used for: A voltage correction adjustment is applied to the sampled reference voltage; wherein the voltage correction adjustment is used to generate a reset offset that reduces the voltage deviation of the sampled reference voltage.

13. The exception handling circuit according to claim 12, characterized in that, The fake eye decision module is further used for: Based on the periodic DC imbalance deviation of multiple consecutive periodic samples, determine the offset direction of the voltage offset that causes the sampling clock phase to be currently locked at the position of the artificial eye; The voltage correction adjustment is used to cause the sampled reference voltage to generate the reset offset in a direction opposite to the offset direction.

14. The exception handling circuit according to claim 13, characterized in that, The deviation determination result of the ratio of the first logic level and the second logic level in the periodic sample compared with the balance standard of the DC balance includes one of the following: a first determination result indicating that the ratio of the first logic level is too high, a second determination result indicating that the ratio of the second logic level is too high, and a third determination result indicating that the ratios of the first logic level and the second logic level are balanced. The fake eye decision module is specifically configured as follows: In response to the occurrence of the first determination result in the periodic DC imbalance deviation of any of the periodic samples, the dynamic monitoring value is incremented by 1; wherein the dynamic monitoring value is used to characterize the degree of deviation between the proportion of the first logic level and the second logic level in the sampled data and the balance standard of the DC balance; In response to the occurrence of the second determination result in the periodic DC imbalance deviation of any of the periodic samples, the dynamic monitoring value is decremented by 1. In response to the occurrence of the third determination result in the periodic DC imbalance deviation of any of the periodic samples, the dynamic monitoring value is incremented or decremented by 0 once; In response to the overflow of the dynamic monitoring value in the addition or subtraction direction, a determination result is generated indicating that the sampling clock phase is currently locked at the position of the artificial eye due to the voltage offset, and the offset direction of the voltage offset; in: The negative overflow of the dynamic monitoring value in the decreasing direction is used to characterize the voltage offset direction as: a first offset direction relative to the intersection point and closer to the first logic level; The positive overflow of the dynamic monitoring value in the addition direction is used to characterize the voltage offset direction as a second offset direction relative to the crossover point and closer to the second logic level.

15. An anomaly handling method for clock data recovery, characterized in that, include: A periodic sample of the sampling data of the data receiver is obtained; wherein the sampling data is obtained by the data receiver sampling the scrambled data transmitted by the data sender through a physical channel, the scrambled data is generated by the data sender by performing data scrambling on the target data to be transmitted with DC balance as the target, the DC balance is used to make the proportion of the first logic level and the second logic level in the scrambled data tend to be balanced, the sampling operation of the data receiver on the scrambled data is performed on the sampling clock phase based on the sampling reference voltage, and the clock data recovery is used to dynamically calibrate the sampling clock phase using the eye diagram of the scrambled data; The periodic DC imbalance deviation of the periodic sample is detected; wherein, the periodic DC imbalance deviation is used to characterize the deviation judgment result of the ratio of the number of the first logic level and the second logic level in the periodic sample compared with the balance standard of the DC balance; Based on the periodic DC imbalance deviation of multiple consecutive periodic samples, it is determined whether the sampling clock phase is currently locked at the false eye position in the eye diagram due to the voltage offset of the sampling reference voltage; wherein, the false eye position includes the intersection point formed by the rising edge and falling edge in the eye diagram; In response to a determination that the sampling clock phase is currently locked at the position of the artificial eye due to the voltage offset, an unlocking phase adjustment is performed on the sampling clock phase; wherein the unlocking phase adjustment is used to remove the sampling clock phase from the position of the artificial eye.

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