A method, device and medium for optimizing LED chip packaging based on thermal management

Abstract

The application discloses an LED chip packaging optimization method and device based on heat management, equipment and medium, relates to the technical field of semiconductor device packaging and heat management, and comprises the following steps: performing heat field simulation on an LED chip packaging three-dimensional model, acquiring temperature distribution, heat flow direction and thermal resistance path in the packaging body, performing heat flow analysis on the thermal resistance path, determining a heat conduction channel, and generating a heat conduction path parameter set; applying a packaging glue function zoning scheme to the updated LED chip packaging three-dimensional model, performing heat-stress joint simulation, obtaining an optimized LED chip packaging three-dimensional model, and extracting an LED chip packaging parameter set. The application realizes zoning coordination of the heat conduction performance and flexibility of the packaging glue by performing a heat function zoning operation of the packaging glue based on the optimized heat flow density vector field, improves the heat dissipation performance and the reliability of the structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor device packaging and thermal management, and particularly relates to an LED chip packaging optimization method based on thermal management, a device and a medium. BACKGROUND

[0002] In the field of LED chip packaging, effective thermal management is one of the technologies to ensure the photoelectric performance, service life and reliability of the device; the traditional method usually uses computer-aided engineering method for thermal simulation analysis, the process includes establishing the geometric model of the packaging structure, assigning the thermal physical parameters of the material, applying power and boundary conditions to solve the steady temperature field, and improving the heat dissipation structure according to the simulation results; for the selection and distribution of the packaging adhesive material, the conventional method is mostly based on the homogeneous assumption or the simplified zoning strategy, aiming to realize the basic heat conduction and stress buffering function.

[0003] However, the traditional method still has limitations in realizing the collaborative optimization of heat dissipation and reliability; the heat dissipation structure optimization process often depends on the experience of engineers, lacks automatic and quantitative setting guidance based on physical field data, and it is difficult to explore the limit potential of the material distribution on the heat conduction performance; the layout of the packaging adhesive is usually not associated with the detailed thermal-mechanical coupling response, which easily leads to local thermal stress concentration and insufficient heat dissipation path, affecting the long-term reliability of the packaging. SUMMARY

[0004] In view of the above existing problems, the present application is proposed.

[0005] Therefore, the present application provides an LED chip packaging optimization method based on thermal management to solve the problems of insufficient collaborative optimization of heat dissipation path and material distribution and difficult accurate guarantee of the thermal reliability of the packaging structure.

[0006] To solve the above technical problems, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides a heat management-based LED chip packaging optimization method, which comprises collecting and preprocessing a set of packaging heat management parameters of an LED chip, and constructing an LED chip packaging three-dimensional model; performing heat field simulation on the LED chip packaging three-dimensional model, obtaining temperature distribution, heat flow direction and thermal resistance path in the packaging body, and performing heat flow analysis on the thermal resistance path to determine a heat conduction channel and generate a set of heat conduction path parameters; performing topology optimization on a heat dissipation structure in the LED chip packaging three-dimensional model according to the set of heat conduction path parameters, updating the LED chip packaging three-dimensional model, and obtaining an optimized heat flux density vector field through heat field simulation; based on the optimized heat flux density vector field, calculating heat flux density values and temperature gradient values, and performing heat function partitioning operation on the packaging glue according to the heat flux density values and the temperature gradient values to generate a packaging glue function partitioning scheme; applying the packaging glue function partitioning scheme to the updated LED chip packaging three-dimensional model to perform thermal-stress joint simulation, obtaining an optimized LED chip packaging three-dimensional model, and extracting a set of LED chip packaging parameters.

[0008] As a preferred scheme of the heat management-based LED chip packaging optimization method, the set of packaging heat management parameters of the LED chip comprises thermal boundary condition parameters, packaging structure geometric parameters and material thermal physical property parameters.

[0009] The preprocessing comprises data cleaning, unit unification, standardization processing, data interpolation and denoising processing.

[0010] As a preferred scheme of the heat management-based LED chip packaging optimization method, the construction of the LED chip packaging three-dimensional model comprises the following steps.

[0011] The packaging structure geometric parameters are mapped to geometric feature definition instructions, and three-dimensional geometric modeling is performed through a parameterized driving method to form an LED packaging geometric skeleton model.

[0012] The material thermal physical property parameters are assigned to the LED packaging geometric skeleton model, and finite element meshing is performed to generate an LED packaging grid model.

[0013] The thermal boundary condition parameters are applied to the corresponding surfaces of the LED packaging grid model to generate the LED chip packaging three-dimensional model.

[0014] As a preferred scheme of the heat management-based LED chip packaging optimization method, the generation of the set of heat conduction path parameters comprises the following steps.

[0015] Numerical solution of the steady-state heat conduction equation is performed on the LED chip packaging three-dimensional model to obtain a set of node temperature data, and spatial interpolation and field reconstruction are performed on the set of node temperature data to output a three-dimensional temperature field distribution.

[0016] Perform spatial differentiation on the three-dimensional temperature field distribution to obtain the temperature gradient field, and map the temperature gradient field into a heat flux density vector field according to Fourier's law;

[0017] By performing coupled analysis of the three-dimensional temperature field distribution and the heat flux density vector field, the thermal resistance path with the largest temperature drop and the most concentrated heat flux is identified.

[0018] Calculate the total thermal resistance value of each thermal resistance path, and select the thermal resistance path with a thermal resistance value less than the preset thermal resistance threshold as the target heat conduction channel.

[0019] The path geometry information of the target heat conduction channel and the corresponding heat flux density vector field data are integrated to generate a set of heat conduction path parameters.

[0020] As a preferred embodiment of the LED chip packaging optimization method based on thermal management described in this invention, the steps for obtaining the optimized heat flux density vector field through thermal field simulation are as follows:

[0021] Based on the set of heat conduction path parameters, within the heat dissipation structure, maximizing heat conduction performance is set as the optimization objective, and the total volume of the encapsulation material is set as the constraint condition to generate a topology optimization task environment;

[0022] Within the topology optimization task environment, the variable density method is used for iterative calculations to search for the optimal distribution of the encapsulation material within the heat dissipation structure and obtain the topology optimization configuration of the heat dissipation structure.

[0023] Based on the optimized topology of the heat dissipation structure, the heat dissipation structure in the 3D model of the LED chip package is remodeled to generate an updated 3D model of the LED chip package.

[0024] Thermal boundary condition parameters are applied to the updated 3D model of the LED chip package, and thermal field simulation is performed again to obtain the optimized node temperature dataset.

[0025] Spatial interpolation, differentiation, and mapping calculations based on Fourier's law are performed on the optimized node temperature dataset to generate an optimized heat flux density vector field.

[0026] As a preferred embodiment of the LED chip packaging optimization method based on thermal management described in this invention, the steps for calculating the heat flux density value and temperature gradient value are as follows:

[0027] The modulus of the optimized heat flux density vector field is calculated to obtain the heat flux density values ​​at all grid node positions within the package.

[0028] The optimized heat flux density vector field is traced back to the corresponding temperature field, and spatial differentiation and modulus calculation are performed to obtain the temperature gradient values ​​at all grid node positions within the package.

[0029] As a preferred embodiment of the LED chip packaging optimization method based on thermal management described in this invention, the steps for generating the functional partitioning scheme of the encapsulating adhesive are as follows:

[0030] Based on the performance requirements of the encapsulating adhesive material, zoning thresholds are set for heat flux density and temperature gradient values, and a set of thermal functional zoning rules is established.

[0031] Based on the thermal functional zoning rule set, the encapsulating adhesive area is identified and classified to generate the encapsulating adhesive functional zoning configuration;

[0032] From a predefined encapsulant material library, match the corresponding encapsulant material for each functional area in the encapsulant functional partition configuration to generate an encapsulant functional partition scheme.

[0033] As a preferred embodiment of the LED chip packaging optimization method based on thermal management described in this invention, the steps of applying the functional zoning scheme of the encapsulating adhesive to the updated three-dimensional model of the LED chip packaging, performing thermal-stress co-simulation to obtain the optimized three-dimensional model of the LED chip packaging, and extracting the LED chip packaging parameter set are as follows.

[0034] The encapsulation material parameters of different functional areas in the encapsulation functional zoning scheme are assigned to the corresponding encapsulation areas in the updated LED chip package 3D model to generate a fine LED package model.

[0035] After applying thermal boundary condition parameters to the fine model of LED packaging, thermal field simulation calculation is performed to obtain the thermal deformation field;

[0036] The thermal deformation field is applied as a load to the fine model of the LED package and structural mechanics analysis is performed to calculate the maximum internal stress value.

[0037] The maximum internal stress value is reliably determined by calling the preset allowable stress value of the packaging material, and the optimized three-dimensional model of the LED chip packaging is output.

[0038] Extract the thermal structure geometry, encapsulating adhesive material parameters, and thermal-stress co-simulation performance data from the optimized 3D model of the LED chip package to generate an LED chip package parameter set.

[0039] In a second aspect, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, wherein when the computer program is executed by the processor, it implements any step of the LED chip packaging optimization method based on thermal management as described in the first aspect of the present invention.

[0040] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements any step of the LED chip packaging optimization method based on thermal management as described in the first aspect of the present invention.

[0041] The beneficial effects of this invention are as follows: by performing topology optimization on the heat dissipation structure in the three-dimensional model of LED chip packaging according to the heat conduction path parameter set, the structural reconstruction of the heat dissipation channel is realized, making the material layout highly matched with the heat conduction requirements, improving heat dissipation efficiency and controlling material usage; by performing thermal functional zoning operation on the encapsulating adhesive based on the optimized heat flux density vector field, the zoning synergy of thermal conductivity and flexibility of the encapsulating adhesive is realized, improving heat dissipation performance and structural reliability. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Fig. 1 This is a flowchart of an LED chip packaging optimization method based on thermal management.

[0044] Fig. 2 A flowchart for generating a set of heat conduction path parameters.

[0045] Fig. 3 A flowchart for generating the optimized heat flux density vector field.

[0046] Fig. 4 A flowchart for generating a functional partitioning scheme for encapsulating adhesive. Detailed Implementation

[0047] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0048] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0049] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0050] Reference Figs. 1-4 This is one embodiment of the present invention, which provides an LED chip packaging optimization method based on thermal management, including the following steps:

[0051] S1. Collect and preprocess the thermal management parameter set of the LED chip package to construct a three-dimensional model of the LED chip package.

[0052] S1.1 The package thermal management parameter set of LED chips includes thermal boundary condition parameters, package structure geometric parameters, and material thermal property parameters.

[0053] It should be noted that the thermal boundary condition parameters are the core input conditions for driving the thermal simulation of LED packaging. The chip heating power parameter is calculated by measuring the chip's operating voltage and driving current using the photoelectric conversion efficiency formula. The ambient temperature parameter is obtained by direct measurement using a temperature sensor under operating conditions. The convective heat transfer coefficient is calculated based on the shape and orientation of the packaged device's outer surface, as well as the flow velocity and properties of the surrounding fluid. For forced convection, it is estimated using the power-law form of the Dittus-Belth formula based on the Reynolds number (Re) and Prandtl number (Pr). For natural convection, it is solved using the correlation between the Grashof number (Gr) and the Prandtl number (Pr). An exemplary value range is 5-25 W / (m³). 2 • K), determined based on the actual heat dissipation environment of the packaged device; Package structure geometric parameters refer to the data describing the precise physical dimensions of all components from the chip to the periphery of the LED package. These are obtained by measuring the packaged sample using precision measuring tools (such as optical microscopes and contour projectors), including the length, width, and thickness of the LED chip, the diameter and arc length of the gold wire, the thickness and area of ​​the encapsulant, the dimensions, thickness, and copper circuit routing of the substrate, and the outline dimensions of the packaged material; Material thermal property parameters refer to the material property data characterizing the rate of heat transfer and distribution within the package. These are obtained through direct testing of material samples, including the thermal conductivity of the chip semiconductor material, the thermal conductivity and thickness of the die bond material, the thermal conductivity, specific heat capacity, and density of the encapsulant, and the thermal conductivity and structural thickness of the substrate material.

[0054] S1.2 Preprocessing includes data cleaning, unit unification, standardization, data interpolation, and noise reduction.

[0055] It should be noted that data cleaning refers to identifying and removing erroneous and obviously abnormal data that deviates from physical reality from the LED chip packaging thermal management parameter set, thus eliminating gross errors; unit unification refers to converting data from different sources and with different units of measurement in the LED chip packaging thermal management parameter set to the International System of Units (SI) to ensure unit consistency; standardization refers to linearly scaling the values ​​of each parameter to [0,1] using the min-max normalization method for data with huge differences in dimensions and orders of magnitude in the LED chip packaging thermal management parameter set, thus eliminating the influence of dimensions; data interpolation refers to filling in the missing values ​​of the collected packaging thermal management parameter set using interpolation algorithms to ensure data integrity; and noise reduction refers to smoothing high-frequency signal data with random fluctuations (such as transient test data of chip junction temperature) obtained from experimental measurements in the LED chip packaging thermal management parameter set using digital filtering algorithms to suppress random interference.

[0056] S1.3 Map the geometric parameters of the package structure to geometric feature definition instructions, and perform three-dimensional geometric modeling through a parameterized driving method to form an LED package geometric skeleton model.

[0057] Furthermore, the geometric parameters of the packaging structure are analyzed and classified. The dimensions and positioning information of the components, including the chip, bonding wires, die bond layer, support structure, substrate, and encapsulant, are mapped one by one into precise instructions for creating corresponding geometric elements (such as cuboids, cylinders, spheres, stretched bodies, and bodies of revolution) in the 3D modeling environment, i.e., geometric feature definition instructions. Based on the geometric feature definition instructions, a parametric driving method is adopted to generate the 3D geometry of the chip, bonding wires, die bond layer, support structure, substrate, and encapsulant in sequence through feature modeling and Boolean operations. According to the physical assembly relationship, the 3D geometry of the chip, bonding wires, die bond layer, support structure, substrate, and encapsulant is spatially positioned and assembled to form an LED packaging geometric skeleton model.

[0058] S1.4 Assign the material thermal properties to the LED package geometric skeleton model and perform finite element mesh generation to generate the LED package mesh model.

[0059] Furthermore, the thermal conductivity, specific heat capacity, and density parameters of the chip, bonding wire, die bond layer, support structure, substrate, and encapsulant are extracted from the material thermal properties parameters, and then assigned to the corresponding geometric parts in the LED packaging geometric skeleton model. This ensures that each component of the LED packaging geometric skeleton model is given the correct material properties, thereby transforming the LED packaging geometric skeleton model into an LED packaging physical model with physical properties. Differentiated mesh control strategies are defined for different geometric parts in the LED packaging physical model: hexahedral dominant mesh types are selected for the chip geometry, support structure geometry, and substrate geometry to improve calculation accuracy, and encapsulant... For the geometry, a tetrahedral mesh type is selected to enhance adaptability. A neutral-axis-based swept mesh is specified for the bonding wire geometry. The global reference mesh size is set based on the expected heat flow path and geometric feature scale. Local mesh refinement strategies are applied in the chip junction region, die-attach interface, and solder joint connection area to reduce the mesh size. Based on the mesh control strategy, the LED packaging physical model is automatically discretized by a mesh generator. The continuous chip geometry, bonding wire geometry, die-attach geometry, bracket geometry, substrate geometry, and encapsulant geometry are discretized into a finite element set containing a large number of mesh nodes and elements, ultimately generating the LED packaging mesh model.

[0060] It should be noted that the local mesh refinement strategy is a fine discretization method in finite element analysis that uses smaller mesh sizes for key areas of the heat flow path within the 3D model of the LED package (such as the chip junction, die bond interface, and solder joint connection). The local mesh refinement strategy is based on the heat flow path analysis before thermal field simulation combined with the geometric feature scale of the package structure. After setting the global baseline mesh size, local refinement is automatically triggered in the key areas of the heat flow path based on the gradient criterion. The aim is to significantly improve the accuracy and reliability of the simulation results of the temperature field and thermal stress field in the key areas of the heat flow path at the cost of controllable increase in computing resources.

[0061] S1.5 Apply thermal boundary condition parameters to the corresponding surfaces of the LED package mesh model to generate a three-dimensional model of the LED chip package.

[0062] Furthermore, the chip heating power parameter in the thermal boundary condition parameters is used as a bulk heat source load and applied to all grid regions in the LED packaging mesh model corresponding to the active region of the chip. The ambient temperature parameter and the convective heat transfer coefficient are combined as convective heat transfer boundary conditions and applied to all outer surface grid regions in the LED packaging mesh model that are in contact with the external air. This generates a solvable 3D model of the LED chip packaging that defines complete material properties, geometric discretization, heat source and heat dissipation boundary conditions.

[0063] S2. Perform thermal field simulation on the 3D model of the LED chip package to obtain the temperature distribution, heat flow direction and thermal resistance path inside the package, and perform heat flow analysis on the thermal resistance path to determine the heat conduction channel and generate a set of heat conduction path parameters.

[0064] S2.1 Numerical solution of steady-state heat conduction equation for the three-dimensional model of LED chip packaging, obtain node temperature dataset, perform spatial interpolation and field reconstruction on the node temperature dataset, and output three-dimensional temperature field distribution.

[0065] Furthermore, the steady-state heat conduction partial differential equations contained in the 3D model of the LED chip package are processed using a discretization scheme based on the Galerkin weighted residual method, transforming the steady-state heat conduction partial differential equations into a system of linear algebraic equations concerning the temperature of the grid nodes. The system of linear algebraic equations is numerically solved using a conjugate gradient iterative algorithm combined with incomplete Choresky preconditions. Through multiple iterations until the residuals meet the preset convergence tolerance, the temperature values ​​of each grid node are obtained, forming a node temperature dataset. For the node temperature dataset, spatial interpolation calculations are performed using finite element shape functions to construct a continuous temperature field representation within each grid. By stitching and smoothing the temperature field representations within all grids, a 3D temperature field distribution covering the entire geometric part of the 3D model of the LED chip package is generated.

[0066] It should be noted that the incomplete Chollisky preconditioner is a numerical analysis method used to accelerate the iterative solution of large linear equation systems. The principle is to perform an incomplete triangular decomposition on the coefficient matrix of the linear algebraic equation system, retaining only the portion of the decomposed linear algebraic equation system corresponding to the non-zero elements of the original system. This generates an approximate but computationally efficient preprocessing matrix to improve the solution characteristics of the linear algebraic equation system. The convergence tolerance setting process is as follows: A baseline value is determined based on the physical characteristics of the temperature field. Using the LED junction temperature in the hundreds of degrees Celsius range as a reference, the initial tolerance is set at 1×10⁻⁶. 0 The tolerance is adjusted based on the discrete scale of the node temperatures, and tightened to 1×10 when the number of grid nodes exceeds one million. -2 The magnitude of the discrete error is matched with the magnitude of the truncation error. Finally, simulation is performed under typical conditions, and the maximum node temperature change is monitored. The residual norm corresponding to the maximum temperature change between consecutive iteration steps being less than 0.01℃ is the convergence tolerance. An exemplary value range is 1×10. -3 Up to 1×10 -5 .

[0067] S2.2 performs spatial differentiation on the three-dimensional temperature field distribution to obtain the temperature gradient field, and maps the temperature gradient field into a heat flux density vector field according to Fourier's law.

[0068] Furthermore, the first-order partial derivatives of the continuous three-dimensional temperature field are calculated in three orthogonal directions in space, and the components of the first-order partial derivatives in the three directions are combined into a vector to construct a temperature gradient field describing the magnitude and direction of the maximum rate of temperature change at any point in space. According to Fourier's law, the gradient vector of each calculation point in the temperature gradient field is multiplied by the thermal conductivity of the material at the corresponding spatial location in the thermal property parameters of the packaging material. Through vector operation, the temperature gradient field is converted into a heat flux density vector field characterizing the rate and direction of heat transfer.

[0069] S2.3 performs coupled analysis of the three-dimensional temperature field distribution and heat flux density vector field to identify the thermal resistance path with the largest temperature drop and the most concentrated heat flux.

[0070] Furthermore, the highest temperature point in the three-dimensional temperature field distribution is located as the starting point of the heat flow path, and the heat loss boundary in the heat flux density vector field is located as the ending point of the path. Starting from the starting point of the heat flow path, the path is traced point by point along the direction of the vector in the heat flux density vector field. The path extension direction is always consistent with the direction of the heat flux density vector of the traced grid node, forming a continuous heat flow transfer trajectory. On the heat flow transfer trajectory, the temperature value at the corresponding position in the three-dimensional temperature field distribution is extracted, the temperature difference between adjacent grid nodes on the heat flow transfer trajectory is calculated, and the magnitude of the heat flux density vector of each grid node is obtained by calculating the magnitude of the heat flux density vector component of each grid node in the heat flux density vector field. When a certain segment of the heat flow transfer trajectory shows the largest temperature difference per unit length and the heat flux density vector magnitude of all grid nodes is continuously higher than the preset magnitude threshold, the heat flow transfer trajectory is determined to be the thermal resistance path with the largest temperature drop and the most concentrated heat flow.

[0071] It should be noted that the amplitude threshold is calculated by taking 70% of the maximum amplitude of the heat flux density vector of all grid nodes in the heat flux density vector field as the initial threshold. Through sensitivity analysis, the influence of different values ​​on the stability of thermal resistance path identification is observed under typical working conditions. Finally, the value that can ensure path continuity and exclude local disturbances is selected as the amplitude threshold. The exemplary value range is 60%-80% of the maximum value. Values ​​above 80% will miss critical paths, while values ​​below 60% will cause the path to contain too many non-dominant heat flux regions.

[0072] S2.4 Calculate the total thermal resistance value of each thermal resistance path and select the thermal resistance path with a value less than the preset thermal resistance threshold as the target heat conduction channel.

[0073] Furthermore, the temperature values ​​at the starting and ending points of each thermal resistance path are extracted. The starting temperature is taken from the highest temperature in the three-dimensional temperature field distribution, and the ending temperature is taken from the temperature of the heat dissipation boundary at the end of the thermal resistance path. The temperature difference between the starting and ending points of the path is calculated, and the heat flux density vector field is calculated by surface integral at the vertical cross-section of the thermal resistance path to obtain the total heat flux through the thermal resistance path. Based on the ratio of the temperature difference to the total heat flux, the total thermal resistance value of each thermal resistance path is obtained. The total thermal resistance value is compared with a preset thermal resistance threshold, and thermal resistance paths with a total thermal resistance value less than the thermal resistance threshold are selected as target heat conduction channels.

[0074] The expression for calculating the total thermal resistance is:

[0075] ;

[0076] in, This represents the total thermal resistance of the thermal resistance path; Indicates the temperature at the starting point of the path; Indicates the temperature at the end of the path; Represents the heat flux density vector; This indicates the integration region, specifically the vertical cross-section selected along the thermal resistance path; It is an area infinitesimal vector; This represents the total heat flux calculated through the thermal resistance path;

[0077] It should be noted that the thermal resistance threshold setting process is as follows: The distribution range of the total thermal resistance value of all thermal resistance paths is statistically analyzed, and the median is taken as the initial reference. By analyzing the heat dissipation performance requirements, the thermal resistance threshold is set to be one standard deviation below the median to screen efficient paths. After multiple rounds of simulation verification, the thermal resistance threshold that can effectively screen the dominant thermal channels and avoid missing critical paths is selected as the final value. An exemplary value range is 1-5K / W. A value higher than 5K / W will result in too many screened paths including inefficient channels, while a value lower than 1K / W may miss important heat dissipation paths.

[0078] S2.5 integrates the path geometry information of the target heat conduction channel with the corresponding heat flux density vector field data to generate a heat conduction path parameter set.

[0079] Furthermore, the spatial coordinate sequence of the target heat conduction channel is extracted as path geometric information, and the corresponding heat flux density vector field data is extracted, including the direction and amplitude of the heat flux density vector at each grid point. At the same time, the sequence of encapsulated structural components passed through by the target heat conduction channel is recorded. The path geometric information and the heat flux density vector field data are correlated according to spatial coordinates to form a heat conduction path parameter set that includes spatial location, structural composition, heat flow direction and heat flux density.

[0080] S3. Based on the heat conduction path parameter set, perform topology optimization on the heat dissipation structure in the 3D model of the LED chip package, update the 3D model of the LED chip package, and obtain the optimized heat flux density vector field through thermal field simulation.

[0081] S3.1 Based on the set of heat conduction path parameters, within the heat dissipation structure, the optimization objective is set to maximize heat conduction performance, and the total volume of the encapsulation material is set as a constraint condition to generate a topology optimization task environment.

[0082] Furthermore, based on the heat conduction path parameter set, the continuous region with the highest heat flux density vector field amplitude in the heat dissipation structure is identified as the key conduction region. The weighted average of the heat flux density amplitude of the grid nodes within the key conduction region is set as the optimization objective, establishing a target function that maximizes the physical quantity. The upper limit of the total volume of the encapsulation material used in the heat dissipation structure is set as the constraint function. Based on the above, the parameters of the topology optimization algorithm are configured: the adjoint variable method is used to perform sensitivity analysis of the optimization variables to guide the optimization direction, and parameters are set based on a residual norm less than 10. -4 The iterative convergence criterion is used to control the computational accuracy. A solid isotropic material penalty model is selected, and the intermediate density is promoted to be distributed to the 0-1 polarity by setting the penalty factor to 3. After completing the configuration of the objective function, constraint function and algorithm parameters, the topology optimization task environment is generated.

[0083] The constitutive relation for the penalty model of solid isotropic materials is:

[0084] ;

[0085] in, The elastic modulus of the material after penalty; The elastic modulus of a solid material; Design variables for relative density; The penalty factor is set to 3.

[0086] It should be noted that the adjoint variable method introduces an "adjoint equation" corresponding to the original governing equation (such as the heat conduction equation) and solves the adjoint variables of the adjoint equation, thereby calculating the global sensitivity information of the objective function (such as heat dissipation performance) relative to all adjustable parameters (such as material distribution) at once. This reduces the computational complexity of gradient calculation from being proportional to the number of parameters to the constant level without sacrificing accuracy.

[0087] S3.2. Within the topology optimization task environment, the variable density method is used for iterative calculation to search for the optimal distribution of the encapsulation material within the heat dissipation structure and obtain the topology optimization configuration of the heat dissipation structure.

[0088] Furthermore, the relative density optimization variables of each grid point within the heat dissipation structure are initialized, and iterative calculations are performed using the variable density method. In each iteration, the sensitivity of the objective function to the relative density optimization variables is calculated using the adjoint variable method. The relative density optimization variables are updated using the optimization criterion method to achieve material redistribution. Simultaneously, the intermediate density values ​​are discretized to 0 or 1 using a solid isotropic material penalty model. The above iterative process is repeated, and the satisfaction of the constraint function is checked synchronously at each step until the change in the objective function is less than the preset convergence threshold and the volume constraint is met. The optimal distribution form of the encapsulation material characterized by 0-1 discrete density values ​​is obtained, which is the topology optimization configuration of the heat dissipation structure.

[0089] It should be noted that the convergence threshold setting process is as follows: based on the physical magnitude of the objective function (e.g., 10). 0 -10 2 To determine the baseline order of magnitude (W / m²), establish an initial threshold range, and observe different values ​​(e.g., 10) through convergence testing. -3 10 -4 10 -5 The relative fluctuation amplitude of the objective function and the stability relationship of the number of iterations were investigated. Finally, based on the test results, a value that simultaneously satisfies the requirements for computational accuracy and convergence efficiency was selected as the convergence threshold. An exemplary value range is 10. -3 -10 -5 higher than 10 -5 This can lead to insufficient optimization, resulting in a score below 10. -3 This will result in a waste of computing resources.

[0090] S3.3 Based on the topology optimization configuration of the heat dissipation structure, the heat dissipation structure in the 3D model of the LED chip package is remodeled to generate an updated 3D model of the LED chip package.

[0091] Furthermore, the spatial contour of the region with a density value of 1 in the topology optimization configuration of the heat dissipation structure is extracted to obtain the geometric boundary definition of the new heat dissipation structure. Based on the geometric boundary definition, a parameterized driving method is used to reconstruct and generate a new three-dimensional geometric model of the heat dissipation structure. The new three-dimensional geometric model of the heat dissipation structure is then reassembled and subjected to Boolean union operation with the chip geometry, bonding wire geometry, die bonding layer geometry, substrate geometry, and encapsulant geometry retained in the three-dimensional model of the LED chip package according to the original physical assembly relationship, to form an updated three-dimensional model of the LED chip package.

[0092] S3.4 Apply thermal boundary condition parameters to the updated 3D model of the LED chip package and perform thermal field simulation again to obtain the optimized node temperature dataset.

[0093] Furthermore, the chip heating power parameter in the thermal boundary condition parameters is applied as a volume heat source load to the mesh region corresponding to the chip geometry in the updated LED chip package 3D model. The ambient temperature parameter combined with the convective heat transfer coefficient is applied as a convective heat transfer boundary condition to the outer surface mesh region of the updated LED chip package 3D model. The steady-state heat conduction equation of the updated LED chip package 3D model with the thermal boundary condition parameters applied is solved by finite element numerical method. The partial differential equation is transformed into a system of linear algebraic equations by Galerkin weighted residual method, and the conjugate gradient method is used for iterative solution until the convergence tolerance is met. After the solution is completed, the temperature values ​​of all mesh nodes in the updated LED chip package 3D model are output to form the optimized node temperature dataset.

[0094] S3.5. Perform spatial interpolation, differentiation, and mapping calculation based on Fourier's law on the optimized node temperature dataset to generate the optimized heat flux density vector field.

[0095] Furthermore, spatial interpolation calculations are performed on the optimized node temperature dataset using finite element shape functions to reconstruct the continuously distributed optimized three-dimensional temperature field distribution. Spatial differentiation operations are then performed on the optimized three-dimensional temperature field distribution in three directions of the Cartesian coordinate system to obtain the optimized temperature gradient field. Based on Fourier's law, the gradient vector of each calculation point in the optimized temperature gradient field is multiplied by the thermal conductivity of the corresponding position in the thermal property parameters of the packaging material to complete the vector mapping operation and generate the optimized heat flux density vector field.

[0096] S4. Based on the optimized heat flux density vector field, calculate the heat flux density value and temperature gradient value, and perform thermal functional zoning operation on the encapsulating adhesive according to the heat flux density value and temperature gradient value to generate the encapsulating adhesive functional zoning scheme.

[0097] S4.1 Calculate the modulus of the optimized heat flux density vector field to obtain the heat flux density values ​​at all grid node positions within the package.

[0098] Furthermore, the heat flux density vectors at each grid node location are extracted from the optimized heat flux density vector field, and the magnitudes of the three directional components of the heat flux density vectors are calculated using the vector magnitude formula to obtain the heat flux density values ​​at all grid node locations within the package.

[0099] The expression for calculating the heat flux density is:

[0100] ;

[0101] in, This represents the modulus of the heat flux density vector at a specific grid node, i.e., the heat flux density value at the grid node location; , and These represent the components of the heat flux density vector at the grid node location in the three orthogonal directions of X, Y, and Z, respectively, in the Cartesian coordinate system;

[0102] S4.2. The optimized heat flux density vector field is traced back to the corresponding temperature field, and spatial differentiation and modulus calculation are performed to obtain the temperature gradient values ​​at all grid node positions within the package.

[0103] Furthermore, based on the one-to-one correspondence between the heat flux density vector field and the temperature field established through mesh node numbers during the finite element solution process, the optimized three-dimensional temperature field distribution, which was discretized by the same mesh and relied upon when generating the optimized heat flux density vector field, is directly accessed by accessing the optimized node temperature dataset. Spatial partial derivative operations are performed on the optimized three-dimensional temperature field distribution in the three directions of the Cartesian coordinate system to obtain the optimized temperature gradient field. The scalar magnitude value is calculated for the temperature gradient vector at each mesh node position in the optimized temperature gradient field using the vector magnitude formula to obtain the temperature gradient values ​​at all mesh node positions within the package.

[0104] S4.3. Based on the performance requirements of the encapsulating adhesive material, set zoning thresholds for heat flux density and temperature gradient values ​​respectively, and establish a set of thermal functional zoning rules.

[0105] Furthermore, to achieve high thermal conductivity of the encapsulating adhesive, a threshold value for heat flux density is set for partitioning the area. To achieve high flexibility of the encapsulating adhesive to buffer thermal stress, a threshold value for temperature gradient is set for partitioning the area. By statistically sorting the heat flux density values ​​of all grid nodes in the encapsulating adhesive area (from largest to smallest), a critical value that can cover the area with higher heat flux density (such as the lowest value of the first 15% of data points in the sorted sequence) is selected as the heat flux density threshold for the high thermal conductivity functional area. By statistically sorting the temperature gradient values ​​of all grid nodes in the encapsulating adhesive area (from largest to smallest), a critical value that can cover the area with higher temperature gradient (such as the lowest value of the first 25% of data points in the sorted sequence) is selected as the temperature gradient threshold for the high flexibility functional area. By combining the heat flux density threshold and the temperature gradient threshold, the discrimination conditions for high thermal conductivity area (heat flux density value higher than the heat flux density threshold), high flexibility area (temperature gradient value higher than the temperature gradient threshold), and normal area (both heat flux density value and temperature gradient value are lower than the corresponding threshold) are defined, forming a set of thermal functional partitioning rules.

[0106] S4.4. Based on the thermal functional zoning rule set, the encapsulation adhesive area is identified and classified to generate the encapsulation adhesive functional zoning configuration.

[0107] Furthermore, each grid node in the encapsulating adhesive region is traversed, and the corresponding heat flux density value and temperature gradient value are read. The heat flux density threshold and temperature gradient threshold set in the thermal functional zoning rule set are applied for judgment. If the heat flux density value is higher than the heat flux density threshold, it is marked as a high thermal conductivity zone. If the temperature gradient value is higher than the temperature gradient threshold, it is marked as a high flexibility zone. If both the heat flux density value and the temperature gradient value are lower than the corresponding threshold, it is marked as a normal zone. The zoning marking result of each grid node is recorded as a zoning attribute number (e.g., high thermal conductivity zone is numbered 1, high flexibility zone is numbered 2, and normal zone is numbered 3). The zoning attribute numbers of all grid nodes in the encapsulating adhesive region are combined with the corresponding spatial coordinates to generate a complete encapsulating adhesive functional zoning configuration that describes the spatial distribution of each zoning zone.

[0108] S4.5. From the predefined encapsulating adhesive material library, match the corresponding encapsulating adhesive material for each functional area in the encapsulating adhesive functional partition configuration to generate an encapsulating adhesive functional partition scheme.

[0109] Furthermore, the partition attribute number marked in the encapsulant functional partition configuration is read, and the encapsulant materials pre-selected for high thermal conductivity areas in the predefined encapsulant material library are matched to the grid areas of all high thermal conductivity areas in the encapsulant functional partition configuration. The encapsulant materials pre-selected for high flexibility areas are matched to the grid areas of high flexibility areas, and the encapsulant materials pre-selected for ordinary areas are matched to the grid areas of ordinary areas, thereby generating an encapsulant functional partition scheme that specifies the specific encapsulant material model used in each spatial area.

[0110] It should be noted that the encapsulating adhesive material library is established by collecting technical data sheets of various encapsulating adhesive materials available on the market, extracting performance parameters including thermal conductivity, elastic modulus, and coefficient of thermal expansion, and classifying the encapsulating adhesive materials according to thermal management functional requirements. Encapsulating adhesive materials with thermal conductivity higher than 2.0 W / (m·K) are classified as candidate materials in the high thermal conductivity zone, encapsulating adhesive materials with elastic modulus lower than 3.0 GPa are classified as candidate materials in the high flexibility zone, and the rest are classified as candidate materials in the ordinary zone. Finally, the thermomechanical properties of each encapsulating adhesive material under actual encapsulation conditions are verified through experiments, and a structured database containing material type, performance parameters, and applicable zone information is established.

[0111] S5. Apply the encapsulating adhesive functional zoning scheme to the updated LED chip packaging 3D model, perform thermal-stress co-simulation, obtain the optimized LED chip packaging 3D model, and extract the LED chip packaging parameter set.

[0112] S5.1 Assign the encapsulating adhesive material parameters of different functional areas in the encapsulating adhesive functional zoning scheme to the corresponding encapsulating adhesive areas in the updated LED chip packaging 3D model to generate a fine LED packaging model.

[0113] Furthermore, the encapsulant material parameters corresponding to the high thermal conductivity zone, high flexibility zone, and ordinary zone in the encapsulant functional zoning scheme are read, including thermal conductivity, elastic modulus, and coefficient of thermal expansion. In the updated LED chip packaging 3D model, based on the spatial location information recorded in the encapsulant functional zoning scheme, the encapsulant mesh area corresponding to the high thermal conductivity zone is located and its encapsulant material parameters are assigned. Similarly, the encapsulant mesh area corresponding to the high flexibility zone is located and its encapsulant material parameters are assigned. Finally, the encapsulant mesh area corresponding to the ordinary zone is located and its encapsulant material parameters are assigned. After assigning the encapsulant material parameters to all encapsulant mesh areas, a fine LED packaging model with non-uniform material properties is generated.

[0114] S5.2 After applying thermal boundary condition parameters to the fine model of LED packaging, perform thermal field simulation calculations to obtain the thermal deformation field.

[0115] Furthermore, the chip heating power parameter in the thermal boundary condition parameters is again applied as a volume heat source load to the mesh region corresponding to the chip area in the LED package fine model. The ambient temperature parameter combined with the convective heat transfer coefficient is applied as a convective heat transfer boundary condition to the outer surface mesh region of the LED package fine model. The steady-state heat conduction equation of the LED package fine model with the thermal boundary condition parameters applied is solved numerically using the finite element method. The partial differential equation is transformed into a system of linear algebraic equations using the Galerkin weighted residual method, and iteratively solved using the conjugate gradient method until the convergence tolerance is met. After the solution is completed, the LE is output. The temperature values ​​of all mesh nodes in the D-package fine model are calculated, and the temperature values ​​of all mesh nodes are interpolated using finite element shape functions to reconstruct a continuous temperature field distribution. Based on the temperature field distribution, the difference between the temperature value of each mesh node and the ambient temperature parameter is calculated, and multiplied with the linear expansion coefficient of the encapsulating adhesive material corresponding to the mesh node to obtain the thermal strain tensor of the mesh node. According to the generalized Hooke's law, the thermal strain tensor is substituted into the stress-strain constitutive relation to calculate the thermal expansion displacement vector generated by each mesh node under constraint conditions, and integrated to generate a thermal deformation field describing the thermal deformation state of the encapsulation structure.

[0116] The expression for calculating the thermal expansion displacement vector is:

[0117] ;

[0118] ;

[0119] in, These are components of the thermal strain tensor; It is the coefficient of thermal expansion of the encapsulating adhesive material; It's the temperature difference; Represents the Kronecker delta notation, when = The value is 1 if the condition is met, and 0 otherwise, ensuring that the thermal strain tensor is equal on its diagonal component. The off-diagonal component is zero, indicating that thermal strain in isotropic materials only produces normal strain (volume expansion) and not shear strain. and Represents spatial directions (e.g., x, y, z); It is the thermal expansion displacement vector, representing the displacement vector of each mesh node under constraints. The shear modulus, representing the encapsulating adhesive material, is one of the elastic parameters. The first Lamé constant, representing the encapsulating adhesive material, is one of the elastic parameters;

[0120] It should be noted that elastic parameters are a set of physical property parameters that describe the ability of a solid material to resist deformation during the elastic deformation stage (when it can return to its original shape after the external force is removed). These parameters include the elastic modulus (which describes the material's ability to resist normal strain), Poisson's ratio (which describes the contraction effect of a material in the perpendicular direction when it is stretched in one direction), the shear modulus (which describes the material's ability to resist shear strain), and the corresponding derived Lamé constant. The elastic modulus, Poisson's ratio, shear modulus, and the corresponding derived Lamé constant together constitute the stiffness tensor in the generalized Hooke's law, which is used to establish the linear constitutive relationship between stress and strain.

[0121] S5.3 Apply the thermal deformation field as a load to the fine model of the LED package and perform structural mechanics analysis to calculate the maximum internal stress value.

[0122] Furthermore, the thermal expansion displacement vector of each grid node in the thermal deformation field is used as a forced displacement boundary condition and applied to the corresponding grid nodes of the LED packaging fine model through grid node numbering. Fixed constraint boundary conditions are set on the bottom mounting surface of the LED packaging fine model substrate, and the translational and rotational degrees of freedom of all grid nodes are set to zero. The stress-strain constitutive relationship is established based on the generalized Hooke's law, and the stress tensor of all grid nodes is calculated by solving the linear elasticity equilibrium equation. The von Mises yield criterion is applied to the stress tensor of each grid node to calculate the von Mises equivalent stress, and the largest von Mises equivalent stress is selected as the maximum internal stress value.

[0123] The expression for calculating the von Mises equivalent stress is:

[0124] ;

[0125] in, It is the von Mises equivalent effect; , and These represent the three normal stress components in the stress tensor. Represents the normal stress in the x-direction. Represents the normal stress in the y-direction. The normal stress represents the stress in the z-direction; , and These represent the three shear stress components in the stress tensor. This represents the shear stress acting along the y-direction in a plane perpendicular to the x-axis. This represents the shear stress acting along the z-direction in a plane perpendicular to the y-axis. This represents the shear stress acting along the x-direction in a plane perpendicular to the z-axis.

[0126] S5.4. Call the preset allowable stress value of the packaging material to determine the reliability of the maximum internal stress value, and output the optimized three-dimensional model of the LED chip packaging.

[0127] Furthermore, the maximum internal stress value is compared with the preset allowable stress value of the encapsulation material. If the maximum internal stress value is less than or equal to the allowable stress value of the encapsulation material, the LED encapsulation fine model is determined to meet the reliability requirements, which is defined as the output of the optimized LED chip encapsulation three-dimensional model. If the maximum internal stress value is greater than the allowable stress value of the encapsulation material, the functional zoning scheme of the encapsulation adhesive is readjusted and the thermal-stress joint simulation verification is performed again until the judgment condition is met.

[0128] It should be noted that the allowable stress value setting process for the encapsulation material is as follows: The yield strength of the encapsulation material is determined by standard material mechanics tests, and the yield strength decay characteristics of the encapsulation material are evaluated by accelerated aging tests. A safety factor (e.g., 1.5) is introduced according to the reliability requirements of the encapsulation structure. The allowable stress value of the encapsulation material is obtained by calculating the ratio between the yield strength of the encapsulation material and the safety factor. An exemplary range of 20-40 MPa is obtained. A value higher than 40 MPa may cause the material to yield and fail during long-term operation, while a value lower than 20 MPa will result in a waste of material strength and an increased burden on the heat dissipation structure.

[0129] S5.5 Extract the heat dissipation structure geometry, encapsulation adhesive material parameters, and thermal-stress co-simulation performance data from the optimized LED chip package 3D model to generate an LED chip package parameter set.

[0130] Furthermore, the geometric dimensions of the heat dissipation structure in the optimized 3D model of the LED chip package are extracted, including the outline dimensions and thickness distribution of the heat dissipation structure; the encapsulation material parameters of each functional area determined in the encapsulation functional zoning scheme are extracted, including the thermal conductivity of the encapsulation material in the high thermal conductivity area, the elastic modulus of the encapsulation material in the high flexibility area, and the density of the encapsulation material in each area; the performance data in the thermal-stress co-simulation results are extracted, including the total thermal resistance and the maximum internal stress; the geometric dimensions of the heat dissipation structure, the encapsulation material parameters, and the thermal-stress co-simulation performance data are integrated by category to form an LED chip package parameter set containing complete geometric parameters, material parameters, and performance verification data.

[0131] This embodiment also provides a computer device applicable to the LED chip packaging optimization method based on thermal management, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the LED chip packaging optimization method based on thermal management as proposed in the above embodiment.

[0132] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0133] This embodiment also provides a storage medium storing a computer program, which, when executed by a processor, implements the LED chip packaging optimization method based on thermal management as proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0134] In summary, this invention achieves structural reconstruction of the heat dissipation channel by optimizing the heat dissipation structure in the 3D model of LED chip packaging based on the heat conduction path parameter set, thereby highly matching the material layout with the heat conduction requirements, improving heat dissipation efficiency and controlling material usage; and by performing thermal functional zoning operations on the encapsulating adhesive based on the optimized heat flux density vector field, it achieves zoning synergy between the thermal conductivity and flexibility of the encapsulating adhesive, thereby improving heat dissipation performance and structural reliability.

[0135] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for optimizing LED chip packaging based on thermal management, characterized in that: include, Collect and preprocess the thermal management parameter set of LED chip packaging to construct a three-dimensional model of LED chip packaging; Perform thermal field simulation on the 3D model of LED chip packaging to obtain the temperature distribution, heat flow direction and thermal resistance path inside the package, and perform heat flow analysis on the thermal resistance path to determine the heat conduction channel and generate a set of heat conduction path parameters. Based on the heat conduction path parameter set, the heat dissipation structure in the 3D model of LED chip packaging is topologically optimized, the 3D model of LED chip packaging is updated, and the optimized heat flux density vector field is obtained through thermal field simulation. Based on the optimized heat flux density vector field, the heat flux density value and temperature gradient value are calculated, and the thermal functional zoning operation of the encapsulant is performed according to the heat flux density value and temperature gradient value to generate the encapsulant functional zoning scheme. The encapsulating adhesive functional zoning scheme was applied to the updated LED chip package 3D model, and thermal-stress co-simulation was performed to obtain the optimized LED chip package 3D model and extract the LED chip package parameter set.

2. The LED chip packaging optimization method based on thermal management as described in claim 1, characterized in that: The package thermal management parameter set of the LED chip includes thermal boundary condition parameters, package structure geometric parameters, and material thermal property parameters; The preprocessing includes data cleaning, unit unification, standardization, data interpolation, and noise reduction.

3. The LED chip packaging optimization method based on thermal management as described in claim 2, characterized in that: The steps for constructing a 3D model of an LED chip package are as follows. The geometric parameters of the packaging structure are mapped to geometric feature definition instructions, and three-dimensional geometric modeling is performed through a parameter-driven method to form an LED packaging geometric skeleton model. The thermal properties of the material are assigned to the geometric skeleton model of the LED package, and finite element mesh generation is performed to generate the LED package mesh model. Thermal boundary condition parameters are applied to the corresponding surfaces of the LED package mesh model to generate a three-dimensional model of the LED chip package.

4. The LED chip packaging optimization method based on thermal management as described in claim 1, characterized in that: The steps for generating the heat conduction path parameter set are as follows: Numerical solution of steady-state heat conduction equation is performed on the 3D model of LED chip packaging to obtain node temperature dataset. Spatial interpolation and field reconstruction are then performed on the node temperature dataset to output the 3D temperature field distribution. Perform spatial differentiation on the three-dimensional temperature field distribution to obtain the temperature gradient field, and map the temperature gradient field into a heat flux density vector field according to Fourier's law; By performing coupled analysis of the three-dimensional temperature field distribution and the heat flux density vector field, the thermal resistance path with the largest temperature drop and the most concentrated heat flux is identified. Calculate the total thermal resistance value of each thermal resistance path, and select the thermal resistance path with a thermal resistance value less than the preset thermal resistance threshold as the target heat conduction channel. The path geometry information of the target heat conduction channel and the corresponding heat flux density vector field data are integrated to generate a set of heat conduction path parameters.

5. The LED chip packaging optimization method based on thermal management as described in claim 1, characterized in that: The steps for obtaining the optimized heat flux density vector field through thermal field simulation are as follows: Based on the set of heat conduction path parameters, within the heat dissipation structure, maximizing heat conduction performance is set as the optimization objective, and the total volume of the encapsulation material is set as the constraint condition to generate a topology optimization task environment; Within the topology optimization task environment, the variable density method is used for iterative calculations to search for the optimal distribution of the encapsulation material within the heat dissipation structure and obtain the topology optimization configuration of the heat dissipation structure. Based on the optimized topology of the heat dissipation structure, the heat dissipation structure in the 3D model of the LED chip package is remodeled to generate an updated 3D model of the LED chip package. Thermal boundary condition parameters are applied to the updated 3D model of the LED chip package, and thermal field simulation is performed again to obtain the optimized node temperature dataset. Spatial interpolation, differentiation, and mapping calculations based on Fourier's law are performed on the optimized node temperature dataset to generate an optimized heat flux density vector field.

6. The LED chip packaging optimization method based on thermal management as described in claim 1, characterized in that: The steps for calculating the heat flux density and temperature gradient are as follows: The modulus of the optimized heat flux density vector field is calculated to obtain the heat flux density values ​​at all grid node positions within the package. The optimized heat flux density vector field is traced back to the corresponding temperature field, and spatial differentiation and modulus calculation are performed to obtain the temperature gradient values ​​at all grid node positions within the package.

7. The LED chip packaging optimization method based on thermal management as described in claim 1, characterized in that: The steps for generating the encapsulating adhesive functional partition scheme are as follows: Based on the performance requirements of the encapsulating adhesive material, zoning thresholds are set for heat flux density and temperature gradient values, and a set of thermal functional zoning rules is established. Based on the thermal functional zoning rule set, the encapsulating adhesive area is identified and classified to generate the encapsulating adhesive functional zoning configuration; From a predefined encapsulant material library, match the corresponding encapsulant material for each functional area in the encapsulant functional partition configuration to generate an encapsulant functional partition scheme.

8. The LED chip packaging optimization method based on thermal management as described in claim 1, characterized in that: The steps are as follows: applying the encapsulating adhesive functional zoning scheme to the updated LED chip package 3D model, performing thermal-stress co-simulation to obtain the optimized LED chip package 3D model, and extracting the LED chip package parameter set. The encapsulation material parameters of different functional areas in the encapsulation functional zoning scheme are assigned to the corresponding encapsulation areas in the updated LED chip package 3D model to generate a fine LED package model. After applying thermal boundary condition parameters to the fine model of LED packaging, thermal field simulation calculation is performed to obtain the thermal deformation field; The thermal deformation field is applied as a load to the fine model of the LED package and structural mechanics analysis is performed to calculate the maximum internal stress value. The maximum internal stress value is reliably determined by calling the preset allowable stress value of the packaging material, and the optimized three-dimensional model of the LED chip packaging is output. Extract the thermal structure geometry, encapsulating adhesive material parameters, and thermal-stress co-simulation performance data from the optimized 3D model of the LED chip package to generate an LED chip package parameter set.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the LED chip packaging optimization method based on thermal management as described in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the LED chip packaging optimization method based on thermal management as described in any one of claims 1 to 8.

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