Pixel circuit and display panel

Abstract

The invention relates to a pixel circuit and a display panel. The pixel circuit comprises a switch transistor, a driving transistor, a compensation transistor and a calibration module which are connected, the potential of a second node is calibrated through the calibration module in the compensation stage of the pixel circuit, and the potential of a third node is compensated through the compensation transistor; according to the pixel circuit, the compensation transistor and the calibration module are arranged in the pixel circuit, so that the compensation transistor compensates the potential of the third node in the compensation stage, the calibration module compensates the potential of the second node in the compensation stage, and compensation of the potential of the gate end and the source end of the driving transistor is achieved at the same time; the problem that the potential difference between the gate end and the source end of the driving transistor deviates is solved, the accuracy of the working current flowing into the light-emitting device is improved, and the display effect of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel circuit and a display panel. BACKGROUND

[0002] With the development of display technology, users have higher and higher requirements for display quality, and micro light emitting diode display application technology has also entered a rapid development stage, such as MiniLED and MicroLED, which can be collectively referred to as MLED; the driving technology of MLED is divided into PM (Passive Matrix, passive matrix) driving and AM (Active Matrix, active matrix) driving; AM driving MLED has better cost advantage than PM driving MLED technology.

[0003] In the current MLED display panel, due to the threshold voltage drift of the thin film transistor and the difference in the K value of different thin film transistors, the potential difference between the gate terminal and the source terminal of the driving transistor deviates, that is, the working current flowing into the light emitting device deviates, which causes the display of the display panel to be abnormal. SUMMARY

[0004] The present application provides a pixel circuit and a display panel to solve the technical problem of the working current deviation of the light emitting device in the existing display panel.

[0005] To solve the above problems, the technical scheme provided by the present application is as follows:

[0006] The present application provides a pixel circuit for connecting with a light emitting device, wherein the pixel circuit comprises:

[0007] a switch transistor, a first electrode of the switch transistor being connected to a data input terminal;

[0008] a driving transistor, a first electrode of the driving transistor being connected to a second electrode of the switch transistor at a first node;

[0009] a compensation transistor, a first electrode of the compensation transistor being connected to a second electrode of the driving transistor at a second node, a second electrode of the compensation transistor being connected to a gate of the driving transistor at a third node; and

[0010] a calibration module, connected to the compensation transistor and the driving transistor at the second node;

[0011] The pixel circuit comprises a continuous compensation phase and a display phase, in the compensation phase, the calibration module is used for calibrating the potential of the second node, and the compensation transistor is used for compensating the potential of the third node.

[0012] The application further provides a display panel comprising the pixel circuit. BRIEF DESCRIPTION OF DRAWINGS

[0013] The technical scheme and other beneficial effects of the application will be apparent from the following detailed description of the specific embodiments of the application in conjunction with the accompanying drawings.

[0014] Figure 1 A first circuit diagram in some embodiments of the application;

[0015] Figure 2 A second circuit diagram in some embodiments of the application;

[0016] Figure 3 A timing diagram before compensation for the circuit diagram in Figure 2

[0017] Figure 4 A timing diagram after compensation for the circuit diagram in Figure 2

[0018] Figure 5 A structural diagram of a display device provided by the application;

[0019] Figure 6 A structural diagram of a pixel circuit of a display device provided by the application;

[0020] Figure 7 A timing diagram of the pixel circuit in Figure 6

[0021] Figures 8A to 8F Working process diagrams of the pixel circuit in Figure 6

[0022] Figure 9 Partial timing diagrams of each transmission line of the pixel circuit in Figure 7

[0023] Figures 10A to 10C Working process diagrams of the pixel circuit in Figure 6

[0024] Figure 11 Partial timing diagrams of each transmission line of the pixel circuit in Figure 7 DETAILED DESCRIPTION

[0025] ​​​​​​​With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0026] Please refer to Figure 1 , Figure 1 for the first circuit diagram in some embodiments of the present application.

[0027] Figure 1 The circuit diagram in the above embodiment includes a driving transistor T2, a switch transistor T5, a compensation transistor T4, a first reset transistor T6, a second reset transistor T7, a first light-emitting transistor T1 and a second light-emitting transistor T3. In the data writing stage, the driving transistor T2, the switch transistor T5 and the compensation transistor T4 are turned on. The driving transistor T2 forms a diode. The data signal input by the data signal terminal Data is coupled to the Q point. The voltage at the Q point is changed to the sum of Vdata and Vth. The voltage at the gate terminal of the driving transistor T2 is compensated, and the internal compensation of the circuit structure is completed.

[0028] Please refer to Figure 2 , Figure 3 and Figure 4 , Figure 2 for the second circuit diagram in some embodiments of the present application. Figure 3 is Figure 2 the timing diagram before compensation of the circuit diagram in the above embodiment. Figure 4 is Figure 2 the timing diagram after compensation of the circuit diagram in the above embodiment.

[0029] Figure 2 The circuit diagram in the above embodiment includes a first transistor T11, a second transistor T12 and a third transistor T13. The first transistor T11 and the second transistor T12 are connected to the gate node G11. The second transistor T12 and the third transistor T13 are connected to the source node S11. The end of the third transistor T13 away from the source node S11 is connected to an analog-to-digital converter and a reference potential.

[0030] In the above embodiment Figure 2In the structure, during the threshold voltage detection of the second transistor T12, the first transistor T11 and the third transistor T13 are first turned on, and the data voltage output from the data signal terminal is stored in the gate node G11. The second switch is turned on, and the reference potential resets the potential of the source node S11. After the second switch is closed, the constant voltage high-level source VDD continuously charges the source node S11. At the same time, during the pull-up process of the source node S11, the first switch is turned on and the potential of Vs is detected. When the current flowing into the light-emitting device is 0, the difference between the potential of the source node S11 and the potential of the gate node G11 is the threshold voltage of the second transistor T12. At this time, the threshold voltage of the second transistor T12 can be obtained based on the difference between the potential of the source node S11 and the potential of the gate node G11.

[0031] exist Figure 2 In this structure, when performing threshold voltage compensation, the K value can be compensated simultaneously. The operating current before threshold voltage compensation is Ids = K(Vgs - Vth). 2 The operating current after threshold voltage compensation is Ids = K(Vgs). 2 Therefore, the difference in operating current is proportional to K, but the value of K is different for different transistors, depending on the specific components involved. Figure 3 The slopes of the two different transistors in the diagram will differ depending on the K value during the continuous charging and pull-up of the source node S11 by the constant high-level source VDD. Therefore, different K values ​​need to be applied for different transistors. Please refer to [link to relevant documentation] for details. Figure 4 .

[0032] at the same time, Figure 2 In the circuit structure, when compensating for the threshold voltage of the second transistor T12, threshold voltage compensation can only be performed in the initial stage. As the display screen is displayed, the electrical properties of the thin-film transistor will drift, which will also cause abnormal display of the display panel.

[0033] therefore, Figure 1 The circuit structure can only perform internal compensation of the threshold voltage. Figure 2 The circuit structure can only perform threshold voltage compensation and K value compensation in the initial stage. K value compensation requires first obtaining the threshold voltage and then synchronously calculating K based on the potential of the revised gate node G11. This compensation method is relatively complex and requires more algorithm resources and compensation time.

[0034] Please see Figure 5The application provides a display device 100, which comprises a display panel 200 and a driving module 300. The display panel 200 comprises a plurality of data lines and a plurality of scan lines. One data line is connected with a plurality of data signal ends Data, one scan line is connected with a plurality of scan signal ends Scan, the plurality of data lines and the plurality of scan lines enclose a plurality of sub-pixels 210, one pixel circuit 211 and a light emitting device 212 connected with the pixel circuit 211 are arranged in each sub-pixel 210.

[0035] In Figure 5 In the structure, the driving module 300 can comprise a timing controller 310, a data processor 320, a row scan circuit 330 and a column scan circuit 340. The timing controller 310 controls the row scan circuit 330 to output a scan signal to the display panel 200, the timing controller 310 outputs an image data signal to the data processor 320, and the data processor 320 transmits a data voltage signal to the column scan circuit 340 according to the image data signal.

[0036] It should be noted that the row scan circuit 330 or / and the column scan circuit 340 can also be directly integrated in the display panel 200.

[0037] Please refer to Figure 6 The pixel circuit 211 comprises a switching transistor T5, a driving transistor T2, a compensation transistor T4 and a calibration module 220 which are connected.

[0038] In the embodiment, the first electrode of the switching transistor T5 is connected with the data input end Data, the first electrode of the driving transistor T2 and the second electrode of the switching transistor T5 are connected with a first node A, the first electrode of the compensation transistor T4 and the second electrode of the driving transistor T2 are connected with a second node S, the second electrode of the compensation transistor T4 and the gate of the driving transistor T2 are connected with a third node G, and the calibration module 220 is connected with the second node S, the compensation transistor T4 and the driving transistor T2.

[0039] In the embodiment, the pixel circuit 211 comprises a compensation stage Ta and a display stage Tb which are continuous. In the compensation stage Ta, the calibration module 220 is used for calibrating the potential of the second node S, and the compensation transistor T4 is used for compensating the potential of the third node G.

[0040] The compensation transistor T4 and the calibration module 220 are arranged in the pixel circuit 211, so that the compensation transistor T4 compensates the potential of the third node G in the compensation stage Ta, and the calibration module 220 compensates the potential of the second node S in the compensation stage Ta, while the potentials of the gate terminal and the source terminal of the driving transistor T2 are compensated, the problem of deviation of the potential difference between the gate terminal and the source terminal of the driving transistor T2 is solved, the accuracy of the working current flowing into the light emitting device 212 is improved, and the display effect of the display panel is improved.

[0041] The technical solutions of the present application will be described below according to specific embodiments.

[0042] Please refer to Figure 6 The pixel circuit 211 can include a first reset transistor T6, a first electrode of the first reset transistor T6 is connected to a first reset line Vi1, a second electrode of the first reset transistor T6 is connected to the third node G, and a gate of the first reset transistor T6 is connected to a first control signal line Scan1, and the first reset transistor T6 is used to reset the potential of the third node G.

[0043] Please refer to Figure 6 The pixel circuit 211 further includes a second reset transistor T7, a first electrode of the second reset transistor T7 is connected to a second reset line Vi2, a second electrode of the second reset transistor T7 is connected to an anode of the light emitting device 212, and a gate of the second reset transistor T7 is connected to a second control signal line RD1, and the second reset transistor T7 is used to reset the potential of the anode of the light emitting device 212.

[0044] Please refer to Figure 6 The pixel circuit 211 further includes a first light emitting transistor T1 and a second light emitting transistor T3, a first electrode of the first light emitting transistor T1 is connected to a first potential line VDD, a second electrode of the first light emitting transistor T1 is connected to the first node A, and a gate of the first light emitting transistor T1 is connected to a first light emitting control line EM1; at the same time, a first electrode of the second light emitting transistor T3 is connected to the second node S, a second electrode of the second light emitting transistor T3 is connected to the anode of the light emitting device 212, and a gate of the second light emitting transistor T3 is connected to a second light emitting control line EM2.

[0045] It should be noted that in the compensation stage Ta, the first light-emitting control line EM1 controls the first light-emitting transistor T1 to be turned on, and the second light-emitting control line EM2 controls the second light-emitting transistor T3 to be turned off; in the light-emitting period of the display stage Tb, the first light-emitting control line EM1 controls the first light-emitting transistor T1 to be turned on, and the second light-emitting control line EM2 controls the second light-emitting transistor T3 to be turned on; that is, the first light-emitting transistor T1 is turned on, and the compensation transistor T4 compensates the potential of the gate terminal of the driving transistor T2 in this stage, and the second light-emitting transistor T3 is turned on, so that the working current flows into the light-emitting device 212 through the second light-emitting transistor T3 to drive the light-emitting device 212 to emit light.

[0046] In the embodiment, the gate of the switch transistor T5 and the gate of the compensation transistor T4 are connected to the third control signal line Scan2, and the first control signal line Scan1 and the third control signal line Scan2 transmit different levels of the same control signal; for example, the first control signal line Scan1 transmits the (n-1)th level of the Scan signal, and the third control signal line Scan2 transmits the nth level of the Scan signal.

[0047] Please refer to Figure 5 The calibration module 220 includes a calibration transistor T8, a measuring device 221, and a calibration device 222, the first electrode of the calibration device 222 is connected to the second node S, the first switch S1 is arranged between the measuring device 221 and the second electrode of the calibration transistor T8, the second switch S2 is arranged between the calibration device 222 and the second electrode of the calibration transistor T8, and the gate of the calibration transistor T8 is connected to the fourth control signal line RD2.

[0048] In the embodiment, the calibration device 222 is used to calibrate the potential of the second node S to the reference potential Vref, and the measuring device 221 is used to obtain the potential of the second node S.

[0049] It should be noted that since there is a certain error in the detection of the node potential, in order to ensure the accuracy of the detection of the node potential, the working time length of the first switch S1 is greater than that of the second switch S2 in the compensation stage Ta, which is equivalent to increasing the time length of the detection of the potential of the second node S and improving the accuracy of the detection of the potential of the second node S.

[0050] It should be noted that since the compensation stage Ta needs to complete the compensation of the gate terminal potential and the calibration of the source terminal potential of the driving transistor T2 at the same time, the pulse width of the compensation stage Ta of the present application needs to be greater than that of the display stage Tb.

[0051] It should be noted that the calibration device 222 can be a constant voltage source outputting a reference potential Vref, and mainly used for resetting the potential of the second node S to the reference potential Vref, and the measuring device 221 can be an analog-to-digital converter (ADC), which can directly obtain the potential of the second node S.

[0052] Referring to Figure 6 The pixel circuit 211 further includes a second potential line VSS, which is electrically connected with the cathode of the light emitting device 212.

[0053] Referring to Figure 6 The pixel circuit 211 further includes a bootstrap capacitor Cst, one end of which is connected with the first potential line VDD, and the other end of which is connected with the third node G.

[0054] It should be noted that the first potential line VDD in the present application can be a high potential line, and the second potential line VSS can be a low potential line.

[0055] It should be noted that the first electrode in the present application is one of a source electrode and a drain electrode, and the second electrode is the other one of the source electrode and the drain electrode.

[0056] It should be noted that the first reset line Vi1 and the second reset line Vi2 in the present application are used for outputting a reset signal, which is a constant voltage.

[0057] It should be noted that the switch transistor T5, the drive transistor T2, the compensation transistor T4, the first reset transistor T6, the second reset transistor T7, the first light emitting transistor T1, the second light emitting transistor T3 and the calibration transistor T8 in the present application can be one of an N-type transistor and a P-type transistor, and the above transistors are taken as N-type transistors for illustration.

[0058] Referring to Figure 7 One display frame of the pixel circuit 211 can include a compensation stage Ta and a display stage Tb, the compensation stage Ta is mainly used for correcting the potentials of the source end and the gate end of the drive transistor T2, and the display stage Tb is mainly used for light emitting of the light emitting device 212.

[0059] Referring to Figure 8A and Figure 9In the first sub-stage t1 of the compensation stage Ta, the first control signal line Scan1, the first light emitting control line EM1, the second light emitting control line EM2 and the third control signal line Scan2 output low level, that is, the first reset transistor T6, the first light emitting transistor T1, the second light emitting transistor T3, the compensation transistor T4 and the switch transistor T5 are all cut off; at the same time, the second control signal line RD1 outputs high level, the second reset transistor T7 is turned on, the potential of the anode point of the light emitting device 212 is reset to the first potential V1, the fourth control signal line RD2 outputs high level, the calibration transistor T8 is turned on, and the second switch S2 is closed, the potential of the second node S is reset to the reference potential Vref.

[0060] Please refer to Figure 8B and Figure 9 In the second sub-stage t2 of the compensation stage Ta, the first light emitting control line EM1, the second light emitting control line EM2, the third control signal line Scan2 and the fourth control signal line RD2 output low level, the first light emitting transistor T1, the second light emitting transistor T3, the compensation transistor T4, the switch transistor T5 and the calibration transistor T8 are all cut off; at the same time, the second control signal line RD1 outputs high level, the second reset transistor T7 is turned on, the potential of the anode point of the light emitting device 212 is maintained at the first potential V1, the first control signal line Scan1 outputs high level, the first reset transistor T6 is turned on, the potential of the third node G is reset to the second potential V2, and the potential of the second node S is maintained at the reference potential Vref.

[0061] Please refer to Figure 8C and Figure 9 In the third sub-stage t3 of the compensation stage Ta, the first control signal line Scan1, the first light emitting control line EM1, the second light emitting control line EM2 and the fourth control signal line RD2 output low level, the first reset transistor T6, the first light emitting transistor T1, the second light emitting transistor T3 and the calibration transistor T8 are all cut off; at the same time, the second control signal line RD1 outputs high level, the second reset transistor T7 is turned on, the potential of the anode point of the light emitting device 212 is maintained at the first potential V1, the third control signal line Scan2 outputs high level, the driving transistor T2, the switch transistor T5 and the compensation transistor T4 are turned on, the data voltage Vdata output by the data signal line enters the second node S through the driving transistor T2 and the switch transistor T5, so that the potential of the second node S increases from the reference potential Vref to Vdata, and the potential of the gate terminal of the driving transistor T2 is compensated, so that the potential of the third node G increases from the second potential V2 to the sum of Vdata and Vth.

[0062] Please refer to Figure 8D and Figure 9In the fourth sub-stage t4 of the compensation stage Ta, the first control signal line Scan1, the first light emitting control line EM1, the second light emitting control line EM2 and the third control signal line Scan2 all output low level, i.e. the first reset transistor T6, the first light emitting transistor T1, the second light emitting transistor T3, the compensation transistor T4 and the switch transistor T5 are all cut off; at the same time, the second control signal line RD1 outputs high level, the second reset transistor T7 is turned on, the potential of the anode point of the light emitting device 212 is maintained at the first potential V1, the fourth control signal line RD2 outputs high level, the calibration transistor T8 is turned on, and the second switch S2 is closed, the potential of the second node S is reset to the reference potential Vref, and the potential of the third node G is maintained at the sum of Vdata and Vth.

[0063] Please refer to Figure 8E and Figure 9 In the fifth sub-stage t5 of the compensation stage Ta, the first control signal line Scan1, the second light emitting control line EM2 and the third control signal line Scan2 all output low level, i.e. the first reset transistor T6, the second light emitting transistor T3, the compensation transistor T4 and the switch transistor T5 are all cut off; at the same time, the second control signal line RD1 outputs high level, the second reset transistor T7 is turned on, and the potential of the anode point of the light emitting device 212 is maintained at the first potential V1; the fourth control signal line RD2 outputs high level, the calibration transistor T8 is turned on, but since the first switch S1 and the second switch S2 are both in non-working state, the calibration device 222 cannot maintain the potential of the second node S at the reference potential Vref; secondly, the first light emitting control line EM1 outputs high level, the first light emitting transistor T1 is turned on, and the high level of the first potential line VDD is transmitted to the first node A, at this time, the gate of the driving transistor T2 is in a suspended state, so the driving transistor T2 is turned on, and at the same time, due to the bootstrap effect of the bootstrap capacitor Cst, the potentials of the second node S and the third node G will increase with time.

[0064] Please refer to Figure 8F and Figure 9In the sixth sub-stage t6 of the compensation stage Ta, the first control signal line Scan1, the second light-emitting control line EM2 and the third control signal line Scan2 all output low levels, that is, the first reset transistor T6, the second light-emitting transistor T3, the compensation transistor T4 and the switch transistor T5 are all cut off; at the same time, the second control signal line RD1 outputs a high level, the second reset transistor T7 is turned on, and the potential at the anode point of the light-emitting device 212 is maintained at the first potential V1; secondly, the first light-emitting control line EM1 outputs a high level, the first light-emitting transistor T1 is turned on, and the high level of the first potential line VDD is transmitted to the first node A; at this time, the gate of the driving transistor T2 is in a floating state, so the driving transistor T2 is turned on, and at the same time, due to the bootstrap effect of the bootstrap capacitor Cst, the potentials of the second node S and the third node G will increase with time; thirdly, the fourth control signal line RD2 outputs a high level, the calibration transistor T8 is turned on, but since the first switch S1 is in a working state, the measuring device 221 will detect the potential of the second node S in real time, and the Vdata signal output through the potential data signal input end of the second node S is changed to Vdata*, so as to realize compensation of the source end potential of the driving transistor T2 in the pixel circuit 211.

[0065] It should be noted that due to the effects of resistance and capacitance and leakage current, even if the source end potential of the driving transistor T2 is reset to the reference potential Vref, there is still a certain deviation, so the application updates the data voltage input by the data input end Data to compensate for the difference in the source end potential of the driving transistor T2.

[0066] The compensation principle of the application in the compensation stage is described below according to the related formulae as follows:

[0067] The working current before the compensation stage is formula (1): Ids=K*(Vdata-Vs) 2 ;

[0068] The detection capacitor charging is formula (2): Ids*dt=Csen*dVs

[0069] Substitute formula (1) into formula (2) to obtain formula (3): K / Csen*dt=dVs / (Vdata-Vs) 2 ;

[0070] Since the voltage difference between the third node G and the second node S is a constant value, that is, the difference between the data voltage Vdata and the reference voltage Vref is a constant value, that is, formula (3) can be changed to formula (4):

[0071] K*t / Csen=(Vs-Vref) / (Vdata-Vref) 2 ;

[0072] Assuming the compensated K value is changed to Ktrg, the voltage of the second node S will be lifted from the original Vs to the preset voltage Vtrg in the detection phase. For a driving transistor DTn in a certain sub-pixel, the voltage of the second node S obtained by detection is Vsn, and the voltages Vtrg and Vsn are brought into equation (4) to obtain equation (5):

[0073]

[0074] and equation (6) is obtained:

[0075]

[0076] According to equation (5) and equation (6), equation (7) is obtained:

[0077]

[0078] Therefore, the updated data voltage is:

[0079] At the same time, Vdata" is updated to the data input end by algorithm to realize compensation of the K value.

[0080] It should be noted that, in the structure of Figure 7 , G1 and S1 are the voltages of the gate end and the source end of the driving transistor T2 in one pixel circuit 211 in the display panel, and G2 and S2 are the voltages of the gate end and the source end of the driving transistor T2 in another pixel circuit 211 in the display panel; similarly, in the compensation phase, the voltages of the gate end and the source end of the driving transistor T2 in each pixel circuit 211 can be obtained, and the K value of the driving transistor T2 in different pixel circuits 211 can be compensated according to the voltages.

[0081] It should be noted that Vth in the present application is the threshold voltage of the driving transistor T2, Vg is the voltage of the gate end of the driving transistor T2, Vs is the voltage of the source end of the driving transistor T3, Vgs is the voltage difference between the gate end and the source end of the driving transistor T3, and Vdata is the voltage input to the pixel circuit 211 from the data input end Data.

[0082] Please refer to Figure 11 , Figure 11 for Figure 7 the partial timing diagram of the transmission line in the display phase. In the transition section Tc between the display phase Tb and the compensation phase Ta, the potentials of the internal nodes of the pixel circuit 211 are initialized to the initial potentials.

[0083] Please refer to Figure 11 and Figure 10AIn the first sub-stage t7 of the display stage Tb, the first emission control line EM1, the second emission control line EM2, the third control signal line Scan2, and the fourth control signal line RD2 output low levels, and the first light emitting transistor T1, the second light emitting transistor T3, the compensation transistor T4, the switch transistor T5, and the calibration transistor T8 are all turned off; at the same time, the second control signal line RD1 outputs a high level, the second reset transistor T7 is turned on, the potential of the anode point of the light emitting device 212 is maintained at the first potential V1, the first control signal line Scan1 outputs a high level, the first reset transistor T6 is turned on, and the potential of the third node G is reset to the second potential V2, and the potential of the second node S is maintained at the initial potential, i.e., the reference potential Vref.

[0084] Referring to Figure 11 and Figure 10B In the second sub-stage t8 of the display stage Tb, the first control signal line Scan1, the first emission control line EM1, the second emission control line EM2, and the fourth control signal line RD2 output low levels, and the first reset transistor T6, the first light emitting transistor T1, the second light emitting transistor T3, and the calibration transistor T8 are all turned off; at the same time, the second control signal line RD1 outputs a high level, the second reset transistor T7 is turned on, the potential of the anode point of the light emitting device 212 is maintained at the first potential V1, the third control signal line Scan2 outputs a high level, the drive transistor T2, the switch transistor T5, and the compensation transistor T4 are turned on, and the updated data voltage Vdata output by the data signal line and the sum of Vth are input to the second node S through the drive transistor T2 and the switch transistor T5, so that the potential of the second node S is increased from the reference potential Vref to the sum of Vdata and Vth.

[0085] Referring to Figure 11 and Figure 10C In the third sub-stage t9 of the display stage Tb, the first control signal line Scan1, the second control signal line RD1, the third control signal line Scan2, and the fourth control signal line RD2 all output low levels, and the first reset transistor T6, the second reset transistor T7, the compensation transistor T4, the switch transistor T5, and the calibration transistor T8 are all turned off; secondly, the first emission control line EM1 and the second emission control line EM2 output high levels, the first light emitting transistor T1 and the second light emitting transistor T3 are turned on, at the same time, the potential of the third node G turns on the drive transistor T2, the bootstrap capacitor Cst is discharged and maintains the potential of the third node G at the sum of Vdata and Vth, and the light emitting device 212 emits light.

[0086] It should be noted that the potential of the third node G has been compensated in the compensation stage Ta of the present application, and therefore in the second sub-stage t8 of the display stage Tb, the input voltage of the data input end Data can be directly revised according to the revised K value, that is, the sum of Vdata and Vth is directly input.

[0087] It should be noted that the compensation transistor T4 is used to compensate the potential of the third node G in the display stage Tb. That is, in the second sub-stage t8 of the display stage Tb, since the input voltage of the data input end of the present application is the sum of Vdata and Vth, the potential of the third node G is directly changed to the sum of Vdata and Vth in the display stage Tb immediately after the compensation stage Ta, and the voltage of the third node G does not need to be compensated. In the subsequent display frame, the voltage of the third node G still needs to be compensated to the sum of Vdata and Vth of the corresponding display frame due to the drift of the threshold voltage.

[0088] It should be noted that the compensation stage Ta of the present application can be performed only in the opening or closing stage of the display panel 100, or in each display frame or a certain display frame in the continuous display frames.

[0089] It should be noted that in the compensation stage Ta of the present application, the data voltage input to each pixel circuit 211 from the data input end Data is equal, so that each sub-pixel 210 compensates the K value on the same basis. In the display stage Tb of the present application, the data voltage input to each pixel circuit 211 from the data input end Data can be adjusted according to the difference of the image data due to the difference of the display image.

[0090] In some embodiments of the present application, for example, the structure of Figure 1 only sets the compensation transistor T4 inside the pixel circuit 211 to compensate the potential of the gate end of the driving transistor T2, but does not set the calibration module 220 in Figure 1 , so that the potential of the second node S is inaccurate, causing the output working current to deviate. In other embodiments, for example, the structure of Figure 2 does not set the compensation transistor T4 inside the pixel circuit 211, but only sets the calibration module 220. However, when updating the potential of the second node S, the calibration module 220 needs to be corrected according to the potential of the gate end of the driving transistor T2. The inaccuracy of the potential of the gate end makes it necessary to first acquire the threshold voltage and calculate K synchronously according to the revised potential of the gate node when compensating the K value. This compensation method is relatively complex and requires more algorithm resources and compensation time.

[0091] In the embodiment, the application sets the compensation transistor T4 and the calibration module 220 in the pixel circuit 211 at the same time, and simultaneously corrects the potential of the gate terminal of the driving transistor T2 by using the compensation transistor T4 when correcting the potential of the source terminal of the driving transistor T2, and compensates the K value, thereby improving the accuracy of the potential correction of the source terminal of the driving transistor T2; in the display stage Tb, the potential of the gate terminal of the driving transistor T2 is corrected again by using the compensation transistor T4, that is, the compensation of the potentials of the gate terminal and the source terminal of the driving transistor T2 is completed at the same time in one display frame, thereby solving the problem of the deviation of the potential difference between the gate terminal and the source terminal of the driving transistor T2, improving the accuracy of the working current flowing into the light emitting device 212, and improving the display effect of the display panel.

[0092] In the above embodiments, the description of each embodiment has its own focus, and the part not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0093] The technical solutions provided by the embodiments of the application are described in detail above, and the principle and implementation mode of the application are described by using specific examples; the above embodiment is only used to help understand the technical solutions and the core idea of the application; the person skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced by equivalents; and the modification or replacement does not make the essence of the corresponding technical solution deviate from the scope of the technical solutions of the embodiments of the application.

Claims

1. A pixel circuit for connection with a light emitting device, characterized by, The pixel circuit comprises: a switch transistor, a first electrode of the switch transistor being connected to a data input terminal; a drive transistor, a first electrode of the drive transistor being connected to a second electrode of the switch transistor at a first node; a compensation transistor, a first electrode of the compensation transistor being connected to a second electrode of the drive transistor at a second node, a second electrode of the compensation transistor being connected to a gate of the drive transistor at a third node; and a calibration module, the calibration module being connected to the second node at the second node and being connected to the compensation transistor and the drive transistor; wherein the pixel circuit comprises a continuous compensation phase and a display phase, in the compensation phase, the calibration module is configured to calibrate an electric potential of the second node, and the compensation transistor is configured to compensate an electric potential of the third node.

2. The pixel circuit as claimed in claim 1, characterized in that The calibration module comprises: a calibration transistor, a first electrode of the calibration device being connected to the second node; a measurement device, a first switch being arranged between the measurement device and a second electrode of the calibration transistor; a calibration device, a second switch being arranged between the calibration device and the second electrode of the calibration transistor; wherein the calibration device is configured to calibrate the electric potential of the second node to a reference potential, and the measurement device is configured to obtain the electric potential of the second node.

3. The pixel circuit as claimed in claim 2, characterized in that In the compensation phase, a working duration of the first switch is greater than a working duration of the second switch.

4. The pixel circuit as claimed in claim 1, characterized in that A pulse width of the compensation phase is greater than a pulse width of the display phase.

5. The pixel circuit as claimed in claim 1, characterized in that, The pixel circuit further comprises a first reset transistor, a first electrode of the first reset transistor being connected to a first reset line, a second electrode of the first reset transistor being connected to the third node, and a gate of the first reset transistor being connected to a first control signal line.

6. The pixel circuit as claimed in claim 5, characterized in that The pixel circuit further comprises a second reset transistor, a first electrode of the second reset transistor being connected to a second reset line, a second electrode of the second reset transistor being connected to an anode of the light emitting device, and a gate of the second reset transistor being connected to a second control signal line.

7. The pixel circuit as claimed in claim 6, characterized in that The pixel circuit further comprises a first light emitting transistor and a second light emitting transistor, a first electrode of the first light emitting transistor being connected to a first potential line, a second electrode of the first light emitting transistor being connected to the first node, and a gate of the first light emitting transistor being connected to a first light emitting control line; a first electrode of the second light emitting transistor being connected to the second node, a second electrode of the second light emitting transistor being connected to the anode of the light emitting device, and a gate of the second light emitting transistor being connected to a second light emitting control line.

8. The pixel circuit as claimed in claim 7, characterized in that In the compensation phase, the first light emitting control line controls the first light emitting transistor to be turned on, and the second light emitting control line controls the second light emitting transistor to be turned off; in a light emitting period of the display phase, the first light emitting control line controls the first light emitting transistor to be turned on, and the second light emitting control line controls the second light emitting transistor to be turned on.

9. The pixel circuit as claimed in claim 5, characterized in that, The gate of the switch transistor and the gate of the compensation transistor are both connected to a third control signal line; wherein the first control signal line and the third control signal line transmit different levels of the same control signal.

10. A display panel, characterized by, The display panel comprises the pixel circuit as claimed in any one of claims 1 to 9. The display panel comprises the pixel circuit as claimed in any one of claims 1 to 9.

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