Frame synchronization method, receiver, electronic equipment and computer readable storage medium

Abstract

The invention relates to the technical field of communication interaction, in particular to a frame synchronization method, a receiver, electronic equipment and a computer readable storage medium. The frame synchronization method comprises the following steps: determining first frequency offset estimation of a first frame signal based on a first detection result obtained by performing coarse synchronization detection on the first frame signal; based on the first frequency offset estimation and a target link gain corresponding to the first signal strength of the first frame signal, performing fine synchronization verification detection on the first frame signal to analyze and determine the signal content of the first frame signal; wherein in the process of executing the fine synchronization check detection, frame signals are continuously received, when the difference value between the second signal intensity of the second frame signal and the first signal intensity is greater than or equal to a first threshold value, the fine synchronization check detection is stopped, and the fine synchronization check detection is executed on the basis of the second signal intensity and a second detection result obtained by performing the coarse synchronization detection on the second frame signal. And performing fine synchronization verification detection on the second frame signal to analyze and determine the signal content of the second frame signal.

Description

Technical Field

[0001] This disclosure relates to the field of communication and interaction technology, specifically to a frame synchronization method, a receiver, an electronic device, and a computer-readable storage medium. Background Technology

[0002] Bluetooth is a single-carrier frequency-hopping system operating in the 2400MHz to 2480MHz frequency band. Bluetooth technology uses frequency hopping within this band, transmitting data using a frequency bandwidth of 1MHz or 2MHz for each transmission. Frequency hopping effectively avoids interference with other wireless devices. In the 2.4GHz band, many other devices (such as Wi-Fi and microwave ovens) also use the same frequency for communication. By frequently switching frequencies, Bluetooth devices can avoid interference sources, thereby improving communication reliability.

[0003] In related technologies, high data throughput (HDT) technology can be used for signal transmission to improve data transmission rates. However, in actual processing, because the receiver's startup time is usually earlier than the arrival time of the HDT signal, the power of the received signal will change once before and after the arrival of the HDT signal. The receiver gain needs to be adjusted according to the strength of the HDT signal, but this process will consume some valid STS symbols, thus affecting the reliability of HDT signal reception. Summary of the Invention

[0004] To overcome the problems existing in related technologies, an exemplary embodiment of this disclosure provides a frame synchronization method applied to a receiver. The method includes: determining a first signal strength of the first frame signal based on a received first frame signal; adjusting a current link gain based on the first signal strength to determine a target link gain; determining a first frequency offset estimate of the first frame signal based on a first detection result of coarse synchronization detection of the first frame signal; and performing fine synchronization verification detection on the first frame signal based on the first frequency offset estimate and the target link gain to parse and determine the signal content of the first frame signal. During the fine synchronization verification detection, frame signals are continuously received. When a second frame signal is detected, and the difference between the second signal strength and the first signal strength of the second frame signal is greater than or equal to a first threshold, the fine synchronization verification detection of the first frame signal is stopped, and fine synchronization verification detection is performed on the second frame signal based on the second signal strength and the second detection result of coarse synchronization detection of the second frame signal to parse and determine the signal content of the second frame signal.

[0005] In some embodiments, determining a first frequency offset estimate of the first frame signal based on a first detection result of coarse synchronization detection of the first frame signal includes: normalizing the amplitude of the first frame signal and performing phase compensation on the first frame signal based on the phase difference between the current link gain and the initial link gain to obtain an intermediate signal; detecting the intermediate signal based on multiple symbols in the target short training sequence and the periodic changes of the multiple symbols to obtain a first detection result; and determining a first frequency offset estimate of the first frame signal in response to the first detection result characterizing that the first frame signal includes the target short training sequence.

[0006] In some embodiments, detecting an intermediate signal based on multiple symbols in a target short training sequence and the periodic changes of the multiple symbols to obtain a first detection result includes: extracting a test sequence from the intermediate signal based on the periodic changes of the multiple symbols, a target oversampling factor, and a target number of periods; matching the test sequence with the multiple symbols to determine the symbol matching result; determining the symbol change characteristics of the test sequence based on the periodic changes of the multiple symbols; and determining the first detection result based on the symbol matching result and the symbol change characteristics.

[0007] In some embodiments, determining a first detection result based on symbol matching results and symbol change features includes: determining that the first frame signal includes a target short training sequence in response to the symbol matching result indicating that the sequence to be tested matches multiple symbols and that the symbol change features are the same as the periodic changes of the multiple symbols; and determining that the first frame signal does not include a target short training sequence in response to the symbol matching result indicating that the sequence to be tested does not match multiple symbols and / or that the symbol change features are different from the periodic changes of the multiple symbols.

[0008] In some embodiments, a fine synchronization check is performed on the first frame signal based on a first frequency offset estimate and a target link gain to parse and determine the signal content of the first frame signal, including: performing fine synchronization detection on the first frame signal based on the first frequency offset estimate and the target link gain to obtain a third detection result; determining a second frequency offset estimate in response to the third detection result indicating that the first frame signal includes a target long training sequence; demodulating the control frame header in the first frame signal based on the first frequency offset estimate and the second frequency offset estimate to obtain a demodulation result; and parsing and determining the signal content of the first frame signal based on the demodulation result.

[0009] In some embodiments, stopping the fine synchronization check detection of the first frame signal includes: stopping the fine synchronization detection of the first frame signal, or stopping the demodulation of the control frame header in the first frame signal.

[0010] In some embodiments, during the fine synchronization check detection, the method further includes: in response to the difference between the second signal strength and the first signal strength of the second frame signal being less than a first threshold, determining a frequency offset estimate of the second frame signal based on a second detection result of coarse synchronization detection of the second frame signal.

[0011] In some embodiments, determining the first signal strength of the first frame signal based on the received first frame signal includes: determining the first signal strength of the first frame signal based on the reference received power corresponding to the current link gain and the number of target samples.

[0012] In some embodiments, adjusting the current link gain based on a first signal strength to determine a target link gain includes: determining a reference signal strength corresponding to the current link gain; and adjusting the current link gain based on a comparison between the first signal strength and the reference signal strength to determine the target link gain.

[0013] In some embodiments, adjusting the current link gain and determining the target link gain based on the comparison result between the first signal strength and the reference signal strength includes: in response to the difference between the first signal strength and the reference signal strength being greater than or equal to a second threshold, determining the link gain corresponding to the first signal strength based on a preset correspondence between signal strength and link gain, and switching the current link gain to the link gain corresponding to the first signal strength as the target link gain; in response to the difference between the first signal strength and the reference signal strength being less than the second threshold, determining the current link gain as the target link gain.

[0014] Secondly, this disclosure also provides a receiver, comprising: a first processing module, configured to determine a first signal strength of the first frame signal based on a received first frame signal; adjust a current link gain based on the first signal strength to determine a target link gain; and determine a first frequency offset estimate of the first frame signal based on a first detection result of coarse synchronization detection of the first frame signal; and a second processing module, configured to perform fine synchronization verification detection on the first frame signal based on the first frequency offset estimate and the target link gain to parse and determine the signal content of the first frame signal; wherein, during the fine synchronization verification detection process, frame signals are continuously received, and when a second frame signal is detected, and in response to a difference between the second signal strength and the first signal strength of the second frame signal being greater than or equal to a first threshold, the fine synchronization verification detection on the first frame signal is stopped, and the second frame signal is subjected to fine synchronization verification detection based on the second signal strength and the second detection result of coarse synchronization detection of the second frame signal to parse and determine the signal content of the second frame signal.

[0015] Thirdly, this disclosure also provides an electronic device, including:

[0016] The memory and the processor are interconnected and communicate with each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the frame synchronization method provided by any of the above aspects.

[0017] Fourthly, this disclosure also provides a computer-readable storage medium storing a program for performing the frame synchronization method provided in any of the foregoing aspects.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure.

[0019] The technical solutions provided by the embodiments of this disclosure can include the following beneficial effects: According to the frame synchronization method provided by this disclosure, determining the target link gain based on the first signal strength of the first frame signal can provide a stable and reliable signal basis for coarse synchronization detection, ensuring its accuracy. Furthermore, combined with the first frequency offset estimate obtained by coarse synchronization detection of the first frame signal, fine synchronization verification can be performed on the first frame signal to parse and determine the signal content of the first frame signal, meeting the requirements of frame synchronization. Moreover, to avoid missing the correct HDT signal, frame signals are continuously received after obtaining the target link gain and the first frequency offset estimate. When a second frame signal is detected whose signal strength differs from the first signal strength by a factor greater than or equal to a first threshold, the fine synchronization verification detection of the first frame signal is stopped. Then, based on the second signal strength of the second frame signal and the second detection result of coarse synchronization detection of the second frame signal, fine synchronization verification detection is performed on the second frame signal. This ensures the timeliness of frame synchronization processing for the second frame signal, effectively avoiding missed detections, thereby helping to ensure the reliability and accuracy of frame synchronization processing. Attached Figure Description

[0020] This disclosure can be better understood by describing exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, in which:

[0021] Figure 1 This is a schematic diagram of a frame structure according to an exemplary embodiment disclosed in a publication;

[0022] Figure 2 This is a structural block diagram of a receiver according to an exemplary embodiment disclosed in a publication;

[0023] Figure 3 This is a schematic diagram of the state transition of a receiver according to an exemplary embodiment disclosed in a publication;

[0024] Figure 4 It is a time-varying correspondence diagram of receiver state and frame signal content, as shown in an exemplary embodiment of a public document;

[0025] Figure 5 It is a time-varying correspondence diagram of receiver state and frame signal content, as shown in an exemplary embodiment of a public disclosure.

[0026] Figure 6 It is another time-varying correspondence diagram of receiver state and frame signal content shown in an exemplary embodiment of the present invention;

[0027] Figure 7 This is a flowchart illustrating a frame synchronization method according to an exemplary embodiment of a published document;

[0028] Figure 8 This is a structural block diagram of another receiver illustrated in an exemplary embodiment of a publication;

[0029] Figure 9 This is a schematic diagram of the state transition of another receiver according to an exemplary embodiment disclosed in a publication;

[0030] Figure 10 This is a structural block diagram of another receiver shown according to an exemplary embodiment disclosed in a publication;

[0031] Figure 11 This is a block diagram illustrating an electronic device according to an exemplary embodiment disclosed in a publication. Detailed Implementation

[0032] The following describes specific embodiments of this disclosure. It should be noted that, in order to provide a concise description, this specification cannot exhaustively describe all features of the actual embodiments. It should be understood that, in the actual implementation of any embodiment, just as in any engineering or design project, various specific decisions are often made to achieve the developer's specific goals and to meet system-related or business-related constraints, and this can change from one embodiment to another. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this disclosure, changes in design, manufacturing, or production based on the technical content disclosed in this disclosure are merely conventional technical means and should not be construed as insufficient content of this disclosure.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. The terms “a” or “one,” etc., do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising,” “including,” etc., mean that the element or object preceding “comprising” or “including” encompasses the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected,” “linked,” etc., are not limited to physical or mechanical connections, nor are they limited to direct or indirect connections.

[0034] In related technologies, signal transmission can be based on High Data Throughput (HDT) technology to improve data transmission rate.

[0035] like Figure 1 As shown, the frame structure for signal transmission at the physical layer based on HDT technology can include three parts: a preamble sequence, a control header, and a payload. The preamble sequence includes a Short Training Sequence (STS) and a Long Training Sequence (LTS). The STS consists of four symbols (sym), namely +1, -j, j, and 1, and is repeated nine times consecutively within the same frame. The LTS is a Zadoff Chu (a complex sequence with constant amplitude, zero cyclic autocorrelation, and excellent cross-correlation properties, hereinafter referred to as ZC) sequence consisting of 17 symbols, and is repeated twice consecutively within the same frame. A guard interval GL is set between the last STS and the first LTS to transmit the last four symbols of the LTS. In total, the preamble sequence includes 74 symbols, of which the ZC sequences (16 in total) within the LTS are specified by the upper-layer protocol and are known to the receiver's physical layer. The receiver can adjust its gain, achieve time-frequency synchronization, and perform channel estimation based on the preamble sequence. The control frame header uses ( This modulation, based on Quadrature Phase Shift Keying (QPSK) modulation, involves rotating all even-numbered symbols in the sequence by -90 degrees to reduce the peak-to-average power ratio (PAPR). The control frame header contains the Physical Channel Address (PCA), Physical Layer Format Identifier, and Rate Identifier. The control frame header has a fixed length of 64 symbols. The data payload, based on the Physical Layer Format Identifier, includes a data frame header and data content. The modulation and coding scheme used is specified by the Rate Identifier. It supports (…). It supports three modulation methods: 8PSK, 16-quadrature amplitude modulation (QAM); the encoding can use binary convolutional codes, and the code rate can be configured to 1 / 2, 2 / 3, 4 / 3, or 15 / 16. The length of the data payload is determined by relevant fields in the control frame header and the data frame header.

[0036] like Figure 2 As shown, the receiver may include a receiving antenna, an RF front-end, a digital front-end, a gain control module, and a synchronization / demodulation module. The receiving antenna receives signals in a specific frequency band, which are then processed and initially amplified by the RF front-end to obtain an analog signal. The digital front-end converts the analog signal into a digital signal. The gain control module controls the amplification factor for gain conversion of the analog signal. The synchronization / demodulation module performs synchronization / demodulation processing on the digital signal to determine its content.

[0037] In related technologies, the state transition process of a receiver processing HDT signals can be as follows: Figure 3 As shown, the process includes: After startup, the receiver needs to adjust the analog and digital gains based on the STS (Signal Transmission Time) portion of the received signal. With the gain stable, it detects the arrival of a signal conforming to the HDT (High-Density Transmission Time) format based on the STS and simultaneously uses the known STS to determine the frequency offset estimate. After compensating for the frequency offset obtained based on the STS, it locks the currently determined gain, uses the known LTS (Low-Density Transmission Time) to perform a more accurate frequency offset estimate, synchronizes the instantaneous phase of the received signal with the local carrier, completes symbol synchronization, and locates the control frame header. Finally, it demodulates and decodes the control frame header and the data payload in sequence. The time-varying correspondence between the received digital signal frame content and the receiver state can be described as follows: Figure 4 As shown.

[0038] In actual processing, since the receiver's startup time is usually earlier than the arrival time of the HDT signal, the power of the received signal will change once before and after the arrival of the HDT signal. The receiver's gain needs to be adjusted according to the strength of the HDT signal. However, this process will consume some effective STS symbols, which will prevent the full utilization of the STS symbols in the HDT signal when performing coarse synchronization detection (including arrival detection and frequency offset estimation), thus leading to missed detections or false detections.

[0039] Furthermore, when interference signals are present in the environment, although the signal power of the interference signals is usually much lower than that of the useful signal (meaning the signal-to-interference ratio, or the ratio of useful signal power to interference signal power, is still high enough), the receiver may still lose the opportunity to correctly synchronize and receive the useful signal because it is synchronized with other interference signals in the environment, especially HDT signals transmitted and received between other devices.

[0040] For example, such as Figure 5 As shown, the receiver synchronizes with the STS portion of the interfering HDT signal and then performs LTS synchronization. However, the STS portion of the correct HDT signal has only just arrived at the receiver at this time. When the receiver fails to perform precise synchronization processing of the interfering signal for LTS, the STS portion of the correct HDT signal has been completely missed, resulting in the correct HDT signal being unable to be received correctly.

[0041] Or, for example Figure 6 As shown, the receiver synchronizes not only the STS portion of the interfering HDT signal but also the LTS portion. The probability that the LTS sequence in the interfering signal is identical to the correct HDT signal is 1 / 16. The receiver will only discover that the signal currently undergoing frame synchronization processing is the interfering HDT signal when attempting to demodulate the control frame header. However, by this time, most of the STS of the correct HDT signal has already passed, leading to a missed opportunity to successfully receive the useful signal.

[0042] Therefore, this disclosure provides a frame synchronization method for a receiver. For example... Figure 7 As shown, the frame synchronization method may include the following steps:

[0043] Step S110: Determine the first signal strength of the first frame signal based on the received first frame signal.

[0044] The first frame signal can be understood as one frame of the digital signal output from the receiver's digital front end. To determine whether the first frame signal is the required HDT signal, the compatibility between the current link gain and the first frame signal is quantitatively evaluated, and the first signal strength of the first frame signal is determined. Based on the first signal strength, it is determined whether the current link gain matches the first frame signal, so as to ensure the reliability of subsequent coarse synchronization detection.

[0045] Step S120: Based on the first signal strength, adjust the current link gain and determine the target link gain.

[0046] Link gain is used to calibrate the signal strength to the receiver's relatively optimal processing range, in order to avoid the signal being too strong and causing analog-to-digital conversion saturation, or too weak and causing noise interference with the synchronization algorithm.

[0047] To ensure accurate identification of STS in the first frame signal during subsequent coarse synchronization detection, the current link gain is adjusted based on the magnitude of the first signal strength. This ensures that the final target link gain is effective and reliable, matching the first signal strength of the first frame signal, thus providing a stable and reliable signal foundation for coarse synchronization detection and guaranteeing its accuracy.

[0048] Step S130: Based on the first detection result of coarse synchronization detection of the first frame signal, determine the first frequency offset estimate of the first frame signal.

[0049] Because of slight differences between the crystal oscillators of the transmitter and receiver, the received signal will deviate from the local carrier frequency, thus affecting the accuracy of subsequent signal demodulation. Therefore, in order to initially determine the starting position of the data load in the first frame signal, coarse synchronization detection needs to be performed on the first frame signal.

[0050] In the process of coarse synchronization detection of the first frame signal, the short training sequence (STS) in the first frame signal is used as the detection object. Based on the first detection result, it can be quickly determined whether the first frame signal meets the requirements of HDT frame format to eliminate interference signals. If it is determined that the first frame signal meets the requirements of HDT frame format, the frequency offset of the first frame signal can be initially estimated to obtain the first frequency offset estimate for correcting the first frame signal, so as to provide a basis for frequency offset correction for subsequent fine synchronization verification.

[0051] Step S140: Based on the first frequency offset estimate and the target link gain, perform fine synchronization verification detection on the first frame signal to analyze and determine the signal content of the first frame signal.

[0052] Given a clear estimate of the first frequency offset and the target link gain, a more precise synchronization check can be performed on the first frame signal to further determine whether it is an HDT signal, thereby minimizing interference from other signals. This precise synchronization check includes, but is not limited to: performing precise synchronization detection on the LTS of the first frame signal to achieve high-precision symbol synchronization, phase synchronization, and frequency offset correction; and demodulating the control frame header of the first frame signal.

[0053] If the first frame signal can pass the fine synchronization check, it can be considered that the first frame signal is the required HDT signal. Then, based on the demodulation result of the control frame header adjustment, the method of parsing the data load in the first frame signal can be determined, thereby determining the signal content of the first frame signal.

[0054] If the first frame signal fails the fine synchronization check, it can be considered that the first frame signal is not the required HDT signal, and the fine synchronization check process is stopped to save resources.

[0055] Step S150: During the fine synchronization check detection, frame signals are continuously received. When a second frame signal is detected, and the difference between the second signal strength and the first signal strength of the second frame signal is greater than or equal to a first threshold, the fine synchronization check detection of the first frame signal is stopped. Based on the second signal strength and the second detection result of the coarse synchronization detection of the second frame signal, the fine synchronization check detection of the second frame signal is performed to parse and determine the signal content of the second frame signal.

[0056] Since the receiver is powered on during frame synchronization, interference signals may occur during actual signal reception, affecting the reception of the correct HDT signal. Furthermore, the probability of the LTS sequence in the interference signal being identical to the correct HDT signal is 1 / 16, meaning there's a possibility that the interference signal might pass through the fine synchronization detection, thus affecting the timing of frame synchronization processing for the correct HDT signal.

[0057] Therefore, during the fine synchronization check and detection process, frame signals are continuously received and signal strength is detected to determine whether a new frame signal has been received based on changes in signal strength.

[0058] When a second frame signal is detected, and the difference between the second signal strength and the first signal strength of the second frame signal is greater than or equal to a first threshold, it indicates that the first frame signal may be an interference signal and not the actual desired HDT signal. The first threshold can be the minimum signal strength difference at which a new, more likely HDT signal enters. Therefore, the fine synchronization check detection of the first frame signal is stopped, and instead, based on the second signal strength of the second frame signal and the second detection result of the coarse synchronization detection of the second frame signal, a fine synchronization check detection is performed on the second frame signal to analyze and determine its signal content, thereby ensuring the reliability and accuracy of the receiver's frame synchronization processing.

[0059] According to the frame synchronization method provided in this disclosure, determining the target link gain based on the first signal strength of the first frame signal provides a stable and reliable signal foundation for coarse synchronization detection, ensuring its accuracy. Furthermore, combined with the first frequency offset estimate obtained through coarse synchronization detection of the first frame signal, fine synchronization verification can be performed on the first frame signal to analyze and determine its signal content, meeting the requirements of frame synchronization. Moreover, to avoid missing the correct HDT signal, frame signals are continuously received after obtaining the target link gain and the first frequency offset estimate. When a second frame signal is detected whose signal strength differs from the first signal strength by a factor greater than or equal to a first threshold, the fine synchronization verification detection of the first frame signal is stopped. Then, based on the second signal strength of the second frame signal and the second detection result of the coarse synchronization detection of the second frame signal, fine synchronization verification detection is performed on the second frame signal. This ensures the timeliness of frame synchronization processing for the second frame signal, effectively avoiding missed detections, and thus helps ensure the reliability and accuracy of frame synchronization processing.

[0060] In some embodiments, step S130 above may include the following steps:

[0061] Step a1: Normalize the amplitude of the first frame signal and perform phase compensation on the first frame signal based on the phase difference between the current link gain and the initial link gain to obtain the intermediate signal.

[0062] To improve the accuracy and stability of coarse synchronization detection of the first frame signal, the amplitude of the first frame signal is normalized to eliminate interference caused by differences in channel attenuation, noise fluctuations, or gain adjustment.

[0063] Since the receiver has an initial link gain when it is turned on, in order to eliminate the phase deviation caused by gain adjustment, the phase compensation of the first frame signal is performed based on the phase difference between the current link gain and the initial link gain to restore the original phase characteristics of the signal and ensure the accuracy of coarse synchronization detection.

[0064] The first frame signal is For example, the intermediate signal obtained after amplitude normalization and phase compensation can be ,in, It is the channel amplitude response. This represents the difference in phase rotation that is additionally assigned to the link compared to the default initial gain configuration at startup.

[0065] Step a2: Based on multiple symbols in the target short training sequence and the periodic changes of multiple symbols, detect the intermediate signal to obtain the first detection result.

[0066] The target short training sequence is a known sequence used for STS detection. The arrangement of its multiple symbols is determined by periodic variation characteristics.

[0067] To determine whether the intermediate signal contains the target short training sequence, the intermediate signal is detected based on the known multiple symbols and periodic change features, and then the intermediate signal is judged to conform to the characteristics of the target short training sequence through the first detection result.

[0068] In some embodiments, step a2 above may include the following steps:

[0069] Step a21: Extract the sequence to be tested from the intermediate signal based on the periodic changes of multiple symbols, the target oversampling factor, and the target number of periods;

[0070] Step a22: Match the sequence to be tested with multiple symbols to determine the symbol matching results;

[0071] Step a23: Determine the symbol change characteristics of the sequence under test based on the periodic changes of multiple symbols;

[0072] Step a24: Determine the first detection result based on the symbol matching results and symbol change characteristics.

[0073] Specifically, the target short training sequence includes Symbols, among which, This refers to using the target number of STS cycles for detection, and it is a receiver algorithm parameter that can be configured according to requirements.

[0074] Based on the periodic variations of multiple symbols, the target oversampling factor, and the number of target periods, the sequence to be tested can be extracted from the intermediate signal. , ,in, This refers to the target oversampling factor, i.e., the signal oversampling factor. The target sampling rate is higher than the symbol rate.

[0075] The process of matching the sequence to be tested with multiple symbols can be represented by the following formula:

[0076] ;

[0077] Among them, the operation Represents the relationship between complex variables Find conjugate; operation Represents integer variables Perform modulo 4 operations; , , , .

[0078] like , which indicates that the sequence to be tested matches multiple symbols. Here, R represents the minimum threshold value at which symbols are considered to match.

[0079] The process of determining whether the sign change characteristics of the sequence under test match the periodic changes of multiple symbols can be represented by the following formula: .like Then, the symbol change characteristics of the sequence under test match the periodic changes of multiple symbols. Among them, This represents the minimum critical value at which the periodic characteristics are considered to match.

[0080] In some examples, in response to the symbol matching result indicating that the sequence under test matches multiple symbols and that the symbol change characteristics are the same as the periodic changes of multiple symbols, the frame structure of the intermediate signal indicates that the target short training sequence is included, and thus it can be determined that the first frame signal includes the target short training sequence.

[0081] In other examples, in response to the symbol matching result indicating that the sequence under test does not match multiple symbols, but the symbol change feature is the same as the periodic change of multiple symbols, it can be considered that although the frame structure of the intermediate signal contains symbols with the same periodic change as multiple symbols, it does not include multiple symbols that can express the target short training sequence. Therefore, it can be determined that the first frame signal does not include the target short training sequence.

[0082] In some other examples, in response to the symbol matching result indicating that the test sequence matches multiple symbols, but the symbol change characteristics are different from the periodic changes of multiple symbols, it can be considered that although the frame structure of the intermediate signal contains multiple symbols of the target short training sequence, the change pattern is different from the periodic changes of multiple symbols of the target short training sequence. Therefore, it can be determined that the frame structure of the intermediate signal does not contain the target short training sequence, and the first frame signal does not contain the target short training sequence, thus ensuring the accuracy of the judgment.

[0083] In some other examples, in response to the symbol matching result indicating that the sequence under test does not match multiple symbols, and the symbol change characteristics are different from the periodic changes of multiple symbols, it can be determined that the frame structure of the intermediate signal does not contain the target short training sequence at all, and thus it can be determined that the first frame signal does not contain the target short training sequence.

[0084] Step a3: In response to the first detection result characterizing the first frame signal as including the target short training sequence, determine the first frequency offset estimate of the first frame signal.

[0085] In response to the first detection result indicating that the first frame signal includes the target short training sequence, it can be preliminarily considered that the format of the first frame signal conforms to the requirements of the HDT format, and interference signals without STS can be excluded. Thus, in order to further determine whether it is the real HDT signal, the first frequency offset estimate of the first frame signal is determined, so as to provide a basis for frequency offset correction for subsequent fine synchronization verification.

[0086] In some embodiments, step S140 above may include the following steps:

[0087] Step b1: Based on the first frequency offset estimate and the target link gain, perform fine synchronization detection on the first frame signal to obtain the third detection result;

[0088] Step b2, in response to the third detection result characterizing the first frame signal as including the target long training sequence, determine the second frequency offset estimate;

[0089] Step b3: Based on the first frequency offset estimate and the second frequency offset estimate, demodulate the control frame header in the first frame signal to obtain the demodulation result;

[0090] Step b4: Based on the demodulation results, analyze and determine the signal content of the first frame signal.

[0091] Specifically, the first frequency offset estimation is used to perform preliminary frequency offset compensation on the first frame signal to eliminate most of the carrier frequency deviation, so as to reduce the frequency offset error to a range that can be handled by fine synchronization; the target link gain is locked to ensure the stability of the signal amplitude when performing fine synchronization detection on the long training sequence (LTS) in the first frame signal, thereby obtaining the third detection result.

[0092] In response to the third detection result indicating that the first frame signal includes the target long training sequence, and that the first frame signal also contains the correct HDT signal target long training sequence, a higher-precision frequency offset detection is achieved for the first frame signal, resulting in a second frequency offset estimate. For example, the theoretical phase difference between adjacent symbols in the LTS is known. By comparing the actual phase difference between adjacent symbols in the LTS in the first frame signal, the remaining frequency offset, i.e., the subtle deviation that the first frequency offset estimate did not eliminate, can be derived, thus obtaining the required second frequency offset estimate for subsequent fine correction of carrier synchronization.

[0093] Based on the first frequency offset estimation and the second frequency offset estimation, joint frequency offset compensation is performed on the control frame header signal of the first frame signal to achieve accurate carrier frequency alignment.

[0094] If the demodulation result is successful, the first frame signal can be considered as the required HDT signal. Based on the demodulation result, the parsing method of the data load part of the first frame signal can be determined, thereby obtaining the signal content of the first frame signal.

[0095] If the demodulation result fails to represent, it can be assumed that the first frame signal is not the required HDT signal, and the process of frame synchronization processing for the first frame signal can be terminated.

[0096] The suspension of fine synchronization verification for the first frame signal includes: suspending the fine synchronization detection of the first frame signal, or suspending the demodulation of the control frame header in the first frame signal. That is, if the second frame signal is detected during the fine synchronization detection of the first frame signal, the fine synchronization detection of the first frame signal is suspended to ensure the timeliness of frame synchronization processing for the second frame signal. If the second frame signal is detected during the demodulation of the control frame header in the first frame signal, the demodulation of the control frame header in the first frame signal is suspended to ensure the timeliness of frame synchronization processing for the second frame signal.

[0097] In other embodiments, during the fine synchronization check detection, if the difference between the second signal strength and the first signal strength of the second frame signal is less than a first threshold, it indicates that although a new frame signal has entered, the increment of the detected second signal strength compared to the first signal strength is small. This may be caused by a potential HDT signal, or it may be caused by interference signals or noise. However, in order to avoid missed detection, the frequency offset estimate of the second frame signal is determined based on the second detection result of the coarse synchronization detection of the second frame signal. This is to determine whether the format of the second frame signal conforms to the HDT format, and to avoid missing effective signals due to similar strengths. This helps to identify potential effective signals in advance, ensures reception efficiency, and thus helps to improve the overall reception robustness.

[0098] In some embodiments, step S110 may include: determining the first signal strength of the first frame signal based on the reference received power corresponding to the current link gain and the number of target samples.

[0099] Specifically, the first frame signal is For example, the first signal strength The process of determining can be represented by the following formula:

[0100] ;

[0101] Among them, the first signal strength The unit is dBm. This represents the reference received power corresponding to the current link gain, that is, the power configured in the current link gain configuration. Below, the receiving power is the power when the received digital signal is a DC signal with an amplitude of 1, expressed in dBm. Characterizes the number of target samples required to accumulate for the preset RSSI calculation.

[0102] In some embodiments, step S120 above may include the following steps:

[0103] Step c1: Determine the reference signal strength corresponding to the current link gain;

[0104] Step c2: Based on the comparison between the first signal strength and the reference signal strength, adjust the current link gain and determine the target link gain.

[0105] Specifically, the current link gain can be considered as the default initial link gain after the receiver is turned on, or it can be the target link gain based on the frame synchronization processing of the previous frame signal.

[0106] Based on the comparison between the first signal strength and the reference signal strength, it can be determined whether the current link gain can calibrate the first signal strength to the receiver's relatively optimal processing range. This allows it to determine whether the current link gain needs to be adjusted to obtain a target link gain that can be specifically calibrated for the first signal strength.

[0107] In some examples, in response to the difference between the first signal strength and the reference signal strength being greater than or equal to a second threshold, based on a preset correspondence between signal strength and link gain, the link gain corresponding to the first signal strength is determined, and the current link gain is switched to the link gain corresponding to the first signal strength as the target link gain. Here, the second threshold can be considered the minimum allowable strength difference. In response to the difference between the first signal strength and the reference signal strength being greater than or equal to the second threshold, indicating that the current link gain cannot calibrate the first signal strength to the receiver's relatively optimal processing range, a link gain suitable for the first signal strength is determined based on the preset correspondence between signal strength and link gain. This link gain is then used as the target link gain to replace the current link gain, ensuring the reliability and accuracy of subsequent processing.

[0108] In other examples, in response to the difference between the first signal strength and the reference signal strength being less than a second threshold, it indicates that the current link gain is capable of calibrating the first signal strength to the receiver's relatively optimal processing range, thus eliminating the need to adjust the current link gain and allowing the current link gain to be directly used as the desired target link gain.

[0109] In some optional application scenarios, the block diagram of the receiver provided in this disclosure can be as follows: Figure 8 As shown, the system includes a receiving antenna, an RF front-end, a digital front-end, a gain control module, a signal strength detection module, a coarse synchronization detection module, a frequency offset compensation module, a fine synchronization detection module, and a demodulation and parsing module. The receiving antenna receives signals in a specific frequency band, which are then processed and initially amplified by the RF front-end to obtain an analog signal. The digital front-end converts the analog signal into a digital signal (i.e., the first frame signal). The gain control module controls the amplification factor for the gain conversion of the analog signal. For the output first frame signal, the first signal strength and corresponding target link gain are determined by signal strength detection; the first frequency offset estimate is determined by the coarse synchronization detection module; and frequency offset compensation is performed by the frequency offset compensation module based on the obtained first frequency offset estimate and target link gain, so that the first frame signal can be finely synchronized by the fine synchronization detection module to obtain the third detection result. In response to the third detection result characterizing the first frame signal as including the target long training sequence, a second frequency offset estimate with higher accuracy than the first frequency offset estimate is determined. Then, based on the first and second frequency offset estimates, the control frame header in the first frame signal is demodulated to obtain the demodulation result. Based on the demodulation result, the data payload content is parsed and the signal content of the first frame signal is determined.

[0110] During the fine synchronization detection or demodulation verification of the first frame signal, the signal strength detection module and the coarse synchronization detection module are continuously running. When the second frame signal is detected, and the difference between the second signal strength and the first signal strength of the second frame signal is greater than or equal to a first threshold, the processing of the first frame signal is stopped, and the fine synchronization verification detection of the second frame signal is performed based on the second signal strength and the second detection result of the coarse synchronization detection of the second frame signal, so as to parse and determine the signal content of the second frame signal. If the difference between the second signal strength and the first signal strength of the second frame signal is less than the first threshold, the target link gain is kept unchanged, and the frequency offset estimate of the second frame signal is determined based on the second detection result of the coarse synchronization detection of the second frame signal, so as to determine the potentially correct HDT signal in advance, improve detection efficiency, and ensure the performance of the receiver in frame synchronization processing. To facilitate understanding of the receiver's state changes, the state transition process of the receiver in frame synchronization processing can be described as follows: Figure 9 As shown.

[0111] The frame synchronization method provided in this disclosure allows for gain adjustment while performing signal detection based on STS, thereby enabling the use of as many STS symbols as possible in signal detection and frequency offset estimation, improving signal detection performance, and ensuring the accuracy of frequency offset estimation results.

[0112] Furthermore, when performing coarse synchronization detection on the first frame signal, the detection threshold is set using the known target STS symbol sequence and periodic characteristics, which can avoid false alarms caused by random noise interference and thus ensure the accuracy of the coarse synchronization detection results.

[0113] Moreover, the receiver disclosed herein continuously detects whether a stronger signal is arriving by checking the signal strength, while performing coarse synchronization detection without interruption (it will not be interrupted by gain adjustment caused by the increase in received signal power). Once a stronger signal is detected, it immediately switches to trying to receive and demodulate that stronger signal, which can effectively ensure the timeliness of frame synchronization processing and effectively avoid the occurrence of missed detection.

[0114] Based on the same inventive concept, this disclosure also provides a receiver. For example... Figure 10 As shown, the receiver 200 may include:

[0115] The first processing module 210 is configured to determine a first signal strength of the first frame signal based on the received first frame signal; adjust the current link gain based on the first signal strength to determine the target link gain; and determine a first frequency offset estimate of the first frame signal based on the first detection result of coarse synchronization detection of the first frame signal.

[0116] The second processing module 220 is used to perform fine synchronization verification on the first frame signal based on the first frequency offset estimation and the target link gain, so as to parse and determine the signal content of the first frame signal; wherein, during the fine synchronization verification process, frame signals are continuously received, and when the second frame signal is detected, and the difference between the second signal strength and the first signal strength of the second frame signal is greater than or equal to the first threshold, the fine synchronization verification on the first frame signal is stopped, and the second frame signal is performed fine synchronization verification on the second frame signal based on the second signal strength and the second detection result of the coarse synchronization detection on the second frame signal, so as to parse and determine the signal content of the second frame signal.

[0117] In some embodiments, the first processing module 210 may include: a first processing unit, configured to normalize the amplitude of the first frame signal and perform phase compensation on the first frame signal based on the phase difference between the current link gain and the initial link gain to obtain an intermediate signal; a first detection unit, configured to detect the intermediate signal based on multiple symbols in the target short training sequence and the periodic changes of the multiple symbols to obtain a first detection result; and a first determination unit, configured to determine a first frequency offset estimate of the first frame signal in response to the first detection result characterizing that the first frame signal includes the target short training sequence.

[0118] In some embodiments, the first detection unit may include: an extraction unit for extracting a sequence to be tested from an intermediate signal based on the periodic changes of multiple symbols, a target oversampling factor, and a target number of periods; a matching unit for matching the sequence to be tested with multiple symbols to determine a symbol matching result; a second determination unit for determining the symbol change characteristics of the sequence to be tested based on the periodic changes of multiple symbols; and a third determination unit for determining a first detection result based on the symbol matching result and the symbol change characteristics.

[0119] In some embodiments, the third determining unit may include: a first execution unit, configured to determine that the first frame signal includes the target short training sequence in response to a symbol matching result indicating that the sequence to be tested matches multiple symbols and that the symbol change characteristics are the same as the periodic changes of the multiple symbols; and a second execution unit, configured to determine that the first frame signal does not include the target short training sequence in response to a symbol matching result indicating that the sequence to be tested does not match multiple symbols and / or that the symbol change characteristics are different from the periodic changes of the multiple symbols.

[0120] In some embodiments, the second processing module 220 may include: a second detection unit, configured to perform fine synchronization detection on the first frame signal based on a first frequency offset estimate and a target link gain, to obtain a third detection result; a fourth determination unit, configured to determine a second frequency offset estimate in response to the third detection result characterizing the first frame signal as including a target long training sequence; a demodulation unit, configured to demodulate the control frame header in the first frame signal based on the first frequency offset estimate and the second frequency offset estimate, to obtain a demodulation result; and a second processing unit, configured to parse and determine the signal content of the first frame signal based on the demodulation result.

[0121] In some embodiments, stopping the fine synchronization check detection of the first frame signal includes: stopping the fine synchronization detection of the first frame signal, or stopping the demodulation of the control frame header in the first frame signal.

[0122] In some embodiments, during the fine synchronization check detection process, the first processing module 210 may further be used to: determine the frequency offset estimate of the second frame signal based on the second detection result of coarse synchronization detection of the second frame signal in response to the difference between the second signal strength and the first signal strength of the second frame signal being less than a first threshold.

[0123] In some embodiments, the first processing module 210 may include: a fifth determining unit, configured to determine the first signal strength of the first frame signal based on the reference received power corresponding to the current link gain and the number of target samples.

[0124] In some embodiments, the first processing module 210 may include: a sixth determining unit, configured to determine the reference signal strength corresponding to the current link gain; and an adjusting unit, configured to adjust the current link gain based on the comparison result between the first signal strength and the reference signal strength, and determine the target link gain.

[0125] In some embodiments, the adjustment unit may include: a third execution unit, configured to, in response to a difference between a first signal strength and a reference signal strength being greater than or equal to a second threshold, determine a link gain corresponding to the first signal strength based on a preset correspondence between signal strength and link gain, and switch the current link gain to the link gain corresponding to the first signal strength as the target link gain; and a fourth execution unit, configured to, in response to a difference between the first signal strength and the reference signal strength being less than the second threshold, determine the current link gain as the target link gain.

[0126] Regarding the receiver in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0127] Based on the same inventive concept, this disclosure also provides an electronic device having the above-mentioned features. Figure 10 The receiver shown.

[0128] Please see Figure 11 , Figure 11 This is a schematic diagram of the structure of an electronic device provided in an optional embodiment of this disclosure, such as... Figure 11 As shown, the electronic device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise as required. The processors can process instructions executed within the electronic device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple electronic devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 11 Take a processor 10 as an example.

[0129] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0130] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0131] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0132] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0133] The electronic device also includes an input device 30 and an output device 40. The processor 10, memory 20, input device 30, and output device 40 can be connected via a bus or other means. Figure 11 Taking the example of a connection between China and Israel via a bus.

[0134] Input device 30 can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the electronic device, such as a touch screen, keypad, mouse, trackpad, touchpad, joystick, one or more mouse buttons, trackball, joystick, etc. Output device 40 may include display devices, auxiliary lighting devices (e.g., LEDs), and haptic feedback devices (e.g., vibration motors). The aforementioned display devices include, but are not limited to, liquid crystal displays, light-emitting diodes, displays, and plasma displays. In some alternative embodiments, the display device may be a touch screen.

[0135] Based on the same inventive concept, this disclosure also provides a computer-readable storage medium storing a program for performing the device interaction method of any of the foregoing embodiments.

[0136] This disclosure uses specific terms to describe embodiments of the present disclosure. Terms such as "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the present disclosure. Therefore, it should be emphasized and noted that references to "an embodiment," "one embodiment," or "an alternative embodiment" in different locations throughout this specification do not necessarily refer to the same embodiment. Furthermore, certain features, structures, or characteristics in one or more embodiments of the present disclosure can be appropriately combined.

[0137] In the context of this disclosure, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of expressly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0138] Similarly, it should be noted that, in order to simplify the description of this disclosure and thus aid in the understanding of one or more embodiments, the foregoing description of embodiments of this disclosure may sometimes combine multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of this disclosure requires more features than the features claimed. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0139] The basic concepts have been described above. It is obvious that the above disclosure is merely illustrative and does not constitute a limitation of this disclosure. Although not explicitly stated herein, various modifications, improvements, and corrections may be made to this disclosure by those skilled in the art. Such modifications, improvements, and corrections are suggested in this disclosure and therefore remain within the spirit and scope of the embodiments of this disclosure.

Claims

1. A frame synchronization method applied to a receiver, the method comprising: determining a first signal strength of a first frame signal based on the received first frame signal; adjusting a current link gain based on the first signal strength to determine a target link gain; determining a first frequency offset estimation of the first frame signal based on a first detection result of coarse synchronization detection on the first frame signal; performing fine synchronization verification detection on the first frame signal based on the first frequency offset estimation and the target link gain to resolve and determine signal content of the first frame signal; wherein during the performing of the fine synchronization verification detection, frame signals are continuously received, when a second frame signal is detected, and in response to a difference between a second signal strength of the second frame signal and the first signal strength being greater than or equal to a first threshold, the fine synchronization verification detection on the first frame signal is aborted, and the fine synchronization verification detection is performed on the second frame signal based on the second signal strength and a second detection result of coarse synchronization detection on the second frame signal to resolve and determine signal content of the second frame signal.

2. The frame synchronization method of claim 1, wherein, the determining of the first frequency offset estimation of the first frame signal based on the first detection result of coarse synchronization detection on the first frame signal comprises: normalizing an amplitude of the first frame signal and performing phase compensation on the first frame signal based on a phase difference between the current link gain and an initial link gain to obtain an intermediate signal; detecting the intermediate signal based on a plurality of symbols in a target short training sequence and a period variation of the plurality of symbols to obtain the first detection result; in response to the first detection result representing that the first frame signal comprises the target short training sequence, determining the first frequency offset estimation of the first frame signal.

3. The frame synchronization method of claim 2, wherein, the detecting of the intermediate signal based on the plurality of symbols in the target short training sequence and the period variation of the plurality of symbols to obtain the first detection result comprises: extracting a to-be-tested sequence from the intermediate signal based on the period variation of the plurality of symbols, a target oversampling multiple, and a target period number; determining a symbol matching result by matching the to-be-tested sequence with the plurality of symbols; determining a symbol variation feature of the to-be-tested sequence based on the period variation of the plurality of symbols; determining the first detection result according to the symbol matching result and the symbol variation feature.

4. The frame synchronization method of claim 3, wherein, the determining of the first detection result according to the symbol matching result and the symbol variation feature comprises: in response to the symbol matching result representing that the to-be-tested sequence matches the plurality of symbols, and the symbol variation feature being identical to the period variation of the plurality of symbols, determining that the first frame signal comprises the target short training sequence; in response to the symbol matching result representing that the to-be-tested sequence does not match the plurality of symbols, and / or the symbol variation feature being different from the period variation of the plurality of symbols, determining that the first frame signal does not comprise the target short training sequence.

5. The frame synchronization method of claim 1, wherein, the performing of the fine synchronization verification detection on the first frame signal based on the first frequency offset estimation and the target link gain to resolve and determine the signal content of the first frame signal comprises: perform fine synchronization detection on the first frame signal based on the first frequency offset estimation and the target link gain, to obtain a third detection result; in response to the third detection result representing that the first frame signal comprises a target long training sequence, determine a second frequency offset estimation; based on the first frequency offset estimation and the second frequency offset estimation, demodulate a control frame header in the first frame signal, to obtain a demodulation result; based on the demodulation result, parse and determine signal content of the first frame signal.

6. The frame synchronization method of claim 5, wherein, the aborting the fine synchronization verification detection on the first frame signal comprises aborting the fine synchronization detection on the first frame signal, or aborting the demodulation of the control frame header in the first frame signal.

7. The frame synchronization method of claim 5 or 6, wherein, in the process of performing the fine synchronization verification detection, the method further comprises: in response to a difference between the second signal strength of the second frame signal and the first signal strength being less than the first threshold, determining a frequency offset estimation of the second frame signal based on the second detection result of the coarse synchronization detection on the second frame signal.

8. The frame synchronization method of claim 1, wherein, the determining the first signal strength of the first frame signal based on the received first frame signal comprises: determining the first signal strength of the first frame signal based on a reference received power corresponding to the current link gain and a target sample quantity.

9. The frame synchronization method of claim 1, wherein, the adjusting the current link gain based on the first signal strength, to determine the target link gain, comprises: determining a reference signal strength corresponding to the current link gain; adjusting the current link gain based on a comparison result between the first signal strength and the reference signal strength, to determine the target link gain.

10. The frame synchronization method of claim 9, wherein, the adjusting the current link gain based on the comparison result between the first signal strength and the reference signal strength, to determine the target link gain, comprises: in response to a difference between the first signal strength and the reference signal strength being greater than or equal to a second threshold, determining a link gain corresponding to the first signal strength based on a preset corresponding relationship between signal strength and link gain, and switching the current link gain to the link gain corresponding to the first signal strength as the target link gain; in response to the difference between the first signal strength and the reference signal strength being less than the second threshold, determining the current link gain as the target link gain.

11. A receiver, comprising: a first processing module configured to determine a first signal strength of a first frame signal based on the received first frame signal; adjust a current link gain based on the first signal strength, to determine a target link gain; and determine a first frequency offset estimation of the first frame signal based on a first detection result of coarse synchronization detection on the first frame signal; The second processing module is configured to perform fine synchronization verification detection on the first frame signal based on the first frequency offset estimation and the target link gain, to parse and determine the signal content of the first frame signal; wherein during the fine synchronization verification detection, frame signals are continuously received, when a second frame signal is detected, and in response to a difference between a second signal strength of the second frame signal and the first signal strength being greater than or equal to a first threshold value, the fine synchronization verification detection on the first frame signal is stopped, and the fine synchronization verification detection is performed on the second frame signal based on the second signal strength and a second detection result of coarse synchronization detection on the second frame signal, to parse and determine the signal content of the second frame signal. 12.An electronic device comprising: a memory and a processor, which are communicatively connected, and the memory stores computer instructions, and the processor performs the frame synchronization method of any one of claims 1-10 by executing the computer instructions. 13.A computer-readable storage medium storing a program for performing the frame synchronization method of any one of claims 1-10.

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