Hemt device integrating p-algan with graphene layer at the drain region and method of fabrication

Abstract

The application relates to a HEMT device integrating P-AlGaN and a graphene layer in a drain region and a manufacturing method, and belongs to the field of semiconductor power device manufacturing. The HEMT device comprises a substrate, a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer from bottom to top. A source metal is arranged above the left side of the AlGaN barrier layer. A graphene layer is arranged above the right side of the AlGaN barrier layer. A p-GaN cap layer is arranged between the source metal and the graphene layer above the AlGaN barrier layer. A gate metal is arranged above the p-GaN cap layer. A plurality of p-AlGaN islands are arranged in the graphene layer. A drain metal is arranged above the graphene layer. The application combines the PN junction regulation and the ohmic contact, and combines the graphene electrode to reduce the resistance, improve the heat dissipation and the like, optimizes the comprehensive performance of the device, effectively improves the breakdown voltage, reduces the on-resistance and suppresses the current collapse, and provides a new idea for the preparation of high-performance GaN power and radio frequency devices.

Description

Technical Field

[0001] This invention relates to a novel device structure and manufacturing method of gallium nitride (GaN) high electron mobility transistors (HEMTs), particularly a HEMT device and manufacturing method integrating P-AlGaN and graphene layers in the drain region, belonging to the field of semiconductor power device manufacturing technology. This technology can be widely applied in the field of high-power, high-voltage GaN power electronic devices, such as power electronic switches, radio frequency power amplifiers, and high-frequency converters. Background Technology

[0002] As the performance of Si-based materials gradually approaches its theoretical limits, GaN, representing third-generation semiconductor materials, is increasingly becoming the mainstream in semiconductor device development. GaN materials possess excellent electrical properties such as a high bandgap, high electron mobility, high saturation velocity, and high breakdown electric field, making them highly promising for use in harsh environments such as high frequency, high power, and high temperature. This has led to widespread attention and application of GaN devices in power electronics, microwave radio frequency, and 5G communications.

[0003] However, existing GaN enhancement-mode HEMT devices still face many technical bottlenecks in practical applications, including limited breakdown voltage, uneven electric field distribution leading to localized overheating, insufficient gate withstand voltage, excessive leakage current in the off-state, and "current collapse" under dynamic operation. To address these issues, industry and academia have proposed various improvement schemes. For example, introducing a gate field plate structure can improve the breakdown voltage to some extent, but the extended metal field plate increases junction capacitance, causing a decline in high-speed performance. Another approach is to use acceptor doping (such as a carbon-doped GaN buffer layer) in the epitaxial structure or introduce local p-type doped regions into the buffer layer, which can improve the device breakdown voltage by compensating for impurities and creating a uniform electric field. Simultaneously, appropriate p-type doping can release holes into the semi-insulating buffer layer after turn-off to neutralize trapped charges, reduce dynamic on-resistance degradation, and suppress the current collapse effect. However, the above methods often bring new challenges: for example, the overall incorporation of a p-type layer may increase process complexity and reduce channel carrier density, thus affecting the on-current; field plates or extended drift regions will increase the parasitic capacitance and on-resistance of the device, which is detrimental to high-speed switching. There is a lack of a solution in the existing technology that balances all aspects of performance.

[0004] Furthermore, traditional ohmic contacts typically employ metal systems such as Ti / Al / Ni / Au, using high-temperature annealing (600–850℃) to achieve metal diffusion and compound formation of GaN. However, this contact method has the following significant drawbacks:

[0005] 1. Interface degradation problem caused by high temperature annealing: Metals tend to diffuse into the AlGaN layer at high temperatures, which can damage the integrity of the barrier layer, leading to interface roughening and degradation of current-carrying channels.

[0006] 2. Contact resistance is difficult to reduce further: The lowest specific contact resistance of traditional metal systems is close to the material limit, making it difficult to meet the needs of higher power density devices.

[0007] 3. Local hot spot effect caused by high heat density: Under high current operating conditions, the drain region experiences significant current concentration and heat accumulation, which affects the reliability and long-term stability of the device.

[0008] 4. Poor metal / semiconductor interface stability: Long-term electrothermal stress can easily cause interdiffusion and electromigration between metals, reducing contact life. Summary of the Invention

[0009] To address the shortcomings of existing technologies, this invention provides a HEMT device and its fabrication method that integrates a P-AlGaN and graphene layer in the drain region. By combining PN junction modulation with ohmic contacts, and leveraging the reduced resistance and improved heat dissipation effects of graphene electrodes, the overall performance of the device is optimized. This technical solution effectively improves breakdown voltage, reduces on-resistance, and suppresses current collapse, providing a new solution for the fabrication of high-performance GaN power and RF devices.

[0010] The present invention adopts the following technical solution:

[0011] A HEMT device integrating a P-AlGaN and a graphene layer in the drain region includes, from bottom to top, a substrate, a GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer. A source metal is disposed above the left side of the AlGaN barrier layer, a graphene layer is disposed above the right side of the AlGaN barrier layer, a p-GaN cap layer is disposed above the AlGaN barrier layer between the source metal and the graphene layer, and a gate metal is disposed above the p-GaN cap layer.

[0012] The graphene layer contains several p-AlGaN islands, and a drain metal is disposed on top of the graphene layer.

[0013] Graphene is a two-dimensional material with high carrier mobility, high thermal conductivity, and good chemical stability. Its unique atomic-level thickness, excellent lateral conductivity, and diffusion barrier properties allow it to reduce interfacial contact resistance and effectively suppress downward diffusion of metal atoms when introduced between a metal and GaN layer. In the device of this invention, a discontinuous p-type AlGaN layer, i.e., a p-AlGaN island, is introduced below the drain metal and above the AlGaN barrier layer, achieving both PN junction control and ohmic contact. This optimizes the overall performance of the device, including improving switching speed, reducing on-resistance, increasing breakdown voltage, improving threshold stability, and suppressing current collapse. Furthermore, the introduction of the metal / graphene composite contact layer also reduces contact resistance, suppresses metal diffusion, and improves thermal stability.

[0014] Preferably, the thickness of the graphene layer is 20-200 nm.

[0015] Preferably, the thickness of the p-AlGaN island is 10-500 nm;

[0016] Each individual p-AlGaN island has a width of 1-200 nm;

[0017] The spacing between adjacent p-AlGaN islands is 1-400 nm.

[0018] In this invention, the p-AlGaN island below the drain and the graphene layer together form a composite structure of "longitudinal PN junction field control + transverse graphene current / thermal diffusion layer", and its electrical behavior is determined by the junction depletion width, carrier transport path and thermal diffusion capability.

[0019] When the graphene layer is too thin (<20nm), it is prone to problems such as island growth, discontinuity and increased density of grain boundary defects, and a large number of scattering centers and local barriers will be formed at the interface.

[0020] From an electrical perspective, local open circuits / high resistance regions can disrupt the "lateral current diffusion" and "metal diffusion blocking" effects of graphene, causing the drain current to concentrate in a few areas. The electric field and temperature are also re-concentrated locally, weakening the effect of the present invention in suppressing hot spots and improving breakdown voltage.

[0021] Furthermore, excessively thin graphene is more susceptible to damage from metals or plasma during high-temperature annealing and long-term operation, resulting in poor long-term interface stability.

[0022] When the graphene layer is too thick (>200nm), it forms a "bulk carbonization layer." Although its in-plane resistivity is small, the increased longitudinal equivalent thickness increases the equivalent series resistance of the metal-graphene-semiconductor system, raising the Ron of the conduction state. The internal stress and thermal expansion mismatch of the thick carbon material also increase significantly, making it prone to warping and microcracks, affecting the tight contact with the metal and p-AlGaN, and even posing a risk of delamination under high-temperature cycling.

[0023] When the thickness is too great, the shielding effect on the electric field below is enhanced, which weakens the mapping of the potential steps formed locally by the p-AlGaN islands in the graphene layer, thus weakening the synergistic effect of "PN junction control field + graphene mean field".

[0024] In this invention, the preferred thickness of the graphene layer is 48-52 nm. A graphene / multilayer graphene film of approximately 50 nm can easily form a continuous and dense conductive film using current CVD / PECVD processes, ensuring both low lateral resistance and sufficient thickness to block metal diffusion. At this thickness, the graphene layer is still thin enough to have a limited impact on the electric field distribution of the underlying p-AlGaN / AlGaN junction, thus maintaining the drain electric field gradient and depletion region distribution designed in this invention.

[0025] Meanwhile, multilayer graphene can still fully utilize its high in-plane thermal conductivity within this thickness range, rapidly diffusing the heat generated by the high field region near the p-AlGaN islands along the drain direction, which is beneficial to improving the thermal stability of the device.

[0026] Therefore, limiting the thickness of graphene to 48-52 nm can achieve a good balance between conductivity, diffusion barrier capability and thermal management performance.

[0027] In this invention, the thickness of the p-AlGaN island determines the longitudinal dimension of the depletion region and the amount of depletion charge in the PN junction, thus directly affecting the electric field distribution near the drain and the conduction series resistance. When the p-AlGaN island is too thin, the depletion region under reverse bias is difficult to fully establish, the amount of depletion layer charge is insufficient, and the clamping ability to high electric fields is weak. Since acceptors such as Mg are incompletely ionized in GaN / AlGaN, when the thickness is too thin, the number of effective acceptors is even smaller, the potential step of the PN junction becomes lower, and early punch-through or tunneling leakage is more likely to occur, making it difficult to increase the breakdown voltage.

[0028] In addition, in terms of process technology, p-AlGaN with a thickness of <10nm is extremely sensitive to thickness fluctuations. Even slight process deviations may result in some areas having almost no field control effect, leading to poor reliability.

[0029] Excessively thick p-AlGaN islands increase the junction capacitance of the PN junction, leading to longer charge / discharge times during turn-off / turn-on and potentially reducing switching speed. Thick p-AlGaN islands also create significant series resistance and potential steps in the on-state, significantly increasing the drain equivalent resistance and raising conduction losses. Since p-AlGaN is a highly doped p-type, excessive thickness introduces more defects and stress, negatively impacting interface reliability. Preferably, the p-AlGaN island thickness in this invention is 25-35 nm. In the on-state, a p-AlGaN island thickness of around 30 nm introduces only limited series resistance, achieving PN junction field control without significantly increasing the on-state voltage drop. This strikes a good balance between breakdown voltage increase and on-state Ron control. Furthermore, this thickness is easily and precisely controlled in MOCVD / MBE, and the impact of process fluctuations on electrical performance is manageable, making it suitable for mass production.

[0030] In this invention, the width of each individual island in the p-AlGaN islands determines the lateral projection size of a single PN junction, affecting the local electric field distribution and the degree of "current interception" in the current channel. If the island width is too narrow, its effective junction area is too small, and the depletion region's effect on regulating the overall electric field distribution is limited, failing to form a significant "stepped potential distribution" and resulting in weak field control capability. When the island width is too large, the depletion regions of adjacent islands are prone to complete connection at low voltages, equivalent to introducing a continuous p-type drift region, significantly compressing the lateral channel of the conduction current. This significantly increases the drain series resistance, raising the device's conduction loss. Simultaneously, since the electric field is mainly concentrated at the edge of the p-region, new high-field peaks are easily formed at the island edges, weakening the overall field-averaging effect. In this invention, the width of each individual island in the p-AlGaN islands is 50 nm, with a Mg doping concentration of approximately 1 × 10¹. 9 Under the condition of cm⁻³, the 50 nm wide p-AlGaN island depletion region can be close to or slightly overlap with the neighboring island depletion region at higher voltages, thereby achieving better electric field broadening and gradient transition, while still retaining enough neutral region for carriers to pass through in the low voltage conduction state, reducing the conduction state Ron.

[0031] The spacing between adjacent p-AlGaN islands controls the "gaps" between the depletion regions of adjacent PN junctions, and is a key parameter determining whether the electric field continuously widens or refocuses at the gaps. When the spacing is extremely small or even close to zero, adjacent p-AlGaN islands almost form a continuous p-region, equivalent to the traditional "continuous p-GaN / p-AlGaN drift layer" structure: although the field control direction is relatively uniform, almost the entire drain side passes through the p-region during conduction, causing a sharp increase in series resistance, and the structure degenerates into a "continuous PN drift region," making it difficult to reflect the "PN field control + ohmic channel coexistence" feature of this invention. When the spacing is too large, the depletion regions of adjacent p-AlGaN islands are difficult to approach each other within the operating voltage range, forming wide uncontrolled high-field gaps between the islands: the electric field will refocus in these gaps, becoming new breakdown initiation points and weakening the overall breakdown voltage improvement effect. At the same time, the surface / buffer traps in these regions are more likely to capture charge carriers under high voltage, further amplifying the current collapse effect. In this invention, the spacing between adjacent p-AlGaN islands is 95-105 nm. Considering the typical depletion width of GaN / AlGaN systems at voltages ranging from hundreds to thousands of volts, a spacing of approximately 100 nm allows the depletion regions of adjacent islands to be essentially connected under high voltage, while maintaining a certain degree of separation under low / medium voltage. In the off and high-voltage states, the interconnected depletion regions facilitate the formation of a "stepped, gradually varying electric field," increasing the breakdown voltage and reducing the surface high field. In the on state, a neutral region of approximately 100 nm width still exists for electron flow, ensuring a low series resistance. Combined with the 50 nm island width, this forms a periodic structure of approximately 150 nm "p-AlGaN island / gap," enabling the construction of multi-level electric field homogenization structures within the device scale, balancing field control and conduction.

[0032] A method for fabricating the above-mentioned HEMT device in which a P-AlGaN and graphene layer are integrated in the drain region includes:

[0033] S1, GaN buffer layer, GaN channel layer, AlGaN barrier layer, p-AlGaN layer and p-GaN cap layer are grown on the substrate;

[0034] S2, dry etching removes the p-AlGaN layer outside the drain metal and the p-GaN cap layer outside the gate metal;

[0035] S3, perform local dry etching on the remaining p-AlGaN layer to separate it into p-AlGaN islands;

[0036] S4, a graphene layer is grown on top of the p-AlGaN island;

[0037] S5, source metal is deposited above the left side of the AlGaN barrier layer, and drain metal is deposited above the graphene layer.

[0038] S6, annealing in the drain metal and source metal regions to form an ohmic contact;

[0039] S7, gate metal is deposited over the p-GaN cap layer.

[0040] Preferably, the doping concentration of the p-AlGaN islands is 1×10⁻⁶. 16 -1×10 20 cm -3 Preferably, the doping concentration of the p-AlGaN islands is 1×10⁻⁶. 19 cm -3 The doping source is magnesium or boron.

[0041] Preferably, the substrate is silicon carbide, silicon, or sapphire; the GaN buffer layer has a thickness of 0.1-50 μm, preferably 5.2 μm; the GaN channel layer has a thickness of 1-1000 nm, and the GaN channel layer has a thickness of 200 nm; the AlGaN barrier layer has a thickness of 5-50 nm, and the molar ratio of Al is 5-35%, more preferably 18 nm, and the molar ratio of Al is 20%.

[0042] Preferably, the thickness of the p-GaN cap layer is 1-1000 nm, and more preferably, the thickness of the p-GaN cap layer is 100 nm;

[0043] The doping concentration of the p-GaN cap layer is 1×10⁻⁶. 17 -1×10 20 cm -3 More preferably, the doping concentration of the p-GaN cap layer is 3 × 10⁻⁶. 19 cm -3 The doping source is magnesium or boron;

[0044] The device has a gate-source pitch of 4μm, a gate length of 4μm, a gate-drain pitch of 12μm, and a gate width of 100μm. The gate-source pitch is the distance from the left side of the p-GaN cap layer to the source metal, the gate length is the length from the left end to the right end of the p-GaN cap layer, the gate-drain pitch is the distance from the right side of the p-GaN cap layer to the drain metal, and the gate width is the width of the gate metal extending into the paper.

[0045] The source metal and drain metal are made of Ti / Al / Ni / Au, Ti / Al / Ti / Au, or Ti / Al / Mo / Au metal stacks. Preferably, the source metal and drain metal are made of Ti / Al / Ni / Au metal stacks; the gate metal is made of Ni / Au metal stacks.

[0046] Preferably, in step S1, the growth method of the GaN buffer layer, GaN channel layer, AlGaN barrier layer, p-AlGaN layer and p-GaN cap layer is metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0047] The graphene layer in step S4 is grown using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or a solid-phase carbon source method.

[0048] Preferably, the etching methods for steps S2 and S3 are inductively coupled plasma etching (ICP) or reactive ion etching (RIE).

[0049] The annealing method in step S6 is laser selective annealing.

[0050] The structure of this invention firstly establishes discontinuous p-type AlGaN segments below the drain metal and on the surface of the AlGaN barrier layer in the GaN HEMT device, forming a local PN junction structure; simultaneously, the drain metal is retained in direct contact with the AlGaN barrier layer in adjacent regions. These PN junctions can support a higher electric field and share the voltage near the drain, and stress is no longer concentrated in the gate and channel regions, thereby significantly improving the breakdown voltage of the device. At the same time, the depletion effect of the PN junctions reduces channel electron leakage and surface trapping effects, significantly suppressing current collapse and improving the stability of the threshold voltage. In the on-state of the device, thanks to the fact that a portion of the drain metal still directly contacts the AlGaN barrier layer, an ohmic contact path in the high-speed channel is maintained, allowing electrons to be injected unimpeded from the channel to the drain, ensuring that the on-resistance remains at a low level and that the device's conduction performance is not sacrificed due to the introduction of the PN junction structure. Thus, through the synergistic effect of PN junction modulation and the ohmic path, this invention achieves an optimized balance between high-voltage withstand capability and low-loss fast switching performance in GaN power devices.

[0051] Furthermore, this invention introduces a graphene film between the traditional Ti / Al and other metal contact systems and the AlGaN layer, forming a graphene / metal composite contact structure. Graphene, as an interlayer, possesses both high conductivity and good interfacial wettability, enabling efficient current transport without disrupting the AlGaN barrier. Simultaneously, graphene acts as a diffusion barrier layer, effectively suppressing the diffusion of metal elements into the GaN under annealing and long-term operating conditions. Moreover, graphene's extremely high in-plane thermal conductivity (>2000 W / m·K) allows it to rapidly dissipate heat in the drain region during high-power operation, mitigating localized hotspot effects and improving the device's thermal reliability and lifespan.

[0052] This invention achieves effective control of the drain electric field, effective optimization of heat concentration in the drain region, and low-loss transmission of conduction current without introducing additional complex processes, thereby significantly improving the device's withstand voltage and operational stability. In short, this invention provides a GaN HEMT structure that combines the advantages of PN junction field control, low resistance of ohmic contacts, and strong hotspot dissipation capabilities, significantly improving device performance to meet the demands of high-voltage and high-speed applications.

[0053] For any details not covered in this invention, please refer to the prior art.

[0054] The beneficial effects of this invention are as follows:

[0055] 1. Improved Breakdown Voltage: The p-AlGaN / AlGaN PN junction below the drain forms a space charge region when turned off, expanding and homogenizing the electric field distribution at the drain. Compared to traditional GaN HEMT structures, the device of this invention can withstand higher drain bias voltages without breakdown, significantly improving the breakdown voltage. This provides the device with a greater safety margin in high-voltage applications and allows it to meet more stringent operating voltage requirements.

[0056] 2. Improved Switching Speed: This invention effectively reduces drain parasitic capacitance and dynamic resistance by introducing discontinuous p-AlGaN islands and a graphene layer. During device switching, the presence of the PN junction reduces charge storage and RC delay, suppressing the impact of current collapse on the conduction state, enabling the device to complete switching transitions at a faster speed and improving switching efficiency at high frequencies.

[0057] 3. Reduced On-Resistance: Graphene's high carrier mobility and good conductivity enable efficient lateral electron transport within the graphene layer. Simultaneously, its work function can be adjusted through chemical doping or annealing to match the band structure of the metal and GaN, thereby reducing the barrier height and achieving lower ohmic contact resistance. Compared to structures using only PN junctions, the hybrid structure of this invention avoids a significant increase in forward conduction voltage, ensuring unimpeded flow of conduction current through the drain, thus reducing the total on-resistance. While achieving higher withstand voltage, it does not increase or even slightly reduces the device's conduction loss per unit area.

[0058] 4. Suppressing metal diffusion: The dense honeycomb lattice of the graphene layer can effectively prevent the downward diffusion of metal elements such as Ti and Al during the high-temperature annealing process, prevent the degradation of the AlGaN barrier layer, and maintain the integrity and stability of the interface.

[0059] 5. Compatibility with conventional processes and metal systems: Graphene layers can be introduced after epitaxy via wet or dry transfer methods without altering the main flow of existing GaN HEMT manufacturing processes. Only a transfer step is added before metal deposition, making the process highly feasible. Furthermore, graphene layers can form stable composite contact layers with various conventional metals (such as Ti / Al, Ni / Au, Mo / Au, etc.), exhibiting good material versatility and scalability.

[0060] 6. Improved Threshold Stability: The structure of this invention mitigates the impact of high drain voltage on the gate and channel. The electric field clamping effect of the PN junction reduces the electrical stress in the channel region under the gate, avoiding threshold voltage drift caused by hot carrier injection or trap charging. After repeated switching and long-term high-voltage bias, the device threshold voltage exhibits superior stability, contributing to improved circuit control accuracy and system reliability.

[0061] 7. Suppressing Current Collapse: This invention suppresses the trapping effect in the high-field region of the drain using a p-AlGaN PN junction. The depletion region of the PN junction reduces the probability of electrons being injected into surface and buffer layer traps at high potentials, thus reducing the impact of the charge stored in the traps during transient turn-off on the next turn-on, thereby significantly suppressing current collapse. During high-frequency switching operation, the drain-source current remains more stable, and the increase in dynamic on-resistance is effectively controlled.

[0062] 8. Reduced Leakage Current: Due to the blocking effect of the drain PN junction on charge carriers in the off state, the structure of this invention can significantly reduce the static leakage current of the drain. The potential barrier formed by the PN junction effectively blocks the leakage path from the drain to the channel and along the drain surface, allowing the device to maintain a very low leakage current even under high temperature and high pressure. This not only reduces no-load losses but also reduces the need for protective resistors or bleeder circuits in circuit design, improving the system's energy efficiency.

[0063] 9. Enhanced Thermal Stability and Reliability: Through the aforementioned electric field optimization and trap suppression effects, along with the extremely high in-plane thermal conductivity of graphene (>2000 W / m·K), the structure of this invention significantly reduces local hot spots and electrical stress generated during high-power operation, mitigating performance degradation caused by thermal stress. Long-term operating experiments show that this structure helps suppress the cumulative effects of material defects and interface states, reducing performance drift and device failure caused by electrothermal stress. The device exhibits better stability and durability under harsh conditions such as high temperature and high current, extending its lifespan and ensuring the reliability of GaN power devices during long-term continuous operation.

[0064] 10. Expanded application range: GaN HEMT devices with improved breakdown voltage and stability can be widely used in high-power fields such as radio frequency communication, radar systems, satellite communication, and power electronics. Attached Figure Description

[0065] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an undue limitation of this application.

[0066] Figure 1 This is a schematic diagram of the HEMT device structure in which P-AlGaN and graphene layers are integrated in the drain region according to the present invention.

[0067] Figure 2 This is a schematic diagram of a conventional device structure;

[0068] Figure 3 This is a comparison chart of the transfer curves of the device of the present invention and conventional devices;

[0069] Figure 4 This is a comparison chart of the breakdown curves of the device of the present invention and conventional devices;

[0070] In the figure, 1-substrate, 2-GaN buffer layer, 3-GaN channel layer, 4-AlGaN barrier layer, 5-p-AlGaN island, 6-p-GaN cap layer, 7-source metal, 8-graphene layer, 9-drain metal, 10-gate metal. Detailed Implementation

[0071] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. However, this is not the only description; all aspects not described in detail herein are based on conventional techniques in the art.

[0072] Example 1

[0073] A HEMT device integrating a P-AlGaN and a graphene layer in the drain region includes, from bottom to top, a substrate 1, a GaN buffer layer 2, a GaN channel layer 3, an AlGaN barrier layer 4, a source metal 7 disposed above the left side of the AlGaN barrier layer 4, a graphene layer 8 disposed above the right side of the AlGaN barrier layer 4, a p-GaN cap layer 6 disposed above the AlGaN barrier layer 4 between the source metal 7 and the graphene layer 8, and a gate metal 10 disposed above the p-GaN cap layer 6.

[0074] Several p-AlGaN islands 5 are arranged inside the graphene layer 8, and a drain metal 9 is arranged above the graphene layer 8.

[0075] Graphene is a two-dimensional material with high carrier mobility, high thermal conductivity, and good chemical stability. Its unique atomic-level thickness, excellent lateral conductivity, and diffusion barrier properties allow it to reduce interfacial contact resistance and effectively suppress downward diffusion of metal atoms when introduced between a metal and GaN layer. In the device of this invention, a discontinuous p-type AlGaN layer, i.e., a p-AlGaN island, is introduced below the drain metal and above the AlGaN barrier layer, achieving both PN junction control and ohmic contact. This optimizes the overall performance of the device, including improving switching speed, reducing on-resistance, increasing breakdown voltage, improving threshold stability, and suppressing current collapse. Furthermore, the introduction of the metal / graphene composite contact layer also reduces contact resistance, suppresses metal diffusion, and improves thermal stability.

[0076] Example 2

[0077] A method for fabricating a HEMT device that integrates a P-AlGaN and a graphene layer in the drain region, as described in Example 2, except that the thickness of the graphene layer is 50 nm.

[0078] The thickness of the p-AlGaN island 5 is 30 nm; the width of each individual p-AlGaN island 5 is 50 nm; and the spacing between adjacent p-AlGaN islands is 100 nm.

[0079] The doping concentration of the p-AlGaN islands is 1×10⁻⁶. 19 cm -3 The doping source is magnesium.

[0080] In this embodiment, the graphene layer is 50 nm thick. This thickness facilitates the formation of a continuous and dense conductive film using current CVD / PECVD processes, ensuring both low lateral resistance and sufficient thickness to block metal diffusion. At this thickness, the graphene layer has limited impact on the electric field distribution of the underlying p-AlGaN / AlGaN junction, maintaining the drain electric field gradient and depletion region distribution designed in this invention. Simultaneously, the 50 nm thickness of the multilayer graphene still fully utilizes its high in-plane thermal conductivity, rapidly diffusing heat generated by the high-field region near the p-AlGaN islands along the drain direction, thus improving device thermal stability. Therefore, a 50 nm graphene thickness achieves a good balance between conductivity, diffusion blocking capability, and thermal management performance.

[0081] In this embodiment, the p-AlGaN island thickness is 30 nm. In the on-state, the approximately 30 nm p-AlGaN island thickness introduces only a limited series resistance, achieving PN junction field control without significantly increasing the on-state voltage drop. This strikes a good balance between breakdown voltage increase and on-state Ron control. Furthermore, this thickness is easily and precisely controlled in MOCVD / MBE, and the impact of process fluctuations on electrical performance is controllable, making it suitable for actual mass production. The approximately 30 nm p-AlGaN island thickness matches the 18 nm AlGaN barrier layer, and its depletion width is sufficient to penetrate the entire p-AlGaN island, forming a stable space charge region near the drain and effectively distributing the peak electric field between the gate and drain.

[0082] Each independent p-AlGaN island 5 has a width of 50 nm. The 50 nm wide p-AlGaN island depletion region can be close to or slightly overlap with the depletion region of the neighboring island at higher voltages, thereby achieving better electric field broadening and gradient transition. At low voltage conduction state, it still retains enough neutral region for carriers to pass through, reducing the conduction state Ron.

[0083] The spacing between adjacent p-AlGaN islands is 100 nm. This 100 nm spacing allows the depletion regions of adjacent islands to be essentially connected under high voltage, while maintaining a certain degree of separation under low / medium voltage. In the off and high-voltage states, the depletion regions are interconnected, which is beneficial for forming a "stepped, gradually varying electric field," increasing the breakdown voltage and reducing the surface high field. In the on state, there is still a neutral region with a width of about 100 nm for electron flow, ensuring a low series resistance. Combined with the 50 nm island width, a periodic structure of "p-AlGaN islands / gap" with a period of about 150 nm is formed, which can construct a multi-level electric field homogenization structure within the device scale, balancing field control and conduction.

[0084] Example 3

[0085] A method for fabricating a HEMT device integrating a P-AlGaN and a graphene layer in the drain region, according to Embodiment 2, includes:

[0086] S1, GaN buffer layer 2, GaN channel layer 3, AlGaN barrier layer 4, p-AlGaN layer and p-GaN cap layer 6 are grown on substrate 1;

[0087] S2, dry etching away the p-AlGaN layer outside the drain metal and the p-GaN cap layer 6 outside the gate metal 10;

[0088] S3, perform local dry etching on the remaining p-AlGaN layer to separate it into p-AlGaN islands 5;

[0089] S4, a graphene layer 8 is grown on top of the p-AlGaN island 5;

[0090] S5, source metal 7 is deposited above the left side of AlGaN barrier layer 4, and drain metal 9 is deposited above graphene layer 8.

[0091] S6, annealing is performed in the drain metal 9 and source metal 7 region to form an ohmic contact;

[0092] S7, gate metal 10 is deposited on top of p-GaN cap layer 6.

[0093] Example 4

[0094] A method for fabricating a HEMT device integrating a P-AlGaN and graphene layer in the drain region, as described in Example 3, except that the substrate is silicon carbide; the GaN buffer layer has a thickness of 5.2 μm; the GaN channel layer has a thickness of 200 nm; the AlGaN barrier layer 4 has a thickness of 18 nm; and the molar ratio of Al is 20%.

[0095] The thickness of the p-GaN cap layer 6 is 100 nm;

[0096] The doping concentration of the p-GaN cap layer is 3×10⁻⁶. 19 cm -3 The doping source is boron;

[0097] The device has a gate-source pitch of 4μm, a gate length of 4μm, a gate-drain pitch of 12μm, and a gate width of 100μm.

[0098] The source and drain metals are made of Ti / Al / Ni / Au metal stacks; the gate metal is made of Ni / Au metal stacks.

[0099] Example 5

[0100] A method for fabricating a HEMT device integrating a P-AlGaN and graphene layer in the drain region, as described in Example 4, except that in step S1, the GaN buffer layer, GaN channel layer, AlGaN barrier layer, p-AlGaN layer and p-GaN cap layer are grown by metal-organic chemical vapor deposition (MOCVD).

[0101] The graphene layer in step S4 is grown using plasma-enhanced chemical vapor deposition (PECVD).

[0102] The etching method for steps S2 and S3 is inductively coupled plasma etching (ICP).

[0103] The annealing method in step S6 is laser selective annealing.

[0104] The performance improvement of this structure was verified in Sentaurus TCAD simulation. Specifically, this invention sets discontinuous p-type AlGaN segments (i.e., p-AlGaN islands) on the surface of the AlGaN barrier layer below the drain metal, and sets up a graphene / metal composite contact structure. It was found that this structure can significantly improve the breakdown voltage without affecting the threshold voltage.

[0105] (1) Simulation model construction: A two-dimensional structural model of GaN HEMT was constructed in Sentaurus TCAD software.

[0106] (2) Simulation parameter settings: Set appropriate boundary conditions and initial conditions, including voltage and current. For the transfer curve, first apply a drain voltage of 10V, and then apply a varying gate voltage. For breakdown, first apply a gate voltage of -6V to ensure depletion, and then apply a drain voltage until breakdown.

[0107] (3) Simulation process: Perform simulation and observe the changes in electrical properties of this device compared with conventional GaN HEMT.

[0108] (4) Result Analysis: Based on the constant current method with 10⁻² mA / mm as the judgment standard, ... Figure 3 It can be seen that the threshold voltage of the device remains unchanged at 1.8V. Figure 4 In the breakdown curves, with a drain current of 1 mA / mm as the standard, the breakdown voltage of the drain-integrated AlGaN device reached 1461 V, which is better than the 1249 V of conventional devices, and the off-state leakage current level was reduced by four orders of magnitude. This indicates that the enhanced gallium nitride device architecture based on drain-region integrated AlGaN and graphene structures can significantly improve the overall performance and reliability of the device.

[0109] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A HEMT device integrating a P-AlGaN and a graphene layer in the drain region, characterized in that, From bottom to top, the structure includes a substrate, a GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer. A source metal is disposed on the upper left side of the AlGaN barrier layer, a graphene layer is disposed on the upper right side of the AlGaN barrier layer, a p-GaN cap layer is disposed above the AlGaN barrier layer between the source metal and the graphene layer, and a gate metal is disposed above the p-GaN cap layer. The graphene layer contains several p-AlGaN islands, and a drain metal is disposed above the graphene layer. The graphene layer has a thickness of 48-52 nm, and the p-AlGaN islands have a thickness of 25-35 nm; the width of each individual p-AlGaN island is 50 nm; and the spacing between adjacent p-AlGaN islands is 95-105 nm.

2. A method for manufacturing a HEMT device with a P-AlGaN and graphene layer integrated in the drain region as described in claim 1, characterized in that, include: S1, a GaN buffer layer, a GaN channel layer, an AlGaN barrier layer, a p-AlGaN layer, and a p-GaN cap layer are grown on the substrate; S2, dry etching removes the p-AlGaN layer outside the drain metal and the p-GaN cap layer outside the gate metal; S3, perform local dry etching on the remaining p-AlGaN layer to separate it into p-AlGaN islands; S4, a graphene layer is grown on top of the p-AlGaN island; S5, source metal is deposited above the left side of the AlGaN barrier layer, and drain metal is deposited above the graphene layer. S6, annealing in the drain metal and source metal regions to form an ohmic contact; S7, gate metal is deposited over the p-GaN cap layer.

3. The method for manufacturing a HEMT device integrating a P-AlGaN and graphene layer in the drain region according to claim 2, characterized in that, The doping concentration of the p-AlGaN island is 1×10⁻⁶. 16 -1×10 20 cm -3 The doping source is magnesium.

4. The method for manufacturing a HEMT device integrating a P-AlGaN and graphene layer in the drain region according to claim 3, characterized in that, The substrate is silicon carbide, silicon, or sapphire; the GaN buffer layer has a thickness of 0.1-50 μm; the GaN channel layer has a thickness of 1-1000 nm; the AlGaN barrier layer has a thickness of 5-50 nm, and the molar ratio of Al is 5-35%.

5. The method for manufacturing a HEMT device integrating a P-AlGaN and graphene layer in the drain region according to claim 4, characterized in that, The thickness of the p-GaN cap layer is 1-1000 nm; The doping concentration of the p-GaN cap layer is 1×10⁻⁶. 17 -1×10 20 cm -3 The doping source is magnesium; The device has a gate-source pitch of 4μm, a gate length of 4μm, a gate-drain pitch of 12μm, and a gate width of 100μm. The source metal and drain metal are made of Ti / Al / Ni / Au, Ti / Al / Ti / Au, or Ti / Al / Mo / Au metal stacks; the gate metal is made of Ni / Au metal stacks.

6. The method for manufacturing a HEMT device integrating a P-AlGaN and graphene layer in the drain region according to claim 5, characterized in that, In step S1, the GaN buffer layer, GaN channel layer, AlGaN barrier layer, p-AlGaN layer and p-GaN cap layer are grown by metal-organic chemical vapor deposition or molecular beam epitaxy. The graphene layer in step S4 is grown by chemical vapor deposition or solid-phase carbon source method.

7. The method for manufacturing a HEMT device integrating a P-AlGaN and graphene layer in the drain region according to claim 6, characterized in that, The etching methods for steps S2 and S3 are inductively coupled plasma etching or reactive ion etching; The annealing method in step S6 is laser selective annealing.

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