A vertical cavity surface emitting laser and a method of manufacturing the same

Abstract

The application relates to the technical field of lasers, and provides a vertical cavity surface emitting laser and a preparation method thereof.The method is characterized in that a first dielectric layer is deposited on a substrate surface, and an alignment mark, a contact window, a mesa and a scribe lane structure of the VCSEL laser are constructed through a first photoetching process; secondly, a gold barrier layer is constructed through a second photoetching process, the mesa and a scribe lane are etched based on a wet etching process to open a gallium arsenide substrate deep groove, and an epitaxy is subjected to oxidation treatment; finally, the top of the mesa and a wire bonding area are opened through a third photoetching, the contact window and the wire bonding area are connected through metal sputtering, and the P-face electrode interconnection of the vertical cavity surface emitting laser is realized.The application greatly shortens the VCSEL preparation process, reduces the alignment deviation introduced by the multiple photoetching, improves the photoetching overlay precision and the product yield.

Description

Technical Field

[0001] This application relates to the field of laser technology, and in particular to a vertical cavity surface-emitting laser and its fabrication method. Background Technology

[0002] As a core optoelectronic device, the fabrication of a VCSEL (Vertical-Cavity Surface-Emitting Laser) typically requires multiple photolithography steps (usually 5-6 steps) to sequentially create various micro / nano structures, including alignment marks, mesas, vias, p-side metal (PMT), scribe lines (STR), and pad windows (PWD). In existing technologies, silicon nitride is first deposited on the wafer to create the Mark pattern. Mesa patterns are then constructed using overlay etching to confine the light-emitting area after oxidizing the OA pattern. After oxidation, silicon nitride is deposited again for protection. Via patterns are then lithographically etched down to the gallium arsenide layer for p-side current injection. The pMT pattern is lithographically lithographically etched and the p-side metal is deposited, allowing current to pass through after stripping. Finally, STR and PWD patterns are fabricated using lithography and PWD, respectively, to bisect the chip and open the pad window for easy wire bonding. In existing technologies, the overlay accuracy of multi-step lithography and the alignment accuracy of the lithography machine are strongly correlated with the operator's operating skills, resulting in poor alignment accuracy.

[0003] Furthermore, as the manufacturing process progresses, VCSEL wafers often experience significant warpage due to factors such as epitaxial stress release and stress introduced by thin film deposition. This warpage prevents the lithography equipment from accurately matching the optical alignment marks of the previous layer in subsequent photolithography steps. Local alignment deviations accumulate and are amplified, severely affecting the alignment accuracy of the lithography and making it impossible to guarantee the center position of the light output port. Ultimately, this leads to a series of problems such as reduced device output power, decreased uniformity, and reduced reliability. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor laser and a method for fabricating its P-side electrode, so as to improve the technical problems mentioned in the background section.

[0005] For the purposes mentioned above, this application provides the following technical solution:

[0006] The first aspect of this application provides a method for fabricating a vertical-cavity surface-emitting laser, comprising:

[0007] A first dielectric layer is deposited on the substrate surface, and multiple patterned structures, including alignment marks, contact windows, mesa and scribe lines, are etched on the surface of the first dielectric layer based on a first photolithography process. The position of the light-emitting aperture is then determined based on the position of the mesa. The contact window, the mesa and the light-emitting aperture are concentrically arranged.

[0008] A first metal layer is formed on the surface of the first dielectric layer based on a second photolithography process. The first metal layer covers the area of ​​the first dielectric layer except for the light-emitting aperture, the mesa, and the dicing track.

[0009] The substrate at the location of the platform and the dicing channel is etched to obtain a first oxide tank and a second oxide tank. The first oxide tank and the second oxide tank are oxidized respectively to deposit a second dielectric layer. The second dielectric layer covers the first metal layer, the first oxide tank, the second oxide tank and the light-emitting hole respectively.

[0010] The second dielectric layer in the preset areas on both sides of the table and the second dielectric layer covering the wire bonding area are removed by the third photolithography process, and the second metal layer is covered in the preset areas on the bottom and both sides of the table and the wire bonding area respectively.

[0011] Furthermore, the method also includes:

[0012] After depositing a first dielectric layer on the substrate surface, a metasurface pattern is etched on the surface of the first dielectric layer.

[0013] After obtaining the first oxide tank and the second oxide tank, the first dielectric layer at the location of the metasurface pattern is etched by dry etching. The etched first dielectric layer is a hard mask with the metasurface pattern.

[0014] The metasurface pattern on the hard mask is transferred to the substrate using a first wet etching process.

[0015] Furthermore, after transferring the metasurface pattern on the hard mask to the substrate, the hard mask on the metasurface pattern is removed again by dry etching to obtain the metasurface pattern formed on the substrate.

[0016] Furthermore, in the dry etching process, trifluoromethane and oxygen with a volume fraction ratio of 10:1 are used as etching gases; in the first wet etching process, a first combined solution composed of phosphoric acid, hydrogen peroxide and water with a volume fraction ratio of 1:6:50 to 1:6:100 is used for etching.

[0017] Furthermore, the etching of multiple patterned structures on the surface of the first dielectric layer based on the first photolithography process includes:

[0018] Based on positive photoresist, a patterned region of the patterned structure is defined on the surface of the first dielectric layer. Using the positive photoresist as a mask, trifluoromethane is used as a reactive gas for dry etching to transfer the patterned region to the first dielectric layer, thereby obtaining multiple patterned structures. The patterned region is used to determine the position of the multiple patterned structures.

[0019] Further, the formation of the first metal layer on the surface of the first dielectric layer based on the second photolithography process includes:

[0020] Through the second photolithography process, photoresist patterns are coated on the light-emitting holes, the mesa and the dicing area on the surface of the first dielectric layer, respectively, and the sidewall morphology of the photoresist patterns is an inverted trapezoid.

[0021] A first metal layer is obtained by vapor deposition over the first dielectric layer and the photoresist pattern, and the photoresist pattern and the metal above it are stripped off.

[0022] Furthermore, the vertical cavity surface-emitting laser is wet-immersed based on the second wet etching process to selectively etch the substrate at the mesa and the dicing position to obtain the first oxide tank and the second oxide tank; in the second wet etching process, a second combined solution of phosphoric acid, hydrogen peroxide and alkaline solution with a volume fraction ratio of 1:6:10 to 1:6:20 is used for etching.

[0023] Furthermore, the material of the first metal layer is gold, and / or the second metal layer is deposited by metal sputtering, and the second metal layer is a composite metal layer with titanium as the upper layer and gold as the lower layer.

[0024] The second aspect of this application provides a vertical-cavity surface-emitting laser, which is fabricated using the fabrication method of the vertical-cavity surface-emitting laser described in the first aspect of this application.

[0025] Furthermore, the vertical-cavity surface-emitting laser includes a substrate and a stacked structure disposed on the substrate, wherein:

[0026] The stacked structure includes a first dielectric layer, a first metal layer, a second dielectric layer and a second metal layer stacked sequentially upward from the substrate, wherein the first metal layer and the second metal layer are electrically connected.

[0027] The stacked structure forms a graphic structure, a light-emitting aperture, and a wire bonding area, respectively.

[0028] The graphic structure includes an alignment mark, a contact window, a platform, and a scribe line. The contact window and the platform are both aligned with the center of the light-emitting aperture. The platform is located on the side of the contact window away from the light-emitting aperture. The alignment mark is located on the side of the platform away from the contact window, and the scribe line is located on the other side of the platform away from the contact window.

[0029] The wire bonding area is located on the side of the platform away from the light emission hole, and the wire bonding area is covered with the second metal layer.

[0030] The method for fabricating a vertical-cavity surface-emitting laser described above in this application achieves at least the following technical effects:

[0031] The method for fabricating a vertical-cavity surface-emitting laser (VCSEL) provided in this application involves etching alignment marks, contact windows, mesa, and scribe lines on the surface of a first dielectric layer using a first photolithography process. The position of the emission aperture is then determined based on the position of the mesa, achieving concentric etching of the contact window, mesa, and emission aperture. Simultaneously, a second and third photolithography process is used to form the functional device structure of the VCSEL. Only three photolithography steps are required to achieve precise alignment and concentric distribution of key semiconductor laser patterns. This simplifies the process flow, facilitates machine operation, and significantly improves process efficiency while enhancing photolithography overlay accuracy and product yield. It also reduces alignment deviations and manufacturing costs. In cases of poor machine alignment accuracy, this method reduces the device power reduction problem caused by large local alignment deviations due to multiple independent photolithography steps in existing technologies, ensuring the emission aperture is centered on the mesa. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0033] Figure 1 A schematic diagram of the VCSEL structure is provided in the background section of this application;

[0034] Figure 2 This is a schematic flowchart of a method for fabricating a vertical cavity surface-emitting laser, provided in the embodiments of this application.

[0035] Figure 3 This is a schematic diagram of the metasurface pattern structure provided in the embodiments of this application.

[0036] Reference numerals in the figures: 1. Substrate; 2. First dielectric layer; 3. First metal layer; 4. Second dielectric layer; 5. Second metal layer; 11. Contact window; 12. Mesh surface; 13. Dicing track; 14. Light exit hole; 15. Alignment mark; 6. First oxide trench; 7. Second oxide trench; 8. Wire bonding area; 9. Grating pattern. Detailed Implementation

[0037] The technical solutions of this application will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] This application provides a method for fabricating a vertical-cavity surface-emitting laser (VCSEL) to prepare the P-side electrode of the VCSEL. Only three photolithography steps are required to achieve precise alignment and concentric distribution of key semiconductor laser patterns. This simplifies the process flow, significantly improves process efficiency, enhances photolithography overlay accuracy and product yield, and also reduces costs. Specifically, as... Figure 1 and Figure 2 As shown, the method includes:

[0039] S1. A first dielectric layer 2 is deposited on the surface of substrate 1. Multiple patterned structures are etched on the surface of the first dielectric layer 2 based on a first photolithography process, including alignment marks 15, contact windows 11, mesa 12 and scribe lines 13. The position of the light-emitting aperture 14 is determined based on the position of the mesa 12. The contact window 11, the mesa 12 and the light-emitting aperture 14 are concentrically arranged.

[0040] S2. A first metal layer 3 is formed on the surface of the first dielectric layer 2 based on the second photolithography process. The first metal layer 3 covers the area of ​​the first dielectric layer 2 except for the light-emitting hole 14, the mesa 12, and the dicing track 13.

[0041] S3. The portion of the substrate 1 at the position of the platform 12 and the dicing channel 13 is etched downward to obtain the first oxide tank 6 and the second oxide tank 7. The first oxide tank 6 and the second oxide tank 7 are oxidized respectively to deposit the second dielectric layer 4. The second dielectric layer 4 covers the first metal layer 3, the first oxide tank 6, the second oxide tank 7 and the light-emitting hole 14 respectively.

[0042] S4. The second dielectric layer 4 in the preset areas on both sides of the platform 12 and the second dielectric layer 4 covering the wire bonding area 8 are removed based on the third photolithography process, and the second metal layer 5 is covered in the preset areas on the bottom and both sides of the platform 12 and the wire bonding area 8 respectively.

[0043] Preferably, in step S1, the first dielectric layer 2 is deposited based on plasma-enhanced chemical vapor deposition.

[0044] Specifically, in step S1, the entire wafer is placed into the PECVD machine and a first dielectric layer 2 is deposited. The first dielectric layer 2 is used to protect the surface of the epitaxial substrate 1.

[0045] Based on the first photolithography process, positive photoresist is first used to define each patterned structure on the surface of the first dielectric layer 2, including the patterned areas of alignment mark 15, contact window 11, mesa 12 and scribe line 13, and the remaining parts are protected with photoresist; using the positive photoresist as a mask, the patterned areas of the first dielectric layer 2 of each patterned structure are etched away to obtain each patterned structure.

[0046] The center position of the light-emitting aperture 14 is determined based on the mesa 12, and the area of ​​the light-emitting aperture 14 is determined by the mesa 12 and the oxidation depth in subsequent oxidation operations. In each pattern structure, the contact window 11, the mesa 12, and the light-emitting aperture 14 are concentrically arranged. This embodiment forms the concentrically arranged pattern structures of the VCSEL in a single photolithography step, avoiding alignment deviations between multiple photolithography steps, achieving zero alignment tolerance, and realizing a completely concentric structure of the contact window 11, the mesa 12, and the light-emitting aperture 14. A schematic diagram of each functional area of ​​the VCSEL is shown below. Figure 1 As shown.

[0047] Preferably, CHF3 (trifluoromethane) is used as the reaction gas, and the first dielectric layer 2 covering each patterned structure region is removed using a RIE (reactive ion etching) process. Figure 2 (a) Process steps. Since only one photolithography step is used to construct each pattern structure region, the alignment deviation between multiple photolithography steps can be completely avoided, achieving zero alignment tolerance. The complete concentricity of the photolithographic design of the vertical cavity surface-emitting laser is achieved through the above process.

[0048] Preferably, in step S2, the first metal layer 3 is made of gold (Au).

[0049] Specifically, in step S2, the first metal layer 3 is constructed using a second photolithography process. In the second photolithography process, the first metal layer 3, i.e., the gold barrier layer, is obtained by photolithography using a positive photoresist and subsequent vapor deposition. Figure 2 (b) Process steps.

[0050] Preferably, the areas of the light-emitting aperture 14, mesa 12, and dicing channel 13 are protected with photoresist having inverted trapezoidal sidewalls, while the remaining areas are fully exposed. After the first metal layer 3 is obtained by vapor deposition, the photoresist is stripped off using an organic solvent, and the photoresist covering the areas of the light-emitting aperture 14, mesa 12, and dicing channel 13, along with the metal above it, is stripped off. Thus, except for the areas of the light-emitting aperture 14, mesa 12, and dicing channel 13, the remaining areas of the first dielectric layer 2 are covered with metal, forming the first metal layer 3.

[0051] Preferably, in step S2, the first metal layer 3 is deposited using an electron beam evaporation process.

[0052] Preferably, in step S3, a second combined solution of phosphoric acid, hydrogen peroxide, and water (or an alkaline solution such as ammonia) with a volume fraction ratio of 1:6:10 to 1:6:20 is used to immerse and etch the entire wafer. Because the second combined solution is selective in its etching, it only etches the gallium arsenide substrate 1, while having no corrosive effect on the areas covered by the first metal layer 3 and the first dielectric layer 2. Therefore, portions of the gallium arsenide substrate 1 in the mesa 12 and dicing channel 13 areas are respectively etched by the second combined solution, correspondingly forming the first oxide tank 6 and the second oxide tank 7, i.e. Figure 2 In step (c) of the process, the first oxide tank 6 is the mesa 12 formed after oxidation, and the second oxide tank 7 is the dicing channel 13 formed after oxidation. By combining photolithography and selective etching, the number of photolithography steps required in the process is greatly reduced, thus reducing alignment errors.

[0053] Preferably, in step S3, the wafer after the formation of the first oxide tank 6 and the second oxide tank 7 is placed in a tube furnace, water vapor and oxygen are introduced, and the temperature is raised to 400°C to oxidize the first oxide tank 6 and the second oxide tank 7, thereby restricting the light exit aperture 14 of the device. After oxidation, the wafer is placed in PECVD and a second dielectric layer 4 is deposited, covering the exposed first oxide tank 6 and the second oxide tank 7 with the second dielectric layer 4, i.e. Figure 2 (d) Process steps. The second dielectric layer 4 covers the surface of the first metal layer 3, the light-emitting hole 14, the first oxide tank 6, and the second oxide tank 7, respectively.

[0054] Preferably, in step S4, the second metal layer 5 is deposited by metal sputtering, and the sputtered metal material is a composite metal layer with titanium as the upper layer and gold as the lower layer.

[0055] Specifically, in step S4, based on the third photolithography process, photoresist is used to protect the front side of the wafer. Through exposure and development, the two sides of the mesa 12 (i.e., the portions of the second dielectric layer 4 connected to the left and right sidewalls of the mesa 12 in the horizontal direction) and the wire bonding area 8 are opened, and the remaining portion is covered with photoresist as a mask.

[0056] The silicon nitride on both sides of the mesa 12 and the wire bonding area 8 is removed again by RIE (reactive ion etching), exposing the first metal layer 3 on both sides of the mesa 12 and the wire bonding area 8. A second metal layer 5 is then sputtered onto the wafer surface, and the photoresist and the second metal layer 5 above it are stripped away, so that the final second metal layer 5 only covers the bottom of the mesa 12, the sidewalls, and the portion of the first metal layer 3 that connects horizontally to the left and right sidewalls of the mesa 12, and the wire bonding area 8. Figure 2 In step (e) of the process, since the second metal layer 5 overlaps with the first metal layer 3, electrical connections are achieved between the two sides of the mesa 12, the contact window 11, and the wire bonding area 8, thus constructing a current propagation and injection path from the outer wire bonding area to the central active region. Electrical injection can be performed on the P-side by bonding wires in the wire bonding area 8, thus completing the P-side process of the vertical cavity surface mount laser.

[0057] Preferably, in steps S1 to S4, the first dielectric layer 2 and the second dielectric layer 4 are both silicon nitride (SiNx) materials.

[0058] Furthermore, as an optional implementation, steps S1 to S4 also include:

[0059] S11. After depositing the first dielectric layer 2 on the substrate surface, a metasurface pattern is formed by etching on the surface of the first dielectric layer 2.

[0060] S12. After obtaining the first oxide tank 6 and the second oxide tank 7, the first dielectric layer 2 at the position of the metasurface pattern is etched by dry etching. The etched first dielectric layer 2 is a hard mask with the metasurface pattern.

[0061] S13. The metasurface pattern on the hard mask is transferred to the substrate 1 by a first wet etching process.

[0062] Further, in step S13, after transferring the metasurface pattern on the hard mask to the substrate 1, the hard mask on the metasurface pattern is removed again by the dry etching process to obtain the metasurface pattern formed on the substrate 1.

[0063] Specifically, a metasurface pattern is etched on the first dielectric layer 2 using EBL (electron beam lithography) to create a periodic pattern on the surface of the first dielectric layer 2. The SiNx film thickness is smaller at the locations of the metasurface pattern, while the film thickness is larger in other areas, creating a contrast difference. The metasurface pattern includes gratings, lenses, or periodic patterns formed by wavefront processing, such as... Figure 3 The diagram shows a schematic of the grating pattern 9 fabricated on the wafer.

[0064] Preferably, in step S12, trifluoromethane and oxygen with a volume fraction ratio of 10:1 are used as dry etching gas; in step S13, a first combined solution of phosphoric acid, hydrogen peroxide and water with a volume fraction ratio of 1:6:50 to 1:6:100 is used for wet etching.

[0065] This embodiment also provides a vertical-cavity surface-emitting laser (VCSEL), the structure of which is fabricated based on the fabrication method of a VCSEL described above in this embodiment. Since the principle by which a VCSEL solves the problem is similar to the fabrication method of a VCSEL, the implementation of a VCSEL can refer to the implementation of the fabrication method of a VCSEL, and repeated details will not be elaborated further.

[0066] Furthermore, according to Figure 2 As shown, the vertical cavity surface-emitting laser includes a substrate 1 and a stacked structure disposed on the substrate, wherein:

[0067] The stacked structure includes a first dielectric layer 2, a first metal layer 3, a second dielectric layer 4 and a second metal layer 5 stacked sequentially upwards from the substrate 1, wherein the first metal layer 3 and the second metal layer 5 are electrically connected.

[0068] The stacked structure forms a graphic structure, a light-emitting aperture 14, and a marking area 8, respectively. The graphic structure includes an alignment mark 15, a contact window 11, a platform 12, and a scribe line 13. The contact window 11 and the platform 12 are both aligned with the center of the light-emitting aperture 14. The platform 12 is located on the side of the contact window 11 away from the light-emitting aperture 14. The alignment mark 15 is located on the side of the platform 12 away from the contact window 11, and the scribe line 13 is located on the other side of the platform 12 away from the contact window 11.

[0069] The wire bonding area 8 is located on the side of the platform 12 away from the light emission hole 14, and the second metal layer 5 is covered above the wire bonding area 8; the wire bonding area 8 is used to determine the wire bonding position.

[0070] Specifically, the second dielectric layer 4 covers the area above the first metal layer 3, the area above the light-emitting aperture 14, the area above the first oxide trench 6, and the area above the second oxide trench 7, respectively; the second metal layer 5 covers the area above the bottom and sidewalls of the mesa 12, the area above the portion of the first metal layer 3 connected to the left and right sidewalls of the mesa 12 in the horizontal direction, and the area above the wire bonding region 8, respectively. The vertical cavity surface-emitting laser provided in this embodiment forms a metal interconnect structure through a stacked structure, constructing a current extension and injection path from the outer wire bonding region to the central active region on the device surface, thereby realizing a reliable and efficient electrical interconnect between the active region of the device and the external circuit, improving the device performance of the vertical cavity surface-emitting laser.

[0071] The embodiments of the present invention achieve the following technical effects:

[0072] 1. The vertical-cavity surface-emitting laser fabrication method provided in this application achieves precise alignment and concentric distribution of key pattern structures in only three photolithography steps, without relying on machine tools or manual alignment. It achieves the construction of concentric circle patterns with zero alignment error through simple process technology, eliminating the relative position deviation between different structures introduced by step-by-step photolithography. Using Au as a mask, ohmic contact is achieved in advance while etching the mesa, ensuring the quality of the ohmic contact and ensuring that the light outlet is centered on the mesa. While simplifying the process flow and greatly improving process efficiency, it also improves the photolithography overlay accuracy and product yield, and reduces costs.

[0073] 2. The method for fabricating a vertical cavity surface-emitting laser in this application also includes the construction of a metasurface pattern capable of processing the wavefront, which greatly shortens the process, reduces manufacturing costs, and improves the optical performance of semiconductor devices.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a vertical-cavity surface-emitting laser, characterized in that, The method includes: A first dielectric layer is deposited on the substrate surface, and multiple patterned structures, including alignment marks, contact windows, mesa and scribe lines, are etched on the surface of the first dielectric layer based on a first photolithography process. The position of the light-emitting aperture is then determined based on the position of the mesa, wherein the contact window, the mesa and the light-emitting aperture are concentrically arranged. A first metal layer is formed on the surface of the first dielectric layer based on a second photolithography process. The first metal layer covers the area of ​​the first dielectric layer except for the light-emitting aperture, the mesa, and the dicing track. The substrate at the location of the platform and the dicing channel is etched to obtain a first oxide tank and a second oxide tank. The first oxide tank and the second oxide tank are oxidized respectively to deposit a second dielectric layer. The second dielectric layer covers the first metal layer, the first oxide tank, the second oxide tank and the light-emitting hole respectively. The second dielectric layer in the preset areas on both sides of the table and the second dielectric layer covering the wire bonding area are removed by the third photolithography process, and a second metal layer is covered in the preset areas on the bottom and both sides of the table and the wire bonding area respectively.

2. The method for fabricating a vertical-cavity surface-emitting laser according to claim 1, characterized in that, The method further includes: After depositing a first dielectric layer on the substrate surface, a metasurface pattern is etched on the surface of the first dielectric layer. After obtaining the first oxide tank and the second oxide tank, the first dielectric layer at the location of the metasurface pattern is etched by dry etching. The etched first dielectric layer is a hard mask with the metasurface pattern. The metasurface pattern on the hard mask is transferred to the substrate using a first wet etching process.

3. The method for fabricating a vertical-cavity surface-emitting laser according to claim 2, characterized in that, After transferring the metasurface pattern on the hard mask to the substrate, the hard mask on the metasurface pattern is removed again by dry etching to obtain the metasurface pattern formed on the substrate.

4. The method for fabricating a vertical-cavity surface-emitting laser according to claim 2, characterized in that, In the dry etching process, trifluoromethane and oxygen with a volume ratio of 10:1 are used as etching gases; in the first wet etching process, a first combined solution composed of phosphoric acid, hydrogen peroxide and water with a volume ratio of 1:6:50 to 1:6:100 is used for etching.

5. The method for fabricating a vertical-cavity surface-emitting laser according to claim 1, characterized in that, The etching of multiple patterned structures on the surface of the first dielectric layer based on the first photolithography process includes: Based on positive photoresist, a patterned region of the patterned structure is defined on the surface of the first dielectric layer. Using the positive photoresist as a mask, trifluoromethane is used as a reactive gas for dry etching to transfer the patterned region to the first dielectric layer, thereby obtaining multiple patterned structures. The patterned region is used to determine the position of the multiple patterned structures.

6. The method for fabricating a vertical-cavity surface-emitting laser according to claim 1, characterized in that, The formation of a first metal layer on the surface of the first dielectric layer based on a second photolithography process includes: Through the second photolithography process, photoresist patterns are coated on the light-emitting holes, the mesa and the dicing area on the surface of the first dielectric layer, respectively, and the sidewall morphology of the photoresist patterns is an inverted trapezoid. A first metal layer is obtained by vapor deposition over the first dielectric layer and the photoresist pattern, and the photoresist pattern and the metal above it are stripped off.

7. The method for fabricating a vertical-cavity surface-emitting laser according to claim 1, characterized in that, The vertical cavity surface-emitting laser is wet-immersed based on the second wet etching process to selectively etch the substrate at the mesa and the dicing position to obtain the first oxide tank and the second oxide tank; in the second wet etching process, a second combined solution of phosphoric acid, hydrogen peroxide and alkaline solution with a volume fraction ratio of 1:6:10 to 1:6:20 is used for etching.

8. The method for fabricating a vertical-cavity surface-emitting laser according to claim 1, characterized in that, The first metal layer is made of gold, and / or the second metal layer is deposited by metal sputtering, and the second metal layer is a composite metal layer with titanium as the upper layer and gold as the lower layer.

9. A vertical-cavity surface-emitting laser, characterized in that, The vertical cavity surface-emitting laser is fabricated using the fabrication method of a vertical cavity surface-emitting laser as described in any one of claims 1 to 8.

10. A vertical-cavity surface-emitting laser according to claim 9, characterized in that, The vertical cavity surface-emitting laser includes a substrate and a stacked structure disposed on the substrate, wherein: The stacked structure includes a first dielectric layer, a first metal layer, a second dielectric layer and a second metal layer stacked sequentially upward from the substrate, wherein the first metal layer and the second metal layer are electrically connected. The stacked structure forms a graphic structure, a light-emitting aperture, and a wire-punching area, respectively. The graphic structure includes an alignment mark, a contact window, a platform, and a scribe line. The contact window and the platform are both aligned with the center of the light-emitting aperture. The platform is located on the side of the contact window away from the light-emitting aperture. The alignment mark is located on the side of the platform away from the contact window, and the scribe line is located on the other side of the platform away from the contact window. The wire bonding area is located on the side of the platform away from the light emission hole, and the wire bonding area is covered with the second metal layer.

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