Programmable frequency divider and phase-locked loop

Abstract

The application relates to a programmable frequency divider and a phase-locked loop, the programmable frequency divider comprising a plurality of cascaded subtractors, a period end detection module and a delay reset circuit, wherein the plurality of cascaded subtractors are connected to corresponding initial value signals, under the triggering of a clock signal to be divided, the signals output by the plurality of cascaded subtractors correspond to the output results of decrement, and under the condition that the signals output by the plurality of cascaded subtractors reach a period end condition, the period end detection module outputs a period end signal to the delay reset circuit based on the signals output by the plurality of cascaded subtractors and the period end condition. Under the condition that the delay reset circuit receives the period end signal, a reset trigger signal is output to each subtractor so as to reset each subtractor. After a preset delay time length of the delay reset circuit after the reset trigger signal, a work trigger signal is output to each subtractor so as to make each subtractor work and enter the next round of decrement cycle operation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of frequency divider, and particularly relates to a programmable frequency divider and a phase-locked loop. BACKGROUND

[0002] The programmable frequency divider is widely used in analog circuits or digital-analog hybrid circuits such as phase-locked loops. With the continuous improvement of chip performance, the working frequency of the phase-locked loop is getting higher and higher, and the upper limit frequency of the programmable frequency divider is required to be more and more stringent. However, the upper limit frequency of the asynchronous subtracter counter of the traditional structure is low, and the upper limit frequency decreases with the increase of the frequency division ratio. SUMMARY

[0003] Therefore, it is necessary to provide a programmable frequency divider and a phase-locked loop.

[0004] In a first aspect, a programmable frequency divider is provided, comprising:

[0005] A plurality of cascaded subtracters, the plurality of cascaded subtracters having an input end and an output end, the input end of the plurality of cascaded subtracters being used to access a clock signal to be divided, and a parameter configuration end of each subtracter being used to access an initial value signal;

[0006] A cycle end detection module, a plurality of input ends of the cycle end detection module being connected to the output ends of the plurality of subtracters one by one; the cycle end detection module being used to output a cycle end signal according to the case that the signal output by the subtracter reaches a cycle end condition;

[0007] A delay reset circuit, a first input end of the delay reset circuit being connected to the output end of the cycle end detection module, a second input end of the delay reset circuit being used to access the clock signal to be divided, and an output end of the delay reset circuit being connected to the working state switching end of each subtracter; the delay reset circuit being used to output a reset trigger signal to the working state switching end of each subtracter to reset the subtracter, and output a working trigger signal to the working state switching end of each subtracter to make the subtracter work after a preset delay time length of the reset trigger signal is output.

[0008] In one of the embodiments, the delay reset circuit comprises a first flip-flop; the delay reset circuit further comprises a second flip-flop and / or a first combination logic circuit;

[0009] A first input end of the first flip-flop being connected to the output end of the cycle end detection module, a second input end of the first flip-flop being used to access the clock signal to be divided, and an output end of the first flip-flop being connected to the working state switching end of each subtracter; the first flip-flop being used to output a reset trigger signal to the working state switching end of each subtracter to reset the subtracter when the cycle end signal is received;

[0010] The first input end of the second flip-flop is connected with the output end of the first flip-flop, the second input end of the second flip-flop is used for accessing the clock signal to be divided, and the output end of the second flip-flop is connected with the reset end of the first flip-flop; the second flip-flop is used for outputting the first reset signal to the first flip-flop in the case of receiving the reset trigger signal, so that the first flip-flop outputs the working trigger signal to the working state switching end of each subtractor, and the subtractor works.

[0011] The first input end of the first combinational logic circuit is connected with the output end of the period end detection module, the output end of the first combinational logic circuit is connected with the first input end of the first flip-flop, and the second input end of the first combinational logic circuit is connected with the output end of the first flip-flop; the first combinational logic circuit is used for triggering the first flip-flop to output the reset trigger signal in the case of receiving the period end signal and the working trigger signal; the first combinational logic circuit triggers the first flip-flop to output the working trigger signal in the case of receiving the period end signal and the reset trigger signal.

[0012] In one of the embodiments, the first combinational logic circuit comprises:

[0013] The first NOT gate has an input end connected with the output end of the first flip-flop;

[0014] The first AND gate has a first input end connected with the output end of the period end detection module; the second input end of the first AND gate is connected with the output end of the first NOT gate, and the output end of the first AND gate is connected with the first input end of the first flip-flop.

[0015] In one of the embodiments, the timing requirements of the programmable frequency divider need to meet:

[0016] T ckq +T rs2 +T en_dff <T clk ,

[0017] Wherein, T ckq is the total synchronization delay time length of the plurality of cascaded subtractors, T rs2 is the preset delay time length, T en_dff is the minimum setup time required by the plurality of cascaded subtractors, and T clk is the period of one clock signal to be divided.

[0018] In one of the embodiments, the subtractor comprises:

[0019] a third flip-flop, the output end of the third flip-flop corresponding to the plurality of input ends of the period end detection module respectively; the input end of the third flip-flop of the first stage subtracter is used to access the clock signal to be divided; the input end of the third flip-flop of the subtracter other than the first stage subtracter is connected to the output end of the third flip-flop of the subtracter of the previous stage;

[0020] a second combinational logic circuit, the first input end of the second combinational logic circuit being used to access the initial value signal, the second input end of the second combinational logic circuit being connected to the output end of the delay reset circuit, the first output end of the second combinational logic circuit being connected to the reset end of the third flip-flop, and the second output end of the second combinational logic circuit being connected to the set end of the third flip-flop;

[0021] wherein, in the case that the second combinational logic circuit receives the initial value signal and the reset trigger signal, a subtraction reset signal is output to the reset end of the third flip-flop, so as to reset the third flip-flop;

[0022] in the case that the second combinational logic circuit receives the initial value signal and the working trigger signal, a subtraction maintaining signal is output to the reset end of the third flip-flop, and a subtraction set signal is output to the set end of the third flip-flop, so as to work the third flip-flop.

[0023] in one embodiment, the second combinational logic circuit comprises:

[0024] a second NOT gate, the input end of the second NOT gate being connected to the output end of the delay reset circuit;

[0025] an OR gate, the first input end of the OR gate being used to access the initial value signal, and the second input end of the OR gate being connected to the output end of the second NOT gate;

[0026] a third NOT gate, the input end of the third NOT gate being connected to the output end of the OR gate, and the output end of the third NOT gate being connected to the reset end of the third flip-flop;

[0027] a second AND gate, the first input end of the second AND gate being connected to the output end of the delay reset circuit, and the second input end of the second AND gate being used to access the initial value signal;

[0028] a fourth NOT gate, the input end of the fourth NOT gate being connected to the output end of the second AND gate, and the output end of the fourth NOT gate being connected to the set end of the third flip-flop.

[0029] in one embodiment, the third flip-flop is an SR flip-flop.

[0030] in one embodiment, the SR flip-flop is a rising edge triggered SR flip-flop.

[0031] In one of the embodiments, the period end signal is a high level signal, and in the case that the clock signal to be divided is a rising edge, the delay reset circuit outputs a high level reset trigger signal; in the case that the period end signal is a low level signal, the delay reset circuit outputs a low level working trigger signal.

[0032] In a second aspect, a phase-locked loop is provided, comprising the programmable frequency divider.

[0033] The programmable frequency divider and the phase-locked loop, the programmable frequency divider comprises a plurality of cascaded subtractors, a period end detection module and a delay reset circuit, wherein the plurality of cascaded subtractors are connected to the corresponding initial value signals, under the trigger of the clock signal to be divided, the signals output by the plurality of cascaded subtractors correspond to the output results of decrement, in the case that the signals output by the plurality of cascaded subtractors reach the period end condition, it is considered that one decrement cycle of the plurality of cascaded subtractors ends, at this time, the period end detection module outputs a period end signal to the delay reset circuit based on the signals output by the plurality of cascaded subtractors and the period end condition. In the case that the delay reset circuit receives the period end signal, a reset trigger signal is output to each subtractor to reset each subtractor, at this time, each subtractor re-connects the initial value signal. After a preset delay time of the delay reset circuit after the reset trigger signal, a working trigger signal is output to each subtractor to make each subtractor work and enter the next round of decrement cycle operation. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0035] Figure 1 Structure block diagram of the programmable frequency divider of one embodiment;

[0036] Figure 2 Structure block diagram of the programmable frequency divider of one embodiment;

[0037] Figure 3 Structure block diagram of the programmable frequency divider of one embodiment;

[0038] Figure 4 Structure block diagram of the programmable frequency divider of one embodiment;

[0039] Figure 5 Structure block diagram of the programmable frequency divider of one embodiment;

[0040] Figure 6 Timing diagram of a programmable frequency divider in the prior art for an embodiment;

[0041] Figure 7 Timing diagram of a programmable frequency divider for an embodiment;

[0042] Figure 8 Timing diagram of a programmable frequency divider for an embodiment;

[0043] Figure 9 Block diagram of a cycle end detection module of a programmable frequency divider for an embodiment. DETAILED DESCRIPTION

[0044] In order to facilitate the understanding of the present application, the present application will be described in greater detail below with reference to the accompanying drawings. The embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0046] It can be understood that the terms "first", "second", and the like used herein can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. For example, without departing from the scope of the present application, a first flip-flop can be referred to as a second flip-flop, and similarly, a second flip-flop can be referred to as a first flip-flop. Both the first flip-flop and the second flip-flop are flip-flops, but they are not the same flip-flop.

[0047] It can be understood that "connection" in the following embodiments, if the circuits, modules, units, etc. connected to each other have transmission of electrical signals or data, should be understood as "electrical connection", "communication connection", etc.

[0048] It can be understood that "a plurality of" means two or more. "At least part of an element" means part or all of the element.

[0049] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, as used herein, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. Also, the term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0050] To accommodate different power consumption modes, the output frequency of the phase-locked loop needs to be linearly adjustable in a very wide range, which requires the programmable frequency divider to maintain a large frequency division ratio. Moreover, the input clock of the programmable frequency divider is directly the high-frequency output signal of the VCO (Voltage-Controlled Oscillator), and thus the power consumption of the programmable frequency divider is also an important consideration.

[0051] There are three types of programmable frequency dividers commonly used at present. The first type is a synchronous counter, the second type is an asynchronous subtraction counter, and the third type is a multi-mode frequency divider cascaded by dual modulus prescalers. Among them, compared with the asynchronous subtraction counter, the power consumption of the synchronous counter is large, and thus the synchronous counter is generally not used as the frequency divider of the phase-locked loop. The multi-mode frequency divider cascaded by dual modulus prescalers can work at a very high clock frequency, is not very sensitive to the delay of the wiring, and the frequency division ratio can also be linearly adjusted. However, if the frequency division ratio of the multi-mode frequency divider cascaded by dual modulus prescalers is very large, a large number of flip-flops need to be used, and the power consumption is high. Compared with other programmable frequency dividers, the power consumption of the asynchronous subtraction counter is the lowest. However, the upper limit frequency of the asynchronous subtraction counter of the traditional structure is low, and the upper limit frequency decreases as the frequency division ratio increases. Therefore, when the asynchronous subtraction counter is applied in the feedback frequency divider of the phase-locked loop, a prescaler needs to be added in the front stage to reduce the input clock frequency.

[0052] For example, if the maximum frequency division ratio of the programmable frequency divider is M = 2^N, then at least 2(N-1) D flip-flops are needed when the multi-mode frequency divider cascaded by dual modulus prescalers is used, and at least N D flip-flops are needed when the asynchronous subtraction counter is used. The larger the value of N is, the more obvious the low power consumption advantage of the asynchronous subtraction counter is. Compared with the multi-mode frequency divider cascaded by dual modulus prescalers, the asynchronous subtraction counter needs fewer flip-flops to achieve the same frequency division ratio, which makes the chip feature size small when the asynchronous subtraction counter is used as the programmable frequency divider, which makes it possible to directly use the asynchronous subtraction counter without a prescaler in front. However, the traditional asynchronous subtraction counter still has the problem of low upper limit frequency.

[0053] In one specific embodiment, as shown inFigure 1 As shown in the figure, a programmable frequency divider 10 is provided, comprising a plurality of cascaded subtractors 102, a period end detection module 104 and a delay reset circuit 106.

[0054] The plurality of cascaded subtractors 102 have input ends and output ends, the input ends of the plurality of cascaded subtractors 102 are used to access a clock signal to be divided, and the parameter configuration ends of each subtractor 102 are used to access an initial value signal.

[0055] The plurality of input ends of the period end detection module 104 are connected one by one to the output ends of the plurality of subtractors 102; the period end detection module 104 is used to output a period end signal according to the case that the signal output by the subtractor 102 reaches a period end condition.

[0056] The first input end of the delay reset circuit 106 is connected to the output end of the period end detection module 104, the second input end of the delay reset circuit 106 is used to access the clock signal to be divided, and the output end of the delay reset circuit 106 is connected to the working state switching end of each subtractor 102; the delay reset circuit 106 is used to output a reset trigger signal to the working state switching end of each subtractor 102 to reset the subtractor 102, and output a working trigger signal to the working state switching end of each subtractor 102 to make the subtractor 102 work after a preset delay time length after the output of the reset trigger signal.

[0057] As shown in the figure, Figure 1 The clkin is the clock signal to be divided; the eoc=1 represents the period end signal; the reload=0 represents the working trigger signal; the reload=1 represents the reset trigger signal, which is the data reload signal of each subtractor 102; the in represents the initial value signal; the out represents the clock signal to be divided; the clkout represents the divided clock signal; the eoc represents the period end signal; the reload represents the reset trigger signal; the in represents the initial value signal; the out represents the divided clock signal. <n-1>The in<0> is an initial value corresponding to an initial value signal of each subtractor 102, which can be input by an external register; the Q0~QN-1 are signals output by each subtractor 102, corresponding to output results of the plurality of cascaded subtractors 102. In the phase-locked loop, a high-frequency clock signal output by the VCO can be used as the clock signal to be divided.

[0058] The plurality of cascaded subtractors 102 access the corresponding initial value signal, and under the trigger of the clock signal to be divided, the signals output by the plurality of cascaded subtractors 102 correspond to the output results of the plurality of cascaded subtractors 102. In the case where the signals output by the plurality of cascaded subtractors 102 reach the period end condition, it is considered that one cycle of the plurality of cascaded subtractors 102 ends. At this time, the period end detection module 104 outputs a period end signal to the delay reset circuit 106 based on the signals output by the plurality of cascaded subtractors 102 and the period end condition. In the case where the delay reset circuit 106 receives the period end signal, a reset trigger signal is output to each subtractor 102 to reset each subtractor 102. At this time, each subtractor 102 reaccesses the initial value signal. After a preset delay time of the delay reset circuit 106 after the reset trigger signal, a work trigger signal is output to each subtractor 102 to make each subtractor 102 work and enter the next round of the decrement cycle operation.

[0059] The eoc signal output by the period end detection module 104 is logic 0 when the plurality of cascaded subtractors 102 perform the subtraction cycle, and is logic 1 when the signals output by the plurality of cascaded subtractors 102 reach the period end condition, that is, the period end detection module 104 outputs the period end signal when the signals output by the plurality of cascaded subtractors 102 reach the period end condition. The period end detection module 104 and the delay reset circuit 106 can be directly interconnected, and can be indirectly interconnected through other logic circuits.

[0060] The "outputting, by the delay reset circuit 106, the working trigger signal to the working state switching end of each subtracter 102 after a preset delay time of the output reset trigger signal" can be understood as follows: if the period end detection module 104 outputs the period end signal in the clock cycle of the kth to-be-divided clock signal, the delay reset circuit 106 outputs the reset trigger signal after the trigger edge of the k+1th to-be-divided clock signal, and outputs the working trigger signal after the trigger edge of the k+2th to-be-divided clock signal, regardless of whether the period end detection module 104 outputs the period end signal, thereby avoiding the situation that the working trigger signal cannot be output in time to each flip-flop due to the metastability caused by the path delay of the programmable frequency divider 10, and improving the reliability of the programmable frequency divider 10. Specifically, the preset delay time of the delay reset circuit 106 is one unit of time corresponding to the period of the divided clock signal.

[0061] In a specific embodiment, as shown in Figure 2 、 Figure 3 and Figure 4 , the delay reset circuit 106 includes a first flip-flop (see Figure 2 、 Figure 3 and Figure 4 DFFN); the delay reset circuit 106 further includes a second flip-flop (see Figure 2 and Figure 4 DFFN2) and / or a first combination logic circuit (see Figure 3 and Figure 4 AND0). Wherein, the DFF in DFFN represents a D flip-flop (D Flip-Flop), and DFFN represents the Nth D flip-flop.

[0062] The first input end of the first flip-flop is connected to the output end of the period end detection module 104, the second input end of the first flip-flop is used to input the to-be-divided clock signal, and the output end of the first flip-flop is connected to the working state switching end of each subtracter 102; the first flip-flop is used to output the reset trigger signal to the working state switching end of each subtracter 102 in the case of receiving the period end signal, so as to reset the subtracter 102.

[0063] The first input end of the second flip-flop is connected to the output end of the first flip-flop, the second input end of the second flip-flop is used to input the to-be-divided clock signal, and the output end of the second flip-flop is connected to the reset end of the first flip-flop; the second flip-flop is used to output the first reset signal (see Figure 2 set0 signal) to the first flip-flop in the case of receiving the reset trigger signal, so as to make the first flip-flop output the working trigger signal to the working state switching end of each subtracter 102, and make the subtracter 102 work.

[0064] The first input end of the first combinational logic circuit is connected with the output end of the period end detection module 104, the output end of the first combinational logic circuit is connected with the first input end of the first flip-flop, and the second input end of the first combinational logic circuit is connected with the output end of the first flip-flop; the first combinational logic circuit is used for triggering the first flip-flop to output a reset trigger signal in the case of receiving a period end signal and a work trigger signal; and the first combinational logic circuit is used for triggering the first flip-flop to output a work trigger signal in the case of receiving a period end signal and a reset trigger signal.

[0065] As shown in FIG. 1, the period end detection module 104 is directly connected with the first flip-flop in the case that the delay reset circuit 106 includes the first flip-flop and the second flip-flop, and the second flip-flop outputs a first reset signal; the first flip-flop is asynchronously forced to output a work trigger signal in the case that the second flip-flop receives the reset trigger signal. Figure 2

[0066] As shown in FIG. 1, the period end detection module 104 is indirectly connected with the first flip-flop through the first combinational logic circuit in the case that the delay reset circuit 106 includes the first flip-flop and the first combinational logic circuit; the first flip-flop is triggered to output a work trigger signal in the case that the reset trigger signal output by the first flip-flop is fed back to the first combinational logic circuit and the first combinational logic circuit receives a period end signal.

[0067] As shown in FIG. 1, the period end detection module 104 is indirectly connected with the first flip-flop through the first combinational logic circuit in the case that the delay reset circuit 106 includes the first flip-flop and the first combinational logic circuit; the first flip-flop is triggered to output a work trigger signal in the case that the reset trigger signal output by the first flip-flop is fed back to the first combinational logic circuit and the first combinational logic circuit receives a period end signal. Figure 3

[0068] As shown in FIG. 1, the period end detection module 104 is indirectly connected with the first flip-flop through the first combinational logic circuit in the case that the delay reset circuit 106 includes the first flip-flop and the first combinational logic circuit; the first flip-flop is triggered to output a work trigger signal in the case that the reset trigger signal output by the first flip-flop is fed back to the first combinational logic circuit and the first combinational logic circuit receives a period end signal.

[0069] As shown in FIG. 1, the period end detection module 104 is indirectly connected with the first flip-flop through the first combinational logic circuit in the case that the delay reset circuit 106 includes the first flip-flop and the first combinational logic circuit; the first flip-flop is triggered to output a work trigger signal in the case that the reset trigger signal output by the first flip-flop is fed back to the first combinational logic circuit and the first combinational logic circuit receives a period end signal. Figure 4 ​​As shown, the delay reset circuit 106 includes a first flip-flop, a second flip-flop and a first combinational logic circuit, which realizes a redundant setting of a unit delay, so that in the case of a failure of the second flip-flop or the first combinational logic circuit, the programmable frequency divider 10 can still realize the forced output of the working trigger signal based on the first combinational logic circuit or the second flip-flop, thereby ensuring the reliable operation of the programmable frequency divider 10. The forced output of the working trigger signal refers to that the delay reset circuit 106 forcibly outputs the working trigger signal after a unit delay after outputting the reset trigger signal.

[0070] In a specific embodiment, as shown in Figure 3 and Figure 4 As shown, the first combinational logic circuit includes a first NOT gate and a first AND gate.

[0071] The input end of the first NOT gate is connected to the output end of the first flip-flop.

[0072] The first input end of the first AND gate is connected to the output end of the period end detection module 104; the second input end of the first AND gate is connected to the output end of the first NOT gate, and the output end of the first AND gate is connected to the first input end of the first flip-flop.

[0073] In the case that the first NOT gate receives the working trigger signal of reload=0 output by the first flip-flop, the first NOT gate outputs a high level to the first AND gate, and in the case that the first AND gate receives the high level output by the first NOT gate and the period end signal of eoc=1 output by the period end detection module 104, the first AND gate outputs a high level to the first flip-flop, thereby triggering the first flip-flop to output the reset trigger signal of reload=1.

[0074] In the case that the first NOT gate receives the reset trigger signal of reload=1 output by the first flip-flop, the first NOT gate outputs a low level to the first AND gate, and in the case that the first AND gate receives the low level output by the first NOT gate and the period end signal of eoc=1 output by the period end detection module 104, the first AND gate outputs a low level to the first flip-flop, thereby triggering the first flip-flop to output the working trigger signal of reload=0.

[0075] In the case that the first AND gate receives eoc=0 output by the period end detection module 104, the first AND gate outputs a low level to the first flip-flop, thereby triggering the first flip-flop to output the working trigger signal of reload=0.

[0076] In a specific embodiment, the timing requirements of the programmable frequency divider 10 need to meet:

[0077] T ckq +T rs2 +T en_dff <T clk ,

[0078] wherein T ckq is the total synchronization delay time length of the plurality of cascaded subtractors 102, T rs2 is a preset delay time length, T en_dff is the minimum setup time required by the plurality of cascaded subtractors 102, T clk is the period of a clock signal to be divided.

[0079] In order to better illustrate the advantages of the present application, the prior art programmable frequency divider 10 is introduced for description: taking the prior art programmable frequency divider 10 including four subtractors 102 as an example for description, as shown in Figure 5 and Figure 6 DFFNmay be triggered by the clock signal to be divided to enter the trigger state, if DFFNreceives the period end signal in the trigger state, a reload signal with logic 1 will be output, at this time, QN-1~Q0corresponding to DFFN-1~DFF0are reset to in <n-1>in<0>. Since eoc is restored to logic 0 before the rising edge of the next clock signal to be divided, DFFN outputs the working trigger signal after the rising edge of the next clock signal to be divided, and DFFN-1 (the (N-1)th D flip-flop) and DFF0 (the 0th D flip-flop) start counting after the rising edge of the third clock signal to be divided. With the flipping of the clock signal to be divided, QN-1 ~ Q0 sequentially implement subtraction.

[0080] If the period end detection module 104 outputs a period end signal based on the values of QN-1 ~ Q0 after the rising edge of the kth clock signal to be divided, then after the rising edge of the (k+1)th clock signal to be divided, QN-1 ~ Q0 continue to implement subtraction, but after a short fixed delay, DFFN outputs a reload signal with a logic value of 1, which asynchronously sets QN-1 ~ Q0 to in <n-1>in<0> ; after the rising edge of the k+2th clock signal to be divided, and after a short fixed delay, the DFFN outputs the working trigger signal. That is, within the period of the clock signal to be divided, QN-1Q0 continues to maintain in <n-1>in<0> until the rising edge of the k+3th clock signal to be divided arrives, the subtraction counting is restarted.

[0081] If the period end condition is Q3~Q0=0001, then in the last clock signal to be divided, Q3~Q0=0010, after the rising edge of the clock signal to be divided, only Q1 and Q0 flip, Q3 and Q2 remain unchanged, thus, T eoc = T eocf , where T eocf is the delay between the period end detection module 104 receiving Q1 and Q0 and outputting the period end signal; T reload is the delay between the period end detection module 104 outputting the reload signal with logic 1 and the reset circuit 106 outputting the logic 1; if the bit number N of the frequency divider is very high, the wire length between the reset circuit 106 and each subtracter 102 is very long, and there are many load logic gates, T reload will be very large; T rs is the delay between the output of the reload signal with logic 1 to each subtracter 102 and the completion of the setting of Q3~Q0, which is slightly larger than T ckq . T en_dff is the minimum setup time required by the DFF. Among them, T ckq is generally small; T eoc is the combinational logic delay of the period end detection module 104, which is determined by QN-1~Q0 together.

[0082] If after the rising edge of a clock signal to be divided, Q3~Q0=0001, before and after the rising edge of the next clock signal to be divided, the period end detection module 104 outputs the period end signal, at this time, the reload signal with logic 1 has not yet acted on each subtracter 102, Q3~Q0 continues to perform subtraction, reaches Q3~Q0=0000, after T eoc , the eoc corresponding to the output of the period end detection module 104 becomes logic 0 and remains unchanged within the clock period of the clock signal to be divided. After T reload +T rs , the DFF4 outputs the reload signal with logic 1 to set DFF0~DFF3 to 1001. Before the rising edge of the third clock signal to be divided arrives, the eoc corresponding to the output of the period end detection module 104 continues to be logic 0, the rising edge of the third clock signal to be divided drives DFF4 to sample the eoc which continues to be logic 0, and DFF4 outputs the working trigger signal after T reload . After T en_dff After that, the rising edge of the fourth clock signal to be divided can come, triggering a new round of subtraction cycle of the plurality of cascaded subtractors 102. Extending this theory to the programmable frequency divider 10 including at least 4 subtractors 102, in the case of increasing the number of DFFs, T reload increases, in this case, T ckq +T eoc <T reload +T rs . Thus, the main timing requirement of the prior art programmable frequency divider is T reload +T rs <T clk .

[0083] If T rs and T en_dff are similar, T reload can be reduced to a relatively small value under the refined driving path between DFFN and each subtractor 102, in this case, the upper limit frequency of the programmable frequency divider 10 will be very high. However, if in<3>~in<0>=1001, the reload signal outputting logic 1 of DFFN is triggered, due to the parasitic of the layout of the programmable frequency divider 10 and the different paths of the signals accessed by the period end detection module 104, if in this case, the reload signal with logic 1 forces Q1~Q0 from 00 to 01, due to the long delay of Q3~Q2, it still shows 00, then the period end detection module 104 outputs the period end signal based on Q3~Q0 after T eocf delay, at this time, the period end signal is not expected to appear. In this case, only after T eocs delay, Q3~Q2 jumps to 10, so that eoc returns to logic 0. Therefore, the eoc signal generates a narrow pulse with a width of T eocs -T eocf , which exists in the metastable state. Wherein, T eocs is the combined logic delay of the period end detection module 104 obtaining and outputting the eoc signal based on Q3~Q2.

[0084] This narrow pulse is captured by DFF4 during CK2=0, before the rising edge of CK3 comes, the eoc signal may return to logic 0. However, if the setup time is not enough, the reload will not return to logic 0 within the clock signal period after the rising edge of CK3, so that the frequency division ratio of the programmable frequency divider 10 in the prior art is increased by 1. Therefore, the timing requirement of the programmable frequency divider 10 in the prior art is:

[0085] T en_dff <=T setup_mgn <T clk -T reload -T rs -T eocs ,

[0086] wherein T setup_mgn is the setup time margin of the DFF.

[0087] If the number of subtractors 102 included in the programmable frequency divider 10 in the prior art is more, T eocs -T eocf The corresponding narrow pulse is larger, and the condition of the timing requirement of the programmable frequency divider 10 in the prior art is more stringent. Generally, if the condition of T reload +T rs <T clk , the upper limit frequency of the programmable frequency divider 10 in the prior art can reach 5 GHz, and if the condition of T en_dff <=T setup_mgn <T clk -T reload -T rs -T eocs , the upper limit frequency of the programmable frequency divider 10 in the prior art can be less than 2.5 GHz. It can be seen that the metastability of the programmable frequency divider 10 in the prior art reduces the upper limit frequency.

[0088] In the case that the delay value of T eocs is large, and the end time of T eocs has already exceeded the CK2 period and reached the CK3 period, the DFFN will synchronize eoc=1 at the CK3 rising edge stage to output the reload signal with logic 1, and the reload signal with logic 1 will remain 1 in the entire CK3 period. After the CK4 rising edge, the DFFN will synchronize eoc=0 to output the reload signal with logic 0. This causes the frequency division ratio of the programmable frequency divider 10 in the prior art to increase by 1. In actual application, the programmable frequency divider 10 in the prior art will also cause the end edge of T eocs to randomly jump on both sides of the CK3 rising edge due to the changes of temperature and power voltage, causing the frequency division ratio to randomly jitter.

[0089] As Figure 7 As shown, in this application, a programmable frequency divider 10 including four subtractors 102 is also used for explanation, and the first flip-flop is set to rise-edge triggering: After the rising edge of the CK3 clock, the set0 signal jumps to logic 1 after a short delay. This logic 1 set0 signal forces the reload to logic 0, that is, forces the first flip-flop to output the working trigger signal, thereby shielding the aforementioned logic 1 eoc signal caused by random jitter. The delay from the rising edge of CK3 to the forced reload to logic 0 is T. setdl T setdl With T reload Since they are similar, the timing constraints of the CK3 cycle and the CK2 cycle are almost identical, satisfying T reload +T rs <T clk The corresponding timing requirements. After the rising edge of CK4, the set0 signal jumps to logic 0, and each subtractor 102 in the programmable frequency divider 10 enters a new round of subtraction.

[0090] Taking the time-delayed reset circuit 106, which includes a first flip-flop and a first combinational logic circuit, as an example, the following explanation is provided: Figure 8 As shown, Figure 8 Can be with Figure 7 Corresponding, specific Figure 7 T in setdl Corresponding Appendix Figure 8 T in ckq +T rs2 , among which, T setdl This is for asynchronous reset delay. Therefore, the timing requirements for the programmable frequency divider 10 are:

[0091] T ckq +T rs2 +T en_dff <T clk ,

[0092] Among them, T ckq +T rs2 With T reload The sizes are similar; TRS and Ten_dff are similar in size. Compared with the programmable frequency divider 10 in the prior art, the upper limit frequency corresponding to the timing requirement of this programmable frequency divider 10 is twice as high.

[0093] In a specific embodiment, such as Figure 2 , Figure 3 and Figure 4 As shown, the subtractor 102 includes: a third flip-flop 1022 (see...) Figure 2 , Figure 3 and Figure 4 DFF0~DFFN-1) and a second combinational logic circuit. Wherein, DFF0 represents the 0th third flip-flop 1022, and DFFN-1 represents the (N-1)th third flip-flop 1022.

[0094] The output ends of the third flip-flops 1022 are respectively connected to the multiple input ends of the cycle end detection module 104; the input end of the third flip-flop 1022 of the first stage subtracter is used to access the to-be-divided clock signal; the input end of the third flip-flop 1022 of the subtracter 102 other than the first stage subtracter is connected to the output end of the third flip-flop 1022 of the subtracter 102 of the previous stage.

[0095] The first input end of the second combinational logic circuit is used to access the initial value signal, the second input end of the second combinational logic circuit is connected to the output end of the delay reset circuit 106, the first output end of the second combinational logic circuit is connected to the reset end of the third flip-flop 1022, and the second output end of the second combinational logic circuit is connected to the set end of the third flip-flop 1022.

[0096] Wherein, in the case that the second combinational logic circuit receives the initial value signal and the reset trigger signal, the subtraction reset signal is output to the reset end of the third flip-flop 1022, so as to reset the third flip-flop 1022.

[0097] In the case that the second combinational logic circuit receives the initial value signal and the working trigger signal, the subtraction maintenance signal is output to the reset end of the third flip-flop 1022, and the subtraction set signal is output to the set end of the third flip-flop 1022, so as to make the third flip-flop 1022 work.

[0098] Taking the subtraction reset signal output by the second combinational logic circuit as logic 1, the subtraction maintenance signal as logic 0, and the subtraction set signal as logic 0 as an example: in the third flip-flop 1022, the priority of the subtraction reset signal with logic 1 is higher, that is, when the reset end of the third flip-flop 1022 receives the subtraction reset signal with logic 1, no matter what the logic of the signal received by the set end of the third flip-flop 1022 is, the third flip-flop 1022 will forcibly and asynchronously output a signal with logic 0, that is, Q0~QN-1 is logic 0. In the case that the reset end of the third flip-flop 1022 receives the subtraction maintenance signal with logic 0, and the set end of the third flip-flop 1022 receives the subtraction set signal with logic 0, the third flip-flop 1022 will only asynchronously output a signal with logic 1, that is, Q0~QN-1 is logic 1.

[0099] In the case that the second combinational logic circuit receives the reset trigger signal with logic 1 outputted by the delay reset circuit 106, the second combinational logic circuit re-interfaces the initial value signal to output the subtraction reset signal with logic 1 to the reset end of the third flip-flop 1022 to trigger the reset of the third flip-flop 1022. In the case that the second combinational logic circuit receives the work trigger signal with logic 0 outputted by the delay reset circuit 106, the second combinational logic circuit does not re-interface the initial value signal, in which case the second combinational logic circuit outputs the subtraction reset signal with logic 0 to the reset end of the third flip-flop 1022 and outputs the subtraction set signal with logic 0 to the set end of the third flip-flop 1022 to make the third flip-flop 1022 execute the subtraction cycle.

[0100] In one specific embodiment, as shown in Figure 2 、 Figure 3 and Figure 4 , the second combinational logic circuit comprises a second NOT gate, an OR gate, a third NOT gate, a second AND gate and a fourth NOT gate.

[0101] The input end of the second NOT gate is connected to the output end of the delay reset circuit 106.

[0102] The first input end of the OR gate is used to interface the initial value signal, and the second input end of the OR gate is connected to the output end of the second NOT gate.

[0103] The input end of the third NOT gate is connected to the output end of the OR gate, and the output end of the third NOT gate is connected to the reset end of the third flip-flop 1022.

[0104] The first input end of the second AND gate is connected to the output end of the delay reset circuit 106, and the second input end of the second AND gate is used to interface the initial value signal.

[0105] The input end of the fourth NOT gate is connected to the output end of the second AND gate, and the output end of the fourth NOT gate is connected to the set end of the third flip-flop 1022.

[0106] In the case that the delay reset circuit 106 outputs the reset trigger signal with logic 1 to the second NOT gate, the second NOT gate outputs the signal with logic 0; in the case that the delay reset circuit 106 outputs the work trigger signal with logic 0 to the second NOT gate, the second NOT gate outputs the signal with logic 1.

[0107] The OR gate outputs a logic 1 signal in the case that it receives a logic 1 initial value signal and / or receives a logic 1 signal output by the second NOT gate; the OR gate outputs a logic 0 signal in the case that it receives a logic 0 initial value signal and receives a logic 0 signal output by the second NOT gate. That is, the OR gate outputs a logic 1 signal in the case that it receives a logic 1 initial value signal and / or the delay reset circuit 106 outputs a logic 0 working trigger signal to the second NOT gate; the OR gate outputs a logic 0 signal in the case that it receives a logic 0 initial value signal and the delay reset circuit 106 outputs a logic 1 reset trigger signal to the second NOT gate.

[0108] The third NOT gate outputs a logic 0 signal in the case that it receives a logic 1 signal output by the OR gate; the third NOT gate outputs a logic 1 signal in the case that it receives a logic 0 signal output by the OR gate. That is, the third NOT gate outputs a logic 0 signal to the third flip-flop 1022 in the case that the OR gate receives a logic 1 initial value signal and / or the delay reset circuit 106 outputs a logic 0 working trigger signal to the second NOT gate, i.e. the third NOT gate outputs a subtraction maintenance signal to the reset end of the third flip-flop 1022; the third NOT gate outputs a logic 1 signal to the third flip-flop 1022 in the case that the OR gate receives a logic 0 initial value signal and the delay reset circuit 106 outputs a logic 1 reset trigger signal to the second NOT gate, i.e. the third NOT gate outputs a subtraction reset signal to the reset end of the third flip-flop 1022.

[0109] The second AND gate outputs a logic 1 signal in the case that it receives a logic 1 initial value signal and a logic 1 reset trigger signal output by the delay reset circuit 106; the second AND gate outputs a logic 0 signal in the case that it receives a logic 0 initial value signal and / or receives a logic 0 working trigger signal output by the delay reset circuit 106.

[0110] The fourth NOT gate outputs a logic 0 signal in the case that it receives a logic 1 signal output by the second AND gate; the fourth NOT gate outputs a logic 1 signal in the case that it receives a logic 0 signal output by the second AND gate. That is, the fourth NOT gate outputs a logic 0 signal, i.e. the fourth NOT gate outputs a subtraction set signal to the set end of the third flip-flop 1022, in the case that the second AND gate receives a logic 1 initial value signal and a logic 1 reset trigger signal output by the delay reset circuit 106; the fourth NOT gate outputs a logic 1 signal in the case that the second AND gate receives a logic 0 initial value signal and / or receives a logic 0 working trigger signal output by the delay reset circuit 106.

[0111] In one embodiment, the third flip-flop 1022 is an SR (Set-Reset) flip-flop.

[0112] The SR flip-flop can directly respond to the input change without a clock signal, realizing asynchronous control, which enables the third flip-flop 1022 to update the state immediately when the to-be-divided clock signal arrives, without waiting for the edge of the to-be-divided clock signal, thereby reducing the delay.

[0113] The SR flip-flop can be set as reset priority, so that when the third flip-flop 1022 receives a subtraction reset signal with logic 1 at the reset end, the third flip-flop 1022 will forcibly output a signal with logic 0 at the Q0~QN-1, regardless of the logic of the signal received at the set end of the third flip-flop 1022.

[0114] In one embodiment, the SR flip-flop is a rising edge triggered SR flip-flop.

[0115] The rising edge triggered SR flip-flop only samples the signals at the reset end and the set end at the rising edge of the to-be-divided clock signal, and does not respond to the input change of the reset end and the set end throughout. Such a setting can reduce the false recognition caused by the short glitch of the to-be-divided clock signal due to noise or wiring delay, reduce the probability of error flip, and improve the ability of the programmable frequency divider 10 to resist glitch interference.

[0116] In one embodiment, the period end signal is a high-level signal, and the delay reset circuit 106 outputs a high-level reset trigger signal when the to-be-divided clock signal is a rising edge; and outputs a low-level working trigger signal when the period end signal is a low-level signal.

[0117] The period end detection module 104 can be a combinational logic circuit, and the circuit logic of the combinational logic circuit is: when QN-1~Q0 is 0x0 or 0x1, output a period end signal with logic 1, i.e. eoc=1; when QN-1~Q0 is other values, output a 0 signal with logic 0, i.e. eoc=0. The specific logic of the combinational logic circuit is determined according to actual needs. For example, if in <n-1>The decimal value of in<0> is P, and the decimal value of QN-1~Q0 of the period end detection module 104 outputting a period end signal with logic 1 is E, then the frequency division ratio of the programmable frequency divider 10 is P-E+2.

[0118] Taking the programmable frequency divider 10 including four cascaded subtractors 102 as an example, the specific circuit of the period end detection module 104 is shown in Figure 9 The logic of the period end detection module 104 is eoc=Q3+Q2+Q1+Q0b, wherein Q0b is the logic non-signal of Q0. The frequency division ratio of the programmable frequency divider 10 is the decimal value of in<3>~in<0>+1, that is, if in<3>~in<0> is represented as 1111, then the programmable frequency divider 10 is a 16 frequency divider.

[0119] In one specific embodiment, a phase-locked loop is provided, including the programmable frequency divider described above.

[0120] The upper limit frequency of the phase-locked loop with the variable frequency divider is high, which can generate or process higher frequency signals, support wider communication frequency bands, and have a wider application range.

[0121] In the description of the specification, the description referring to the terms "some embodiments", "other embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily mean the same embodiment or example.

[0122] The technical features of the above-described embodiments can be combined in any manner. In order to make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, however, as long as the combination of the technical features does not contradict, it should be considered as the scope of the present application.

[0123] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the present application. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A programmable frequency divider, characterized in that, include: Multiple cascaded subtractors, each having an input terminal and an output terminal, wherein the input terminal of each cascaded subtractor is used to receive a clock signal to be divided, and the parameter configuration terminal of each subtractor is used to receive an initial value signal. The cycle end detection module has multiple input terminals that are connected one-to-one with the output terminals of multiple subtractors; the cycle end detection module is used to output a cycle end signal when the signal output by the subtractor reaches the cycle end condition. The circuit includes a delayed reset circuit. The first input of the delayed reset circuit is connected to the output of the cycle end detection module. The second input of the delayed reset circuit is used to input the clock signal to be divided. The output of the delayed reset circuit is connected to the operating state switching terminals of each of the subtractors. Upon receiving the cycle end signal, the delayed reset circuit outputs a reset trigger signal to the operating state switching terminals of each subtractor to reset the subtractor. After a preset delay after outputting the reset trigger signal, it outputs a working trigger signal to the operating state switching terminals of each subtractor to activate the subtractor.

2. The programmable frequency divider according to claim 1, characterized in that, The circuit with delayed reset includes a first flip-flop; the circuit with delayed reset also includes a second flip-flop and / or a first combinational logic circuit; The first input terminal of the first flip-flop is connected to the output terminal of the cycle end detection module, the second input terminal of the first flip-flop is used to receive the clock signal to be divided, and the output terminal of the first flip-flop is respectively connected to the working state switching terminal of each of the subtractors. The first trigger is used to output a reset trigger signal to the working state switching terminal of each subtractor when the cycle end signal is received, so as to reset the subtractor; The first input terminal of the second flip-flop is connected to the output terminal of the first flip-flop, the second input terminal of the second flip-flop is used to input the clock signal to be divided, and the output terminal of the second flip-flop is connected to the reset terminal of the first flip-flop. The second trigger is used to output a first reset signal to the first trigger when the reset trigger signal is received, so that the first trigger outputs the working trigger signal to the working state switching terminal of each subtractor, so that the subtractor works; The first input terminal of the first combinational logic circuit is connected to the output terminal of the cycle end detection module, the output terminal of the first combinational logic circuit is connected to the first input terminal of the first flip-flop, and the second input terminal of the first combinational logic circuit is connected to the output terminal of the first flip-flop. The first combinational logic circuit is used to trigger the first flip-flop to output the reset trigger signal when it receives the cycle end signal and the working trigger signal. The first combinational logic circuit is also used to trigger the first flip-flop to output the working trigger signal when it receives the cycle end signal and the reset trigger signal.

3. The programmable frequency divider according to claim 2, characterized in that, The first combinational logic circuit includes: The first NOT gate, the input of which is connected to the output of the first flip-flop; The first AND gate has its first input connected to the output of the cycle end detection module; the second input of the first AND gate is connected to the output of the first NOT gate; and the output of the first AND gate is connected to the first input of the first flip-flop.

4. The programmable frequency divider according to claim 1, characterized in that, The timing requirements of the programmable frequency divider must meet the following: T ckq +T rs2 +T en_dff <Tclk, Among them, T ckq T is the total synchronization delay of the multiple cascaded subtractors. rs2 T is the preset delay duration. en_dff T is the minimum setup time required for the multiple cascaded subtractors. clk This represents the period of a clock signal to be divided.

5. The programmable frequency divider according to any one of claims 1-4, characterized in that, The subtractor includes: The third flip-flop, the output of which is respectively connected to multiple inputs of the cycle end detection module; the input of the third flip-flop of the first-stage subtractor is used to connect to the clock signal to be divided; the inputs of the third flip-flops of other subtractors besides the first-stage subtractor are connected to the output of the third flip-flop of the previous stage subtractor; The second combinational logic circuit has a first input terminal for receiving the initial value signal, a second input terminal for connecting to the output terminal of the delay reset circuit, a first output terminal for connecting to the reset terminal of the third flip-flop, and a second output terminal for connecting to the set terminal of the third flip-flop. Specifically, when the second combinational logic circuit receives the initial value signal and the reset trigger signal, it outputs a subtraction reset signal to the reset terminal of the third flip-flop to reset the third flip-flop. When the second combinational logic circuit receives the initial value signal and the working trigger signal, it outputs a subtraction sustain signal to the reset terminal of the third flip-flop and outputs a subtraction set signal to the set terminal of the third flip-flop to make the third flip-flop work.

6. The programmable frequency divider according to claim 5, characterized in that, The second combinational logic circuit includes: The second NOT gate, the input of which is connected to the output of the circuit with delay and reset; The OR gate has its first input terminal used to receive the initial value signal, and its second input terminal connected to the output terminal of the second NOT gate. The third NOT gate has its input connected to the output of the OR gate, and its output connected to the reset terminal of the third flip-flop. The second AND gate has its first input connected to the output of the circuit with delay reset, and its second input is used to receive the initial value signal. The fourth NOT gate has its input connected to the output of the second AND gate, and its output connected to the set terminal of the third flip-flop.

7. The programmable frequency divider according to claim 5, characterized in that, The third trigger is an SR trigger.

8. The programmable frequency divider according to claim 7, characterized in that, The SR trigger is a rising-edge triggered SR trigger.

9. The programmable frequency divider according to claim 8, characterized in that, When the cycle end signal is a high-level signal, and the clock signal to be divided is a rising edge, the delay reset circuit outputs a high-level reset trigger signal; when the cycle end signal is a low-level signal, the delay reset circuit outputs a low-level working trigger signal.

10. A phase-locked loop, characterized in that, Includes the programmable frequency divider according to any one of claims 1-9.

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