Input load compensation circuit, digital-to-analog converter and method for R-2R resistive DAC (Digital-to-Analog Converter)

Abstract

The invention discloses an input load compensation circuit, a digital-to-analog converter and a method for an R-2R resistive DAC (Digital-to-Analog Converter), and aims to solve the problem of unstable reference voltage caused by the change of an input load along with an input code. The circuit comprises a trend compensation branch and an adjacent code compensation branch which are both connected between a first reference voltage and a second reference voltage. The trend compensation branch controls a first resistance network through a thermometer decoder and generates a first compensation current used for compensating the overall change trend of the current. And the adjacent code compensation branch controls the second resistance network through the XOR gate circuit to generate a second compensation current for compensating the current difference between adjacent code words. Through a dual compensation mechanism, the total current on the reference voltage is effectively stabilized, and the linearity and the dynamic performance of the DAC are remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to an input load compensation circuit for R-2R resistor type DAC, a digital-to-analog converter and a method. BACKGROUND

[0002] A digital-to-analog converter (DAC) is an electronic device used to convert digital signals into analog signals, and plays a vital role in modern electronic systems. Among them, the R-2R resistor ladder network type digital-to-analog converter (referred to as R-2R resistor type DAC) is widely used in various signal processing and data conversion fields due to its simple structure, high precision and only two resistance values.

[0003] The circuit structure of a typical N-bit R-2R resistor type DAC is shown in Figure 1 As shown in Figure 1 , its core is a ladder network composed of resistors with resistance values of R and 2R. The network receives a pair of differential reference voltages VREFP and VREFN. A group of switches (for example, S0 to S7 in Figure 1 ) are switched according to the state of the input digital code to selectively connect the lower end of each 2R resistor to VREFP or VREFN. The ideal output voltage V_OUT conversion relationship can be represented by the following formula:

[0004]

[0005] Where D_{i,bin} is the i-th bit (0 or 1) of the input digital code, and N is the number of bits of the DAC.

[0006] However, the traditional R-2R resistor type DAC has an inherent technical problem. The input current, i.e. input load, drawn from the reference voltage source (VREF = VREFP - VREFN) will change with the input digital code. Specifically, the current on VREF is determined by the total equivalent resistance value from VREFP to VREFN, and different input codes (i.e. different "bit selection") will change the current path by controlling the state of the switch, thereby forming different total equivalent resistance values. Therefore, according to Kirchhoff's current law (KCL) and voltage law (KVL), the total current I_tot flowing through the reference voltage path is not a constant value, but a function of the input code, as shown in the following formula:

[0007]

[0008] As can be clearly seen from the formula, the total current I_tot is a function of the input code (ΣD_i*2^i). The trend of this current is generally that as the value of the input code increases, the current drawn from the reference voltage source also generally increases, and there are differences and jumps in the current values between adjacent code words.

[0009] This input code-dependent load variation can cause two major adverse effects:

[0010] First, it can cause a load modulation effect on the driving circuit of the reference voltage. When the input code switches rapidly, the dramatic changes in the load current can cause fluctuations in the reference voltage VREF output by the driving circuit, reducing the stability of the reference voltage.

[0011] Second, there are parasitic resistances in the transmission path of the reference voltage. The varying load current flowing through these parasitic resistances produces a fluctuating voltage drop (I x R drop), which also causes changes in the actual reference voltage applied to the R-2R resistance network.

[0012] The instability of the reference voltage caused by the above two factors directly worsens the performance indicators of the digital-to-analog converter, significantly increasing its integral non-linearity error (INL) and differential non-linearity error (DNL). In addition, this input code-dependent disturbance can also introduce harmonic distortion, affecting the spectral purity of the output analog signal.

[0013] Therefore, how to effectively compensate for the input load of the R-2R resistance type DAC so that the total current on the reference voltage source remains constant or smooth across all input code ranges has become a key technical challenge in improving the performance of this type of digital-to-analog converter. SUMMARY

[0014] The technical problem to be solved by the present application is to provide a technical solution that can effectively compensate for the input load variation of an R-2R resistance type DAC, to solve the problem of reference voltage instability and converter performance degradation caused by the variation of load current with input code in the prior art.

[0015] To solve the above technical problems, the present application provides an input load compensation circuit and method for an R-2R resistance type digital-to-analog converter (DAC). This solution cooperatively generates a compensation current that is complementary to the current fluctuations of the R-2R network itself by setting parallel trend compensation branches and adjacent code compensation branches, thereby keeping the total current on the reference voltage stable at different input codes and effectively improving the linearity and dynamic performance of the DAC.

[0016] According to an aspect of the present application, there is provided an input load compensation circuit for an R-2R resistor string digital-to-analog converter (DAC). The R-2R resistor string DAC receives an input code to generate an analog output, and the input load compensation circuit is coupled between a first reference voltage and a second reference voltage, the circuit comprising:

[0017] a trend compensation branch;

[0018] a neighbor code compensation branch;

[0019] wherein the trend compensation branch and the neighbor code compensation branch are both connected between the first reference voltage and the second reference voltage, and:

[0020] the trend compensation branch is configured to generate a first compensation current according to the input code, for compensating an overall trend of current on the reference voltage of the DAC increasing with the value of the input code;

[0021] the neighbor code compensation branch is configured to generate a second compensation current according to the input code, for compensating a difference of current on the reference voltage of the DAC between adjacent input codes.

[0022] Preferably, the input code is an N+1-bit input code.

[0023] Preferably, the trend compensation branch comprises a thermometer decoder for receiving the input code and outputting a thermometer code, and a first resistance network coupled to the output of the thermometer decoder.

[0024] Preferably, the first resistance network comprises a plurality of parallel resistance branches, and the outputs of the thermometer decoder control the on-off of the plurality of parallel resistance branches.

[0025] Preferably, the resistance values of the plurality of parallel resistance branches are in a decreasing relationship.

[0026] Preferably, the neighbor code compensation branch comprises an XOR gate circuit for performing XOR operation on the bits of the input code to generate a control signal, and a second resistance network coupled to the output of the XOR gate circuit.

[0027] Preferably, the inputs of the XOR gate circuit are the high N bits of the input code and the low N bits of the input code.

[0028] Preferably, the second resistance network comprises a plurality of parallel resistors, and the output of the XOR gate circuit controls the on-off of the plurality of parallel resistors.

[0029] Preferably, the resistance values of the plurality of parallel resistors are equal.

[0030] Preferably, the total current on the reference voltage varies in the range of 32 μA to 43 μA after applying the input load compensation circuit.

[0031] Preferably, the present application further provides an R-2R resistor type digital-to-analog converter, comprising: an R-2R resistor array connected between a first reference voltage and a second reference voltage; and an input load compensation circuit as described above.

[0032] According to another aspect of the present application, there is provided an input load compensation method for an R-2R resistor type digital-to-analog converter (DAC). The R-2R resistor type DAC receives an input code to generate an analog output, the method comprising: generating a first compensation current according to the input code for compensating a general trend of the current on a reference voltage of the DAC to increase with the value of the input code; generating a second compensation current according to the input code for compensating a difference of the current on the reference voltage between adjacent input codes; and providing the first compensation current and the second compensation current to the reference voltage.

[0033] Preferably, the input code is an N+1-bit input code.

[0034] Preferably, the generating the first compensation current comprises: decoding the input code with a thermometer decoder to generate a thermometer code; and controlling a first resistor network comprising a plurality of parallel resistor branches based on the thermometer code.

[0035] Preferably, the resistors in the plurality of parallel resistor branches in the first resistor network have resistances in a decreasing relationship.

[0036] Preferably, the generating the second compensation current comprises: performing an exclusive-OR operation on the input code to generate a control signal; and controlling a second resistor network comprising a plurality of parallel resistors based on the control signal.

[0037] Preferably, the plurality of parallel resistors in the second resistor network have equal resistances.

[0038] As described above, the input load compensation circuit, the digital-to-analog converter and the method for an R-2R resistor type DAC according to the present application have the following advantages:

[0039] The present application decomposes the complex current fluctuation problem into two aspects, i.e. the general trend and the difference between adjacent code words, and uses thermometer decoding and exclusive-OR logic to realize compensation respectively. This design idea is clear and efficient, and can accurately solve different types of load current fluctuation problems without introducing too much circuit complexity. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1Fig. 1 is a schematic diagram of a circuit structure of an R-2R resistor type DAC in the prior art;

[0041] Figure 2 Fig. 2 is a schematic diagram of a circuit of an input load compensation circuit according to an embodiment of the present application;

[0042] Figure 3 Fig. 3 is a schematic diagram of simulation results of total current on a reference voltage varying with input codes when the compensation circuit is not used according to the present application;

[0043] Figure 4 Fig. 4 is a schematic diagram of simulation results of total current on a reference voltage varying with input codes after the compensation circuit is used according to an embodiment of the present application. DETAILED DESCRIPTION

[0044] Other advantages and effects of the present application can be easily understood by those skilled in the art from the above description. The present application can also be implemented or applied in other different specific embodiments, and the details in the description can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0045] An input load compensation circuit for an R-2R resistor type digital-to-analog converter (DAC) is provided according to an embodiment of the present application. The R-2R resistor type DAC receives an input code to generate an analog output, and the input load compensation circuit is coupled to a first reference voltage and a second reference voltage.

[0046] The circuit includes a trend compensation branch and a neighbor code compensation branch. The trend compensation branch and the neighbor code compensation branch are both connected between the first reference voltage (e.g., VREFP) and the second reference voltage (e.g., VREFN).

[0047] The trend compensation branch is configured to generate a first compensation current according to the input code, for compensating an overall trend of the current on the reference voltage of the DAC increasing with the value of the input code; and

[0048] The neighbor code compensation branch is configured to generate a second compensation current according to the input code, for compensating a difference of the current on the reference voltage of the DAC between adjacent input codes.

[0049] Through such a double compensation mechanism, the circuit can effectively offset the current fluctuation of the R-2R resistor network itself caused by the change of the code word, so as to finally keep the total current drawn from the reference voltage source stable, which helps to weaken the load modulation effect on the reference voltage driving circuit and reduce the voltage fluctuation caused by the parasitic resistance, thereby improving the linearity (such as INL and DNL indicators) and dynamic performance of the DAC, and reducing the input code related harmonic distortion.

[0050] In some embodiments, the input code is an N+1-bit input code. More specifically, the input code can be represented as D <n:0>where D represents a digital input signal, <n:0>represents a bus that includes N+1 bits from bit 0 (the least significant bit) to bit N (the most significant bit).

[0051] In some embodiments, the trend compensation branch includes a thermometer decoder and a first resistance network. The thermometer decoder is configured to receive an input code and output a thermometer code; and the first resistance network is coupled to the output of the thermometer decoder and configured to generate a first compensation current based on the thermometer code. For example, the input code D <n:0>The input code is sent to a thermometer decoding circuit, which converts it into a 2^(N+1)-bit thermometer code. Each bit of the thermometer code is used to control a corresponding resistor branch in a first resistor network, which can be represented as R<2^(N+1)-1:0>. The resistors in the parallel resistor branches of the first resistor network have a decreasing resistance. This design of decreasing resistance can accurately generate a non-linear compensation current that is positively correlated with the value of the input code, thereby effectively fitting and offsetting the overall trend of the R-2R network current increasing with the code word.

[0052] In some embodiments, the neighbor code compensation branch includes an XOR gate circuit and a second resistor network. The XOR gate circuit is used to perform an XOR operation on the bits of the input code to detect the jump of the code word and generate a control signal; the second resistor network is coupled to the output of the XOR gate circuit and generates a second compensation current according to the control signal. Specifically, the high bit part D <n:1>(i.e., from bit 1 to bit N) and the low-order part D <n-1:0>(i.e., from the 0th bit to the N-1th bit) are performed. The N-bit output result of the operation can be expressed as SX <n-1:0>is used as a control signal to drive the second resistance network. The second resistance network is made up of a plurality of parallel resistors Ra <n-1:0>The resistance values of the multiple parallel resistors in the second resistance network are equal. This equal resistance value design simplifies the circuit layout and ensures consistency in compensation for any adjacent code transition, improving the reliability of the compensation.

[0053] Referring to Figure 2 , a circuit diagram of an input load compensation circuit according to one embodiment of the present application is shown. In order to more clearly illustrate the technical solutions of the present application, the following describes the 3-bit DAC compensation circuit shown in Figure 2 , which corresponds to the case of N = 2 in the general scheme described above. In this example, the input code is a 3-bit code D<2:0>. As shown in Figure 2 , the input code D<2:0> is fed into a 3-8 thermal decoder, which converts the 3-bit binary code into an 8-bit thermometer code output signal S<7:0>. The output signal S<7:0> controls eight parallel resistance branches through switches S<7> to S<0>, and the resistances in these branches are R7 to R0. In order to compensate for the overall change in current as the input code value increases, the resistance values of R7 to R0 are set to gradually decrease. At the same time, in order to compensate for the current difference between adjacent code words, the high two bits D<2:1> and the low two bits D<1:0> of the input code D<2:0> are fed into an XOR circuit to generate a 2-bit output signal SX<1:0>. This output signal SX<1:0> is used to control two additional parallel resistance branches through switches SX<1> and SX<0>, and the resistances of these branches are Ra1 and Ra0, respectively. In order to provide consistent compensation for code transitions, the resistance values of Ra1 and Ra0 are set to be equal.

[0054] In some embodiments, after applying the input load compensation circuit, the total current on the reference voltage varies in the range of 32 μA to 43 μA. According to the simulation results, compared to the large range of 0-38 μA of current fluctuation without compensation, the present circuit significantly narrows the current variation range, controlling the fluctuation amplitude within a smaller interval, proving the effectiveness of the compensation scheme and providing a stable reference voltage basis for achieving high-precision digital-to-analog conversion.

[0055] Referring to Figure 3 , a simulation result curve showing the total current on the reference voltage varying with the input code without using the compensation circuit of the present application is shown. As can be seen from Figure 3 , without compensation, the total current (vertical axis, in amperes) fluctuates dramatically with the input code (horizontal axis), with the current value varying in a wide range of 0 to about 38 μA. This significant current fluctuation is one of the main reasons for the degradation of DAC performance.

[0056] Referring to Figure 4 which shows the simulation result curve of the total current on the reference voltage after the compensation circuit of an embodiment of the present application is adopted. Compared with Figure 3 it can be clearly seen from Figure 4 that the stability of the total current is significantly improved after the compensation circuit of the present application is applied. The total current value is stabilized in a more narrow range, specifically between 32 μA and 43 μA. This result powerfully proves that the compensation scheme of the present application can effectively smooth the input load and provide a stable reference voltage basis for realizing high-precision digital-to-analog conversion.

[0057] The embodiment of the present application also provides an R-2R resistance type digital-to-analog converter, comprising: an R-2R resistance array connected between a first reference voltage and a second reference voltage; and the input load compensation circuit as described in any of the above embodiments, wherein the trend compensation branch and the adjacent code compensation branch of the input load compensation circuit are also connected between the first reference voltage and the second reference voltage.

[0058] The embodiment of the present application also provides an input load compensation method for an R-2R resistance type digital-to-analog converter (DAC), the R-2R resistance type DAC receiving an input code to generate an analog output, the method comprising: generating a first compensation current according to the input code, for compensating the overall trend that the current on the reference voltage of the DAC increases with the value of the input code; generating a second compensation current according to the input code, for compensating the difference of the current on the reference voltage between adjacent input codes; and providing the first compensation current and the second compensation current to the reference voltage, so that the total current on the reference voltage remains stable under different input codes. By superimposing the two compensation currents into the reference voltage path and the current consumed by the R-2R network itself, real-time and double-dimensional compensation of the load current is realized, and the purpose of stabilizing the total current is finally achieved.

[0059] In some embodiments, the generating of the first compensation current comprises: decoding the input code by using a thermometer decoder to generate a thermometer code; and controlling a first resistance network having a plurality of parallel resistance branches with resistance values in a decreasing relationship to generate the first compensation current based on the thermometer code.

[0060] In some embodiments, the generating of the second compensation current comprises: performing exclusive OR operation on the high N bits of the input code and the low N bits of the input code to detect the jump of the code word and generate a control signal; and controlling a second resistance network having a plurality of parallel resistances with equal resistance values to generate the second compensation current based on the control signal.

[0061] In some embodiments, the input code used in the method is an N+1-bit input code.

[0062] The core of the present invention is to generate a complementary current to the current fluctuation of the R-2R network by a parallel compensation circuit, which contains a part for compensating the overall trend and a part for compensating the difference between adjacent code words. The "thermometer decoder + decreasing resistance network" and "XOR gate + equivalent resistance network" described in the above embodiments are only two preferred ways to realize this core idea, but not the only way.

[0063] In other possible embodiments, the function of the trend compensation branch can be realized by other technical solutions.

[0064] For example, instead of using a thermometer decoder, a solution based on a lookup table or read-only memory (ROM) can be used. The input code can be input as an address, and the lookup table has pre-stored control signals for the compensation branch to be turned on for each input code. This way has high flexibility and can realize more complex non-linear compensation curves. Alternatively, a direct binary weighted compensation network can also be used, in which each bit of the input code directly controls a compensation unit with binary weight.

[0065] Similarly, the function of the adjacent code compensation branch can also have multiple alternative implementations.

[0066] The above embodiments detect the code word jump by a specific bit-wise XOR operation. In another embodiment, a latch can be set to store the input code at the previous time, and the current input code is compared with the input code at the previous time. When the two are not equal, a general digital logic circuit can generate one or more compensation pulses to smooth the transition according to the difference between the two code words. In addition, the logic circuit can be specially designed to activate compensation only when a major bit flip occurs (such as from 0111... to 1000...), because such a flip usually causes the largest current fluctuation.

[0067] Furthermore, from the bottom circuit structure, the unit that generates the compensation current is not limited to a passive resistance controlled by a switch. In other embodiments, the compensation branch can be realized by an array of one or more controllable current sources or current sinks. The output signals of the trend compensation logic and the adjacent code compensation logic will be used to control the opening, closing or current size of these current sources, thereby directly injecting or extracting precise compensation current to the reference voltage node. These current source units themselves can be copied from a high-precision bandgap reference current source through a current mirror, thereby improving the accuracy and stability of the compensation.

[0068] In summary, the present application concept covers all circuit structures and methods for generating trend compensation current and neighbor code difference compensation current by parallel resistance, controllable current source or other equivalent electronic components using digital or analog algorithm to stabilize the input load of R-2R resistance type DAC. Therefore, the protection scope of the present application should be defined by the appended claims.

[0069] It is to be understood that the above-mentioned embodiments are only illustrative of the basic idea of the present application, and the drawings only show the components related to the present application, not the number, shape and size of the components in actual implementation. The actual implementation of each component may be arbitrarily changed in shape, number and proportion, and the component layout may be more complex.

[0070] The above-mentioned embodiments only illustratively explain the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. An input load compensation circuit for an R-2R resistor string digital-to-analog converter (DAC) that receives an input code to produce an analog output, and the input load compensation circuit is coupled to a first reference voltage and a second reference voltage, characterized in that, comprises: a trend compensation branch; a neighbor code compensation branch; wherein the trend compensation branch and the neighbor code compensation branch are both connected between the first reference voltage and the second reference voltage, and: the trend compensation branch is configured to generate a first compensation current according to the input code, for compensating an overall change trend of the current on the reference voltage of the DAC as the input code value increases; the neighbor code compensation branch is configured to generate a second compensation current according to the input code, for compensating a difference of the current on the reference voltage between adjacent input codes.

2. The input load compensation circuit for an R-2R resistive digital-to-analog converter (DAC) of claim 1, wherein: The input code is an N+1-bit input code.

3. The input load compensation circuit for an R-2R resistor string digital-to-analog converter (DAC) of claim 1, wherein: The trend compensation branch comprises a thermometer decoder for receiving the input code and outputting a thermometer code, and a first resistance network coupled to the output of the thermometer decoder and configured to generate the first compensation current according to the thermometer code.

4. The input load compensation circuit for an R-2R resistor string digital-to-analog converter (DAC) of claim 3, wherein: The first resistance network comprises a plurality of parallel resistance branches, and the outputs of the thermometer decoder control the on-off of the plurality of parallel resistance branches.

5. The input load compensation circuit for an R-2R resistor string digital-to-analog converter (DAC) of claim 4, wherein: The resistances in the plurality of parallel resistance branches have a decreasing relationship.

6. The input load compensation circuit for an R-2R resistive digital-to-analog converter (DAC) of claim 1, wherein: The neighbor code compensation branch comprises an XOR gate circuit for performing XOR operation on the bits of the input code to detect the jump of the code word and generate a control signal, and a second resistance network coupled to the output of the XOR gate circuit and configured to generate the second compensation current according to the control signal.

7. The input load compensation circuit for an R-2R resistor string digital-to-analog converter (DAC) of claim 6, wherein: The inputs of the XOR gate circuit are the high N bits of the input code and the low N bits of the input code.

8. The input load compensation circuit for an R-2R resistor string digital-to-analog converter (DAC) of claim 6 or 7, wherein: The second resistance network comprises a plurality of parallel resistances, and the output of the XOR gate circuit controls the on-off of the plurality of parallel resistances.

9. The input load compensation circuit for an R-2R resistor string digital-to-analog converter (DAC) of claim 8, wherein: The resistances in the plurality of parallel resistances are equal.

10. The input load compensation circuit for an R-2R resistive digital-to-analog converter (DAC) of claim 1, wherein: After applying the input load compensation circuit, the total current on the reference voltage varies in the range of 32 μA to 43 μA.

11. An R-2R resistive digital-to-analog converter, characterized by comprises: an R-2R resistance array connected between a first reference voltage and a second reference voltage; and The input load compensation circuit of any one of claims 1 to 10, wherein the trend compensation branch and the neighbor code compensation branch of the input load compensation circuit are also connected between the first reference voltage and the second reference voltage.

12. A method for input load compensation for an R-2R resistor string digital-to-analog converter (DAC) that receives an input code to produce an analog output, the method comprising: comprises: generating a first compensation current according to the input code, for compensating an overall change trend of the current on the reference voltage of the DAC as the input code value increases; generating a second compensation current according to the input code, for compensating a difference of the current on the reference voltage between adjacent input codes; and providing the first compensation current and the second compensation current to the reference voltage, so that the total current on the reference voltage remains stable under different input codes.

13. The input load compensation method for an R-2R resistor string digital-to-analog converter of claim 12, wherein: The input code is an N+1-bit input code.

14. The input load compensation method for an R-2R resistor string digital-to-analog converter of claim 12, wherein: The generating of the first compensation current comprises decoding the input code using a thermometer decoder to generate a thermometer code, and controlling a first resistance network comprising a plurality of parallel resistance branches based on the thermometer code to generate the first compensation current.

15. The input load compensation method for an R-2R resistor string digital-to-analog converter of claim 14, wherein: The resistances in the plurality of parallel resistance branches in the first resistance network have a decreasing relationship.

16. The input load compensation method for an R-2R resistor string digital-to-analog converter of claim 12, wherein: The generating the second compensation current comprises: performing exclusive-OR operation on the high N bits of the input code and the low N bits of the input code to detect a jump of a code word and generate a control signal; and based on the control signal, controlling a second resistance network with multiple parallel resistances to generate the second compensation current.

17. The input load compensation method for an R-2R resistor digital-to-analog converter according to claim 16, wherein: The multiple parallel resistances in the second resistance network have equal resistance values.

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