Embedded system reset and restart circuit, electronic equipment and control method thereof
By linking the power control circuit, processor GPIO pins, watchdog timer, and reset circuit in the embedded system reset and restart circuit, the system achieves automatic restart after power failure, solving the problem of unreliable reset in the event of power failure in existing technologies, and improving the stability and reliability of the system.
Patent Information
- Application Number
- CN202511628301.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-07
- Publication Date
- 2026-02-06
AI Technical Summary
Existing embedded systems cannot reliably reset and restart in the event of a power outage, requiring the assistance of an external MCU, which increases costs and is not reliable enough.
Design an embedded system reset and restart circuit. By linking the power control circuit, the processor GPIO pins, the watchdog timer, and the reset circuit, the system power enable is directly controlled to achieve automatic restart of the system after power failure.
It ensures a complete reset of the system in case of crashes or abnormalities, avoids residual hardware states, achieves a complete reset from hardware to software, and improves the long-term operational stability of the system in unattended or harsh environments.
Smart Images
Figure CN121478095A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of embedded application technology, and in particular relates to an embedded system reset and restart circuit, electronic device and control method thereof. Background Technology
[0002] Currently, embedded technology is widely used, and various embedded products are ubiquitous in people's production and daily lives, bringing various enjoyments and conveniences. However, in the development and application of embedded products, in order to ensure that the system has high reliability and self-recovery capability, existing technologies usually adopt a "watchdog" (a dedicated reset chip) reset circuit design. However, traditional watchdog modules can only realize the reset operation when the system is not powered off (for example, if a product operates at high temperature for a long time, a chip enters an unrecoverable protection mode, and external power must be turned off to recover. In this case, watchdog reset alone will not work, and manual power-on may be required to restart). To realize power-off reset and restart (that is, high-reliability reset and restart), an external MCU-like unit is usually required to assist in implementation. However, the involvement of an MCU adds another layer of software unreliability and increases costs. However, this high-reliability reset and restart function is particularly important for some products with high reliability requirements.
[0003] Based on this, the present invention provides an embedded system reset and restart circuit, an electronic device, and a control method thereof. Summary of the Invention
[0004] To address the above technical problems, this invention provides an embedded system reset and restart circuit, an electronic device, and a control method thereof.
[0005] The technical solution adopted by this invention to solve its technical problem is: An embedded system reset and restart circuit includes: Power control circuit, used to control the enable signal of the system power supply; The processor system is configured with at least two GPIO pins. The first GPIO pin is defined as the output terminal of the watchdog enable control signal, and the second GPIO pin is defined as the output terminal of the processor system active power-down restart signal. The watchdog and reset circuits are as follows: the watchdog circuit is connected to the processor system and is used to output a watchdog timeout signal to the power control circuit when the watchdog times out due to abnormal operation of the processor system; the reset circuit is used to generate a reset release signal after the system power output is normal, so that the processor system enters the reset release state and ensures reliable system reset. When the power control circuit receives an active power-down restart signal or a watchdog timeout signal, it pulls the system power enable signal low to shut down the system power. Subsequently, the system power enable signal is automatically reset and pulled high due to the shutdown of the system power, thus enabling the system power again and achieving automatic restart after a power failure.
[0006] Preferably, the power control circuit controls the system power enable signal through a switching transistor and includes a NOT gate circuit. The input of the NOT gate circuit receives a watchdog timeout signal, and the output of the NOT gate circuit, together with the active power-down restart signal, is connected to the control logic of the switching transistor to control the switching transistor's on and off states. When the NOT gate circuit outputs a valid level or the active power-down restart signal is valid, the switching transistor is turned on, pulling the system power enable signal low.
[0007] Preferably, the watchdog circuit in the watchdog and reset circuit is an external watchdog circuit or a watchdog module integrated inside the processor system; when using an internal watchdog module, the watchdog timeout signal is directly output by the GPIO pin of the processor system.
[0008] Preferably, the system operating states include: system shutdown state, system power-on state, system power-enabled state, system power-normal state, system reset release state, watchdog start and business software running state, system power-enabled off state, and system power failure and system power failure state; wherein, from the watchdog start and business software running state to the triggering of power failure reset, the system successively enters the system power enabled off state and the system power failure and system power failure state, and then automatically returns to the system power enabled state and restarts the system.
[0009] Preferably, during normal operation, the processor system activates the watchdog circuit via a watchdog enable signal and periodically outputs a watchdog feed signal via the third GPIO pin configured by the processor system to prevent the watchdog circuit from generating a timeout signal.
[0010] Preferably, the switching transistor is a field-effect transistor, and its control terminal is controlled by the output signal of the NOT gate circuit and the active power-down restart signal output by the CPU. When either of them outputs a valid high level, the switching transistor is turned on, pulling the system power enable signal down to a low level.
[0011] Preferably, the system power supply includes a multi-stage voltage output module that generates different voltages, and the power control circuit shuts down the entire system power supply by enabling the first stage power supply inside the system power supply.
[0012] Preferably, it also includes a power normal signal for monitoring the status of each power supply level. When all monitored power supplies at each level are working normally, the power normal signal is at a high level, triggering the reset circuit to generate a processor reset release signal.
[0013] An electronic device including an embedded system reset / reboot circuit.
[0014] A control method based on an embedded system reset and restart circuit, the method includes the following steps: When the system is powered on, the system power supply is enabled, and the various power supplies inside the system power supply are started in sequence. After the power supply at each level is established normally, the processor system releases the reset signal, the processor system starts and runs the business software, and at the same time outputs the watchdog enable signal through the first GPIO pin to start the watchdog function. When the watchdog circuit outputs a watchdog timeout signal because it has not received a watchdog feed signal in time, or when the processor system actively outputs a power-down restart signal through the second GPIO pin, the system power enable signal is pulled low, thereby shutting down the system power. After a power outage, the system power enable signal is automatically reset and pulled high due to the loss of power, re-enabling the system power supply, and the system automatically completes one power outage restart cycle.
[0015] The aforementioned embedded system reset and restart circuit, electronic device, and control method, through the coordinated design of the power control circuit, processor GPIO pins, and integrated watchdog reset circuit, directly control the system power enable, forcibly shut down the entire system power, clear any hardware state residue, and ensure a complete reset from hardware to software. The system automatically restores power enable after a power outage and restarts upon power-on, forming a closed-loop control that effectively solves the problem of potentially ineffective software resets. Attached Figure Description
[0016] Figure 1 Block diagram for designing a conventional reset circuit for an embedded system; Figure 2 This is a block diagram illustrating the design principle of the embedded system reset and restart circuit of this invention. Figure 3 This is a diagram showing the working state of the embedded system reset and restart circuit of the present invention. Figure 4 This is a reference diagram for the design of the embedded system reset and restart circuit of the present invention. Detailed Implementation
[0017] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings.
[0018] Figure 1This is a common reset (watchdog) startup design block diagram for embedded systems. After the power output of each stage of the system is normal (PWR_GOOD), the reset chip is triggered to start resetting the processor system. After the software starts running, it will activate an external or internal watchdog timer (some systems use a serial port to send heartbeats to an auxiliary MCU system to simulate the watchdog function). In this way, the system runs normally and continuously monitors the watchdog heartbeat to maintain system reliability. However, this method cannot achieve power-off restart of the system; if the system crashes, it will only reset the processor system (without cutting off the entire power supply). This invention studies the startup principle of the power supply and designs a linkage between the power control circuit, watchdog timer, and reset circuit. In this way, only some simple peripheral components are needed to achieve power-off reset and restart control of the system, i.e., high-reliability reset and restart.
[0019] In one embodiment, an embedded system reset and restart circuit includes: Power control circuit, used to control the enable signal of the system power supply; The processor system is configured with at least two GPIO pins. The first GPIO pin is defined as the output terminal of the watchdog enable control signal, and the second GPIO pin is defined as the output terminal of the processor system active power-down restart signal. The watchdog and reset circuits are as follows: the watchdog circuit is connected to the processor system and is used to output a watchdog timeout signal to the power control circuit when the watchdog times out due to abnormal operation of the processor system; the reset circuit is used to generate a reset release signal after the system power output is normal, so that the processor system enters the reset release state and ensures reliable system reset. When the power control circuit receives an active power-down restart signal or a watchdog timeout signal, it pulls the system power enable signal low to shut down the system power. Subsequently, the system power enable signal is automatically reset and pulled high due to the shutdown of the system power, thus enabling the system power again and achieving automatic restart after a power failure.
[0020] The aforementioned embedded system reset and restart circuit, through the coordinated design of the power control circuit, processor GPIO pins, watchdog timer, and reset circuit, achieves a complete power-off self-restart of the system in the event of a crash or active triggering. Unlike traditional watchdog resets that only reset the processor, this invention directly controls the system power enable, forcibly shutting down the entire system power, clearing any hardware state remnants, and ensuring a complete reset from hardware to software. The system automatically restores power enable after a power outage and restarts upon power-up, forming a closed-loop control system that effectively solves the problem of potentially ineffective software resets.
[0021] In one embodiment, the power control circuit controls the system power enable signal through a switching transistor and includes a NOT gate circuit. The input of the NOT gate circuit receives a watchdog timeout signal, and the output of the NOT gate circuit, together with the active power-down restart signal, is connected to the control logic of the switching transistor to control the switching transistor's on and off states. When the NOT gate circuit outputs a valid level or the active power-down restart signal is valid, the switching transistor is turned on, pulling the system power enable signal low.
[0022] In one embodiment, the switching transistor is a field-effect transistor, and its control terminal is controlled by the output signal of the NOT gate circuit and the active power-down restart signal output by the CPU. When either of them outputs a valid high level, the switching transistor is turned on, pulling the system power enable signal down to a low level.
[0023] In one embodiment, the watchdog circuit in the watchdog and reset circuit is an external watchdog circuit or a watchdog module integrated inside the processor system; when using an internal watchdog module, the watchdog timeout signal is directly output from the GPIO pin of the processor system.
[0024] In one embodiment, the processor system starts the watchdog circuit via a watchdog enable signal during normal operation, and periodically outputs a watchdog feed signal via a third GPIO pin configured by the processor system to prevent the watchdog circuit from generating a timeout signal.
[0025] Specifically, the watchdog circuit (external or internal) continuously monitors the processor's operating status. When external, it periodically feeds a signal to the third GPIO pin configured in the processor system to detect whether the system is running. If a timeout occurs, the watchdog circuit outputs a timeout signal, triggering the power control circuit to shut down the system. This mechanism can respond promptly to anomalies such as system crashes and program crashes, preventing prolonged system stagnation and achieving automatic fault recovery. Furthermore, the watchdog circuit can be flexibly configured as external or internal, compatible with different system architectures, reducing design complexity.
[0026] The watchdog and reset circuit generates a reset release signal after the system power is restored, ensuring that the processor only starts when the power supply is stable, thus avoiding startup failures caused by power fluctuations or timing issues. This circuit works in conjunction with the normal power signal (PWR_GOOD) to guarantee the reliability of the processor initialization environment and reduce the risk of false system startup or data corruption. Furthermore, the reset circuit supports multi-level power monitoring, further enhancing the robustness of system startup.
[0027] Specifically, such as Figure 2As shown in the diagram, the most significant feature of the new design is the implementation of system power control (P5V_EN in the example). Simultaneously, the processor system adds two GPIO pins to control the activation of the external watchdog timer (if the actual system's main control chip has an internal watchdog timer, that can be used) and directly control the system's power-down reset and restart. Once the processor actively controls the system to lose power (or the watchdog timeout occurs), the system power enable pin is pulled low, shutting down all power. At this point, both the processor system and the high-reliability reset and restart circuit module lose power. The previously pulled-low system power enable pin is then released and pulled high again, re-enabling the system power. The system then restarts, resets, and begins running the system software. This achieves the entire system's power-down self-restart process.
[0028] In one embodiment, the system operating states include: system shutdown state, system power-on state, system power-enabled state, system power-normal state, system reset release state, watchdog start and business software running state, system power-enabled off state, and system power failure and system power failure state; wherein, from the watchdog start and business software running state to the triggering of power failure reset, the system successively enters the system power enabled off state and the system power failure and system power failure state, and then automatically returns to the system power enabled state and restarts the system.
[0029] Specifically, such as Figure 3 As shown, an embedded system initially operates in a state of no power, called S0 (system shutdown). When power is supplied (or the power is turned on), it enters the S1 (system power-on) state. Upon power-on, the system defaults to enabling each power supply level, entering the S2 (system power-enabled) state. Subsequently, each power supply level starts its output in a predetermined sequence until the S3 (system power normal) state. Once the power is normal, the system reset module is triggered to release the processor system's reset signal, entering the S4 (system reset released) state. Afterward, the system normally loads drivers and initializes, enables the watchdog timer, and begins running the application software, thus entering the S5 (watchdog timer startup and application software running) state. In state S5... In this state, if a system crash occurs (causing the watchdog timeout) or a user actively sends a power-down reset and restart signal, the aforementioned high-reliability reset and restart circuit module will disable the system power supply, i.e., the system enters the S6 (system power supply disabled) state. As the system power supply is disabled, the power supplies at each level of the system will begin to drop, eventually entering the S7 (system power failure) state. Once the S7 state stabilizes or meets the decision conditions, the system power supply enable pin, which was originally controlled by the high-reliability reset and restart circuit module, will be re-enabled due to the power failure of the system. In this way, the system returns to the S2 (system power enabled) state and starts a new startup process after the power failure.
[0030] Normally, the system operates under S5 conditions. The high-reliability reset and restart circuit module will only be triggered to start the power-down reset and restart process when the system crashes or is actively triggered by the user (such as during upgrades, debugging restarts, or remote command restarts).
[0031] In one embodiment, the system power supply includes a multi-stage voltage output module that generates different voltages, and the power control circuit shuts down the entire system power supply by enabling the first stage power supply inside the system power supply.
[0032] Specifically, by controlling the enable signal of the first-stage power supply to shut down all subsequent power supplies, this strategy simplifies power management logic and ensures synchronized power cut-off and restoration across the entire system. This design reduces the need for direct control of multiple power supplies, lowers circuit complexity, and guarantees thorough power outage. The dependencies between subsequent power supplies ensure that the system powers on according to a predetermined sequence upon restart, avoiding power contention or timing issues.
[0033] In one embodiment, an embedded system reset and restart circuit further includes a power normal signal for monitoring the power status of each level. When all monitored power levels are working normally, the power normal signal is at a high level, triggering the reset circuit to generate a processor reset release signal.
[0034] Specifically, the high-reliability reset and restart circuit can be optimized according to the actual situation of the system. For example, some reset systems use 1.8V or 2.5V, so different chips need to be replaced accordingly. Some systems have a built-in watchdog, so the external watchdog circuit needs to be removed and the timeout output pin of the built-in watchdog needs to be used for corresponding control to achieve power-down reset and restart. The design is flexible and can be adjusted according to different systems.
[0035] The following is a brief description of the design practice and working process of the external watchdog circuit: Assuming that the first stage power supply of the system is 12V, the first stage power supply output is 5V, and all subsequent power supply circuits use 5V power supply, then cutting off the 5V output of the first stage power supply can shut down all subsequent power supplies of the system. Figure 4In the diagram, assuming the system is powered on, pin 1 of Q1 is pulled low by default when the system is not powered, so Q1 is not conducting. At this time, pin 3 of Q1 outputs a high level (Power_IC_EN signal), enabling the first-stage power supply and outputting 5V. Then, each stage of the system's power supply powers on according to a predetermined sequence until all power supplies are outputting normally, generating a PWR_GOOD logic 1 signal on pin D1 (this signal is low when any stage of the power supply is abnormal). At this point, pin 7 of U4 outputs a high level, starting the processor system (CPU) reset, and then the processor system begins to boot. The processor system's "PWR_reboot" is initially low by default (internal pull-down). As long as the software does not control this pin, pin 1 of Q1 will be low, not affecting Q1's shutdown. The processor system's "WDG_EN" is also initially low by default (internal pull-down). As long as the software does not control this pin, Q2 cannot be turned on, and the input of U3 (NOT gate) is high, then inverted and outputs a low level, also not affecting the shutdown state of Q1. When the system is booting up, the watchdog timer is enabled by the processor starting the watchdog timer (WDI) by pulling the "WDG_EN" pin high. If the watchdog timeout occurs, pin 1 of Q2 is high and pin 2 of Q2 is low (WDO is low on timeout). This turns Q2 on, causing pin 3 of Q2 to also go low. The input to U3 is then low, which, after inversion, outputs a high level. This high level turns on Q1, causing the "Power_IC_EN" signal to go low. Therefore, the first-stage 5V power supply is turned off due to the enable pin being pulled low. Similarly, if the processor actively pulls "PWR_reboot" high for a task, it will also turn on Q1 and turn off the first-stage 5V power supply. When the system 5V is turned off, the power supply of the subsequent stages will also be de-energized (e.g., 3.3V). At this time, U3 cannot output a high level, and the processor system cannot output a high level either. Then Q1 returns to the non-conducting state, and the 5V enable pin "Power_IC_EN" of the system's primary power supply is pulled high again. The power supply of the subsequent stages of the system starts to receive power again until the reset chip outputs a normal reset, and the system reloads the software to run the task.
[0036] The aforementioned embedded system reset and restart circuit enables self-recovery control of the embedded system power supply. When the embedded system software is not involved or actively triggered, the system can power on and operate normally (i.e., power is enabled by default). Once the system initiates reverse logic control on relevant chip pins (CPU active trigger or watchdog timeout trigger), the system power supply is disabled, causing the system power output to shut down. When the system power is off, the aforementioned pin states return to their initial states, thus restoring the system power supply enable control pins to their initial state (i.e., enabled by default). The system power supply then resumes its output according to the predetermined sequence, and the system begins its second normal startup process. This circuit significantly improves the long-term operational stability of embedded systems in unattended or harsh environments, reduces maintenance requirements, and is suitable for high-reliability applications such as industrial control and IoT devices.
[0037] In one embodiment, an electronic device is also provided, including an embedded system reset and restart circuit.
[0038] For specific limitations regarding an electronic device including an embedded system reset and restart circuit, please refer to the limitations regarding an embedded system reset and restart circuit mentioned above, which will not be repeated here.
[0039] In one embodiment, a control method for an embedded system reset and restart circuit is also provided, the method comprising the following steps: When the system is powered on, the system power supply is enabled, and the internal power supplies at each level are started sequentially. After the power supply at each level is established normally, the processor system releases the reset signal, the processor system starts and runs the business software, and at the same time outputs the watchdog enable signal through the first GPIO pin to start the watchdog function. When the watchdog circuit outputs a watchdog timeout signal because it has not received a watchdog feed signal in time, or when the processor system actively outputs a power-down restart signal through the second GPIO pin, the system power enable signal is pulled low, thereby shutting down the system power. After a power outage, the system power enable signal is automatically reset and pulled high due to the loss of power, re-enabling the system power supply, and the system automatically completes one power outage restart cycle.
[0040] For specific limitations on the control method of an embedded system reset and restart circuit, please refer to the limitations on an embedded system reset and restart circuit mentioned above, which will not be repeated here.
[0041] The above provides a detailed description of an embedded system reset and restart circuit, electronic device, and control method provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the core ideas of the invention. It should be noted that those skilled in the art can make various improvements and modifications to the invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention.
Claims
1. An embedded system reset and restart circuit, characterized in that, include: Power control circuit, used to control the enable signal of the system power supply; The processor system is configured with at least two GPIO pins. The first GPIO pin is defined as the output terminal of the watchdog enable control signal, and the second GPIO pin is defined as the output terminal of the processor system active power-down restart signal. The watchdog and reset circuits are as follows: the watchdog circuit is connected to the processor system and is used to output a watchdog timeout signal to the power control circuit when the watchdog times out due to abnormal operation of the processor system; the reset circuit is used to generate a reset release signal after the system power output is normal, so that the processor system enters the reset release state and ensures reliable system reset. When the power control circuit receives an active power-down restart signal or a watchdog timeout signal, it pulls the system power enable signal low to shut down the system power. Subsequently, the system power enable signal is automatically reset and pulled high due to the shutdown of the system power, thus enabling the system power again and achieving automatic restart after a power failure.
2. The embedded system reset and restart circuit as described in claim 1, characterized in that, The power control circuit controls the system power enable signal through a switching transistor and includes a NOT gate circuit. The input of the NOT gate circuit receives the watchdog timeout signal, and the output of the NOT gate circuit, together with the active power-down restart signal, is connected to the control logic of the switching transistor to control the switching transistor's on and off states. When the NOT gate circuit outputs a valid level or the active power-down restart signal is valid, the switching transistor is turned on, pulling the system power enable signal low.
3. The embedded system reset and restart circuit as described in claim 2, characterized in that, The watchdog circuit in the watchdog and reset circuit can be an external watchdog circuit or a watchdog module integrated into the processor system; when using an internal watchdog module, the watchdog timeout signal is directly output from the GPIO pin of the processor system.
4. The embedded system reset and restart circuit as described in claim 3, characterized in that, During normal operation, the processor system activates the watchdog circuit via the watchdog enable signal and periodically outputs the watchdog feed signal through the third GPIO pin configured by the processor system to prevent the watchdog circuit from generating a timeout signal.
5. The embedded system reset and restart circuit as described in claim 4, characterized in that, The system's operating states include: system shutdown, system power-on, system power-enabled, system power-normal, system reset release, watchdog timer startup and business software operation, system power-enabled shutdown, and system power failure. From the watchdog timer startup and business software operation state to the triggering of a power failure reset, the system successively enters the system power-enabled shutdown state and the system power failure state, before automatically returning to the system power-enabled state and restarting the system.
6. The embedded system reset and restart circuit as described in claim 5, characterized in that, The switching transistor is a field-effect transistor. Its control terminal is controlled by the output signal of the NOT gate circuit and the active power-down restart signal output by the CPU. When either of them outputs a valid high level, the switching transistor is turned on, pulling the system power enable signal low.
7. The embedded system reset and restart circuit as described in claim 6, characterized in that, The system power supply includes multiple voltage output modules that generate different voltages. The power control circuit shuts down the entire system power supply by enabling the first-stage power supply inside the system power supply.
8. The embedded system reset and restart circuit as described in claim 7, characterized in that, It also includes a power normal signal for monitoring the status of each power supply level. When all monitored power supplies are working normally, the power normal signal is high, triggering the reset circuit to generate a processor reset release signal.
9. An electronic device, characterized in that, Includes an embedded system reset and restart circuit as described in any one of claims 1 to 8.
10. A control method based on a reset / restart circuit as described in any one of claims 1 to 8, characterized in that, The method includes the following steps: When the system is powered on, the system power supply is enabled, and the various power supplies inside the system power supply are started in sequence. After the power supply at each level is established normally, the processor system releases the reset signal, the processor system starts and runs the business software, and at the same time outputs the watchdog enable signal through the first GPIO pin to start the watchdog function. When the watchdog circuit outputs a watchdog timeout signal because it has not received a watchdog feed signal in time, or when the processor system actively outputs a power-down restart signal through the second GPIO pin, the system power enable signal is pulled low, thereby shutting down the system power. After a power outage, the system power enable signal is automatically reset and pulled high due to the loss of power, re-enabling the system power supply, and the system automatically completes one power outage restart cycle.