Method and assembly wire mesh for processing semiconductor wafers

Abstract

The invention relates to a method for processing a wafer (100), comprising the following steps: providing the wafer having a structure for a plurality of chips (120) and having a first surface and a second surface opposite the first surface, providing a wire mesh (300) having a base (320) and one or more support structures (310) arranged on the base, the invention relates to a method for producing a wafer comprising one or more support structures of a wire mesh, separating the wafer into the chips, each chip having a surface to be protected (122b), removing the chips from the wafer, placing at least a portion of the removed chips on the one or more support structures of the wire mesh in such a way that a desired arrangement of the placed chips is achieved, the surface to be protected is directed towards the bottom of the wire mesh and is not in direct contact with the one or more support structures, and subsequently connecting the placed chips to a common element, the placement of the placed chips relative to each other being maintained.

Description

Technical Field

[0001] This invention relates to the field of manufacturing chips, particularly for microelectromechanical devices, from wafers, and to a method for processing wafers and a screen for placing chips. Background Technology

[0002] Devices incorporating microelectromechanical systems (MEMS), such as micromirror arrays or micromirror actuators, are now used in a variety of devices, including smartphones, projectors, head-up displays, barcode readers, mask exposure equipment in semiconductor processing, and microscopes. Corresponding micromirror arrays are known, for example, from documents DE 10 2013 208446 A1, EP 0 877 272 A1, and WO 2010 / 049076 A2. DE 10 2006 032 195 A1 describes a method for fabricating MEMS structures. DE 10 2009 029 202 A1 discloses a micromechanical system and a method for fabricating such a system. The EPyC process (epitaxial polysilicon cycle) for fabricating microelectromechanical structures with large vertical stretching scales is known from DE 10 2015 206 996 A1. The epitaxial polysilicon is used as both a functional and sacrificial material and a layered structure consisting of epitaxial polysilicon layers is constructed by repeated cycles.

[0003] When manufacturing individual microelectromechanical systems (MEMS) on a wafer-based basis, it is essential to ensure continuous protection of the system's MEMS structures to avoid unwanted damage to the MEMS chip. Thus, the surfaces to be protected are typically temporarily protected by suitable protective structures, but these structures significantly reduce the fill factor of the final product, i.e., the manufactured chip. Summary of the Invention

[0004] According to the present invention, a method for processing wafers and a wire mesh for placing chips with surfaces to be protected are provided.

[0005] According to a first aspect of the invention, a method for processing semiconductor wafers (also referred to as wafers within the framework of the invention) is provided. The method includes providing a wafer preferably having silicon or made of silicon. The wafer has a structure for multiple semiconductor chips (also referred to as chips within the framework of the invention) and has a first surface and a second surface opposite to the first surface. The first and second surfaces are thus two distinct bottom surfaces of the wafer. Furthermore, an assembly wire mesh (also referred to as wire mesh within the framework of the invention) is provided, having a bottom, for example, in the form of a base plate, and one or more support structures disposed on the base plate. After separating the wafer into chips, wherein each chip has a surface to be protected, the chip is removed from the wafer. Thus, each chip is removed from the remaining wafer (the remaining portion of the wafer). In this case, the surface to be protected of the chip is the surface for which the chip seeks protection. The one or more support structures of the wire mesh may, for example, take the form of continuous or interrupted walls, arcs, grids, struts, and / or pillars preferably arranged in a raster. In particular, the one or more support structures can be in the form of one or more rectangular, triangular, hexagonal, and / or trapezoidal frames and / or one or more rectangular, triangular, hexagonal, and / or trapezoidal grids. Especially in the case of multiple support structures, all support structures of the wire mesh can have the same form, such as the form of rectangular, triangular, hexagonal, or trapezoidal frames or rectangular, triangular, hexagonal, or trapezoidal grids.

[0006] Subsequently, at least a portion of the removed chip is placed on one or more support structures of the screen to achieve the desired arrangement, i.e., position and orientation, of the placed chip such that the surface to be protected of the placed chip faces the bottom of the screen and does not directly contact the one or more support structures. The placed chip is then connected to a common element, such as an electronic device, wherein the arrangement of the placed chips relative to each other is maintained. The proposed method is used to achieve an optimized and defined mutual arrangement of separate chips using a screen. Preferably, the screen is implemented such that the chips, after being placed on the support structures, are arranged in a common plane and, in particular, leveled with respect to an axis perpendicular to the surface to be protected.

[0007] Advantageously, the wafer has a retaining structure and / or is constructed within the wafer before or during separation, wherein the retaining structure is configured to restrict possible movement of the chip in at least one direction perpendicular to a first surface of the wafer after separation. The retaining structure may, for example, protrude from suitable protrusions (receiving tabs) on the chip and / or the remaining wafer. The retaining structure may, for example, be arranged on the edge of the chip to be detached by separation and / or as part of the remaining wafer and is used to hook the chip to the remaining wafer after separation, thereby preventing free movement of the chip in a direction perpendicular to the first surface of the wafer. In this way, for example, the chip can be prevented from falling off when the wafer is pointing horizontally (i.e., perpendicular to the direction of gravity). In this case, when the retaining structure is part of the remaining wafer, the retaining structure is preferably configured such that it does not touch the surface of the chip to be protected during hooking.

[0008] Furthermore, prior to wafer separation, a slot structure with multiple slots can be constructed within the wafer, surrounding a single chip and partially perforating the wafer, with the separation occurring at least partially along these slots. In this case, constructing the slot structure with partial perforation preferably results in tabs protruding between the slots, the tabs extending horizontally or vertically about a first surface and holding the chip within the wafer. The tabs connect the chip to the remainder of the wafer. Alternatively, during wafer separation, a slot structure with one or more slots surrounding a single chip and continuously penetrating the wafer can be constructed within the wafer, with the separation occurring at least partially by constructing the slot structure. In the case of a continuously penetrating slot structure, unlike the slot structure with partial perforation, tab protrusion is not performed. The chip to be detached from the wafer is completely (in the case of a continuously penetrating slot structure) or partially (in the case of a slot structure with partial perforation) separated from the remaining wafer by constructing the slot structure. This method allows the chip to be easily removed from the wafer, for example, when removing the chip from the protective device. In the case of a slot structure with partial perforation, chip removal can correspond to the separation, as the separation is achieved, for example, by simply breaking off the tab, in which case the chip is simply folded out of the wafer. The tab can also be evaporated by using a suitable laser cutting method. This has the advantage that the tab is completely removed without producing uncontrolled fragments. If a continuous through-hole slot structure is constructed, the separation can be performed by constructing the slot structure. Therefore, separate separation is not required. The slot structure can consist of non-interconnected grooves, for example, a slot-shaped groove surrounding each chip can be provided. The overall arrangement of the slots is referred to as a slot structure within the framework of this invention. A slot structure with partial perforation is correspondingly a type of slot structure, which, in contrast to a continuous through-hole slot structure, does not form a closed shape. Separating wafers by constructing gap structures within them is particularly advantageous because, in this case, the release of particles that could lead to contamination of sensitive structures on the wafer can be completely avoided.

[0009] Within the framework of this invention, a slot structure is understood as one or more grooves in a wafer that penetrate the wafer completely in the vertical direction. Separation of the wafer along a slot structure with partial perforations refers to a separation in which multiple grooves of the slot structure are used to remove a chip from the remaining wafer by means of disruption, such as breakage, of the remaining connection (e.g., in the form of a splice) between the chip and the remaining wafer. The slots in the slot structure can differ from simple slots extending vertically through the wafer, i.e., rectangular grooves and notches; for example, a horizontally extending region of the slot, i.e., parallel to the first surface of the wafer, is conceivable. In particular, the slots can be configured such that at least a partially formed retaining structure is formed, which, as described above, retains the individual chips within the wafer after separation, i.e., specifically restricts the movement of the individual chips in a particular direction after separation, so as to, for example, prevent the individual chips from accidentally detaching from the wafer during wafer movement. The retaining structure can exist not only in the presence of slot structures with partial perforations but also in the presence of continuously penetrating slot structures.

[0010] Preferably, the slits are constructed using an etching process, thus creating continuous through-slit structures and / or partially perforated slit structures. In this case, deep reactive ion etching (DRIE) can be used as the etching method. Such an etching process is preferably combined with an etching process for releasing chip structures, such as MEMS structures, such as silicon sacrificial layer etching (also known as sacrificial layer etching), so that in one method step, not only are continuous through-slit structures and / or partially perforated slit structures constructed, but also said structures of the chip are released. For example, complex structures, such as retaining structures, can be produced by the EPyC process, which are released within such a sacrificial layer etching framework.

[0011] Preferably, the structure for the chip has a MEMS structure for microelectromechanical systems (MEMS), wherein the surface to be protected is part of the MEMS structure. A chip having a MEMS structure is referred to as a MEMS chip within the framework of this invention. In this case, the release of the MEMS structure occurs before or during the separation of the wafer by sacrificial layer etching, and preferably in conjunction with the construction of a slot structure that surrounds a single chip and partially or continuously extends through the wafer. Particularly advantageously, these open MEMS structures include MEMS structures for micromirror arrays.

[0012] According to a second aspect of the invention, a screen for placing a chip with a surface to be protected is provided, preferably for use in the method described above. In this case, the screen comprises, for example, a bottom in the form of a base plate and one or more support structures disposed on the bottom. In this case, the support structures are configured such that the chip can be placed on the one or more support structures such that the surface of the chip to be protected does not directly contact the one or more support structures.

[0013] Preferably, one or more support structures have the form of one or more rectangular, triangular, hexagonal, and / or trapezoidal frames and / or one or more rectangular, triangular, hexagonal, and / or trapezoidal grids, thus defining notches in the screen for placing the chip and protecting the surface to be protected, such as a MEMS structure. In particular, in the case of multiple support structures, all support structures of the screen can have the same form, such as rectangular, triangular, hexagonal, or trapezoidal frames or rectangular, triangular, hexagonal, or trapezoidal grids. The notches defined by one or more frames and / or one or more grids preferably have one or more walls (e.g., sidewalls or bottom) with one or more channels suitable for applying low pressure or vacuum to adsorb the chip placed on the notch. In addition to these optional channels, the walls of the notches are preferably sealed or only have low permeability.

[0014] It is also conceivable that at least a portion, or preferably the entire bottom or the entire mesh, of the screen is at least partially transparent to light in a certain wavelength range. Typically, the screen can have both transparent and opaque materials in a specific wavelength range. In this case, the light is understood as electromagnetic beams in the visible range of the electromagnetic spectrum, as well as ultraviolet and infrared beams. This enables optical testing and measurement to be performed on a single chip. Correspondingly, it is advantageous to use a material that is transparent in or at a desired wavelength range for a portion of the screen, such as the bottom or a portion of the bottom. Possible wavelength ranges include, for example, the UV range, the visible range, and the IR range. The material can be selected according to the wavelength to achieve transparency. Examples of suitable optical measurement methods are measurements performed by a white light interferometer (e.g., in the wavelength range of 400 to 800 nm) or by a laser vibrometer (e.g., at wavelengths of 633 or 1550 nm). Therefore, at least a portion, or preferably the entire bottom or the entire mesh, of the screen can be made of or have glass. For example, borosilicate glass, quartz glass, or sapphire glass are suitable as the glass. Other light-transmitting materials are also conceivable as alternatives to glass. For example, silicon can be used as an IR-transmitting material for measurements in the IR range.

[0015] Advantages of the invention The present invention discloses a method and an apparatus suitable for protecting semiconductor chips, such as MEMS chips, from damage and / or contamination during the manufacturing process of components while ensuring a high fill rate.

[0016] Therefore, the assembly screen proposed and used in the method enables the chips to be arranged in a predetermined manner after separation from the based wafer and then processed further, i.e., connected to another common component. Such a method also enables high throughput of the components to be manufactured, as the chips can be selected before being connected to the common component. When the screen is implemented optically, the chips can undergo optical testing, such as wafer-level testing, before and / or after connection to another common component. Furthermore, the correspondingly implemented screen enables the leveling of the chips along an axis perpendicular to the surface to be protected.

[0017] This leads to another advantage: it eliminates the need for bonding methods, such as those typically involving gluing or bonding the chip to the screen. Therefore, the support structure can be configured much narrower compared to that required in cases of shielding bonding or bonding. This enables a higher fill factor than many solutions known from the prior art. The screen can be configured such that low pressure or vacuum can be applied to temporarily hold the chip in place, if desired. Modifying the screen design also allows for a more flexible arrangement of the chips relative to each other, and thus a more cost-effective way to adapt wiring to the components being manufactured. Attached Figure Description

[0018] Embodiments of the present invention will be further explained with reference to the accompanying drawings and the following description.

[0019] The attached diagram shows: Figure 1 : A schematic diagram illustrating a cross-section of a wafer having a chip according to the method of the present invention; Figure 2 A schematic diagram of a cross-section of a wafer having a chip, corresponding to the removal of a chip according to the method of the present invention; Figure 3 : A schematic diagram showing the chip being placed on a wire mesh according to the method of the present invention; Figure 4 A schematic cross-section of a chip placed in a wire mesh according to the invention, the chip being connected to a common component according to the method of the invention; and Figure 5 An exemplary method according to the invention for processing wafers is schematically illustrated in flowchart form. Detailed Implementation

[0020] In the following description of embodiments of the present invention, the same or similar elements are identified by the same reference numerals, and repeated descriptions of elements are omitted in certain cases. The accompanying drawings are only schematic illustrations of the subject matter of the invention. Furthermore, in the accompanying drawings... Figures 1 to 4 For the sake of overview, the various components shown are only partially marked with reference symbols when they appear multiple times.

[0021] Figure 1 A schematic cross-section of a wafer 100 having a chip 120 is shown to illustrate a method for processing the wafer 100 according to the present invention. In this example, the chip 120 is a MEMS chip 120, which is shown in different discrete variants. The wafer 100 is shown here after the sacrificial layer is etched, through which structure 122 is released and a notch 110 and slot structures 180a, 180b, 180c with slots 182a, 182b, 182c are created. Structure 122 may include, for example, a MEMS structure 122' for a micromirror array, the MEMS structure having a surface 122b to be protected, such as a mirror. The initial shape of the wafer 100 before the sacrificial layer is denoted by a dashed line 101, which also indicates the initial orientation of the first surface 100a and the second surface 100b of the wafer 100.

[0022] The left-side chip 120a and the middle chip 120b of the MEMS chip 120 have tabs 150a and 150b, respectively, which connect the chip to the remainder 105 of the wafer 100. In this case, chip 120a is connected to the corresponding remainder 105 of the wafer 100 via the vertical tab 150a and chip 120b via the horizontal tab 150b. In contrast, the right-side chip 120c is completely separated and is not held in the wafer 100 by tabs. The slot structures 180a and 180b with slots 182a and 182b are correspondingly partially perforated slot structures. The slot structure 180c can be a continuous through-hole slot structure 180c having slots 182c surrounding the chip 120c, through which the chip 120c is detached from the wafer 100. However, the movement of chip 120c along a direction 140 perpendicular to the first surface 100a of wafer 100, as shown by corresponding arrows in the figures, is confined within the remainder 105 of wafer 100 by means of a retaining structure 160 in the form of a protrusion extending into the slot 182c. The retaining structure 160 blocks the path of chip 120c as it moves along direction 140, wherein the retaining structure 160 is configured such that it contacts only the portion of chip 120c that is not on the surface 122b to be protected.

[0023] The wafer 100 is also shown to have metal contacts 124 that can be used for electrical contact with other components, such as for electrically controlling the MEMS chip 120.

[0024] Figure 2 Show Figure 1 A schematic cross-section of a wafer 100 having a MEMS chip 120 when the MEMS chip 120 is removed according to the method according to the invention. In this case, the removal is performed, for example, by means of a picking and placing device 200 (picking and placing device, such as a picking and placing robot), which generates a low pressure for moving the MEMS chip 120. Figure 2 The removal of the left-side chip 120a is being carried out, and the removal is performed together with the separation by breaking the vertical connector 150a.

[0025] exist Figure 3 The diagram schematically illustrates the state of a MEMS chip 120 when or after being placed on a screen 300 according to the invention by a picking and placing device 200, corresponding to the method according to the invention. The screen 300 has a bottom 320 in the form of a base plate 320 on which a support structure 310 is located. The support structure 310 may, for example, have the shape of a rectangular frame. The support structure 310 forms a plurality of notches 350 with the base plate 320, these notches for receiving the MEMS structure 122' and its surface 122b to be protected. Thus, the notches 350 have sidewalls 352 that simultaneously form the support structure 310, and each has a bottom 354 that is part of the base plate 320.

[0026] Therefore, the screen 300 protects the surface 122b of the MEMS chip 120 to be protected, for example, during subsequent steps in the chip-based assembly manufacturing process. Furthermore, the screen 300 enables a defined arrangement of the MEMS chip 120. To better secure the MEMS chip 120, it can be... Figure 3 The diagram shows that the notches 350 created by the base plate 320 and the support structure 310 are provided with channels 360 in the wall, specifically in the bottom 354 of the corresponding notches 350. These channels can be used to apply low pressure or vacuum. As shown, the MEMS chips 120 can be placed on the screen 300 with small spacing between them. This enables the achievement of a high fill factor for the MEMS chips 120.

[0027] As in Figure 4 As shown, the MEMS chip 120, thus positioned, can be connected to a common component 400, for example, by means of soldering metal contacts 124. This common component 400 can be, for example, an assembly having electronic components for controlling the MEMS chip 120. Electrical connections can be made after soldering, for example, via the now-soldered metal contacts 124'.

[0028] Figure 5 Finally, an exemplary method for processing a wafer 100 according to the present invention is illustrated schematically as a flowchart. First, in step 510a, a wafer 100 having a first surface 100a and a second surface 100b opposite to the first surface 100a is provided. The wafer 100 has structures 122 for a plurality of chips 120, such as MEMS chips 120, each structure having a surface 122b to be protected. Furthermore, in step 510b, a wire mesh 300 having a bottom 320 and one or more support structures 310 disposed on the bottom is provided.

[0029] Prior to separation of wafer 100, 520, slot structures 180a and 180b, comprising a configuration 512 surrounding a single chip 120 and partially perforating wafer 100, may be constructed within wafer 100, the slot structures having a plurality of slots 182a and 182b. Separation 520 is then performed at least partially along the plurality of slots 182a and 182b, wherein the slot structures 180a and 180b, with partial perforation by configuration 512, preferably have tabs 150a and 150b protruding between slots 182a and 182b, these tabs extending horizontally or vertically about the first surface 100a respectively and retaining chip 120 within wafer 100. Such a step, typically performed by means of etching, can be combined with releasing 514 any present MEMS structures 122' prior to separation of wafer 100.

[0030] After wafer 100 is separated into chip 120, chip 120 can be removed from wafer 100 in step 530. The separation is typically performed after or together with the sacrificial layer etching.

[0031] Finally, in step 540, at least a portion of the removed chip 120 is placed on one or more support structures 310 of the screen 300 to achieve the desired arrangement, i.e., the desired position and orientation, of the placed chip 120. In this case, the surface 122b to be protected points toward the bottom 320 of the screen 300. The surface to be protected does not directly contact the one or more support structures 310. Subsequently, the placed chip 120 is connected 550 to the common element 400, wherein the arrangement of the placed chips 120 relative to each other is maintained.

[0032] The invention is not limited to the embodiments described herein and the aspects highlighted therein. Rather, various modifications that are within the scope of the claims are possible and are of skill to those skilled in the art.

Claims

1. A method for processing a wafer (100) comprising the following steps: a. Provide (510a) the wafer (100) having a structure (122) for a plurality of chips (120) and having a first surface (100a) and a second surface (100b) opposite to the first surface (100a); b. Provide (510b) a wire mesh (300) having a bottom (320) and one or more support structures (310) arranged on the bottom; c. Separating (520) the wafer (100) into the chip (120), wherein, Each chip (120) has a surface (122b) to be protected; d. Remove the chip (120) from the wafer (100) (530); e. At least a portion of the removed chip (120) is placed (540) on one or more support structures (310) of the wire mesh (300) to achieve a desired arrangement of the placed chip (120) such that the surface (122b) to be protected points toward the bottom (320) of the wire mesh (300) and does not directly contact the one or more support structures (310); and f. The placed chip (120) is then connected (550) to a common element (400), wherein the arrangement of the placed chips (120) relative to each other is maintained.

2. The method according to claim 1, wherein, The wafer (100) has a holding structure (160) and / or the holding structure (160) is constructed (512) in the wafer (100) before or during separation (520), wherein the holding structure (160) is configured to restrict possible movement of the chip (120) after separation (520) along at least one direction (140) perpendicular to the first surface (100a) of the wafer (100).

3. The method according to any one of the preceding claims, wherein, Before separating (520) the wafer (100), a slot structure (180a, 180b) with a plurality of slots (182a, 182b) is constructed (512) in the wafer (100) to surround a single chip (120) and to partially perforate the wafer (100), and the separation (520) is carried out at least partially along the plurality of slots (182a, 182b), wherein the slot structure (180a, 180b) with partial perforation by construction (512) preferably causes tabs (150a, 150b) to protrude between the slots (182a, 182b), the tabs extending horizontally or vertically about the first surface (100a) respectively and holding the chip (120) in the wafer (100).

4. The method according to any one of the preceding claims, wherein, During the separation (520) of the wafer, a slot structure (180c) having one or more slots (182c) is constructed (512) in the wafer (100) to surround a single chip (120) and to continuously extend through the wafer (100), and the separation (520) is carried out at least in part by constructing the slot structure (180c).

5. The method according to any one of the preceding claims, wherein, The structure (122) for the chip (120) includes a MEMS structure (122') for a microelectromechanical system, and the surface to be protected (122b) is part of the MEMS structure (122'), wherein the release (514) of the MEMS structure (122') is performed before the separation (520) of the wafer (100).

6. The method according to claim 5, wherein, The open MEMS structure (122') includes a MEMS structure for a micromirror array.

7. A screen (300) for placing a chip (120) having a surface (122b) to be protected, preferably used in the method according to any one of the preceding claims, wherein, The screen (300) includes a bottom (320) and one or more support structures (310) disposed on the bottom, wherein the support structures (310) are configured such that the chip (120) can be placed on the one or more support structures (310) such that the surface (122b) to be protected does not come into direct contact with the one or more support structures (310).

8. The wire mesh (300) according to claim 7, wherein, The one or more support structures (310) are in the form of one or more rectangular, triangular, hexagonal and / or trapezoidal frames and / or one or more rectangular, triangular, hexagonal and / or trapezoidal grids, thereby defining a notch (350) in the wire mesh (300) for placing the chip (120) and protecting the surface to be protected (122b).

9. The wire mesh (300) according to claim 8, wherein, The notches (350) defined by the one or more frames and / or the one or more grids each have walls (352, 354) with channels (360) adapted to apply low pressure or vacuum to attract the chip (120) placed on the notches.

10. The wire mesh (300) according to any one of claims 7 to 9, wherein, At least a portion of the bottom (320) of the mesh (300) is at least partially transparent to light within a wavelength range.

11. The wire mesh (300) according to any one of claims 7 to 10, wherein, At least a portion of the bottom (320) of the wire mesh (300) is made of or has glass.

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