A low-power multi-core SOC

Abstract

This invention provides a low-power multi-core SoC, relating to the field of chip design technology. It includes a first CPU, a second CPU, a clock network, peripheral units associated with the first CPU, and peripheral units associated with the second CPU. The clock network provides clock signals to the first CPU, the second CPU, and the peripheral units associated with the first CPU and the second CPU, respectively. A configuration register (LPMCR) is included to configure the clock gating mode of the multi-core SoC, which includes three clock gating modes. The low-power multi-core SoC chip of this invention has multiple low-power modes, including a configurable protected context mode for power-down modes; it supports multiple wake-up methods, including internal interrupt wake-up and external GPIO wake-up.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and more specifically, to a low-power multi-core SoC. Background Technology

[0002] Power consumption is divided into dynamic power consumption and static power consumption. Dynamic power consumption accounts for the majority when the gate circuit flips (i.e., the load capacitor charges and discharges). Static power consumption accounts for the majority when the gate circuit does not flip but is still in a powered state. With the continuous upgrading and iteration of chip manufacturing processes and the functional integration of chip designs, power consumption has become a key factor affecting its performance. Therefore, more and more designs are using techniques such as power gating or clock gating to reduce power consumption.

[0003] Clock network-related power consumption accounts for nearly half of all dynamic power consumption. In the clock network, energy is primarily consumed in the clock trees, which are the units with the highest toggle rates in the entire system. Furthermore, to ensure reduced network latency, these clock buffers typically have high drive capability. The purpose of clock toggle is to drive the update of register data. When a register is not needed, the clock connected to the register can be turned off; this is clock gating. Power gating technology is similar; when a module is not working, its power is turned off to prevent static power consumption, and it is turned on again when needed. Gated power counting is more complex than gated clock counting, including a gated power controller, a power switch network, the controlled module, the always-powered module, and isolators. In a System-on-a-Chip (SoC), the controlled module is connected to the power output of a power switch via a power switch network, while the power switch input is a normally open voltage and logic switch control.

[0004] Currently, low power consumption is mainly achieved through clock gating. However, different applications have different low power requirements, especially in SOC products. Some application environments require the CPU to be in low power mode while peripherals are still working. Other application environments require the CPU and CPU clock-controlled peripherals to be in low power mode. In some multi-chip scenarios, a certain SOC chip may not need to work for a long time. In such cases, power gating technology must be used to shut down the power of most of the SOC's circuitry. This requires multiple low power modes to meet the power consumption requirements of different scenarios.

[0005] Regarding power gating technology, power outages can disrupt the internal logic state of devices. In some applications, it is necessary to save the data before the power outage. The current approach is to temporarily store some critical information through external communication via external devices, which is a redundant solution.

[0006] Once in low-power mode, the non-power-down low-power mode can only be woken up via an external port using a wake-up frame. This is inefficient. Summary of the Invention

[0007] To address the aforementioned technical problems in related technologies, this invention proposes a low-power multi-core SoC, comprising a first CPU, a second CPU, a clock network, peripheral units associated with the first CPU, and peripheral units associated with the second CPU. The clock network provides clock signals to the first CPU, the second CPU, and the peripheral units associated with the first CPU and the second CPU, respectively. A configuration register LPMCR is also included, which configures the clock gating modes of the multi-core SoC. The clock gating modes include three types: a first clock gating mode that disables the clock of either the first CPU or the second CPU; a second clock gating mode that disables the clock of either the first CPU or the second CPU, as well as the clocks of the peripheral units associated with the first CPU and the second CPU; and a third clock gating mode that disables the clocks of the first CPU, the second CPU, and the peripheral units associated with the first CPU and the second CPU.

[0008] Specifically, the clock network includes: a first clock source INTOSC1, a second clock source INTOSC2, a third clock source X1; a clock selection circuit CLKSRCCTL1, which is used to select the corresponding clock source; and a peripheral clock register CPUx.PCLKCRx, which is used to configure the clock of the corresponding peripheral.

[0009] Specifically, the clock selection circuit CLKSRCCTL1 is used to select the corresponding clock source. The 0th bit of CLKSRCCTL1 is used for clock source selection, the 1st bit of CLKSRCCTL1 is used to determine whether to use the frequency multiplier clock output by the PLL, and the 2nd bit is used to determine whether the watchdog clock is turned off in the third clock gating mode.

[0010] Specifically, the low-power multi-core SoC enters different clock gating modes by setting the LPMCR register and executing the IDLE instruction.

[0011] Specifically, the way to enter the first clock-gated mode is to write 0 to the LPMCR register and then execute the ILDE instruction.

[0012] Specifically, the method to enter the second clock gating mode is as follows: write 1 to the LPMCR register, enable the wake-up interrupt, configure the required GPIO as a wake-up signal to trigger the low-power module; set the duration of the low level, and execute the IDLE instruction to enter the second clock gating mode.

[0013] Specifically, the method to enter the third clock gating mode is as follows: disable all interrupts of the two CPUs except for the wake-up interrupt; put the second CPU in the first clock gating mode, configure LPMCR to 2, configure the used GPIOs as wake-up signals, set the watchdog clock to 0, turn off the clocks of the first clock source INTOSC1 and the second clock source INTOSC2, and execute the IDLE instruction on the first CPU.

[0014] Specifically, in the third clock-gated mode, the first CPU saves the necessary application-specific context to the first CPU dedicated RAM block, which does not lose power in the third clock-gated mode.

[0015] Specifically, the way to exit the second clock gating mode is to drive the selected GPIO low. If the GPIO drive level goes high during the low level period, the counter will restart counting. At the end of the low level period, the PLL makes the clock source clock enter the CPU, and the wake-up interrupt is latched in the peripheral interrupt extension module.

[0016] Specifically, to exit the third clock gating mode: keep the selected GPIO low for at least 5us; pull the GPIO high to start the initialization of the analog section and PLL; wait 16us plus 1024 OSCLK cycles to allow the PLL to stabilize and the WAKEINT interrupt of both CPUs to be triggered.

[0017] The low-power multi-core SOC of this invention has multiple clock gating modes, which can further reduce the power consumption of the SOC. In addition, there is a configurable protection field mode for power-down mode; it supports multiple wake-up methods, including internal interrupt wake-up and external GPIO wake-up. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a low-power multi-core SOC structure provided in an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of a clock network provided in an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0022] refer to Figure 1 , Figure 1 This is a schematic diagram of a multi-core SOC architecture according to this embodiment, which includes a first CPU1 and a second CPU2. Each CPU subsystem has four dedicated RAM blocks: M0, M1, D0, and D1. The M0 / M1 memory is a small memory block tightly coupled to the CPU. Only the CPU can access these memories. Other hosts (including DMA) cannot access these memories. Each CPU also has a dedicated hardware accelerator (CLA), which has an independent instruction set and can execute control algorithms in parallel to improve system responsiveness. Each CPU also has dedicated memory corresponding to the CLA.

[0023] Among them, the dedicated RAM, DxRAM, where x is 0 or 1, is a RAM with security protection (CPU instruction fetch / CPU write protection).

[0024] The system shared memory MSGRAM is used for sharing between the CPU and DMA of the two subsystems (GSx RAM), and for sending and receiving messages between processors (MSGRAM).

[0025] A RAM block dedicated to each subsystem and accessible only by its CPU and CLA is called Local Shared RAM (LSxRAM).

[0026] The RAM blocks that can be accessed from the CPU and its respective DMA are called Global Shared RAM (GSx RAM). Each shared RAM can be owned by either CPU subsystem based on the configuration of its respective bits in the GSxMSEL register (one bit per GSx memory).

[0027] All of these RAMs are configurable to allow control over write and fetch access to different hosts.

[0028] This embodiment discloses a low-power multi-core SOC, which includes a first CPU, a second CPU, a clock network, peripheral units associated with the first CPU, and peripheral units associated with the second CPU. The clock network is used to provide clock signals to the first CPU, the second CPU, the peripheral units associated with the first CPU, and the peripheral units associated with the second CPU, respectively.

[0029] The configuration register LPMCR is used to configure the clock gating mode of the multi-core SoC. The clock gating mode includes three clock gating modes: the first clock gating mode: turning off the clock of the first CPU or the second CPU; the second clock gating mode: turning off the clock of the first CPU or the second CPU, the clock of the peripheral unit assigned to the first CPU, and the clock of the peripheral unit assigned to the second CPU; the third clock gating mode: turning off the clock of the first CPU, the second CPU, the peripheral unit assigned to the first CPU, and the clock of the peripheral unit assigned to the second CPU.

[0030] Specifically, in this embodiment, the first CPU and the second CPU provide corresponding clock signals CPUCLK through a clock network, and their corresponding peripherals are also provided with peripheral clock signals SYSCLK through a clock network.

[0031] refer to Figure 2 , Figure 2 This embodiment defines a clock network comprising a first clock source INTOSC1, a second clock source INTOSC2, and a third clock source X1. The first and second clock sources are both on-chip crystal oscillators (OSCs), capable of directly outputting a 10MHz clock signal. INTOSC2 is the primary internal clock source and serves as the default system clock during reset. The first clock source is a backup clock source, automatically switching to INTOSC1 when the second clock source INTOSC2 has no clock output. The third clock source is a passive crystal oscillator; X1 requires an external oscillation circuit to output a clock signal.

[0032] The clock selection circuit CLKSRCCTL1 is used to select the corresponding clock source. The 0th bit of CLKSRCCTL1 is used for clock source selection, the 1st bit of CLKSRCCTL1 is used to determine whether to use the frequency multiplier clock output by the PLL, and the 2nd bit is used to determine whether the watchdog clock is turned off in the third clock gating mode.

[0033] The peripheral clock register CPUx.PCLKCRx has each bit corresponding to a peripheral. The peripheral clock configuration CPUSELx determines which CPU's peripheral clock belongs to.

[0034] The system divider register SYSCLKDIVSEL has a maximum divider of 126 and a minimum divider of 1. The default divider after power-on is 4.

[0035] Peripherals typically include communication peripherals such as SPI, SCI, and analog peripherals such as ADC.

[0036] The system phase-locked loop (PLL) multiplies the input clock source before outputting the multiplied clock signal. This multiplied output can then be divided to obtain the PLLSYSCLK.

[0037] PLLSYSCLK controls some global RAM. The CPU clock is obtained as a CPUx clock through gating and some logic control, and these clocks can control some memory.

[0038] Upon power-up, the on-chip 10MHz oscillator INTOSC2 provides the clock signal. INTOSC2 is used to run the boot ROM and can also be used as the system clock source for applications. The external clock is X1, which has a small frequency tolerance and can meet the high clock quality requirements of peripherals such as CAN and USB.

[0039] Specifically, the low-power multi-core SoC enters different clock gating modes by setting the LPMCR register and executing the IDLE instruction.

[0040] Specifically, the configuration of the LPMCR register is received. In this embodiment, the LPMCR register has an address, and data can be written to the corresponding address through software operations.

[0041] To enter the first clock-gated mode: write 0 to the LPMCR register and then execute the ILDE instruction. In the first clock-gated mode (clock-gated mode 1), any enabled interrupt will wake the CPU from clock-gated mode 1. In this embodiment, clock-gated mode 1 only disables the clock of CPUx. In clock-gated mode 1, the watchdog interrupt signal can interrupt the CPU, causing it to exit clock-gated mode 1. Like other peripherals, in clock-gated mode 1, the watchdog interrupt will trigger the WAKEINT interrupt in the Peripheral Interrupt Extension Module (PIE).

[0042] Specifically, in this embodiment, the first CPU and the second CPU each correspond to an LRMCR register. In this embodiment, the specific CPU enters clock gating mode 1 by writing the value of the corresponding LRMCR register.

[0043] To enter the second clock-gated mode (clock-gated mode 2): write 1 to the LPMCR register to enable the wake-up interrupt, configure the required GPIO as a wake-up signal to trigger the low-power module; set the duration of the low level, and execute the IDLE instruction to enter the second clock-gated mode.

[0044] Clock-gated mode 2 controls the gating of the CPU clock and peripheral clocks from the CPU SYSCLK. In clock-gated mode 2, the clocks of all peripherals within the CPU subsystem are disabled. The only peripheral that remains functional is the watchdog timer, as the watchdog module operates on the oscillator clock (OSCCLK). The watchdog interrupt signal is fed to the low-power mode (LPM) block to wake the CPU from standby low-power mode.

[0045] If the watchdog interrupt is used to wake up clock-gated mode 1 or clock-gated mode 2, the software must ensure the watchdog interrupt signal returns to high before attempting to re-enter clock-gated mode. When a watchdog interrupt occurs, the watchdog interrupt signal remains low for 512 OSCCLK cycles. The current state of the watchdog interrupt signal can be determined by reading the watchdog interrupt status bit (WDINTS) in the SCSR register.

[0046] Exit method for clock gating mode 2:

[0047] Drive the selected GPIO low. If the GPIO drive level goes high during the low-level period, the counter will restart counting.

[0048] At the end of the low-level limiting period, the PLL will cause the internal oscillator OSC clock in the clock source to enter the CPU, and the wake-up interrupt will be latched in the peripheral interrupt extension module.

[0049] The system has exited clock gating mode 2.

[0050] The program can be executed normally, and the CPUx and its related peripherals can be configured with clocks normally.

[0051] The method to enter the third clock gating mode (clock gating mode 3) is as follows: disable all interrupts of the two CPUs except for the wake-up interrupt; put the second CPU in the first clock gating mode, configure LPMCR to 2, configure the used GPIOs as wake-up signals, set the watchdog clock valid CLKSRCCTL1.WDHALTI to 0, turn off the clocks of the first clock source INTOSC1 and the second clock source INTOSC2, and execute the IDLE instruction on the first CPU.

[0052] Clock Gating Mode 3 is a global low-power mode. It can gate almost all system clocks and can also shut down the clocks of the oscillator and analog modules. This mode affects two CPU subsystems.

[0053] In clock-gated mode 3, if the user sets the watchdog clock to be valid (CLKSRCCTL1.WDHALTI=1), the internal oscillator and CPU1 watchdog will remain active. A watchdog reset can wake the system from HALT mode, while a watchdog interrupt cannot. In this embodiment, the watchdog function is normal when the watchdog clock is calibrated. The watchdog needs to be fed periodically to ensure the program executes normally; failure to feed the watchdog will result in a reset.

[0054] Exit clock gating mode 3:

[0055] Keep the selected GPIO low for at least 5µs.

[0056] Pull the GPIO high to initiate the initialization of the analog section and PLL.

[0057] Wait 16us plus 1024 OSCLK cycles for the PLL to stabilize and for the WAKEINT interrupts of both CPUs to be triggered.

[0058] The third clock-gated mode (power-down mode) can gate most of the system's power supply voltage. This mode affects two CPU subsystems. Power-down mode is essentially a controlled power-down mode with remote wake-up capability, used to save energy during prolonged inactivity. Because gating the power supply voltage can corrupt the logic state, a reset is required to exit power-down mode. To prevent external systems from being affected by the reset, power-down mode uses M0 and M1 memories to store the state data before the power-down, providing isolation for I / O pin states.

[0059] If required by the user, the first CPU will save the necessary application-specific context to the M0 / M1 memory. If I / O isolation is used, GPIO states are included. Configure the first CPU's LPMCR register to power-down mode.

[0060] Execute the IDLE instruction to put the device into power-down mode.

[0061] This device is now in power-down mode. If configured, I / O isolation is enabled, and M0 and M1 memories are retained. CPU1 and CPU2 are powered down. Digital peripherals are powered down. The oscillator, PLL, analog peripherals, and flash memory are all in software-controlled clock-gated mode. Dx, LSx, and GSx memories are also powered down, and their contents are lost.

[0062] A falling edge on the GPIOHIBWAKEn pin will wake up the driver clock sources INTOSC1, INTOSC2, and X1. The wake-up source must hold the GPIOHIBWAKEn pin low for a sufficient time to ensure that these clock sources are fully powered on.

[0063] After the clock source is powered on, GPIOHIBWAKEn must be driven high to trigger the wake-up sequence of the rest of the device.

[0064] Then, the BootROM will begin execution. The BootROM code will jump to the user-defined IoRestore function (if it is configured).

[0065] At this point, the device exits power-down mode, and the application can continue to run.

[0066] The IoRestore feature is a user-defined feature that allows applications to reconfigure GPIO states, disable I / O isolation, reconfigure PLLs, restore peripheral configurations, or jump to application code.

[0067] If the application does not jump to application code, BootROM will continue after IoRestore is complete. If no processing occurs within IoRestore, it will automatically disable I / O isolation. At this point, CPU2 will also exit the reset state.

[0068] The program jumps to the main function entry point.

[0069] The low-power multi-core SoC in this embodiment has the following power consumption modes:

[0070] Clock-gated mode 1 disables the CPU clock (CPUx.CPUCLK) while keeping all peripheral clocks running. Clock-gated mode 1 can be used to reduce system power consumption when the CPU is waiting for peripheral events. When one CPU is idle, it has no effect on other CPU subsystems. Any enabled interrupt will wake the CPU from mode 1. To enter clock-gated mode 1, low-power related registers must be set and specific instructions executed.

[0071] Clock gating mode 2 consumes less power than mode 1. It gates the CPU clock and peripheral clocks from the CPU SYSCLK. However, the watchdog timer is active. Similar to clock gating mode 1, this mode only affects one CPU subsystem. Other CPU subsystems and all their peripherals are unaffected. Clock gating mode 2 is best suited for applications where the wake-up signal comes from an external system (or CPU subsystem) rather than a peripheral input. Any of GPIOs 0-63 can be configured to wake up the subsystem when active low.

[0072] Clock Gated Mode 3 is a global low-power mode that gates almost the entire system clock and allows the oscillator and analog modules to shut down. This mode affects two CPU subsystems.

[0073] Entering different clock gating modes is user-defined and can be used according to actual applications. Different modes are entered by configuring different values ​​of the LPMCR register. The three different modes operate on different clock domains.

[0074] The advantages are simple configuration. Users can configure it according to the clock domain they use. Each CPU and the CPUs have corresponding RAM for temporary data storage, making data processing more flexible. The wake-up method is also simple. Just pull the external GPIO low for a period of time. Considering different packages, the GPIO can be configured to be used for wake-up.

[0075] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-power multi-core SOC, comprising a first CPU, a second CPU, a clock network, peripheral units associated with the first CPU, and peripheral units associated with the second CPU, wherein the clock network provides clock signals to the first CPU, the second CPU, the peripheral units associated with the first CPU, and the peripheral units associated with the second CPU, respectively; characterized in that: The configuration register LPMCR is used to configure the clock gating mode of the multi-core SoC. The clock gating mode includes three modes: First, the clock of the first CPU or the second CPU is turned off; Second, the clock of the first CPU and its associated peripherals, or the clock of the second CPU and its associated peripherals, is turned off; Third, the clocks of the first CPU, the second CPU, the peripherals associated with the first CPU, and the peripherals associated with the second CPU are turned off. The clock network includes a first clock source INTOSC1 and a second clock source INTOSC2. Entering the third clock gating mode involves disabling all interrupts for both CPUs except for wake-up interrupts; placing the second CPU in the first clock gating mode, configuring LPMCR to 2, configuring the used GPIOs as wake-up signals, setting the watchdog clock to 0, turning off the clocks of the first clock source INTOSC1 and the second clock source INTOSC2, and executing the IDLE instruction on the first CPU; In the third clock gating mode, the first CPU... The necessary application-specific context is saved to the first CPU-dedicated RAM block, which does not lose power in the third clock-gated mode.

2. The low-power multi-core SOC according to claim 1, characterized in that: The clock network also includes: a third clock source X1; a clock selection circuit CLKSRCCTL1, which is used to select the corresponding clock source; and a peripheral clock register CPUx.PCLKCRx, which is used to configure the clock of the corresponding peripheral.

3. The low-power multi-core SOC according to claim 2, characterized in that: The clock selection circuit CLKSRCCTL1 is used to select the corresponding clock source. The 0th bit of CLKSRCCTL1 is used for clock source selection, the 1st bit of CLKSRCCTL1 is used to determine whether to use the frequency multiplier clock output by the PLL, and the 2nd bit is used to determine whether the watchdog clock is turned off in the third clock gating mode.

4. The low-power multi-core SoC according to any one of claims 1-3, characterized in that: The low-power multi-core SoC enters different clock gating modes by setting the LPMCR register and executing the IDLE instruction.

5. The low-power multi-core SOC according to claim 4, characterized in that: To enter the first clock-gated mode, write 0 to the LPMCR register and then execute the ILDE instruction.

6. The low-power multi-core SOC according to claim 4, characterized in that: To enter the second clock-gated mode: write 1 to the LPMCR register, enable the wake-up interrupt, configure the required GPIO as a wake-up signal to trigger the low-power module; set the duration of the low level, and execute the IDLE instruction to enter the second clock-gated mode.

7. The low-power multi-core SOC according to claim 6, characterized in that: In the third clock-gated mode, the first CPU saves the necessary application-specific context to the first CPU dedicated RAM block, which does not lose power in the third clock-gated mode.

8. The low-power multi-core SOC according to claim 6, characterized in that: To exit the second clock gating mode: drive the selected GPIO low. If the GPIO drive level goes high during the low-level period, the counter will restart counting. At the end of the low-level period, the PLL causes the clock source to enter the CPU, and the wake-up interrupt is latched in the peripheral interrupt extension module.

9. The low-power multi-core SOC according to claim 8, characterized in that: To exit the third clock gating mode: Keep the selected GPIO low for at least 5µs; pull the GPIO high to start the initialization of the analog section and PLL; wait 16µs plus 1024 OSCLK cycles to allow the PLL to stabilize and the WAKEINT interrupts of both CPUs to be triggered.

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