Planar device and manufacturing method thereof
By forming patterned semiconductor epitaxial layers and void structures on a semiconductor substrate, the problem of leakage path in planar devices is solved, a fully depleted channel region is realized, device performance is improved and costs are reduced.
Patent Information
- Application Number
- CN202411103674.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-12
- Publication Date
- 2026-02-13
AI Technical Summary
Existing planar devices are prone to leakage paths as the process node shrinks, leading to performance degradation, and the use of SOI substrates is costly.
By forming first and second semiconductor epitaxial layers on a semiconductor substrate and forming a patterned structure between the source/drain formation region and the gate formation region, the channel region and the bottom semiconductor substrate are isolated by the gap structure, and a fully depleted channel region is realized using a semiconductor substrate, thus eliminating leakage paths.
A fully depleted channel region was achieved, which improved device performance, reduced leakage current, and lowered process costs.
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Figure CN121531748A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and particularly to a planar device. This invention also relates to a method for manufacturing a planar device. Background Technology
[0002] like Figure 1 The diagram shown is a cross-sectional view of an existing planar device; the existing planar device includes:
[0003] Semiconductor substrate 101, such as silicon substrate.
[0004] The gate structure is formed on the top surface of the semiconductor substrate 101.
[0005] The gate structure includes a gate dielectric layer 102 and a polysilicon gate 103 stacked sequentially.
[0006] An active region 104 and a drain region 105 are formed in the semiconductor substrates 101 on both sides of the gate structure, respectively.
[0007] The channel region is located between the source region 104 and the drain region 105 and is covered by the gate structure.
[0008] The polysilicon gate 103 is connected to the gate, the source region 104 is connected to the source, and the drain region 105 is connected to the drain.
[0009] When the voltage between the gate and the source, i.e. the gate-source voltage, is greater than or equal to the threshold voltage, a conductive channel composed of carriers with an inversion layer will be formed on the surface region of the channel region. The conductive channel enables the conduction between the source region 104 and the drain region 105, thereby forming the source-drain current.
[0010] However, as the process node continues to shrink, the length of the channel region will shrink proportionally, and the length of the gate structure will also shrink proportionally. In the semiconductor substrate 101 far away from the gate structure, a large leakage path 106 is easily formed. The leakage current of the leakage path 106 will not pass through the conductive channel, so it is not a current controlled by the gate structure. The existence of the leakage path 106 will reduce the performance of the device.
[0011] In existing methods, expensive silicon-on-insulator (SOI) substrates are often required to eliminate leakage path 106, which results in high process costs. Summary of the Invention
[0012] The technical problem to be solved by the present invention is to provide a planar device that can realize a full-depletion channel region using a semiconductor substrate and isolate the channel region from the bottom semiconductor substrate through a gap structure, thereby reducing device leakage current, improving device performance, and reducing process costs. To this end, the present invention also provides a method for manufacturing the planar device.
[0013] To solve the above-mentioned technical problems, the planar device provided by the present invention is formed on a semiconductor substrate, wherein a first semiconductor epitaxial layer and a second semiconductor epitaxial layer are sequentially formed on the top surface of the semiconductor substrate; the material of the first semiconductor epitaxial layer is different from the material of the semiconductor substrate, and the material of the first semiconductor epitaxial layer is different from the material of the second semiconductor epitaxial layer.
[0014] The planar device formation region includes a gate formation region and source / drain formation regions located on both sides of the gate formation region.
[0015] In the formation region of the planar device, the first semiconductor epitaxial layer and the second semiconductor epitaxial layer have a patterned structure.
[0016] The patterned structure includes: the second semiconductor epitaxial layer and the first semiconductor epitaxial layer in the source / drain formation region are removed and a first trench is formed; the second semiconductor epitaxial layer in the gate formation region is retained and the first semiconductor epitaxial layer is removed.
[0017] A first dielectric layer is filled in the first trench, the top surface of the first dielectric layer is located between the top surface and the bottom surface of the second semiconductor epitaxial layer, and the side surface of the second semiconductor epitaxial layer above the top surface of the first dielectric layer is exposed.
[0018] A void structure formed by removing the first semiconductor epitaxial layer is formed in the gate region. The side surface of the void structure is defined by the side surface of the first dielectric layer, the top surface of the void structure is defined by the bottom surface of the second semiconductor epitaxial layer, and the bottom surface of the void structure is defined by the top surface of the semiconductor substrate.
[0019] A third semiconductor epitaxial layer is formed on the top surface and exposed side surface of the second semiconductor epitaxial layer, and the third semiconductor epitaxial layer extends from the exposed side surface of the second semiconductor epitaxial layer to the top surface of the first dielectric layer.
[0020] The second semiconductor epitaxial layer and the third semiconductor epitaxial layer constitute a top epitaxial layer, and the top surface of the top epitaxial layer is a planarized surface.
[0021] A gate structure is formed on the top surface of the top epitaxial layer on top of the void structure, and the top epitaxial layer covered by the gate structure serves as a channel region.
[0022] The source and drain regions are formed in the top epitaxial layer on both sides of the gate structure.
[0023] A further improvement is that the material of the second semiconductor epitaxial layer is the same as the material of the semiconductor substrate; and the material of the third semiconductor epitaxial layer is the same as the material of the second semiconductor epitaxial layer.
[0024] A further improvement is that the material of the second semiconductor epitaxial layer includes Si or SiGe.
[0025] A further improvement is that the material of the first semiconductor epitaxial layer includes Si or SiGe.
[0026] A further improvement is that the material of the second semiconductor epitaxial layer is Si, and the material of the first semiconductor epitaxial layer is SiGe; or, the material of the second semiconductor epitaxial layer is SiGe, and the material of the first semiconductor epitaxial layer is Si.
[0027] A further improvement is that the material of the first dielectric layer includes an oxide layer.
[0028] A further improvement is that the first dielectric layer is a flowable chemical vapor deposition (FCVD) oxide layer.
[0029] A further improvement is that the top surface of the top epitaxial layer is higher than the top surface of the second semiconductor epitaxial layer; or, the top surface of the top epitaxial layer is located below or at the same level as the top surface of the second semiconductor epitaxial layer, and the third semiconductor epitaxial layer on the top surface of the second semiconductor epitaxial layer is planarized and removed.
[0030] To solve the above-mentioned technical problems, the manufacturing method of the planar device provided by the present invention includes the following steps:
[0031] Step 1: Provide a semiconductor substrate, and sequentially form a first semiconductor epitaxial layer and a second semiconductor epitaxial layer on the top surface of the semiconductor substrate.
[0032] The material of the first semiconductor epitaxial layer is different from the material of the semiconductor substrate, and the material of the first semiconductor epitaxial layer is different from the material of the second semiconductor epitaxial layer.
[0033] Step 2: Perform patterned etching on the first semiconductor epitaxial layer and the second semiconductor epitaxial layer, including:
[0034] The source / drain formation region of the planar device is opened and the gate formation region of the planar device is covered, the source / drain formation region being located on both sides of the gate formation region.
[0035] Etching is performed to remove both the second semiconductor epitaxial layer and the first semiconductor epitaxial layer in the source / drain formation region and form a first trench; the second semiconductor epitaxial layer and the first semiconductor epitaxial layer are retained in the gate formation region.
[0036] Step 3: Fill the first trench with a first dielectric layer, the top surface of the first dielectric layer being located between the top and bottom surfaces of the second semiconductor epitaxial layer, and the side surfaces of the second semiconductor epitaxial layer above the top surface of the first dielectric layer being exposed.
[0037] Step 4: Perform a first selective epitaxial growth on the top surface and exposed side surface of the second semiconductor epitaxial layer to form a third semiconductor epitaxial layer.
[0038] The third semiconductor epitaxial layer is formed on the top surface and exposed side surface of the second semiconductor epitaxial layer, and the third semiconductor epitaxial layer extends from the exposed side surface of the second semiconductor epitaxial layer to the top surface of the first dielectric layer.
[0039] The second semiconductor epitaxial layer and the third semiconductor epitaxial layer constitute the top epitaxial layer.
[0040] Step 5: The top epitaxial layer is planarized using a first chemical mechanical polishing process to make the top surface of the top epitaxial layer a planarized surface.
[0041] Step 6: Perform selective etching to remove the first semiconductor epitaxial layer in the gate formation region and form a void structure formed after the first semiconductor epitaxial layer is removed. The side surface of the void structure is defined by the side surface of the first dielectric layer, the top surface of the void structure is defined by the bottom surface of the second semiconductor epitaxial layer, and the bottom surface of the void structure is defined by the top surface of the semiconductor substrate.
[0042] Step 7: A gate structure is formed on the top surface of the top epitaxial layer at the top of the void structure; the top epitaxial layer covered by the gate structure serves as the channel region.
[0043] Step 8: Perform source and drain injection to form source and drain regions in the top epitaxial layers on both sides of the gate structure, respectively.
[0044] A further improvement is that the material of the second semiconductor epitaxial layer is the same as the material of the semiconductor substrate; and the material of the third semiconductor epitaxial layer is the same as the material of the second semiconductor epitaxial layer.
[0045] A further improvement is that the material of the second semiconductor epitaxial layer includes Si or SiGe.
[0046] A further improvement is that the material of the first semiconductor epitaxial layer includes Si or SiGe.
[0047] A further improvement is that the material of the second semiconductor epitaxial layer is Si, and the material of the first semiconductor epitaxial layer is SiGe; or, the material of the second semiconductor epitaxial layer is SiGe, and the material of the first semiconductor epitaxial layer is Si.
[0048] A further improvement is that the material of the first dielectric layer includes an oxide layer.
[0049] A further improvement is that the first dielectric layer is formed using an FCVD process.
[0050] A further improvement is that step three includes the following sub-steps:
[0051] The first dielectric layer is grown using the FCVD process, and the first dielectric layer completely fills the first trench and extends beyond the first trench.
[0052] The first dielectric layer is planarized by performing a 0th chemical mechanical polishing process. The 0th chemical mechanical polishing process removes the first dielectric layer outside the first trench and makes the top surface of the first dielectric layer inside the first trench flush with the top surface of the second semiconductor epitaxial layer.
[0053] The first dielectric layer is etched back so that the top surface of the first dielectric layer is lowered between the top and bottom surfaces of the second semiconductor epitaxial layer.
[0054] A further improvement is that, after the first chemical mechanical polishing process is completed, the top surface of the top epitaxial layer is higher than the top surface of the second semiconductor epitaxial layer; or, after the first chemical mechanical polishing process is completed, the top surface of the top epitaxial layer is located below or at the same level as the top surface of the second semiconductor epitaxial layer, and the third semiconductor epitaxial layer on the top surface of the second semiconductor epitaxial layer is removed.
[0055] This invention eliminates the need for an SOI substrate, allowing for the realization of a fully depleted channel region directly using a semiconductor substrate. The channel region and the underlying semiconductor substrate are isolated by a gap structure, which is obtained by self-aligning and removing the first semiconductor epitaxial layer at the bottom of the channel region. Due to the gap structure separating the channel region and the semiconductor substrate, a thin, fully depleted structure can be achieved in the channel region, thereby improving the gate structure's control over the channel region and thus enhancing device performance. Simultaneously, the isolation effect of the gap structure eliminates the leakage path between the source and drain through the semiconductor substrate, reducing device leakage current. Furthermore, since this invention eliminates the need for an SOI substrate, it reduces process costs. Attached Figure Description
[0056] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0057] Figure 1 This is a schematic diagram of the cross-sectional structure of an existing planar device;
[0058] Figure 2A This is a cross-sectional structural diagram of the planar device according to an embodiment of the present invention;
[0059] Figure 2B This is a schematic cross-sectional view of the semiconductor substrate of the planar device according to an embodiment of the present invention;
[0060] Figures 3A-3F This is a schematic diagram of the cross-sectional structure of the device in each step of the manufacturing method of the planar device according to an embodiment of the present invention. Detailed Implementation
[0061] like Figure 2A The diagram shown is a cross-sectional structural schematic of a planar device according to an embodiment of the present invention; as shown... Figure 2B The diagram shown is a cross-sectional view of the semiconductor substrate 201 of the planar device according to an embodiment of the present invention; the planar device of the present invention is formed on the semiconductor substrate 201, as shown... Figure 2B The semiconductor substrate 201 has a first semiconductor epitaxial layer 202 and a second semiconductor epitaxial layer 203 sequentially formed on its top surface; the material of the first semiconductor epitaxial layer 202 is different from the material of the semiconductor substrate 201, and the material of the first semiconductor epitaxial layer 202 is different from the material of the second semiconductor epitaxial layer 203.
[0062] Figure 2A Only a structural schematic diagram of the forming region of the planar device is shown, such as... Figure 2A As shown, the formation region of the planar device includes a gate formation region 301 and source / drain formation regions 302 located on both sides of the gate formation region 301. Figure 2AIn the diagram, the gate forming region 301 is located between two dashed lines, and the source and drain forming regions 302 on both sides have a symmetrical structure and are represented by the same symbol 302.
[0063] In the formation region of the planar device, the first semiconductor epitaxial layer 202 and the second semiconductor epitaxial layer 203 have a patterned structure.
[0064] The patterned structure includes: the second semiconductor epitaxial layer 203 and the first semiconductor epitaxial layer 202 in the source / drain formation region 302 are removed and a first trench 303 is formed; the second semiconductor epitaxial layer 203 in the gate formation region 301 is retained and the first semiconductor epitaxial layer 202 is removed.
[0065] A first dielectric layer 204 is filled in the first trench 303, the top surface of the first dielectric layer 204 is located between the top surface and the bottom surface of the second semiconductor epitaxial layer 203, and the side surface of the second semiconductor epitaxial layer 203 above the top surface of the first dielectric layer 204 is exposed.
[0066] In this embodiment of the invention, the material of the first dielectric layer 204 includes an oxide layer. In some preferred embodiments, the first dielectric layer 204 is an FCVD oxide layer. The FCVD oxide layer is an oxide layer formed using the FCVD process, and using an FCVD oxide layer is beneficial for improving the quality of filling the first trench 303.
[0067] A void structure 207 is formed in the gate region after the first semiconductor epitaxial layer 202 is removed. The side surface of the void structure 207 is self-aligned with the side surface of the first dielectric layer 204, the top surface of the void structure 207 is self-aligned with the bottom surface of the second semiconductor epitaxial layer 203, and the bottom surface of the void structure 207 is self-aligned with the top surface of the semiconductor substrate 201.
[0068] A third semiconductor epitaxial layer 205 is formed on the top surface and exposed side surface of the second semiconductor epitaxial layer 203, and the third semiconductor epitaxial layer 205 extends from the exposed side surface of the second semiconductor epitaxial layer 203 to the top surface of the first dielectric layer 204.
[0069] The second semiconductor epitaxial layer 203 and the third semiconductor epitaxial layer 205 constitute a top epitaxial layer 206, and the top surface of the top epitaxial layer 206 is a planarized surface. In some embodiments, the top surface of the top epitaxial layer 206 is higher than the top surface of the second semiconductor epitaxial layer 203. In this case, a portion of the thickness of the third semiconductor epitaxial layer 205 is also retained on the top surface of the second semiconductor epitaxial layer 203. In some embodiments, the top surface of the top epitaxial layer 206 may also be located below or at the same level as the top surface of the second semiconductor epitaxial layer 203. In this case, the third semiconductor epitaxial layer 205 on the top surface of the second semiconductor epitaxial layer 203 is planarized and removed, and in the gate formation region 301, the top epitaxial layer 206 is composed of the second semiconductor epitaxial layer 203.
[0070] A gate structure is formed on the top surface of the top epitaxial layer 206 on top of the void structure 207, and the top epitaxial layer 206 covered by the gate structure serves as a channel region.
[0071] In this embodiment of the invention, the thickness of the subsequent channel region can be adjusted by controlling the top surface of the top epitaxial layer 206. In some embodiments, the thickness of the channel region can be adjusted to a fully depleted structure, which facilitates the gate structure's control over the channel region and improves device performance.
[0072] In this embodiment of the invention, the gate structure includes a gate dielectric layer 208 and a gate conductive material layer 209 stacked sequentially. In some specific embodiments, the gate dielectric layer 208 is made of silicon dioxide or a high dielectric constant material. The gate conductive material layer 209 is made of polysilicon or a metal gate.
[0073] The source region 210 and the drain region 211 are formed in the top epitaxial layer 206 on both sides of the gate structure. Figure 2A In this context, the gate conductive material layer 209 is also represented by G, the source region 210 is also represented by S, and the drain region 211 is also represented by D.
[0074] Depend on Figure 2A As shown, the channel region is a region that can be controlled by the gate structure. Because of the gap structure 207, the semiconductor substrate 207, which is far from the gate structure, will not contact the channel region, thus preventing the formation of a leakage path. Therefore, this embodiment of the invention can reduce device leakage.
[0075] Depend on Figure 2A As shown, the planar device in this embodiment of the invention is actually equivalent to an FDSOI device, but due to... Figure 2BAs shown, the planar device in the embodiment of the present invention does not need to use an SOI substrate, but directly uses a bulk semiconductor substrate 201. Since the cost of an SOI substrate is higher, the embodiment of the present invention also has the advantage of low cost.
[0076] In this embodiment of the invention, the material of the second semiconductor epitaxial layer 203 is the same as the material of the semiconductor substrate 201; the material of the third semiconductor epitaxial layer 205 is the same as the material of the second semiconductor epitaxial layer 203.
[0077] The material of the second semiconductor epitaxial layer 203 includes Si or SiGe. The material of the first semiconductor epitaxial layer 202 includes Si or SiGe. Since the materials of the first semiconductor epitaxial layer 202 and the second semiconductor epitaxial layer 203 are different, there can be various combinations of their materials. For example, in some embodiments, the material of the second semiconductor epitaxial layer 203 is Si, and the material of the first semiconductor epitaxial layer 202 is SiGe. In other embodiments, the material of the second semiconductor epitaxial layer 203 may be SiGe, and the material of the first semiconductor epitaxial layer 202 may be Si.
[0078] Depend on Figure 2A As shown, the planar device in this embodiment of the invention is a planar device having a void structure 207 and an insulating structure, namely a first dielectric layer 204, making it a full depletion silicon-on-void device.
[0079] This invention does not require an SOI substrate; a fully depleted channel region can be achieved directly using a semiconductor substrate 201. The channel region and the bottom semiconductor substrate 201 are isolated by a gap structure 207, which is obtained by self-aligning and removing the first semiconductor epitaxial layer 202 at the bottom of the channel region. Because the gap structure 207 isolates the channel region and the semiconductor substrate 201, the channel region can achieve a thin-layer structure of full depletion, thereby improving the gate structure's control over the channel region and thus improving device performance. At the same time, due to the isolation effect of the gap structure 207, this invention can eliminate the leakage path between the source and drain through the semiconductor substrate 201, thus reducing device leakage. Furthermore, since this invention does not require an SOI substrate, it can reduce process costs.
[0080] like Figures 3A to 3E The diagram shown is a schematic cross-sectional view of the device structure in each step of the manufacturing method of the planar device according to an embodiment of the present invention; the manufacturing method of the planar device according to an embodiment of the present invention includes the following steps:
[0081] Step 1, such as Figure 3AAs shown, a semiconductor substrate 201 is provided, and a first semiconductor epitaxial layer 202 and a second semiconductor epitaxial layer 203 are sequentially formed on the top surface of the semiconductor substrate 201.
[0082] The material of the first semiconductor epitaxial layer 202 is different from the material of the semiconductor substrate 201, and the material of the first semiconductor epitaxial layer 202 is different from the material of the second semiconductor epitaxial layer 203.
[0083] In the method of this embodiment of the invention, the material of the second semiconductor epitaxial layer 203 is the same as the material of the semiconductor substrate 201.
[0084] The material of the second semiconductor epitaxial layer 203 includes Si or SiGe. The material of the first semiconductor epitaxial layer 202 includes Si or SiGe. Since the materials of the first semiconductor epitaxial layer 202 and the second semiconductor epitaxial layer 203 are different, there can be various combinations of their materials. For example, in some embodiments, the material of the second semiconductor epitaxial layer 203 is Si, and the material of the first semiconductor epitaxial layer 202 is SiGe. In other embodiments, the material of the second semiconductor epitaxial layer 203 may be SiGe, and the material of the first semiconductor epitaxial layer 202 may be Si.
[0085] Step 2, as follows Figure 3B As shown, patterned etching is performed on the first semiconductor epitaxial layer 202 and the second semiconductor epitaxial layer 203, including:
[0086] The source / drain formation region 302 of the planar device is opened and the gate formation region 301 of the planar device is covered, with the source / drain formation region 302 located on both sides of the gate formation region 301. In some embodiments, a photoresist pattern 304 formed by photolithography is used to open the source / drain formation region 302 of the planar device and cover the gate formation region 301 of the planar device. In other embodiments, the photoresist pattern 304 can also be replaced with a hard mask layer pattern.
[0087] Etching is performed to remove both the second semiconductor epitaxial layer 203 and the first semiconductor epitaxial layer 202 in the source / drain formation region 302 and form a first trench 303; the second semiconductor epitaxial layer 203 and the first semiconductor epitaxial layer 202 in the gate formation region 301 are retained.
[0088] Step 3, as follows Figure 3DAs shown, a first dielectric layer 204 is filled in the first trench 303, the top surface of the first dielectric layer 204 is located between the top surface and the bottom surface of the second semiconductor epitaxial layer 203, and the side surface of the second semiconductor epitaxial layer 203 above the top surface of the first dielectric layer 204 is exposed.
[0089] In the method of this embodiment of the invention, the material of the first dielectric layer 204 includes an oxide layer.
[0090] In some preferred embodiments, the first dielectric layer 204 is formed using an FCVD process. Step three includes the following sub-steps:
[0091] like Figure 3C As shown, the first dielectric layer 204 is grown using the FCVD process, and the first dielectric layer 204 completely fills the first trench 303 and extends beyond the first trench 303.
[0092] like Figure 3C As shown, the first dielectric layer 204 is planarized by performing the 0th chemical mechanical polishing process. The 0th chemical mechanical polishing process removes the first dielectric layer 204 outside the first trench 303 and makes the top surface of the first dielectric layer 204 inside the first trench 303 and the top surface of the second semiconductor epitaxial layer 203 flat.
[0093] like Figure 3D As shown, the first dielectric layer 204 is etched back so that the top surface of the first dielectric layer 204 is lowered between the top and bottom surfaces of the second semiconductor epitaxial layer 203. Figure 3D In the diagram, dashed line AA represents the top surface position of the second semiconductor epitaxial layer 203, and dashed line BB represents the top surface position of the first dielectric layer 204.
[0094] Step 4, as follows Figure 3E As shown, a third semiconductor epitaxial layer 205 is formed by a first selective epitaxial growth on the top surface and exposed side surface of the second semiconductor epitaxial layer 203.
[0095] The third semiconductor epitaxial layer 205 is formed on the top surface and exposed side surface of the second semiconductor epitaxial layer 203 and extends from the exposed side surface of the second semiconductor epitaxial layer 203 to the top surface of the first dielectric layer 204.
[0096] The second semiconductor epitaxial layer 203 and the third semiconductor epitaxial layer 205 constitute the top epitaxial layer 206.
[0097] In the method of this embodiment of the invention, the material of the second semiconductor epitaxial layer 203 is the same as the material of the semiconductor substrate 201; the material of the third semiconductor epitaxial layer 205 is the same as the material of the second semiconductor epitaxial layer 203. Figure 3E In the same pattern, the second semiconductor epitaxial layer 203, the semiconductor substrate 201 and the third semiconductor epitaxial layer 205 are represented.
[0098] Step 5, as follows Figure 3E As shown, the top epitaxial layer 206 is planarized using a first chemical mechanical polishing process, so that the top surface of the top epitaxial layer 206 is a planarized surface.
[0099] In some embodiments, after the first chemical mechanical polishing process is completed, the top surface of the top epitaxial layer 206 is higher than the top surface of the second semiconductor epitaxial layer 203; Figure 3E In the diagram, the dashed line CC represents the position of the top surface of the top epitaxial layer 206. At this point, the position of the dashed line CC will be higher than... Figure 3D At the position of the dashed line AA, in the gate forming region 301, a portion of the thickness of the third semiconductor epitaxial layer 205 is still retained above the top surface of the second semiconductor epitaxial layer 203.
[0100] In some embodiments, the method can also be as follows: after the first chemical mechanical polishing process is completed, the top surface of the top epitaxial layer 206 is located below or at the same level as the top surface of the second semiconductor epitaxial layer 203, and the third semiconductor epitaxial layer 205 on the top surface of the second semiconductor epitaxial layer 203 is removed; at this time, the position of the dashed line CC will be equal to or lower than... Figure 3D At the position of the dashed line AA, in the gate forming region 301, the third semiconductor epitaxial layer 205 above the top surface of the second semiconductor epitaxial layer 203 will be completely removed, and the top surface of the second semiconductor epitaxial layer 203 will remain unchanged or be lowered.
[0101] In the method of this invention embodiment, the position of the top surface of the top epitaxial layer 206 can be adjusted by adjusting the process parameters of the first chemical mechanical polishing process, and finally the thickness of the subsequent channel region can be adjusted, and a fully depleted channel region can be achieved.
[0102] Step Six, as Figure 3FAs shown, selective etching is performed to remove the first semiconductor epitaxial layer 202 in the gate formation region 301 by self-alignment, forming a void structure 207 formed after the removal of the first semiconductor epitaxial layer 202. The side surface of the void structure 207 is defined by self-alignment of the side surface of the first dielectric layer 204, the top surface of the void structure 207 is defined by self-alignment of the bottom surface of the second semiconductor epitaxial layer 203, and the bottom surface of the void structure 207 is defined by self-alignment of the top surface of the semiconductor substrate 201.
[0103] Step 7, as follows Figure 2A As shown, a gate structure is formed on the top surface of the top epitaxial layer 206 on top of the void structure 207; the top epitaxial layer 206 covered by the gate structure serves as a channel region.
[0104] In the method of this invention, the gate structure includes a gate dielectric layer 208 and a gate conductive material layer 209 stacked sequentially. In some specific embodiments, the gate dielectric layer 208 is made of silicon dioxide or a high dielectric constant material. The gate conductive material layer 209 is made of polysilicon or a metal gate.
[0105] Step 8: Perform source and drain injection to form source region 210 and drain region 211 in the top epitaxial layer 206 on both sides of the gate structure, respectively.
[0106] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A planar device, characterized in that, A planar device is formed on a semiconductor substrate, and a first semiconductor epitaxial layer and a second semiconductor epitaxial layer are sequentially formed on the top surface of the semiconductor substrate; the material of the first semiconductor epitaxial layer is different from the material of the semiconductor substrate, and the material of the first semiconductor epitaxial layer is different from the material of the second semiconductor epitaxial layer; The planar device formation region includes a gate formation region and source / drain formation regions located on both sides of the gate formation region; In the formation region of the planar device, the first semiconductor epitaxial layer and the second semiconductor epitaxial layer have a patterned structure; The patterned structure includes: the second semiconductor epitaxial layer and the first semiconductor epitaxial layer in the source / drain formation region are removed and a first trench is formed; the second semiconductor epitaxial layer in the gate formation region is retained and the first semiconductor epitaxial layer is removed; A first dielectric layer is filled in the first trench, the top surface of the first dielectric layer is located between the top surface and the bottom surface of the second semiconductor epitaxial layer, and the side surface of the second semiconductor epitaxial layer above the top surface of the first dielectric layer is exposed. A void structure formed by removing the first semiconductor epitaxial layer is formed in the gate region. The side surface of the void structure is defined by the side surface of the first dielectric layer, the top surface of the void structure is defined by the bottom surface of the second semiconductor epitaxial layer, and the bottom surface of the void structure is defined by the top surface of the semiconductor substrate. A third semiconductor epitaxial layer is formed on the top surface and exposed side surface of the second semiconductor epitaxial layer, and the third semiconductor epitaxial layer extends from the exposed side surface of the second semiconductor epitaxial layer to the top surface of the first dielectric layer; The second semiconductor epitaxial layer and the third semiconductor epitaxial layer constitute a top epitaxial layer, and the top surface of the top epitaxial layer is a planarized surface; A gate structure is formed on the top surface of the top epitaxial layer at the top of the void structure, and the top epitaxial layer covered by the gate structure serves as a channel region. The source and drain regions are formed in the top epitaxial layer on both sides of the gate structure.
2. The planar device as described in claim 1, characterized in that: The material of the second semiconductor epitaxial layer is the same as the material of the semiconductor substrate; the material of the third semiconductor epitaxial layer is the same as the material of the second semiconductor epitaxial layer.
3. The planar device as described in claim 2, characterized in that: The material of the second semiconductor epitaxial layer includes Si or SiGe.
4. The planar device as described in claim 3, characterized in that: The material of the first semiconductor epitaxial layer includes Si or SiGe.
5. The planar device as described in claim 4, characterized in that: The material of the second semiconductor epitaxial layer is Si, and the material of the first semiconductor epitaxial layer is SiGe; or, the material of the second semiconductor epitaxial layer is SiGe, and the material of the first semiconductor epitaxial layer is Si.
6. The planar device as described in claim 1, characterized in that: The material of the first dielectric layer includes an oxide layer.
7. The planar device as described in claim 6, characterized in that: The first dielectric layer is an FCVD oxide layer.
8. The planar device as described in claim 1, characterized in that: The top surface of the top epitaxial layer is higher than the top surface of the second semiconductor epitaxial layer; or, the top surface of the top epitaxial layer is located below or at the same level as the top surface of the second semiconductor epitaxial layer, and the third semiconductor epitaxial layer on the top surface of the second semiconductor epitaxial layer is planarized and removed.
9. A method for manufacturing a planar device, characterized in that, Includes the following steps: Step 1: Provide a semiconductor substrate, and sequentially form a first semiconductor epitaxial layer and a second semiconductor epitaxial layer on the top surface of the semiconductor substrate; The material of the first semiconductor epitaxial layer is different from the material of the semiconductor substrate, and the material of the first semiconductor epitaxial layer is different from the material of the second semiconductor epitaxial layer; Step 2: Perform patterned etching on the first semiconductor epitaxial layer and the second semiconductor epitaxial layer, including: The source / drain formation regions of the planar device are opened and the gate formation region of the planar device is covered, wherein the source / drain formation regions are located on both sides of the gate formation region; Etching is performed to remove both the second semiconductor epitaxial layer and the first semiconductor epitaxial layer in the source / drain formation region, forming a first trench; the second semiconductor epitaxial layer and the first semiconductor epitaxial layer are retained in the gate formation region; Step 3: Fill the first trench with a first dielectric layer, the top surface of the first dielectric layer being located between the top and bottom surfaces of the second semiconductor epitaxial layer, and the side surface of the second semiconductor epitaxial layer above the top surface of the first dielectric layer being exposed. Step 4: Perform a first selective epitaxial growth on the top surface and exposed side surfaces of the second semiconductor epitaxial layer to form a third semiconductor epitaxial layer; The third semiconductor epitaxial layer is formed on the top surface and exposed side surface of the second semiconductor epitaxial layer, and the third semiconductor epitaxial layer extends from the exposed side surface of the second semiconductor epitaxial layer to the top surface of the first dielectric layer; The second semiconductor epitaxial layer and the third semiconductor epitaxial layer constitute the top epitaxial layer; Step 5: The top epitaxial layer is planarized using a first chemical mechanical polishing process to make the top surface of the top epitaxial layer a planarized surface; Step 6: Perform selective etching to remove the first semiconductor epitaxial layer in the gate formation region and form a void structure formed after the first semiconductor epitaxial layer is removed. The side surface of the void structure is defined by the side surface of the first dielectric layer, the top surface of the void structure is defined by the bottom surface of the second semiconductor epitaxial layer, and the bottom surface of the void structure is defined by the top surface of the semiconductor substrate. Step 7: Form a gate structure on the top surface of the top epitaxial layer at the top of the void structure; the top epitaxial layer covered by the gate structure serves as a channel region; Step 8: Perform source and drain injection to form source and drain regions in the top epitaxial layers on both sides of the gate structure, respectively.
10. The method for manufacturing a planar device as described in claim 9, characterized in that: The material of the second semiconductor epitaxial layer is the same as the material of the semiconductor substrate; the material of the third semiconductor epitaxial layer is the same as the material of the second semiconductor epitaxial layer.
11. The method for manufacturing a planar device as described in claim 10, characterized in that: The material of the second semiconductor epitaxial layer includes Si or SiGe.
12. The method for manufacturing a planar device as described in claim 11, characterized in that: The material of the first semiconductor epitaxial layer includes Si or SiGe.
13. The method for manufacturing a planar device as described in claim 12, characterized in that: The material of the second semiconductor epitaxial layer is Si, and the material of the first semiconductor epitaxial layer is SiGe; or, the material of the second semiconductor epitaxial layer is SiGe, and the material of the first semiconductor epitaxial layer is Si.
14. The method for manufacturing a planar device as described in claim 9, characterized in that: The material of the first dielectric layer includes an oxide layer.
15. The method for manufacturing a planar device as described in claim 14, characterized in that: The first dielectric layer is formed using the FCVD process.
16. The method for manufacturing a planar device as described in claim 15, characterized in that: Step three includes the following sub-steps: The first dielectric layer is grown using the FCVD process, and the first dielectric layer completely fills the first trench and extends beyond the first trench. The first dielectric layer is planarized by performing a 0th chemical mechanical polishing process. The 0th chemical mechanical polishing process removes the first dielectric layer outside the first trench and makes the top surface of the first dielectric layer inside the first trench and the top surface of the second semiconductor epitaxial layer flush. The first dielectric layer is etched back so that the top surface of the first dielectric layer is lowered between the top and bottom surfaces of the second semiconductor epitaxial layer.
17. The method for manufacturing a planar device as described in claim 9, characterized in that: After the first chemical mechanical polishing process is completed, the top surface of the top epitaxial layer is higher than the top surface of the second semiconductor epitaxial layer; or, after the first chemical mechanical polishing process is completed, the top surface of the top epitaxial layer is located below or at the same level as the top surface of the second semiconductor epitaxial layer, and the third semiconductor epitaxial layer on the top surface of the second semiconductor epitaxial layer is removed.