Semiconductor package

Abstract

The invention provides a semiconductor package. The semiconductor package includes a semiconductor chip in which a plurality of Hall elements are embedded, and a plurality of external terminals disposed on one surface side of the semiconductor chip. The first Hall element and the second Hall element are configured to be point-symmetric with respect to a point of a center of the semiconductor package in a plan view. At least a part of the first Hall element is covered by one of the plurality of first external terminals in a plan view, and at least a part of the second Hall element is covered by one of the plurality of second external terminals in a plan view. A first region of the first Hall element covered by one first external terminal in plan view and a second region of the second Hall element covered by one second external terminal in plan view are point-symmetric with respect to a point of a center of the semiconductor package in plan view.

Description

[0001] This application is a divisional application of the invention patent application with application number 202310378736.1, application date 2023.04.11, and invention title "Semiconductor Package and Driving Device". Technical Field

[0002] This invention relates to a semiconductor package and a driving device. Background Technology

[0003] Patent Document 1 discloses a semiconductor package having terminals arranged in a serrated shape along its long side. Patent Document 2 discloses a method and apparatus for compensating for Hall sensors in terms of both temperature and mechanical stress. Patent Document 3 discloses reducing offset by switching the direction of the drive current of the Hall element.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent No. 6826088

[0007] Patent Document 2: Japanese Patent No. 6371338

[0008] Patent Document 3: Japanese Patent No. 5658715 Summary of the Invention

[0009] The problem the invention aims to solve

[0010] The goal is to reduce the effects of offset in semiconductor packages that incorporate Hall elements.

[0011] Solution for solving the problem

[0012] One aspect of the present invention relates to a semiconductor package comprising a semiconductor chip having a plurality of built-in Hall elements and a plurality of external terminals disposed on one side of the semiconductor chip. The semiconductor package may be rectangular in shape extending along a first direction when viewed from above. The plurality of external terminals may include a plurality of first external terminals included in a first column along the first direction, and a plurality of second external terminals included in a second column facing the first column and along the first direction, sandwiching the center of the semiconductor package in the middle. The center of gravity of each of the plurality of first external terminals may not overlap with each of the plurality of second external terminals in the first direction and in a second direction intersecting the first direction. The plurality of Hall elements may include a first Hall element and a second Hall element. The first Hall element and the second Hall element may be configured to be point-symmetric about the center of the semiconductor package when viewed from above. The first Hall element may be at least partially covered by one of the plurality of first external terminals when viewed from above. The second Hall element may be at least partially covered by one of the plurality of second external terminals when viewed from above. The first region of the first Hall element, which is covered by the first external terminal when viewed from above, and the second region of the second Hall element, which is covered by the second external terminal when viewed from above, may be point-symmetric about the center of the semiconductor package when viewed from above.

[0013] In the semiconductor package, the plurality of Hall elements may include a first Hall element and a third Hall element belonging to a first group, and a second Hall element and a fourth Hall element belonging to a second group. The third Hall element and the fourth Hall element may be configured to be point-symmetric about the center of the semiconductor package when viewed from above.

[0014] In any of the semiconductor packages, the first Hall element and the third Hall element may be disposed on the first event region and the second Hall element and the fourth Hall element may be disposed on the third event region when the semiconductor package is divided into a first event region, a second event region, a third event region, and a fourth event region by a first axis passing through the center of the semiconductor package in a top view and along the first axis and the second axis passing through the second axis and the second axis passing through the second axis and the third axis passing through the second axis and the fourth axis passing through the second axis and the fourth axis passing through the second axis and the third ..., respectively.

[0015] In any of the semiconductor packages, the semiconductor chip may further include a control circuit that outputs a drive signal for controlling a drive unit that causes the position or orientation of a magnet to change relative to the semiconductor package, based on the sum of outputs representing the magnitude of the magnetic field from the first Hall element, the second Hall element, the third Hall element, and the fourth Hall element.

[0016] In any of the semiconductor packages, the control circuitry may include an amplifier circuitry that amplifies the sum of the outputs.

[0017] In any of the semiconductor packages, the control circuit may further control the drive unit based on the difference between the sum of the outputs representing the magnitude of the magnetic field from the first Hall element and the third Hall element and the sum of the outputs representing the magnitude of the magnetic field from the second Hall element and the fourth Hall element.

[0018] In any of the semiconductor packages, the control circuitry may include an amplifier circuitry that amplifies the ratio of the sum to the difference of the outputs representing the magnitude of the magnetic field from the first Hall element, the second Hall element, the third Hall element, and the fourth Hall element.

[0019] In any of the semiconductor packages, the plurality of external terminals may include a pair of power supply terminals for supplying power to the semiconductor package, a pair of drive terminals for outputting drive signals from the control circuit to the drive unit, and a pair of communication terminals for communicating with the outside. The first external terminal and the second external terminal may be one of the pair of drive terminals and one of the pair of power supply terminals.

[0020] In any of the semiconductor packages, the third Hall element and the fourth Hall element may not overlap with any of the plurality of external terminals when viewed from above.

[0021] In either of the semiconductor packages, the first Hall element can be completely covered by the first external terminal when viewed from above. The second Hall element can be completely covered by the second external terminal when viewed from above.

[0022] In either of the semiconductor packages, the first Hall element and the third Hall element can be completely covered by the first external terminal when viewed from above. The second Hall element and the fourth Hall element can be completely covered by the second external terminal when viewed from above.

[0023] In either of the semiconductor packages, the first Hall element and the second Hall element may have a pair of first electrodes facing each other in the first direction and a pair of second electrodes facing each other in a second direction intersecting the first direction. Alternatively, in the first Hall element, the pair of first electrodes may be output electrodes. Alternatively, in the second Hall element, the pair of second electrodes may be output electrodes.

[0024] In any of the semiconductor packages, the first Hall element is completely covered by the first external terminal when viewed from above. The second Hall element is completely covered by the second external terminal when viewed from above. The third Hall element is partially covered by the first external terminal when viewed from above. The fourth Hall element is partially covered by the second external terminal when viewed from above.

[0025] In either of the semiconductor packages, the third Hall element and the fourth Hall element may have a pair of first electrodes facing each other in the first direction and a pair of second electrodes facing each other in a second direction intersecting the first direction. Alternatively, in the third Hall element, the pair of second electrodes may be output electrodes. Alternatively, in the fourth Hall element, the pair of first electrodes may be output electrodes.

[0026] In any of the semiconductor packages, the first external terminal and the second external terminal may be the external terminal among the plurality of external terminals that is closest to the point of the center of the semiconductor package when viewed from above.

[0027] In any of the semiconductor packages, the first external terminal and the second external terminal may be point-symmetric about the center of the semiconductor package when viewed from above.

[0028] In any of the semiconductor packages, the first Hall element and the third Hall element may be arranged in a row along the first direction. The second Hall element and the fourth Hall element may also be arranged in a row along the first direction.

[0029] In any of the semiconductor packages, the third Hall element and the fourth Hall element may be arranged in a row along a second direction that intersects the first direction.

[0030] In any of the semiconductor packages, the width of the semiconductor package in the first direction may be longer than the width of the semiconductor package in the second direction intersecting the first direction.

[0031] In any of the semiconductor packages, the width in the first direction can be at least 1.65 times the length of the width in the second direction.

[0032] In any of the semiconductor packages, the width in the first direction can be at least 2.5 times the length of the width in the second direction.

[0033] In any of the semiconductor packages, the total area of ​​the plurality of external terminals when viewed from above can be more than 14% of the total area of ​​the semiconductor package when viewed from above.

[0034] In any of the semiconductor packages, the total area of ​​the plurality of external terminals when viewed from above can be more than 19% of the total area of ​​the semiconductor package when viewed from above.

[0035] In any of the semiconductor packages, the plurality of external terminals may be configured in two rows along the first direction.

[0036] Any of the semiconductor packages may further include: a redistribution layer disposed above the semiconductor chip and electrically connected to the semiconductor chip; and a seal disposed above the redistribution layer. The plurality of external terminals may be electrically connected to the redistribution layer through the seal.

[0037] In any of the semiconductor packages, the redistribution layer may include wiring extending more than 100 μm from at least one of the plurality of external terminals along the first direction and electrically connected to the semiconductor chip.

[0038] In any of the semiconductor packages, the wiring may have a portion extending along the first direction at the center of the at least one external terminal when viewed from above.

[0039] In any of the semiconductor packages, the redistribution layer may include wiring extending more than 100 μm from at least one of the plurality of external terminals along the second direction and electrically connected to the semiconductor chip.

[0040] The semiconductor package may be a wafer-level chip-scale package (WL-CSP).

[0041] One aspect of the present invention relates to a driving device that may include a first portion for holding a magnet. The driving device may include a second portion that holds any of the semiconductor packages facing the magnet, and the second portion is held on the first portion in a manner capable of changing the position or orientation of the second portion relative to the first portion. The driving device may include a driving unit for changing the position or orientation of the second portion relative to the first portion. The semiconductor package may output a driving signal to the driving unit based on outputs from the plurality of Hall elements.

[0042] In the driving device, the first part may also retain the lens portion. The second part may also retain an imaging element for capturing an image obtained by imaging via the lens portion.

[0043] Furthermore, the above description of the invention does not enumerate all the features of the invention. In addition, sub-combinations of these feature groups can also form an invention. Attached Figure Description

[0044] Figure 1 This is an exploded 3D view of the camera module.

[0045] Figure 2 This is a diagram illustrating an example of the circuit structure of a semiconductor package.

[0046] Figure 3 This is a diagram illustrating the situation where the offset is increased by amplifying the output signal of the magnetic sensor.

[0047] Figure 4 This is a top view taken from the external terminal side of the semiconductor package.

[0048] Figure 5 It is shown schematically. Figure 4 The diagram shows the AA section.

[0049] Figure 6 This is a graph showing the relationship between the moving distance of the lens unit and the magnitude of the magnetic field detected by the magnetic sensor.

[0050] Figure 7 This is a diagram showing an example of the configuration of multiple Hall elements.

[0051] Figure 8 This is a diagram showing an example of the configuration of multiple Hall elements.

[0052] Figure 9 This is a diagram showing an example of the configuration of multiple Hall elements.

[0053] Figure 10 This is a diagram showing an example of the configuration of multiple Hall elements.

[0054] Figure 11 This is a diagram showing an example of the configuration of multiple Hall elements.

[0055] Figure 12 This is a diagram showing an example of the configuration of multiple Hall elements.

[0056] Figure 13 This is a diagram showing an example of the configuration of multiple Hall elements.

[0057] Figure 14 This is a diagram showing an example of the configuration of multiple Hall elements.

[0058] Figure 15 This is a diagram showing the equivalent circuit of a Hall element.

[0059] Figure 16A This is a diagram showing the equivalent circuit of Hall element 111S1.

[0060] Figure 16B This is a diagram showing the equivalent circuit of Hall element 111S2.

[0061] Figure 16C This is a diagram showing the equivalent circuit of Hall element 111S3.

[0062] Figure 16D This is a diagram showing the equivalent circuit of Hall element 111S4.

[0063] Figure 17 This diagram is used to explain the functions of each external terminal.

[0064] Figure 18 This is a diagram showing the wiring configuration in the redistribution layer of a semiconductor package. Detailed Implementation

[0065] The present invention will now be described through embodiments, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily necessary for the solution of the invention.

[0066] Figure 1 An exploded perspective view of the camera module 10 according to this embodiment is shown. The camera module 10 includes a substrate 300, a base 20, a holding frame 30, and a lens unit 40. An image sensor 302 is disposed on the substrate 300. The image sensor 302 may be composed of a CCD or a CMOS. The image sensor 302 outputs image data of the optical image obtained by imaging via the lens unit 40.

[0067] A retaining frame 30 internally holds the lens unit 40. A magnet 32 ​​is disposed on the outer surface of the retaining frame 30. The base 20 holds the retaining frame 30 and the lens unit 40 together, allowing them to move along the optical axis (Z-axis) and in directions intersecting the optical axis (X-axis and Y-axis). A coil 200 and a semiconductor package 100 are disposed on the side of the base 20. The coil 200 is positioned opposite the magnet 32. The coil 200 can be an air-core coil.

[0068] The magnet 32 ​​and coil 200 function as a VCM (voice coil motor), which is the drive source for moving or rotating the retaining frame 30 relative to the base 20. The retaining frame 30 is an example of the first part, and the base 20 is an example of the second part.

[0069] Within the magnetic field of magnet 32, when current flows through coil 200, a force is generated in coil 200 in a direction perpendicular to the magnetic field. This imparts a thrust to holding frame 30 in the X or Y direction. Alternatively, the configuration of coil 200 or the orientation of the magnetic field of magnet 32 ​​can be designed such that a thrust in the Z direction is imparted to holding frame 30 by current flowing through coil 200.

[0070] A semiconductor package 100 is disposed in the hollow portion of the coil 200. The semiconductor package 100 can function as a position sensor that detects the position or orientation of the holding frame 30 relative to the base 20. The position sensor can be a magnetic sensor including a Hall element. The position sensor can output a voltage corresponding to the magnitude of the change in the magnetic field. As the holding frame 30 moves, the positional relationship between the semiconductor package 100 and the magnet 32 ​​changes, and the magnitude of the magnetic field detected changes according to the position. Thus, the position sensor detects the position of the magnet 32 ​​relative to the semiconductor package 100, that is, the position of the holding frame 30 relative to the base 20. In this embodiment, a magnetic sensor including a Hall element that applies the Hall effect and detects changes in the external magnetic field based on the generated electromotive force is described as an example. However, the magnetic sensor is not limited to having a Hall element. The magnetic sensor can also have an electromagnetic conversion element other than a Hall element. The magnetic sensor can also be a variety of sensors capable of detecting magnetic fields, such as a spin valve magnetoresistive effect element (GMR element, TMR element, etc.) whose resistance changes according to the change in the external magnetic field, or a combination of these various sensors. Alternatively, a magnetic sensor can also be composed of a group of sensor elements, which includes multiple magnetic sensor elements.

[0071] The semiconductor package 100 supplies current to the coil 200 according to the position or orientation of the retaining frame 30 relative to the base 20, so that the position or orientation of the retaining frame 30 is the target position or orientation. The semiconductor package 100 may also be disposed outside the coil 200. Alternatively, the retaining frame 30 may include the semiconductor package 100 and the coil 200, and the base 20 may include a magnet 32.

[0072] The camera module 10 configured in this way uses the magnet 32 ​​and the coil 200 as driving sources. The semiconductor package 100 causes current to flow through the coil 200, so that the position or orientation of the lens unit 40 relative to the imaging surface of the imaging element 302 becomes the desired position or orientation. Thus, the lens unit 40 functions as a zoom lens or a focusing lens. Alternatively, the semiconductor package 100 causes current to flow through the coil 200, so that the position or orientation of the lens unit 40 changes in the direction of eliminating image jitter, thereby performing image jitter correction. In this embodiment, a VCM (voice coil motor) is used as an example to describe the driving source for driving the lens unit 40. However, the driving source is not limited to a VCM. The camera module 10 may also use microelectromechanical systems (MEMS), shape memory alloys (SMA), polymer actuators (EAP), bimetallic actuators, or piezoelectric elements as driving sources for driving the lens unit 40, in addition to a VCM.

[0073] Figure 2 This diagram illustrates an example of the circuit structure of a semiconductor package 100. The semiconductor package 100 includes a magnetic sensor 112, an amplifier 113, an A / D converter 114, a PID control unit 115, a D / A converter 116, and an output driver 117. The magnetic sensor 112, amplifier 113, A / D converter 114, PID control unit 115, D / A converter 116, and output driver 117 can be integrated into a semiconductor chip.

[0074] The magnetic sensor 112 has multiple Hall elements and outputs a voltage or current corresponding to the magnitude of the magnetic field as a position signal representing the position of the lens unit 40. The amplifier 113 amplifies the position signal output from the magnetic sensor 112. The A / D converter 114 converts the amplified analog position signal from the amplifier 113 into a digital signal.

[0075] In order to control the lens unit 40 to change its position to the target position, the PID control unit 115 outputs a drive signal through PID control (proportional-integral-derivative control) based on the position of the lens unit 40 represented by the digital signal output from the A / D converter 114 and the target position of the lens unit 40 output from the position command generation unit 210. The control unit such as the CPU or MPU microprocessor or MCU microcontroller used to control the camera module 10 may have the position command generation unit 210.

[0076] The D / A converter 116 converts the drive signal from a digital signal to an analog signal and outputs it to the output driver 117. The output driver 117 outputs a current corresponding to the drive signal to the coil 200.

[0077] like Figure 3 As shown, the signal output from the magnetic sensor 112 contains considerable noise. The amplifier 113 following the magnetic sensor 112 directly amplifies the noisy signal. If the noise is high, i.e., if the offset is large, even if the amplification rate of the amplifier 113 is increased, it may be impossible to properly amplify the signal other than the noise due to the limited size of the signal that can be input to the A / D converter 114. By reducing the offset contained in the signal output from the magnetic sensor 112, the amplification rate can be increased, resulting in an improved signal-to-noise ratio (S / N ratio).

[0078] Figure 4 This is a top view of the semiconductor package 100 from the side of the external terminals 102. The semiconductor package 100 has multiple external terminals 102. The semiconductor package 100 has six external terminals 102.

[0079] The semiconductor package 100, when viewed from above, is a rectangular shape extending along a first direction (X-axis direction). Here, "rectangular shape" also includes the concept of a generally rectangular shape. A generally rectangular shape includes quadrilaterals with four angles other than 90°, quadrilaterals with four angles within the range of 90° ± 5°, or rounded quadrilaterals with chamfered corners. The semiconductor package 100 may be a rectangle whose width in the first direction (X-axis direction) is longer than its width in the second direction (Z-axis direction) when viewed from above. A plurality of external terminals 102 may be arranged in two columns along the first direction. The plurality of external terminals 102 includes a plurality of external terminals 102A1, 102A2, and 102A3 included in a first column along the first direction (X-axis direction), and a plurality of external terminals 102B1, 102B2, and 102B3 included in a second column facing the first column and along the first direction (X-axis direction) such that the center P of the semiconductor package 100 is sandwiched in the middle. The centroids of each of the plurality of external terminals 102A1, 102A2, and 102A3 do not overlap with the centroids of each of the plurality of external terminals 102B1, 102B2, and 102B3 in the first direction (X-axis direction) and the second direction (Z-axis direction) intersecting the first direction. That is, the plurality of external terminals 102A1, 102A2, 102A3 and the plurality of external terminals 102B1, 102B2, and 102B3 are arranged in a serrated shape along the first direction.

[0080] The spacing between the external terminals 102A1, 102A2, and 102A3 in the first direction is the same as the spacing between the external terminals 102B1, 102B2, and 102B3 in the first direction, and the external terminals 102A1, 102A2, and 102A3 are offset from the external terminals 102B1, 102B2, and 102B3 in the first direction. The external terminals 102A1, 102A2, and 102A3 are also offset from the external terminals 102B1, 102B2, and 102B3 in the second direction. Here, "same" also includes the concept of being substantially the same. That is, the spacing between the external terminals 102A1, 102A2, and 102A3 in the first direction may not be exactly the same as the spacing between the external terminals 102B1, 102B2, and 102B3 in the first direction.

[0081] As the miniaturization of ICs, such as semiconductor packages 100, continues to advance, the proportion of external terminals in the surface area of ​​the IC is increasing. Furthermore, when the semiconductor package 100 is disposed within the hollow portion of the coil 200, the gap in the hollow portion is narrow; therefore, the shape of the semiconductor package 100 is preferably an elongated rectangular shape. By ensuring the surface of such an elongated semiconductor package 100... Figure 4 By arranging the plurality of external terminals 102 in a serrated shape along the first direction as shown, the width of the semiconductor package 100 in the second direction can be narrowed. Each of the plurality of external terminals 102A1, 102A2, and 102A3 is configured to overlap only partially with each of the plurality of external terminals 102B1, 102B2, and 102B3 in the second direction, thereby narrowing the width of the semiconductor package 100 in the second direction. By arranging the plurality of external terminals 102 in a serrated shape, the semiconductor package 100 can be miniaturized in the second direction (width direction) while maintaining the same terminal shape or number. Therefore, even if the semiconductor package 100 is miniaturized in the width direction, the reduction in stability during mounting can be suppressed.

[0082] The width of the semiconductor package 100 in a first direction can be at least 1.65 times its length in a second direction. The width of the semiconductor package 100 in the first direction can be at least 2.5 times its length in a second direction. The total area of ​​the plurality of external terminals 102 in a top view can be at least 14% of the total area of ​​the semiconductor package 100 in a top view. The total area of ​​the plurality of external terminals 102 in a top view can be at least 19% of the total area of ​​the semiconductor package 100 in a top view.

[0083] Figure 5 schematically shown Figure 4 The AA section is shown. In this embodiment, the semiconductor package 100 is described as a wafer-level chip-scale package (WL-CSP) type semiconductor package. However, the semiconductor package 100 may also be a fan-out wafer-level package (FO-WLP) type semiconductor package. The semiconductor package 100 includes a silicon substrate 110, a redistribution layer 120 disposed on a first side of the silicon substrate 110, and a seal 130 disposed on at least one side of the redistribution layer 120 opposite to the side of the silicon substrate 110. A semiconductor chip is embedded in the silicon substrate 110. The semiconductor chip may include a magnetic sensor 112, an amplifier 113, an A / D converter 114, a PID control unit 115, a D / A converter 116, and an output driver 117.

[0084] In the camera module 10 equipped with such a semiconductor package 100, the lens unit 40 is becoming increasingly heavier due to the increasing pixel count. There is a tendency for the image sensor 302 to become larger and hotter with increasing pixel count. Furthermore, the increased weight of the lens unit 40 increases the current required to drive it, leading to a temperature rise. This temperature rise also affects the magnetic sensor 112 built into the semiconductor package 100. Specifically, the offset of the magnetic sensor 112 increases with temperature. If the offset of the magnetic sensor 112 increases, the signal-to-noise ratio (S / N ratio) decreases. When the camera module 10 uses the magnetic sensor 112, which has poor temperature characteristics and a low S / N ratio, to control the lens unit 40, noise suppression performance deteriorates, the error between the actual position and the target position of the lens unit 40 increases, and it becomes impossible to perform high-precision position control of the lens unit 40. Consequently, high-precision image jitter correction is also difficult to achieve.

[0085] Figure 6 This illustrates the relationship between the moving distance of the lens unit 40 and the magnitude of the magnetic field detected by the magnetic sensor 112. Line A1 shows the relationship between the moving distance of the lens unit 40 and the magnitude of the magnetic field detected by the magnetic sensor 112 in the case of a typical camera. Line A2 shows the relationship between the moving distance of the lens unit 40 and the magnitude of the magnetic field detected by the magnetic sensor 112 in the case of a high-resolution, high-performance camera. Figure 6 As shown, in the case of a high-performance camera, the movement distance of the lens unit 40 corresponding to the change in the magnitude of the magnetic field is longer than that in the case of a conventional camera. That is, even if the error of the signal detected by the magnetic sensor 112 is the same, the positional error of the lens unit 40 in the high-performance camera is larger than that in the conventional camera. With increasing pixel density, the positional error of the lens unit 40 significantly manifests as image jitter. In other words, the decrease in the S / N ratio of the magnetic sensor 112 has a more significant impact on high-performance cameras, such as the inability to perform high-precision image jitter correction. Therefore, it is desirable to further reduce the influence of the offset of the magnetic sensor 112.

[0086] However, as Figure 7As shown, when multiple Hall elements 111 constituting the magnetic sensor 112 are arranged side-by-side along a first direction (X-axis direction) and a second direction (Z-axis direction), the size of the overlapping area between the Hall elements 111 and the external terminals 102 when viewed from above will vary due to the serrated arrangement of the external terminals 102. When the size of the overlapping area differs, the magnitude of the stress applied to the Hall element 111 varies due to changes in the temperature or humidity around the semiconductor package 100. When the stress applied to the Hall element 111 changes, the offset contained in the signal output from the Hall element 111 also changes.

[0087] Therefore, in this embodiment, in order to offset the change in offset, such as Figure 8 or Figure 9 As shown, a plurality of Hall elements 111 are configured to be point-symmetric about the center P of the semiconductor package 100 when viewed from above.

[0088] Hall elements 111S1 and 111S2 are configured to be point-symmetric about the center P. Hall elements 111S3 and 111S4 are configured to be point-symmetric about the center P.

[0089] When the semiconductor package 100 is divided into a first event region, a second event region, a third event region, and a fourth event region by a first axis L1 along a first direction (X-axis) and a second axis L2 along a second direction (Z-axis) passing through the center P in a top view, Hall elements 111S1 and 111S3 can be disposed in the first event region. Hall elements 111S2 and 111S4 can be disposed in the third event region, which is point-symmetric to the first event region about the center P. Alternatively, Hall elements 111S1 and 111S3 can be disposed in the second event region. Hall elements 111S2 and 111S4 can be disposed in the fourth event region, which is point-symmetric to the second event region about the center P.

[0090] exist Figure 8 In the first column, Hall elements 111S1 and 111S3 are arranged side-by-side in a first column along a first direction. Hall elements 111S2 and 111S4 are arranged side-by-side in a second column along the first direction, the second column being positioned on the opposite side of the first column, with the center P sandwiched between them. Hall elements 111S1 and 111S3 do not overlap with Hall elements 111S2 and 111S4 in a second direction.

[0091] exist Figure 9In this configuration, Hall elements 111S1 and 111S3 are arranged side-by-side in a first column along a first direction. Hall elements 111S2 and 111S4 are arranged side-by-side in a second column along the first direction, positioned on the opposite side of the first column such that the center P is sandwiched between them. Hall element 111S1 does not overlap with Hall elements 111S2 and 111S4 in a second direction. Hall element 111S2 does not overlap with Hall elements 111S1 and 111S3 in a second direction. On the other hand, Hall element 111S3 overlaps with Hall element 111S4 in a second direction. That is, Hall elements 111S3 and 111S4 are arranged side-by-side along the second direction.

[0092] Here, with the output of Hall element 111S1 set to S1, the output of Hall element 111S2 set to S2, the output of Hall element 111S3 set to S3, and the output of Hall element 111S4 set to S4, the magnetic sensor 112 outputs a signal indicating the magnitude of the magnetic field as the result of the sum / difference operation of S1, S2, S3, and S4, or the sum operation of S1, S2, S3, and S4. That is, the magnetic sensor 112 outputs a signal indicating the magnitude of the magnetic field as (S1+S2+S3+S4) / ((S1+S3)-(S2+S4)) or (S1+S2+S3+S4). By arranging the pairs of Hall elements 111 in a point-symmetric manner about the center P, the outputs of the pairs of Hall elements 111 are summed, thereby canceling out the noise, i.e., the offset, contained in the outputs of the individual Hall elements 111.

[0093] The PID control unit 115 can output a drive signal for controlling the coil 200, which functions as a drive unit that changes the position or orientation of the magnet 32 ​​relative to the semiconductor package 100, based on the sum of the outputs (S1+S2+S3+S4) representing the magnitude of the magnetic field from Hall elements 111S1, 111S2, 111S3, and 111S4. The amplifier 113 can amplify the sum of the outputs (S1+S2+S3+S4) and provide it to the PID control unit 115 via the A / D converter 114.

[0094] The PID control unit 115 can also output a drive signal based on the difference ((S1+S3)-(S2+S4)) between the sum of the outputs representing the magnitude of the magnetic field from Hall elements 111S1 and 111S3 and the sum of the outputs representing the magnitude of the magnetic field from Hall elements 111S2 and 111S4.

[0095] The PID control unit 115 can output a drive signal based on the ratio (S1+S2+S3+S4) of the sum (S1+S2+S3+S4) and difference ((S1+S3)-(S2+S4)) of the outputs representing the magnitude of the magnetic field from Hall elements 111S1, 111S2, 111S3, and 111S4, which is (S1+S2+S3+S4) / ((S1+S3)-(S2+S4)). The amplifier 113 can amplify the ratio (S1+S2+S3+S4) / ((S1+S3)-(S2+S4)) and provide the ratio of the sum and difference of the outputs to the PID control unit 115 via the A / D converter 114.

[0096] like Figure 10 As shown, the plurality of Hall elements 111 include Hall elements 111S1 and 111S3 belonging to a first group, and Hall elements 111S2 and 111S4 belonging to a second group. Hall element 111S1 may be at least partially covered by external terminal 102A1 of the plurality of external terminals 102A1, 102A2, and 102A3 when viewed from above. Hall element 111S2 may be at least partially covered by external terminal 102B1 of the plurality of external terminals 102B1, 102B2, and 102B3 when viewed from above. The area R1 of Hall element 111S1 covered by external terminal 102A1 when viewed from above and the area R2 of Hall element 111S2 covered by external terminal 102B1 when viewed from above are point-symmetric about the center P of the semiconductor package 100 when viewed from above. Hall elements 111S3 and 111S4 are configured to be point-symmetric about the center P of the semiconductor package 100 when viewed from above.

[0097] like Figure 11 As shown, Hall elements 111S1 and 111S3 can be completely covered by external terminal 102A1 when viewed from above. Hall elements 111S2 and 111S4 can be completely covered by external terminal 102B1 when viewed from above.

[0098] like Figure 12 As shown, Hall element 111S1 can be completely covered by external terminal 102A1 when viewed from above. Hall element 111S2 can be completely covered by external terminal 102B1 when viewed from above. On the other hand, Hall elements 111S3 and 111S4 can be completely covered by any of the external terminals of the plurality of external terminals 102 without any part of them being covered. That is, Hall elements 111S3 and 111S4 can be completely non-overlapping with any of the external terminals of the plurality of external terminals 102 when viewed from above.

[0099] like Figure 13As shown, Hall element 111S1 may be partially covered by external terminal 102A1 when viewed from above. Hall element 111S2 may be partially covered by external terminal 102B1 when viewed from above. On the other hand, Hall elements 111S3 and 111S4 may not be partially covered by any of the multiple external terminals 102. That is, Hall elements 111S3 and 111S4 may not overlap with any of the multiple external terminals 102 when viewed from above.

[0100] like Figure 14 As shown, Hall element 111S3 can be completely covered by external terminal 102A1 when viewed from above. Hall element 111S4 can be completely covered by external terminal 102B1 when viewed from above. Hall element 111S1 can be partially covered by external terminal 102A1 when viewed from above. Hall element 111S2 can be partially covered by external terminal 102B1 when viewed from above.

[0101] Here, the Hall element 111 can be as Figure 15 The equivalent circuit shown is obtained by connecting four resistors R1, R2, R3, and R4, each with a resistance of R, in a bridge configuration. The Hall element 111 has a pair of electrodes D1 and D2 facing each other in a first direction, and a pair of electrodes D3 and D4 facing each other in a second direction.

[0102] The four resistors R1, R2, R3, and R4 have the same resistance value R. However, when different stresses are applied to each of the four resistors R1, R2, R3, and R4, the resistance values ​​of the four resistors R1, R2, R3, and R4 will deviate. As a result, the offset contained in the signal output from the Hall element 111 changes.

[0103] To reduce such offset variations, consider switching the pair of electrodes outputting from Hall element 111 and summing the two outputs. Specifically, consider outputting a signal Sa corresponding to the magnitude of the magnetic field from the pair of electrodes D1 and D2 of Hall element 111 at a first timing interval, and then outputting a signal Sb corresponding to the magnitude of the magnetic field from the pair of electrodes D3 and D4 of Hall element 111 at a second timing interval following the first timing interval. The offset is reduced by summing the signals Sa and Sb. However, switching the output electrodes takes time, resulting in a response delay. For example, if such a response delay occurs when moving lens unit 40 for focusing or image shake correction, focusing delay or inability to perform high-precision image shake correction may result.

[0104] Therefore, the electrodes of the outputs of each Hall element 111, which is configured as a point-symmetric Hall element, are set as a pair of electrodes in different directions. By adding the outputs of these Hall elements 111, the offset can be reduced in the same way as the electrode switching. Furthermore, no response delay due to electrode switching occurs. By reducing the offset in this way, not only can the response delay be suppressed, but also the calculation of the outputs of each Hall element 111 can be performed without sacrificing the AD range because the magnetic sensor 112 sequentially calculates S1+S2 and S1+S3 in a time-division manner.

[0105] More specifically, in Figure 14 In the illustrated structures, Hall elements 111S1, 111S2, 111S3, and 111S4 have a pair of electrodes D1 and D2 facing each other in a first direction, and a pair of electrodes D3 and D4 facing each other in a second direction intersecting the first direction. In Hall elements 111S1 and 111S4, the pair of electrodes D1 and D2 are output electrodes. On the other hand, in Hall elements 111S2 and 111S3, the pair of electrodes D3 and D4 are output electrodes.

[0106] exist Figure 14 In the structure shown, only a portion of the Hall element 111S1 is covered by the external terminal 102A1 when viewed from above. As a result, the stress applied to the Hall element 111S1 deviates. Figure 16A The equivalent circuit of Hall element 111S1 is shown. For example... Figure 16A As shown, in the Hall element 111S1, among the four bridged resistors R1, R2, R3, and R4, the resistance value of resistor R1 is R+r, and the resistance values ​​of the other three resistors R2, R3, and R4 are R. That is, there is a difference between the resistance value of resistor R1 and the resistance values ​​of resistors R2, R3, and R4.

[0107] Figure 16BThe equivalent circuit of Hall element 111S2 is shown. Like Hall element 111S1, only a portion of Hall element 111S2 is covered by external terminal 102B1 when viewed from above. As a result, the stress applied to Hall element 111S2 deviates. However, the location of the area of ​​Hall element 111S2 covered by external terminal 102B1 when viewed from above differs from the location of the area of ​​Hall element 111S1 covered by external terminal 102A1 when viewed from above. The area of ​​Hall element 111S2 covered by external terminal 102B1 when viewed from above is point-symmetric to the area of ​​Hall element 111S1 covered by external terminal 102A1 when viewed from above, about the center P. Therefore, in Hall element 111S2, the resistance of resistor R3 out of the four bridged resistors R1, R2, R3, and R4 is R+r, and the resistance of the other three resistors R1, R2, and R4 is R. That is, there is a difference between the resistance value of resistor R3 and the resistance values ​​of resistors R1, R2 and R4.

[0108] Figure 16C The equivalent circuit of Hall element 111S3 is shown. Figure 16D The equivalent circuit of Hall element 111S4 is shown. Hall element 111S3 is completely covered by external terminal 102A1 when viewed from above, and Hall element 111S4 is completely covered by external terminal 102B1 when viewed from above. As a result, the stress applied to Hall elements 111S3 and 111S4 will not deviate. Therefore, the resistance values ​​of the four resistors R1, R2, R3, and R4, which are bridged in Hall elements 111S3 and 111S4, are the same.

[0109] exist Figure 16A In the equivalent circuit of the Hall element 111S1 shown, the offset voltage V, which corresponds to the offset amount, offset_1 As specified by formula (1).

[0110] V offset_1 =V 1_1 -V 2_1 =((R+r) / (2R+r)-1 / 2)×V in

[0111] =r / (2×(2R+r)) …(1)

[0112] exist Figure 16B In the equivalent circuit of the Hall element 111S2 shown, the offset voltage V, which corresponds to the offset amount, offset_2 As specified in formula (2).

[0113] V offset_2 =V 1_2 -V 2_2 =((R / (2R+r))-1 / 2)×V in

[0114] =-r / (2×(2R+r)) …(2)

[0115] exist Figure 16C In the equivalent circuit of the Hall element 111S3 shown, the offset voltage V, which corresponds to the offset amount, offset_3 As specified in formula (3).

[0116] V offset_3 =V 1_3 -V 2_3 =0 …(3)

[0117] exist Figure 16D In the equivalent circuit of the Hall element 111S4 shown, the offset voltage V, which corresponds to the offset amount, offset_4 As specified by formula (4).

[0118] V offset_4 =V 1_4 -V 2_4 =0 …(4)

[0119] When the outputs of Hall elements 111S1, 111S2, 111S3, and 111S4 are all added together according to the above formula, the offset voltage V output from the magnetic sensor 112, which is equivalent to the offset amount, is obtained. offset According to Equation (5), the offsets generated in Hall element 111S1 and Hall element 111S2 are canceled out and become zero.

[0120] V offset =V offset_1 +V offset_2 +V offset_3 +V offset_4

[0121] =r / (2×(2R+r))-r / (2×(2R+r))=0…(5)

[0122] Figure 17 The functions of each external terminal 102 of the semiconductor package 100 are shown. External terminals 102A1 and 102A3, located in the second event region when viewed from above, are a pair of power supply terminals. External terminals 102B2 in the third event region and 102B1 in the fourth event region are a pair of drive terminals for outputting drive signals to the coil 200. External terminals 102A2 in the first event region and 102B3 in the fourth event region are a pair of communication terminals for communicating with the control unit of the camera module 10.

[0123] Hall element 111S1 may overlap at least partially with external terminal 102A1, which is one of a pair of power supply terminals, when viewed from above. Hall element 111S2 may overlap at least partially with external terminal 102B1, which is one of a pair of drive terminals, when viewed from above. Similarly, Hall element 111 may overlap with external terminals other than the pair of communication terminals when viewed from above. However, it is preferable that Hall element 111 does not overlap with the pair of communication terminals when viewed from above. If Hall element 111 overlaps with either of the pair of communication terminals when viewed from above, both Hall element 111 and the pair of communication terminals are affected by noise, increasing the adverse effects.

[0124] The external terminals 102A1 and 102B1, which at least partially overlap with the Hall element 111 when viewed from above, are preferably the external terminals among the plurality of external terminals 102 that are located closest to the center P of the semiconductor package 100 when viewed from above.

[0125] The external terminals 102A1 and 102B1, which at least partially overlap with the Hall element 111 when viewed from above, only need to be point-symmetric about the center P of the semiconductor package 100 when viewed from above. The shape of the external terminals 102A1 and 102B1 when viewed from above does not have to be circular.

[0126] Figure 18 The diagram illustrates the wiring configuration of the semiconductor package 100 within the redistribution layer 120. By arranging a plurality of external terminals 102 in a zigzag pattern along a first direction, space exists in the regions where each external terminal 102 leads in both the first and second directions. Consequently, wiring used for electrical connection to the semiconductor chip can extend relatively long from the external terminals 102 in both the first and second directions. For example, the redistribution layer 120 may include wiring LB1 extending more than 100 μm along the first direction from the external terminal 102B1 and electrically connecting to the semiconductor chip. That is, the portion kb1 of wiring LB1 extending along the first direction can be more than 100 μm. Similarly, the redistribution layer 120 may include wiring LB3 extending more than 100 μm along the first direction from the external terminal 102B3 and electrically connecting to the semiconductor chip. That is, the portion kb3 of wiring LB3 extending along the first direction can be more than 100 μm. By wiring along the first or second direction in this way, wiring can be achieved with the shortest path, thus reducing the area of ​​the semiconductor package 100 in top view.

[0127] Additionally, wiring LB1 includes a portion kb1 extending along a first direction through the center of external terminal 102B1. Wiring LB3 includes a portion kb3 extending along a first direction through the center of external terminal 102B3.

[0128] The redistribution layer 120 may include wiring LB2 extending more than 100 μm from the external terminal 102B2 along a second direction and electrically connected to the semiconductor chip. Wiring LB2 may include a portion kb2 extending along the second direction through the center of the external terminal 102B2.

[0129] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. Those skilled in the art will appreciate that various modifications or improvements can be made to the above embodiments. As can be appreciated from the claims, the manner obtained by applying such modifications or improvements can also be included within the technical scope of the present invention.

[0130] It should be noted that the execution order of actions, processes, steps, and stages in the apparatus, system, program, and method shown in the claims, specification, and drawings can be implemented in any order, unless specifically indicated as "before," "before," etc., and the output of a preceding process is not used in a subsequent process. The flow of actions in the claims, specification, and drawings is described using terms such as "firstly," "next," etc., for convenience, but this does not imply that they must be implemented in this order.

[0131] Explanation of reference numerals in the attached figures

[0132] 10: Camera module; 20: Base; 30: Holding frame; 32: Magnet; 40: Lens unit; 100: Semiconductor package; 102: External terminal; 110: Silicon substrate; 111: Hall element; 112: Magnetic sensor; 113: Amplifier; 114: A / D converter; 115: PID control unit; 116: D / A converter; 117: Output driver; 120: Rewiring layer; 130: Seal; 200: Coil; 210: Position command generation unit; 300: Substrate; 302: Imaging element.

Claims

1. A semiconductor package comprising a semiconductor chip and a plurality of external terminals disposed on a first surface of the semiconductor chip, the semiconductor chip having at least a first Hall element and a second Hall element, the semiconductor package having a rectangular shape in top view with a first direction as its long side and a second direction orthogonal to the first direction as its short side, characterized in that... The first Hall element is configured to be point-symmetric with respect to the second Hall element about the center of the first surface of the semiconductor package when viewed from above. The plurality of external terminals include a plurality of first external terminals configured to form a column along the first direction, and a plurality of second external terminals configured to form a column along the first direction. When viewed from above, the first terminal array formed by the plurality of first external terminals and the second terminal array formed by the plurality of second external terminals are located at different positions in the second direction, and the plurality of first external terminals and the plurality of second external terminals are staggered on the first surface. When viewed from above, the first Hall element is positioned inside the column of the first terminal column formed by the plurality of first external terminals, relative to both ends, and the second Hall element is positioned inside the column of the second terminal column formed by the plurality of second external terminals, relative to both ends.

2. The semiconductor package according to claim 1, characterized in that, The plurality of first external terminals or the plurality of second external terminals include a pair of communication terminals facing the exterior of the semiconductor package. When viewed from above, the first Hall element and the second Hall element are configured not to overlap with the pair of communication terminals.

3. The semiconductor package according to claim 2, characterized in that, The semiconductor chip has multiple Hall elements, including the first Hall element and the second Hall element. The plurality of Hall elements includes the first Hall element and the third Hall element belonging to the first group, and the second Hall element and the fourth Hall element belonging to the second group. The third Hall element and the fourth Hall element are configured to be point-symmetric about the center of the semiconductor package when viewed from above.

4. The semiconductor package according to claim 3, characterized in that, When viewed from above, the third Hall element and the fourth Hall element are configured not to overlap with the pair of communication terminals.

5. The semiconductor package according to claim 4, characterized in that, When viewed from above, the first Hall element and the third Hall element belonging to the first group are arranged along the first terminal column, and the second Hall element and the fourth Hall element belonging to the second group are arranged along the second terminal column.

6. The semiconductor package according to claim 5, characterized in that, The width of the semiconductor package in the first direction is longer than the width of the semiconductor package in the second direction intersecting the first direction.

7. The semiconductor package according to claim 6, characterized in that, The width in the first direction is at least 1.65 times the width in the second direction.

8. The semiconductor package according to claim 6, characterized in that, The width in the first direction is more than 2.5 times the length of the width in the second direction.

9. The semiconductor package according to claim 7 or 8, characterized in that, The total area of ​​the plurality of external terminals when viewed from above is more than 14% of the total area of ​​the semiconductor package when viewed from above.

10. The semiconductor package according to claim 7 or 8, characterized in that, The total area of ​​the plurality of external terminals when viewed from above is more than 19% of the total area of ​​the semiconductor package when viewed from above.

11. The semiconductor package according to claim 5, characterized in that, The external terminals belonging to the first terminal column and the external terminals belonging to the second terminal column, which are located closest to the center of the semiconductor package when viewed from above, are point-symmetrical with respect to the center of the semiconductor package when viewed from above.

12. The semiconductor package according to any one of claims 1 to 5, characterized in that, The semiconductor package further includes a redistribution layer, which is stacked on the first side of the semiconductor chip and electrically connected to the semiconductor chip. At least one of the plurality of external terminals is electrically connected to the first Hall element and the second Hall element via the redistribution layer.

13. The semiconductor package according to claim 12, characterized in that, The redistribution layer includes wiring extending more than 100 μm from at least one of the plurality of external terminals along the first direction and electrically connected to the semiconductor chip.

14. The semiconductor package according to claim 13, characterized in that, The wiring has a portion extending along the first direction from the center of the at least one external terminal when viewed from above.

15. The semiconductor package according to claim 12, characterized in that, The redistribution layer includes wiring extending more than 100 μm from at least one of the plurality of external terminals along a second direction intersecting the first direction and electrically connected to the semiconductor chip.

16. The semiconductor package according to claim 1 or 2, characterized in that, The width of the first terminal column in the first direction includes the total width of each of the first external terminals disposed at both ends in the first terminal column in the first direction. The width of the second terminal column in the first direction is the width including the full width of each of the second external terminals disposed at both ends in the first direction. When viewed from above, the first Hall element is disposed within the width of the first terminal column in the first direction, and the second Hall element is disposed within the width of the second terminal column in the first direction.

17. The semiconductor package according to claim 16, characterized in that, The center of gravity of each of the plurality of first external terminals and the center of gravity of each of the plurality of second external terminals do not overlap in the first direction and the second direction.

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