Semiconductor device and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductors, and is used for improving the heat dissipation capability of the semiconductor device. The semiconductor device includes at least one semiconductor structure. The semiconductor structure comprises a heat dissipation layer and at least one heat dissipation column. The heat dissipation column is embedded in the semiconductor structure and extends along the thickness direction of the semiconductor structure. The heat dissipation layer is located on one side of the heat dissipation column and located on the first surface of the semiconductor structure, and the first surface is a surface on one side in the thickness direction of the semiconductor structure. And the heat dissipation layer is connected with the heat dissipation column. The semiconductor structure is used for realizing data reading and writing operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, a storage system, and an electronic device. Background Technology

[0002] In related technologies, with the rapid development of artificial intelligence, new requirements have been put forward for semiconductor devices, requiring high bandwidth, low power consumption and high capacity semiconductor devices.

[0003] Semiconductor devices are relatively thick, making it difficult for the heat generated during operation to dissipate. This heat accumulation can easily affect the performance of semiconductor devices. Summary of the Invention

[0004] On one hand, a semiconductor device is provided, comprising: at least one semiconductor structure. The semiconductor structure includes a heat dissipation layer and at least one heat dissipation pillar. The heat dissipation pillar is embedded within the semiconductor structure and extends along the thickness direction of the semiconductor structure. The heat dissipation layer is located on one side of the heat dissipation pillar and on a first surface of the semiconductor structure, the first surface being a side surface along its thickness direction. The heat dissipation layer is connected to the heat dissipation pillar.

[0005] In some embodiments, the heat dissipation layer includes a plurality of first heat dissipation strips; each of the first heat dissipation strips is connected to at least one of the heat dissipation columns.

[0006] In some embodiments, the heat dissipation layer further includes a plurality of second heat dissipation strips; each of the second heat dissipation strips and at least one of the first heat dissipation strips intersects and is connected.

[0007] In some embodiments, the material of the heat dissipation layer includes a metallic material.

[0008] In some embodiments, the semiconductor device includes a plurality of semiconductor structures. The plurality of semiconductor structures are stacked along the thickness direction of the semiconductor structures, and adjacent semiconductor structures are bonded to each other.

[0009] In some embodiments, the plurality of semiconductor structures include a first semiconductor structure and a second semiconductor structure. Two adjacent semiconductor structures are the first semiconductor structure and the second semiconductor structure. A first surface of the first semiconductor structure is bonded to a second surface of the second semiconductor structure. The second surface of the second semiconductor structure is the surface opposite to the first surface of the second semiconductor structure.

[0010] In some embodiments, the semiconductor structure includes a first semiconductor structure and a second semiconductor structure. The two adjacent semiconductor structures are the first semiconductor structure and the second semiconductor structure. A first surface of the first semiconductor structure is bonded to a first surface of the second semiconductor structure.

[0011] In some embodiments, the semiconductor structure has a connection region and a functional region located at least one side of the connection region. The heat dissipation pillar is located in the connection region. The semiconductor structure includes a plurality of conductive pillars embedded in the semiconductor structure. The conductive pillars are located in the connection region and extend along the thickness direction of the semiconductor structure. The conductive pillars located in the adjacent two semiconductor structures are bonded to each other.

[0012] In some embodiments, at least part of the plurality of heat dissipation pillars is located between the plurality of conductive pillars and the functional region.

[0013] In some embodiments, the heat dissipation layer includes a plurality of first heat dissipation strips and a plurality of second heat dissipation strips. The first heat dissipation strips extend from the functional region to the connection region and are connected to the heat dissipation pillars. The second heat dissipation strips are located in the functional region.

[0014] In some embodiments, the semiconductor structure further includes a first bonding pattern located on a first surface of the semiconductor structure and connected to the conductive pillars. The first bonding pattern of the semiconductor structure is arranged in the same layer as the heat dissipation layer.

[0015] In some embodiments, the semiconductor structure includes a peripheral device layer and a memory array layer stacked in sequence along the thickness direction of the semiconductor structure. The heat dissipation pillar includes a first sub-pillar and a second sub-pillar connected to each other. The first sub-pillar penetrates the memory array layer, and the second sub-pillar penetrates the peripheral device layer.

[0016] In some embodiments, the semiconductor structure further includes a connection pattern located on a first surface of the semiconductor structure and located in the connection region. The connection pattern is connected to the second sub-pillar. The connection pattern is arranged in the same layer as the heat dissipation layer and is connected to each other.

[0017] In some embodiments, the conductive pillar includes a third sub-pillar and a fourth sub-pillar connected to each other. The third sub-pillar penetrates the memory array layer, and the fourth sub-pillar penetrates the peripheral device layer. The third sub-pillar is arranged in the same layer as the first sub-pillar, and the fourth sub-pillar is arranged in the same layer as the second sub-pillar.

[0018] In some embodiments, the semiconductor structure further comprises a peripheral device layer and a memory array layer stacked in sequence along a thickness direction of the semiconductor structure, and a plurality of shielding walls penetrating through the peripheral device layer and the memory array layer. Each of the shielding walls surrounds the functional region and the connection region.

[0019] In some embodiments, a shielding wall closest to the functional region and the connection region among the plurality of shielding walls is a first shielding wall. The heat dissipation layer is connected with the first shielding wall.

[0020] In some embodiments, the semiconductor structure further comprises a second bonding pattern on a first surface of the semiconductor structure. The second bonding pattern is connected with the shielding wall. The second bonding pattern is disposed in the same layer as the heat dissipation layer and is connected with the heat dissipation layer.

[0021] In some embodiments, the shielding wall comprises a first sub-wall and a second sub-wall connected with each other. The first sub-wall penetrates through the memory array layer, and the second sub-wall penetrates through the peripheral device layer. The heat dissipation column comprises a first sub-column and a second sub-column connected with each other. The first sub-column penetrates through the memory array layer, and the second sub-column penetrates through the peripheral device layer. The first sub-wall is disposed in the same layer as the first sub-column, and the second sub-wall is disposed in the same layer as the second sub-column.

[0022] In another aspect, a method for manufacturing a semiconductor device is provided. The method comprises forming at least one semiconductor structure. The semiconductor structure is embedded with at least one heat dissipation column extending along a thickness direction of the semiconductor structure. A heat dissipation layer is formed on a first surface of the semiconductor structure. The first surface is a side surface along the thickness direction thereof, and the heat dissipation layer is located on one side of the heat dissipation column and is connected with the heat dissipation column.

[0023] In some embodiments, the semiconductor structure comprises a dielectric layer on the first surface. Forming the heat dissipation layer on the first surface of the semiconductor structure comprises forming a plurality of first grooves and a plurality of second grooves on the dielectric layer. The second grooves cross and communicate with at least one of the first grooves. A first heat dissipation strip is formed in the first grooves, and a second heat dissipation strip is formed in the second grooves. Each of the second heat dissipation strips crosses and is connected with at least one of the first heat dissipation strips, and each of the first heat dissipation strips is connected with at least one of the heat dissipation columns.

[0024] In some embodiments, the semiconductor device comprises a plurality of semiconductor structures. The method further comprises sequentially bonding the plurality of semiconductor structures along a thickness direction of the semiconductor structures.

[0025] In some embodiments, the semiconductor structure includes: a memory array device layer, a peripheral device layer, a first substrate, and a conductive pillar penetrating through the memory array layer and the peripheral device layer and extending into the first substrate. The heat dissipation pillar penetrates through the memory array layer, the peripheral device layer, and extends into the first substrate. Before forming the heat dissipation layer on the first surface of the semiconductor structure, the preparation method further includes: removing a portion of the first substrate to expose the conductive pillar and the heat dissipation pillar. During the process of forming the heat dissipation layer on the first surface of the semiconductor structure, a first bonding pattern and a connection pattern are simultaneously formed on the first surface of the semiconductor structure, the first bonding pattern is connected with the conductive pillar located in the semiconductor structure, and the connection pattern is connected with the heat dissipation pillar located in the semiconductor structure. Before sequentially bonding a plurality of semiconductor structures along the thickness direction of the semiconductor structure, the preparation method further includes: forming a third bonding pattern on the second surface of the semiconductor structure to be bonded. The third bonding pattern is connected with the conductive pillar.

[0026] In some embodiments, the memory array device layer includes at least one memory array device, and the peripheral device layer includes at least one peripheral device. A plurality of shielding walls are simultaneously formed during the process of forming the plurality of heat dissipation pillars. The plurality of shielding walls penetrate through the peripheral device layer and the memory array layer. The shielding walls surround the at least one memory array device and the at least one peripheral device.

[0027] In some embodiments, a fourth bonding pattern is simultaneously formed during the process of forming the third bonding pattern on the second surface of the semiconductor structure to be bonded. The fourth bonding pattern is connected with one end of the shielding wall.

[0028] A second bonding pattern is simultaneously formed on the first surface of the semiconductor structure during the process of forming the heat dissipation layer on the first surface of the semiconductor structure. The second bonding pattern is connected with the other end of the shielding wall.

[0029] In another aspect, a storage system is provided, including: a controller, and a semiconductor device as described in any of the above embodiments. The controller is coupled to the semiconductor device and configured to control the semiconductor device to store data.

[0030] In another aspect, an electronic device is provided, including the storage system as described in any of the above embodiments, and a circuit board electrically connected to the storage system. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are only some of the drawings of the present disclosure, and other drawings can also be obtained by those of ordinary skill in the art based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, etc. of the product involved in the embodiments of the present disclosure.

[0032] Figure 1 Structure diagram of an electronic device according to some embodiments of the present disclosure;

[0033] Figure 2A Structure diagram of a storage system according to some embodiments of the present disclosure;

[0034] Figure 2B Structure diagram of another storage system according to some embodiments of the present disclosure;

[0035] Figure 3 Structure diagram of a semiconductor device according to some embodiments of the present disclosure;

[0036] Figure 4 Structure diagram of another semiconductor device according to some embodiments of the present disclosure;

[0037] Figure 5A Structure diagram of still another semiconductor device according to some embodiments of the present disclosure;

[0038] Figure 5B Structure diagram of still another semiconductor device according to some embodiments of the present disclosure;

[0039] Figure 6 Flow chart of a preparation method of a semiconductor device according to some embodiments of the present disclosure;

[0040] Figures 7-15 Structure diagram corresponding to each step of a preparation method of a semiconductor device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] The technical solutions in some embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided in the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0042] In the description of the present disclosure, it needs to be understood that the terms "center", "upper", "lower", "horizontal", "inner", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0043] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise", "comprising", and the like are to be construed in an open, inclusive sense, as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplary", or "some examples" are intended to mean that a particular feature, structure, material, or characteristic included in the embodiment or example is included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any appropriate manner in any one or more embodiments or examples.

[0044] Hereinafter, the terms "first", "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0045] In describing some embodiments, "connected" and / or "coupled" and / or "engaged" and / or variants thereof can be used. For example, the term "connected" can be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.

[0046] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized exemplary illustrations. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

[0047] As Figure 1As shown, some embodiments of this disclosure provide an electronic device 3000, which may include any device capable of storing data, such as a mobile phone, desktop computer, tablet computer, laptop computer, or server. The electronic device 3000 may include a storage system 1000 configured to implement data storage, as described below, and a circuit board 2000 electrically connected to the storage system. The circuit board 2000 is used to provide electrical signals, etc., to the storage system 1000.

[0048] like Figure 2A and Figure 2B As shown, some embodiments of this disclosure provide a storage system 1000. The storage system 1000 is used in the aforementioned electronic device 3000. The storage system 1000 includes a semiconductor device 100 and a controller 200. The controller 200 is coupled to the semiconductor device 100 and is used to control the semiconductor device 100 to store data.

[0049] The storage system 1000 can be integrated into various types of storage devices, for example, within the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other electronic device with memory.

[0050] In some examples, the storage system 1000 includes a controller 200 and a semiconductor device 100; wherein, the storage system 1000 may, for example, be integrated into a memory card. The memory card may include one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0051] In other examples, such as Figure 2A As shown, the storage system 1000 includes a controller 200 and multiple semiconductor devices 100.

[0052] Exemplarily, the storage system 1000 includes the controller 200 and four semiconductor devices 100. Among others, the storage system 1000 can be integrated into a solid state drive (SSD) for example.

[0053] In some examples, in the storage system 1000, the controller 200 is configured for operation in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0054] In other examples, in the storage system 1000, the controller 200 is configured for operation in a high duty cycle environment, such as an SSD or eMMC used for data storage in mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0055] In some examples, the controller 200 can be configured to manage data stored in the semiconductor devices 100 and communicate with an external device (e.g., a host).

[0056] In some examples, the controller 200 can also be configured to control operations of the semiconductor devices 100, such as read, erase, and program operations.

[0057] In some examples, the controller 200 can also be configured to control the semiconductor devices 100 to store data.

[0058] In some examples, the controller 200 can also be configured to manage various functions related to data stored or to be stored in the semiconductor devices 100, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling.

[0059] In some examples, the controller 200 is also configured to process error correction codes related to data read from or written to the semiconductor devices 100.

[0060] It is readily understood that the controller 200 can also perform any other suitable functions, such as formatting the semiconductor devices 100. For example, the controller 200 can communicate with an external device (e.g., a host) through at least one of various interface protocols.

[0061] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0062] The controller 200 may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0063] In some examples, semiconductor device 100 may be high-bandwidth memory (HBM).

[0064] like Figure 3 and Figure 4 As shown, the semiconductor device 100 includes at least one semiconductor structure 10.

[0065] For example, semiconductor device 100 includes one or more semiconductor structures 10.

[0066] For example, the semiconductor structure 10 includes a memory array layer 50 and a peripheral device layer 40 stacked along the thickness direction of the semiconductor structure 10. The peripheral device layer 40 is used to input signals for writing and storing control data to the memory array layer 50. During the process of the semiconductor device 100 performing the storage function, heat is generated.

[0067] The semiconductor structure 10 further includes a heat dissipation layer 30 and at least one heat dissipation pillar 20. For example, the semiconductor structure 10 includes one or more heat dissipation pillars 20.

[0068] The heat sink 20 is embedded inside the semiconductor structure 10 and extends along the thickness direction of the semiconductor structure 10. For example, the heat sink 20 penetrates the memory array layer 50 and the peripheral device layer 40.

[0069] The heat dissipation column 20 is used for heat dissipation, and the heat dissipation column 20 has strong heat dissipation capacity. Therefore, the heat dissipation column 20 can be used as a heat diffusion channel in the thickness direction of the semiconductor structure 10 or the semiconductor device 100, so that the heat inside the semiconductor device 100 is diffused to the surface of the semiconductor structure 10 or outside the semiconductor device 100 through the heat dissipation column 20, thereby improving the heat dissipation capacity of the semiconductor device 100 and avoiding heat accumulation inside the semiconductor device 100 to cause adverse effects on the performance of the semiconductor device 100.

[0070] For example, the heat dissipation layer 30 is arranged on the first surface 10C of the semiconductor structure 10, and the first surface 10C is a side surface in the thickness direction of the semiconductor structure 10. The heat dissipation layer 30 is connected with the heat dissipation column 20.

[0071] The heat dissipation layer 30 is used for heat dissipation. The arrangement of the heat dissipation layer 30 allows the heat inside the semiconductor device 100 to diffuse along the heat dissipation layer 30 on the first surface 10C of the semiconductor structure 10, thereby improving the heat dissipation capacity of the semiconductor device 100. In addition, since the heat dissipation column 20 is a heat diffusion channel in the thickness direction of the semiconductor device 100, and the connected heat dissipation column 20 and heat dissipation layer 30 form a three-dimensional heat diffusion channel inside the semiconductor device 100, thereby accelerating the diffusion of heat, and further improving the heat dissipation capacity of the semiconductor device 100.

[0072] In an implementation, the thickness of the plurality of semiconductor structures in the semiconductor device is large, about 60 μm or so, and the bonding material between the adjacent semiconductor structures is heat-conducting glue, which has poor heat dissipation effect. Therefore, the heat generated by the semiconductor device in the working state cannot be effectively diffused in time, thereby affecting the performance of the semiconductor device.

[0073] In the example of the present disclosure, as shown in Figure 4 The semiconductor device 100 includes a plurality of semiconductor structures 10, and the first surface 10C of the semiconductor structure 10 is provided with a heat dissipation layer 30. The adjacent semiconductor structures 10 are bonded and heat-dissipated by using the heat dissipation layer 30, thereby reducing the adverse effects of heat accumulation on the performance of the semiconductor device 100.

[0074] The semiconductor device 100 provided by the embodiments of the present disclosure is provided with at least one heat dissipation column 20 embedded in the semiconductor structure 10, the heat dissipation column 20 extends along the thickness direction of the semiconductor structure 10, so that the heat generated in the semiconductor device 100 can be diffused out by using the heat dissipation column 20, and the heat dissipation capacity of the semiconductor device 100 is improved. The heat dissipation layer 30 is arranged on the first surface 10C of the semiconductor structure 10, so that the heat in the semiconductor device 100 can be diffused out along the first surface 10C by using the heat dissipation layer 30, and the heat dissipation layer 30 is connected with the heat dissipation column 20, thereby forming a three-dimensional heat diffusion channel in the semiconductor device 100, further improving the heat dissipation capacity of the semiconductor device 100, reducing the temperature and power consumption of the semiconductor device 100, and improving the performance of the semiconductor device 100.

[0075] It can be understood that the structure of the heat dissipation layer 30 can be various, and can be arranged according to actual needs, and the embodiments of the present disclosure do not limit this.

[0076] In some examples, as shown in Figure 5A The heat dissipation layer 30 includes a plurality of first heat dissipation strips 31. Each first heat dissipation strip 31 is connected with at least one heat dissipation column 20.

[0077] For example, the plurality of first heat dissipation strips 31 are arranged at intervals. The extension directions of the plurality of first heat dissipation strips 31 can be the same or different.

[0078] For example, as shown in Figure 5A Each first heat dissipation strip 31 is connected with one heat dissipation column 20.

[0079] For another example, each first heat dissipation strip 31 is connected with a plurality of heat dissipation columns 20.

[0080] Therefore, the heat in the semiconductor device 100 can be transmitted from the first heat dissipation strip 31 in the heat dissipation layer 30 to the heat dissipation column 20, diffused out of the semiconductor device 100 along the thickness direction of the semiconductor structure 10 by the heat dissipation column 20, or diffused onto the first heat dissipation strip 31 by the heat dissipation column 20, and diffused out of the semiconductor device 100 along the first surface 10C by the first heat dissipation strip 31, thereby improving the heat dissipation capacity of the semiconductor device 100.

[0081] For example, as shown in Figure 5B The heat dissipation layer 30 further includes a plurality of second heat dissipation strips 32. Each second heat dissipation strip 32 intersects and connects with at least one first heat dissipation strip 31. For example, one second heat dissipation strip 32 intersects and connects with one or more second heat dissipation strips 32.

[0082] For example, the plurality of second heat dissipation strips 32 are arranged at intervals. The extension directions of the plurality of second heat dissipation strips 32 can be the same or different.

[0083] For example, the first heat dissipation bars 31 and the second heat dissipation bars 32 extend in different directions.

[0084] For example, as shown in FIG. 1, each of the first heat dissipation bars 31 extends in a first direction X, and each of the second heat dissipation bars 32 extends in a second direction Y. The plurality of first heat dissipation bars 31 and the plurality of second heat dissipation bars 32 form a mesh structure, so that the area of the semiconductor structure 10 occupied by the heat dissipation layer 30 is large, and the heat dissipation area of the heat dissipation layer 30 is large, and thus the heat dissipation capacity of the semiconductor device 100 is strong. Figure 5B For example, the metal material can include metal copper or metal tungsten.

[0085] The metal material has strong heat conduction and heat dissipation capacity, so that the heat dissipation capacity of the heat dissipation layer 30 can be further improved.

[0086] In some examples, as shown in FIG. 2, the semiconductor device 100 includes a plurality of semiconductor structures 10. Along the thickness direction of the semiconductor structure 10, the plurality of semiconductor structures 10 are stacked and bonded to each other between adjacent two semiconductor structures 10.

[0087] Here, the bonding type between the adjacent two semiconductor structures 10 can be hybrid bonding. In the examples of the present disclosure, the hybrid bonding specifically refers to bonding the heat dissipation layer 30 on the first surface 10C of the semiconductor structure 10 to the surface of another semiconductor structure 10, and bonding the heat dissipation column 20 and the conductive column 60 to be mentioned below in the adjacent two semiconductor structures 10.

[0088] Figure 4 It can be understood that in the case where the semiconductor device 100 includes a plurality of semiconductor structures 10, the specific structures of the plurality of semiconductor structures 10 can be the same or different.

[0089] In some examples, as shown in FIG. 3, the semiconductor structure 10 has a connection region AA and a functional region BB located on at least one side of the connection region AA.

[0090] For example, the functional region BB is located on one side of the connection region AA. For another example, the functional region BB is located on opposite sides of the connection region AA, respectively.

[0091] For example, the functional region BB is used to realize the storage function of the semiconductor device 100, and the connection region AA is used to realize the interconnection between different semiconductor structures 10, etc. Figure 4

[0092] For example, the functional region BB is used to realize the storage function of the semiconductor device 100, and the connection region AA is used to realize the interconnection between different semiconductor structures 10, etc.

[0093] For example, the functional region BB is used to realize the storage function of the semiconductor device 100, and the connection region AA is used to realize the interconnection between different semiconductor structures 10, etc.

[0094] ​​The heat dissipation pillar 20 is located in the connection region AA. Thus, the arrangement design of the functional region BB is facilitated, and the heat dissipation pillar 20 is prevented from occupying the arrangement space of the functional region BB and affecting the arrangement of functional devices in the functional region BB, such as the storage array 51 or the peripheral device 41 mentioned below.

[0095] For example, the conductive pillar 60 extends along the thickness direction of the semiconductor structure 10, and the conductive pillar 60 penetrates the peripheral device layer 40 and the storage array layer 50.

[0096] The storage array layer 50 includes the storage array 51 located in the functional region BB, and the number of the storage array 51 can be multiple, for example.

[0097] The storage array 51 can include a plurality of storage units arranged in an array. Each storage unit can include a vertical transistor and a capacitor coupled to the vertical transistor. The storage unit can be a 1T1C (wherein “T” represents a transistor, the number before “T” represents the number of transistors, and “C” represents a capacitor, the number before “C” represents the number of capacitors) structure unit composed of one transistor and one capacitor. It should be understood that the storage unit can be any suitable configuration, such as a 2T1C structure unit, a 3T1C structure unit, etc.

[0098] The storage array 51 further includes word lines, bit lines, etc., for example, one end of the bit line is connected to the source or drain of the transistor in the storage unit, and the other end is connected to the peripheral device 41. One end of the word line is connected to the gate of the transistor in the storage unit, and the other end is connected to the peripheral device 41.

[0099] The peripheral device 41 can include any active (or passive) components (e.g., transistors, diodes, resistors, capacitors, etc.) such as page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), or circuits.

[0100] For example, the peripheral device 41 can include a plurality of transistors, all or a part of which are formed in and / or directly on a substrate. Similarly, shallow trench isolation and doped regions (e.g., source and drain regions of transistors) can also be formed in the substrate.

[0101] It should be noted that the peripheral device 41 can also include any other circuits compatible with advanced logic processes.

[0102] For example, peripheral device 41 may also include logic circuitry (e.g., processors and programmable logic devices (PLDs)) and / or storage circuitry (e.g., static random access memory (SRAM)).

[0103] In some examples, such as Figure 4 As shown, along the thickness direction of the semiconductor structure 10, a memory array 51 is at least partially opposite and connected to a peripheral device 41. Specifically, the word lines and bit lines in the memory array 51 are connected to the peripheral device 41.

[0104] For example, the conductive post 60 is located in the connection area AA. Thus, the conductive post 60 is located in a different area from the memory array 51 and the peripheral devices 41, so as to avoid the arrangement of the conductive post 60 affecting the layout of the memory array 51 and the peripheral devices 41.

[0105] The conductive post 60 is connected to the peripheral device 41.

[0106] Conductive pillars 60 located in two adjacent semiconductor structures 10 are bonded together. Thus, the conductive pillars 60 can achieve electrical connection between the two adjacent semiconductor structures 10.

[0107] For example, the plurality of conductive pillars 60 in the first semiconductor structure 11 correspond to and are connected to the plurality of conductive pillars 60 in the second semiconductor structure 12.

[0108] As can be seen from the above, both the conductive post 60 and the heat dissipation post 20 are located in the connection area AA. There are various possible relative positions between the conductive post 60 and the heat dissipation post 20, which can be set according to the actual situation. The embodiments disclosed herein do not limit this.

[0109] In some examples, such as Figure 5B As shown, at least a portion of the heat dissipation pillars 20 are located between the plurality of conductive pillars 60 and the functional area BB.

[0110] For example, some of the heat dissipation pillars 20 are located outside the area occupied by the multiple conductive pillars 60, surrounding the multiple conductive pillars 60.

[0111] For example, such as Figure 5B As shown, multiple heat dissipation pillars 20 are located on the outer side of multiple conductive pillars 60. This facilitates the connection between the heat dissipation pillars 20 and the first heat dissipation strip 31 in the heat dissipation layer 30, avoiding the need for the connection between the heat dissipation pillars 20 and the first heat dissipation strip 31 to bypass the conductive pillars 60, which would cause a short circuit between the first heat dissipation strip 31 and the conductive pillars 60 and thus avoid affecting the performance of the semiconductor device 100.

[0112] In some examples, such asFigure 5B As shown, in the heat dissipation layer 30, the first heat dissipation strip 31 extends from the functional area BB to the connection area AA and connects with the heat dissipation column 20. The second heat dissipation strip 32 is located in the functional area BB.

[0113] Therefore, the heat generated in the functional area BB can be transferred to the connection area AA by the first heat sink 31 and the second heat sink 32, and then diffused to the outside of the semiconductor device 100 through the heat sink column 20 of the connection area AA, thereby realizing the heat dissipation of the semiconductor device 100.

[0114] In some examples, such as Figure 4 As shown, the above-mentioned multiple semiconductor structures 10 include a first semiconductor structure 11 and a second semiconductor structure 12.

[0115] The two adjacent semiconductor structures 10 are the first semiconductor structure 11 and the second semiconductor structure 12.

[0116] The first surface 10C of the first semiconductor structure 11 is bonded to the second surface 10D of the second semiconductor structure 12. The second surface 10D of the second semiconductor structure 12 is the surface opposite to the first surface 10C in the second semiconductor structure 12.

[0117] Therefore, the heat generated by the first semiconductor structure 11 and the second semiconductor structure 12 can be diffused away through the heat dissipation layer 30 of the first semiconductor structure 11 bonded to the second semiconductor structure 12, or through the heat dissipation layer 30 of the second semiconductor structure 12, thereby improving the heat dissipation capability of the semiconductor device 100.

[0118] In other examples, two adjacent semiconductor structures 10 are a first semiconductor structure 11 and a second semiconductor structure 12. The first surface 10C of the first semiconductor structure 11 is bonded to the first surface 10C of the second semiconductor structure 12.

[0119] Therefore, the heat generated by the first semiconductor structure 11 and the second semiconductor structure 12 can be diffused away through the heat dissipation layer 30 of the bonded first semiconductor structure 11 and the heat dissipation layer 30 of the second semiconductor structure 12, thereby improving the heat dissipation capacity of the semiconductor device 100.

[0120] For example, such as Figure 3 As shown, the first surface 10C of the semiconductor structure 10 can be the surface of the peripheral device layer 40 away from the memory array layer 50 in the semiconductor structure 10. Therefore, the distance between the peripheral device layer 40 and the first surface 10C is small, and the heat generated by the peripheral device layer 40 can be diffused away more quickly through the heat dissipation layer 30 of the first surface 10C, thereby improving the heat dissipation capability of the semiconductor device 100.

[0121] For example, the first surface 10C of the semiconductor device 100 can also be a side surface of the semiconductor device 100 away from the peripheral device layer 40. Thus, the distance between the storage array layer 50 and the first surface 10C is small, and the heat generated by the storage array layer 50 can be quickly dissipated through the heat dissipation layer 30 of the first surface 10C, thereby improving the heat dissipation capability of the semiconductor device 100.

[0122] In some examples, as shown in FIG. 1, the semiconductor structure 10 further includes a first bonding pattern 63 on the first surface 10C of the semiconductor structure 10 and connected to the conductive column 60. The first bonding pattern 63 of the semiconductor structure 10 is disposed in the same layer as the heat dissipation layer 30. Figure 3

[0123] For example, the material of the heat dissipation layer 30 and the material of the first bonding pattern 63 are the same, such as a conductive material, e.g., copper or tungsten.

[0124] The heat dissipation layer 30 and the first bonding pattern 63 are in the same layer and of the same material, so that the heat dissipation layer 30 and the first bonding pattern 63 can be formed simultaneously in one patterning process, thereby simplifying the manufacturing process of the semiconductor device 100.

[0125] In some examples, as shown in FIG. 1, the heat dissipation column 20 includes a first sub-column 21 and a second sub-column 22 connected to each other. The first sub-column 21 penetrates the storage array layer 50, and the second sub-column 22 penetrates the peripheral device layer 40. Figure 4 For example, the first sub-column 21 and the second sub-column 22 are bonded to each other.

[0126] In some examples, as shown in FIG. 1, the semiconductor structure 10 further includes a connection pattern 23 on the first surface 10C of the semiconductor structure 10 and located at the connection region AA; the connection pattern 23 is connected to the second sub-column 22.

[0127] Figure 4 The connection pattern 23 is disposed in the same layer as the heat dissipation layer 30 and connected to each other. For example, the connection pattern 23 is connected to the first heat dissipation strip 31 in the heat dissipation layer 30.

[0128] Thus, the connection of the heat dissipation column 20 and the heat dissipation layer 30 can be realized by using the connection pattern 23.

[0129] For example, the material of the connection pattern 23 and the material of the heat dissipation layer 30 are the same, such as a conductive material, e.g., copper or tungsten.

[0130] The heat dissipation layer 30 and the connection pattern 23 are in the same layer and of the same material, so that the heat dissipation layer 30 and the connection pattern 23 can be formed simultaneously in one patterning process, thereby simplifying the manufacturing process of the semiconductor device 100.

[0131] The heat dissipation layer 30 and the connection pattern 23 are in the same layer and of the same material, so that the heat dissipation layer 30 and the connection pattern 23 can be formed simultaneously in one patterning process, thereby simplifying the manufacturing process of the semiconductor device 100. ​​

[0132] In some examples, as shown in Figure 4 The conductive pillar 60 includes a third sub-pillar 61 and a fourth sub-pillar 62 connected to each other. The third sub-pillar 61 penetrates the memory array layer 50, and the fourth sub-pillar 62 penetrates the peripheral device layer 40.

[0133] The third sub-pillar 61 is arranged in the same layer as the first sub-pillar 21, and the fourth sub-pillar 62 is arranged in the same layer as the second sub-pillar 22.

[0134] For example, the material of the conductive pillar 60 can be the same as that of the heat dissipation pillar 20, such as a conductive material, for example, copper or tungsten.

[0135] Thus, the first sub-pillar 21 and the third sub-pillar 61 can be formed synchronously in one patterning process, thereby facilitating the simplification of the manufacturing process of the semiconductor device 100. Similarly, the second sub-pillar 22 and the fourth sub-pillar 62 can be formed synchronously in one patterning process, thereby further simplifying the manufacturing process of the semiconductor device 100.

[0136] In some examples, as shown in Figure 4 and Figure 5B The semiconductor structure 10 further includes a plurality of shielding walls 70 penetrating the peripheral device layer 40 and the memory array layer 50.

[0137] Each of the shielding walls 70 surrounds the functional region BB and the connection region AA.

[0138] The shielding walls 70 can shield external signals, thereby reducing the interference of the external signals on the internal signals of the semiconductor structure 10 and improving the performance of the semiconductor device 100. In addition, one end of the shielding wall 70 can be grounded, thereby releasing the static electricity in the semiconductor device 100 and avoiding the accumulation of static electricity in the semiconductor device 100 to affect the performance thereof.

[0139] In some examples, as shown in Figure 5B The shielding wall 70 closest to the functional region BB and the connection region AA among the plurality of shielding walls 70 is a first shielding wall 75. The heat dissipation layer 30 is connected to the first shielding wall 75.

[0140] For example, the opposite ends of the second heat dissipation strip 32 in the heat dissipation layer 30 are respectively connected to the first shielding wall 75, and one end of the first heat dissipation strip 31 is connected to the first shielding wall 75.

[0141] Thus, the heat transmitted on the heat dissipation layer 30 can be diffused to the outside of the semiconductor device 100 through the connection of the first heat dissipation strip 31 and the second heat dissipation strip 32 with the first shielding wall 75, thereby improving the heat dissipation capacity of the semiconductor device 100.

[0142] In some examples, as shown in Figure 4As shown, the semiconductor structure 10 further includes a second bonding pattern 73 located on the first surface 10C of the semiconductor structure 10. The second bonding pattern 73 is connected to the shielding wall 70.

[0143] The second bonding pattern 73 is disposed on the same layer as the heat dissipation layer 30 and is connected to it. For example, the second bonding pattern 73 is connected to the first heat dissipation strip 31 and the second heat dissipation strip 32 in the heat dissipation layer 30.

[0144] The heat dissipation layer 30 is made of the same material as the second bonding pattern 73, for example, both are conductive materials such as copper or tungsten.

[0145] The heat dissipation layer 30 and the second bonding pattern 73 are made of the same layer and material. Therefore, the heat dissipation layer 30 and the second bonding pattern 73 can be formed simultaneously in one patterning process, thereby simplifying the fabrication process of the semiconductor device 100.

[0146] It is understandable that, such as Figure 4 As shown, the semiconductor structure 10 further includes a third bonding pattern 64, a fourth bonding pattern 74, and an auxiliary connection pattern 24 disposed on the second surface 10D of the semiconductor structure 10. The third bonding pattern 64 is connected to the conductive pillar 60, the fourth bonding pattern 74 is connected to the shielding wall 70, and the auxiliary connection pattern 24 is connected to the heat dissipation pillar 20.

[0147] like Figure 4 As shown, when the first surface 10C of the first semiconductor structure 11 is bonded to the second surface 10D of the second semiconductor structure 12, the conductive pillars 60 in the first semiconductor structure 11 are connected to the conductive pillars 60 in the second semiconductor structure 12 through the first bonding pattern 63 of the first semiconductor structure 11 and the third bonding pattern 64 of the second semiconductor structure 12; the shielding wall 70 in the first semiconductor structure 11 is connected to the shielding wall 70 in the second semiconductor structure 12 through the second bonding pattern 73 of the first semiconductor structure 11 and the fourth bonding pattern 74 of the second semiconductor structure 12; the heat dissipation pillars 20 in the first semiconductor structure 11 are connected to the heat dissipation pillars 20 in the second semiconductor structure 12 through the connection pattern 23 of the first semiconductor structure 11 and the auxiliary connection pattern 24 of the second semiconductor structure 12.

[0148] In the case that the first surface 10C of the first semiconductor structure 11 is bonded to the first surface 10C of the second semiconductor structure 12, the conductive pillar 60 in the first semiconductor structure 11 is connected to the conductive pillar 60 in the second semiconductor structure 12 through the first bonding pattern 63 of the first semiconductor structure 11 and the first bonding pattern 63 of the second semiconductor structure 12; the shielding wall 70 in the first semiconductor structure 11 is connected to the shielding wall 70 in the second semiconductor structure 12 through the second bonding pattern 73 of the first semiconductor structure 11 and the second bonding pattern 73 of the second semiconductor structure 12; and the heat dissipation pillar 20 in the first semiconductor structure 11 is connected to the heat dissipation pillar 20 in the second semiconductor structure 12 through the connection pattern 23 of the first semiconductor structure 11 and the connection pattern 23 of the second semiconductor structure 12.

[0149] In some examples, as shown in FIG. 1, the shielding wall 70 includes a first sub-wall 71 and a second sub-wall 72 connected to each other. Figure 4

[0150] The first sub-wall 71 penetrates the memory array layer 50, and the second sub-wall 72 penetrates the peripheral device layer 40.

[0151] As can be seen from the above embodiments, the heat dissipation pillar 20 includes a first sub-pillar 21 and a second sub-pillar 22 connected to each other. The first sub-pillar 21 penetrates the memory array layer 50, and the second sub-pillar 22 penetrates the peripheral device layer 40.

[0152] The first sub-wall 71 is disposed in the same layer as the first sub-pillar 21, and the second sub-wall 72 is disposed in the same layer as the second sub-pillar 22.

[0153] For example, the first sub-wall 71 is made of the same material as the first sub-pillar 21, and the second sub-wall 72 is made of the same material as the second sub-pillar 22.

[0154] Therefore, the first sub-pillar 21 and the first sub-wall 71 can be formed synchronously in one patterning process, thereby facilitating the simplification of the preparation process of the semiconductor device 100. Similarly, the second sub-pillar 22 and the second sub-wall 72 can be formed synchronously in one patterning process, thereby further simplifying the preparation process of the semiconductor device 100.

[0155] Embodiments of the present disclosure also provide a preparation method of a semiconductor device 100, which is used to prepare the semiconductor device 100 according to any one of the above embodiments.

[0156] The preparation method of the semiconductor device 100 according to some embodiments of the present disclosure includes the following steps: Figure 6 The preparation method of the semiconductor device 100 according to some embodiments of the present disclosure includes the following steps: Figures 7-15 The preparation method of the semiconductor device 100 according to some embodiments of the present disclosure includes the following steps: Figure 6 ​The steps shown are not exclusive and other steps can be performed before, after, or between any of the steps shown. Furthermore, some of the steps can be performed simultaneously, or in a different order than shown. Figure 6 The steps shown are not exclusive and other steps can be performed before, after, or between any of the steps shown. Furthermore, some of the steps can be performed simultaneously, or in a different order than shown.

[0157] In particular, as Figure 6 shown, the preparation method includes: A100-A200.

[0158] A100, as Figure 9 shown, at least one semiconductor structure 10 is formed. The semiconductor structure 10 is embedded with at least one heat dissipation column 20. The heat dissipation column 20 extends along the thickness direction of the semiconductor structure 10.

[0159] For example, in the case of a semiconductor device 100 including one semiconductor structure 10, one semiconductor structure 10 is formed. In the case of a semiconductor device 100 including multiple semiconductor structures 10, multiple semiconductor structures 10 are formed synchronously.

[0160] For example, in the case of a semiconductor device 100 including one semiconductor structure 10, one semiconductor structure 10 is formed. In the case of a semiconductor device 100 including multiple semiconductor structures 10, multiple semiconductor structures 10 are formed synchronously.

[0161] For example, in the case of a semiconductor device 100 including one semiconductor structure 10, one semiconductor structure 10 is formed. In the case of a semiconductor device 100 including multiple semiconductor structures 10, multiple semiconductor structures 10 are formed synchronously.

[0162] For example, in the case of a semiconductor device 100 including one semiconductor structure 10, one semiconductor structure 10 is formed. In the case of a semiconductor device 100 including multiple semiconductor structures 10, multiple semiconductor structures 10 are formed synchronously.

[0163] For example, in the case of a semiconductor device 100 including one semiconductor structure 10, one semiconductor structure 10 is formed. In the case of a semiconductor device 100 including multiple semiconductor structures 10, multiple semiconductor structures 10 are formed synchronously.

[0164] A200, as Figure 11As shown, a heat dissipation layer 30 is formed on the first surface 10C of the semiconductor structure 10. The first surface 10C is a side surface along its thickness direction, and the heat dissipation layer 30 is located on one side of the heat dissipation pillar 20 and is connected to the heat dissipation pillar 20.

[0165] The structure of the heat dissipation layer 30 can be referred to the description in some of the embodiments above in this disclosure, and will not be repeated here.

[0166] The semiconductor device 100 provided in the embodiments of this disclosure has at least one heat sink 20 embedded in the semiconductor structure 10. The heat sink 20 extends along the thickness direction of the semiconductor structure 10, thereby dissipating the heat generated within the semiconductor device 100 and improving the heat dissipation capacity of the semiconductor device 100. A heat dissipation layer 30 is also formed on the first surface 10C of the semiconductor structure 10, thereby dissipating the heat within the semiconductor device 100 along the first surface 10C. The heat dissipation layer 30 is connected to the heat sink 20, thereby forming a three-dimensional heat diffusion channel within the semiconductor device 100, further improving the heat dissipation capacity of the semiconductor device 100, reducing the temperature and power consumption of the semiconductor device 100, and improving the performance of the semiconductor device 100.

[0167] In some examples, the semiconductor device 100 includes a plurality of semiconductor structures 10, and the above-described fabrication method also includes: A300.

[0168] A300, such as Figure 14 As shown, multiple semiconductor structures 10 are sequentially bonded along the thickness direction of the semiconductor structure 10.

[0169] For example, firstly, the first semiconductor structure 11 and the second semiconductor structure 12 of the plurality of semiconductor structures 10 are bonded along the thickness direction to form a first intermediate. Then, the first intermediate is bonded to one of the remaining semiconductor structures 10 along its thickness direction.

[0170] In some examples, such as Figure 8 As shown, the semiconductor structure 10 includes a dielectric layer 80 located on the first surface 10C.

[0171] For example, the dielectric layer 80 includes a first dielectric layer 81 and a second dielectric layer 82 stacked together. The materials of the first dielectric layer 81 and the second dielectric layer 82 can be insulating materials. For example, the material of the first dielectric layer can be silicon oxide, and the material of the second dielectric layer can be silicon nitride or carbon-doped silicon nitride, etc. This facilitates the mutual bonding connection between the semiconductor structure 10 and the semiconductor structure 10 to be bonded.

[0172] For example, a thin film deposition process of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be employed to form the dielectric layer 80.

[0173] In the A200, the heat dissipation layer 30 is formed on the first surface 10C of the semiconductor structure 10, including: A210-A220.

[0174] A210, as shown in the drawings, a plurality of first grooves 83 and a plurality of second grooves 84 are formed on the dielectric layer. The second grooves 84 cross and communicate with at least one first groove 83. Figure 10

[0175] For example, an etching process is employed to form a plurality of first grooves 83 and a plurality of second grooves 84 on the dielectric layer 80. The first grooves 83 and the second grooves 84 are recessed along the thickness direction of the dielectric layer 80. The recessed depth of the first grooves 83 and the second grooves 84 can be equal or substantially equal, for example, the first grooves 83 and the second grooves 84 penetrate the second dielectric layer 82. The extension directions of the first grooves 83 and the second grooves 84 are different.

[0176] A220, as shown in the drawings, a first heat dissipation strip 31 is formed in the first groove 83, and a second heat dissipation strip 32 is formed in the second groove 84. Each second heat dissipation strip 32 crosses and connects with at least one first heat dissipation strip 31, and each first heat dissipation strip 31 connects with at least one heat dissipation column 20. Figure 10 Figure 11

[0177] The first heat dissipation strip 31 and the second heat dissipation strip 32 constitute the heat dissipation layer 30. The material of the heat dissipation layer 30 can be copper. The copper material can be deposited into the first grooves 83 and the second grooves 84 by electroplating process to form the heat dissipation layer 30.

[0178] The preparation method of the heat dissipation layer 30 can make the preparation of the heat dissipation layer 30 more simple, which is conducive to reducing the preparation difficulty of the semiconductor device 100.

[0179] In some examples, as shown in the drawings, the semiconductor structure 10 further includes: a first substrate 42 located on the side of the peripheral device layer 40 away from the storage array layer 50, and a conductive column 60 penetrating the storage array layer 50 and the peripheral device layer 40 and extending into the first substrate. The heat dissipation column 20 penetrates the storage array layer 50, the peripheral device layer 40, and extends into the first substrate 42. Figure 7

[0180] ​​​​For example, the depth to which the heat sink 20 extends into the first substrate 42 is equal to or approximately equal to the depth to which the conductive pillar 60 extends into the first substrate 42.

[0181] For example, the material of the first substrate 42 can be single-crystal silicon (Si), single-crystal germanium (Ge), germanium silicon (GeSi), or silicon carbide (SiC); it can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds.

[0182] Before the heat dissipation layer 30 is formed on the first surface 10C of the semiconductor structure 10 in the above-mentioned A200, the method for fabricating the above-mentioned semiconductor device 100 further includes: A110 to A120.

[0183] A110, such as Figure 8 As shown, a portion of the first substrate 42 is removed, exposing the conductive pillar 60 and the heat dissipation pillar 20.

[0184] For example, a portion of the first substrate 42 can be removed using a chemical mechanical planarization (CMP) process or a grinding process.

[0185] Understandably, the peripheral device layer 40 also includes interconnect contacts 90. The interconnect contacts 90 are connected to the peripheral device 41 and extend along the thickness direction of the semiconductor structure 10. The interconnect contacts 90 extend from the peripheral device layer 40 into the first substrate. After a portion of the first substrate is removed, the interconnect contacts 90 are also exposed. Before forming the heat dissipation layer 30, an interconnect pattern 91 is formed to connect adjacent interconnect contacts 90.

[0186] A120, such as Figure 11 As shown, during the process of forming a heat dissipation layer 30 on the first surface 10C of the semiconductor structure 10, a first bonding pattern 63 and a connection pattern 23 are simultaneously formed on the first surface 10C of the semiconductor structure 10. The first bonding pattern 63 is connected to the conductive pillar 60 located in the semiconductor structure 10, and the connection pattern 23 is connected to the heat dissipation pillar 20 located in the semiconductor structure 10.

[0187] For example, such as Figure 9 As shown, during the formation of the first trench 83 and the second trench 84 on the dielectric layer 80, an etching process is simultaneously employed to form a first via 93 and a second via 94. The first via 93 penetrates the first dielectric layer 81 and the second dielectric layer 82, exposing a portion of the surface of the conductive pillar 60 within the semiconductor structure 10. Figure 9 and Figure 10As shown, the second via 94 penetrates the first dielectric layer 81 and the second dielectric layer 82, and is connected to the first trench 83. The second via 94 exposes a portion of the surface of the heat sink 20 within the semiconductor structure 10. During the formation of the first heat sink 31, an electroplating process is simultaneously employed to form a first bonding pattern 63 within the first via 93 and a connection pattern 23 within the second via 94. The connection pattern 23 is connected to the heat sink 20 and also to the first heat sink 31.

[0188] The material of the connecting pattern 23 is the same as the material of the first bonding pattern 63 and the material of the heat dissipation layer 30.

[0189] Before bonding multiple semiconductor structures 10 sequentially along the thickness direction of semiconductor structure 10 in A300, such as Figure 13 As shown, the method for fabricating the semiconductor device 100 further includes forming a third bonding pattern 64 on the second surface 10D of the semiconductor structure 10 to be bonded. The third bonding pattern 64 is connected to the conductive pillar 60.

[0190] During the sequential bonding of multiple semiconductor structures 10, the third bonding pattern 64 of the semiconductor structure 10 to be bonded is connected to the first bonding pattern 63 of another semiconductor structure 10. Alternatively, the third bonding pattern 64 of the semiconductor structure 10 to be bonded is connected to the third bonding pattern 64 of another semiconductor structure 10.

[0191] For example, such as Figure 7 As shown, the semiconductor structure 10 also includes a second substrate 52 located on the side of the memory array 51 device layer away from the peripheral device layer 40.

[0192] For example, the material of the second substrate 52 can be single-crystal silicon (Si), single-crystal germanium (Ge), germanium silicon (GeSi), or silicon carbide (SiC); it can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds.

[0193] like Figure 12 and Figure 13 As shown, before forming the third bonding pattern 64, the second substrate 52 is removed, and a third dielectric layer and a fourth dielectric layer are sequentially formed on one side of the device layer of the memory array 51. A third via is formed penetrating the fourth dielectric layer and the third dielectric layer, exposing a conductive pillar 60. A third bonding pattern is formed within the third via. During the formation of the third via, a fourth via is simultaneously formed, exposing a heat dissipation pillar 20. An auxiliary connection pattern 24 is formed within the fourth via, and the auxiliary connection pattern 24 is connected to the heat dissipation pillar 20.

[0194] The auxiliary connection pattern 24 and the third bonding pattern 64 are made of the same material as the heat dissipation layer 30.

[0195] In some examples, as shown in FIG. 1A, the semiconductor structure 10 includes a first bonding pattern 63, a second bonding pattern 64, a third bonding pattern 65, a fourth bonding pattern 66, a first connection pattern 23, a second connection pattern 24, a first dielectric layer 31, a second dielectric layer 32, a third dielectric layer 33, a fourth dielectric layer 34, a first heat dissipation layer 30, a second heat dissipation layer 31, a third heat dissipation layer 32, and a fourth heat dissipation layer 33. Figure 14 Figure 15 As shown in FIG. 1B, in the process of sequentially bonding a plurality of semiconductor structures 10, the third bonding pattern 64 of the semiconductor structure 10 to be bonded is connected with the first bonding pattern 63 of another semiconductor structure 10, thereby realizing the connection of the two adjacent conductive pillars 60. And the auxiliary connection pattern 24 of the semiconductor structure 10 to be bonded is bonded and connected with the connection pattern 23 of another semiconductor structure 10, thereby realizing the connection of the two adjacent heat dissipation pillars 20. The fourth dielectric layer of the semiconductor structure 10 to be bonded is bonded and connected with the heat dissipation layer 30 of another semiconductor structure 10, realizing the bonding connection of the semiconductor structure 10 to be bonded and another semiconductor structure 10.

[0196] In other examples, in the process of sequentially bonding a plurality of semiconductor structures 10, the first bonding pattern 63 of the semiconductor structure 10 to be bonded is connected with the first bonding pattern 63 of another semiconductor structure 10, thereby realizing the connection of the two adjacent conductive pillars 60. And the connection pattern 23 of the semiconductor structure 10 to be bonded is bonded and connected with the connection pattern 23 of another semiconductor structure 10, thereby realizing the connection of the two adjacent heat dissipation pillars 20. The heat dissipation layer 30 of the semiconductor structure 10 to be bonded is bonded and connected with the heat dissipation layer 30 of another semiconductor structure 10, realizing the bonding connection of the semiconductor structure 10 to be bonded and another semiconductor structure 10.

[0197] In some examples, the storage array layer 50 includes at least one storage array 51, and the peripheral device layer 40 includes at least one peripheral device 41.

[0198] As shown in FIG. 1C, in the process of forming a plurality of heat dissipation pillars 20 in the semiconductor structure 100, a plurality of shielding walls 70 are simultaneously formed. The plurality of shielding walls 70 pass through the peripheral device layer 40 and the storage array layer 50. The shielding wall 70 surrounds at least one storage array 51 device and at least one peripheral device 41. Figure 9 The preparation method of the shielding wall 70 can refer to the preparation method of the heat dissipation pillar 20 described above. The material of the shielding wall 70 can be the same as the material of the heat dissipation pillar 20 described above. In this way, the shielding wall 70 and the heat dissipation pillar 20 can be simultaneously formed in one patterning process, thereby simplifying the preparation process of the semiconductor device 100.

[0199] In some examples, as shown in FIG. 1D, in the process of forming the third bonding pattern 64 on the second surface 10D of the semiconductor structure 10 to be bonded, the fourth bonding pattern 74 is simultaneously formed. The fourth bonding pattern 74 is connected with one end of the shielding wall 70.

[0200] Figure 13

[0201] ​​​The fourth bonding pattern 74 can be formed by referring to the description of the third bonding pattern 64 in the above-mentioned embodiments.

[0202] As shown in FIG. 7, the second bonding pattern 73 is formed on the first surface 10C of the semiconductor structure 10 in the process of forming the heat dissipation layer 30 on the first surface 10C of the semiconductor structure 10. Figure 11

[0203] For example, as shown in FIG. 8, the third trench 85 is formed in the process of forming the first trench 83 and the second trench 84 on the second dielectric layer 82, and the second bonding pattern 73 is formed in the third trench 85, which is connected with the shielding wall 70. Figure 10 Figure 11

[0204] For example, in the case that the shielding wall 70 is the first shielding wall 75, the third trench 85 is communicated with the second trench 84 and the first trench 83, and the second bonding pattern 73 is connected with the first heat dissipation strip 31 and the second heat dissipation strip 32 in the heat dissipation layer 30.

[0205] The fourth bonding pattern 74 and the second bonding pattern 73 are formed by the above-mentioned preparation method, which can simplify the preparation process of the semiconductor device 100.

[0206] In the process of bonding the plurality of semiconductor structures 10 by the A300, the second bonding pattern 73 of the semiconductor structure 10 to be bonded is connected with the fourth bonding pattern 74 of another semiconductor structure 10. Alternatively, the second bonding pattern 73 of the semiconductor structure 10 to be bonded is connected with the second bonding pattern 73 of another semiconductor structure 10. Thus, the connection of the shielding walls 70 in the adjacent two semiconductor structures 10 is realized.

[0207] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any changes or replacements within the technical scope disclosed by the present disclosure can be easily thought by those skilled in the art, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.​​​

Claims

1. A semiconductor device, characterized by, The semiconductor device includes: at least one semiconductor structure; The semiconductor structure includes a heat dissipation layer and at least one heat dissipation pillar; the heat dissipation pillar is embedded inside the semiconductor structure and extends along the thickness direction of the semiconductor structure; the heat dissipation layer is located on one side of the heat dissipation pillar and on a first surface of the semiconductor structure, the first surface being one side surface along its thickness direction; the heat dissipation layer is connected to the heat dissipation pillar.

2. The semiconductor device according to claim 1, wherein The heat dissipation layer includes a plurality of first heat dissipation strips; Each of the first heat dissipation strips is connected to at least one of the heat dissipation columns.

3. The semiconductor device of claim 2, wherein, The heat dissipation layer also includes multiple second heat dissipation strips; Each of the second heat sinks and at least one of the first heat sinks intersect and are connected.

4. The semiconductor device of claim 1, wherein The heat dissipation layer is made of metallic materials.

5. The semiconductor device of claim 1, wherein The semiconductor device includes multiple semiconductor structures; the multiple semiconductor structures are stacked along the thickness direction of the semiconductor structures, and adjacent semiconductor structures are bonded to each other.

6. The semiconductor device according to claim 5, wherein The plurality of semiconductor structures include a first semiconductor structure and a second semiconductor structure; The two adjacent semiconductor structures are the first semiconductor structure and the second semiconductor structure; the first surface of the first semiconductor structure is bonded to the second surface of the second semiconductor structure. The second surface of the second semiconductor structure is the surface opposite to the first surface in the second semiconductor structure.

7. The semiconductor device of claim 5, wherein The semiconductor structure includes a first semiconductor structure and a second semiconductor structure; The two adjacent semiconductor structures are the first semiconductor structure and the second semiconductor structure; the first surface of the first semiconductor structure is bonded to the first surface of the second semiconductor structure.

8. The semiconductor device according to any one of Claims 1 to 7, wherein The semiconductor structure has a connection region and a functional region located on at least one side of the connection region; The heat dissipation column is located in the connection area; The semiconductor structure includes: a plurality of conductive pillars embedded within the semiconductor structure; the conductive pillars are located in the connection region and extend along the thickness direction of the semiconductor structure; The conductive pillars located in two adjacent semiconductor structures are bonded to each other.

9. The semiconductor device of claim 8, wherein, At least some of the plurality of heat dissipation pillars are located between the plurality of conductive pillars and the functional area.

10. The semiconductor device of claim 8, wherein, The heat dissipation layer includes a plurality of first heat dissipation strips and a plurality of second heat dissipation strips; The first heat dissipation strip extends from the functional area to the connection area and is connected to the heat dissipation column; the second heat dissipation strip is located in the functional area.

11. The semiconductor device of claim 8, wherein, The semiconductor structure further includes: a first bonding pattern located on a first surface of the semiconductor structure and connected to the conductive pillar; The first bonding pattern of the semiconductor structure is disposed in the same layer as the heat dissipation layer.

12. The semiconductor device of claim 8, wherein, The semiconductor structure includes: a peripheral device layer and a memory array layer stacked sequentially along the thickness direction of the semiconductor structure; The heat dissipation column includes a first sub-column and a second sub-column connected to each other; The first sub-pillar penetrates the memory array layer, and the second sub-pillar penetrates the peripheral device layer.

13. The semiconductor device of claim 12, wherein, The semiconductor structure further includes: a connection pattern located on a first surface of the semiconductor structure and in the connection region; the connection pattern is connected to the second sub-pillar; The connection pattern is disposed on the same layer as the heat dissipation layer and is connected to it.

14. The semiconductor device of claim 12, wherein, The conductive column comprises a third sub-column and a fourth sub-column connected with each other; The third sub-column penetrates through the storage array layer, and the fourth sub-column penetrates through the peripheral device layer; The third sub-column is arranged in the same layer as the first sub-column, and the fourth sub-column is arranged in the same layer as the second sub-column.

15. The semiconductor device of claim 8, wherein, The semiconductor structure further comprises a peripheral device layer and a storage array layer stacked in sequence along the thickness direction of the semiconductor structure, and a plurality of shielding walls penetrating through the peripheral device layer and the storage array layer; Each of the shielding walls surrounds the functional region and the connecting region.

16. The semiconductor device of claim 15, wherein, The shielding wall closest to the functional region and the connecting region among the plurality of shielding walls is a first shielding wall; The heat dissipation layer is connected with the first shielding wall.

17. The semiconductor device of claim 16, wherein, The semiconductor structure further comprises a second bonding pattern on a first surface of the semiconductor structure; the second bonding pattern is connected with the shielding wall; The second bonding pattern is arranged in the same layer as the heat dissipation layer and is connected with the heat dissipation layer.

18. The semiconductor device of claim 15, wherein, The shielding wall comprises a first sub-wall and a second sub-wall connected with each other; The first sub-wall penetrates through the storage array layer, and the second sub-wall penetrates through the peripheral device layer; The heat dissipation column comprises a first sub-column and a second sub-column connected with each other; the first sub-column penetrates through the storage array layer, and the second sub-column penetrates through the peripheral device layer; The first sub-wall is arranged in the same layer as the first sub-column, and the second sub-wall is arranged in the same layer as the second sub-column.

19. A method of manufacturing a semiconductor device, characterized by, The preparation method comprises: forming at least one semiconductor structure; the semiconductor structure is embedded with at least one heat dissipation column, and the heat dissipation column extends along the thickness direction of the semiconductor structure; forming a heat dissipation layer on a first surface of the semiconductor structure; the first surface is a side surface along the thickness direction thereof, and the heat dissipation layer is located on one side of the heat dissipation column and is connected with the heat dissipation column.

20. The method of claim 19, wherein, The semiconductor structure comprises a dielectric layer on the first surface; The forming of the heat dissipation layer on the first surface of the semiconductor structure comprises: forming a plurality of first grooves and a plurality of second grooves on the dielectric layer; the second grooves intersect with and communicate with at least one of the first grooves; forming first heat dissipation strips in the first grooves and second heat dissipation strips in the second grooves; each of the second heat dissipation strips intersects with and is connected with at least one of the first heat dissipation strips, and each of the first heat dissipation strips is connected with at least one of the heat dissipation columns.

21. The preparation method according to claim 19, characterized in that, The semiconductor device comprises a plurality of semiconductor structures; the preparation method further comprises: bonding the plurality of semiconductor structures in sequence along the thickness direction of the semiconductor structure.

22. The method of claim 21, wherein, The semiconductor structure comprises a storage array device layer, a peripheral device layer, a first substrate arranged in a stacked manner, and a conductive column penetrating through the storage array layer and the peripheral device layer and extending into the first substrate; the heat dissipation column penetrates through the storage array layer, the peripheral device layer, and extends into the first substrate; Before the forming of the heat dissipation layer on the first surface of the semiconductor structure, the preparation method further comprises: removing a part of the first substrate to expose the conductive column and the heat dissipation column; In the process of forming the heat dissipation layer on the first surface of the semiconductor structure, a first bonding pattern is formed on the first surface of the semiconductor structure, the first bonding pattern is connected with the conductive column in the semiconductor structure, and a connection pattern is formed on the first surface of the semiconductor structure, the connection pattern is connected with the heat dissipation column in the semiconductor structure. Before the plurality of semiconductor structures are sequentially bonded along the thickness direction of the semiconductor structure, the preparation method further comprises: A third bonding pattern is formed on the second surface of the semiconductor structure to be bonded, and the third bonding pattern is connected with the conductive column.

23. The method of claim 22, wherein, The storage array device layer comprises at least one storage array device, and the peripheral device layer comprises at least one peripheral device; A plurality of shielding walls are formed synchronously in the process of forming the plurality of heat dissipation columns. The plurality of shielding walls pass through the peripheral device layer and the storage array layer, and the shielding walls surround the at least one storage array device and the at least one peripheral device.

24. The preparation method of claim 23, wherein In the process of forming the third bonding pattern on the second surface of the semiconductor structure to be bonded, a fourth bonding pattern is formed synchronously. The fourth bonding pattern is connected with one end of the shielding wall. In the process of forming the heat dissipation layer on the first surface of the semiconductor structure, a second bonding pattern is formed on the first surface of the semiconductor structure, and the second bonding pattern is connected with the other end of the shielding wall.

25. A storage system, comprising: The storage system comprises a controller and the semiconductor device according to any one of claims 1-18, wherein the controller is coupled to the semiconductor device and is configured to control the semiconductor device to store data.

26. An electronic device, comprising: The electronic device comprises the storage system according to claim 25 and a circuit board electrically connected with the storage system.

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