Single event effect resistant groove Schottky diode cellular structure and preparation method thereof

Abstract

The invention discloses an anti-single event effect trench Schottky diode cellular structure and a preparation method thereof. The cellular structure comprises a substrate and an epitaxial layer on the surface of the substrate; the trench structure is formed in the epitaxial layer and comprises a deep trench region and a V-shaped opening region above the deep trench region, a gate oxide layer is deposited on the inner surface of the deep trench region, and the deep trench region is filled with a polycrystalline silicon layer covering the gate oxide layer; the Pbody region and the deep energy level recombination center are formed on the side wall of the V-shaped opening region; an anode metal; schottky metal is deposited on the inner surface of the V-shaped opening area, the exposed surface of the polycrystalline silicon layer and the surface of the side, away from the substrate, of the epitaxial layer. The anode metal is located on the upper surface, covered by the Schottky metal, of the epitaxial layer and in the V-shaped opening area. The cathode metal is located on the surface of one side, away from the epitaxial layer, of the substrate. The introduced deep energy level recombination center can efficiently capture holes when a single event effect occurs, and charge accumulation is eliminated through non-radiative recombination, so that instantaneous charges generated by a single event are rapidly eliminated.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a trench Schottky diode cell structure resistant to single-event effects and its fabrication method. Background Technology

[0002] Schottky diodes, due to their unique advantages such as low power consumption and high current, also have broad application prospects in aerospace and other space fields. However, power electronic systems operating in the space environment will inevitably face the severe challenges of high-temperature and high-radiation environments.

[0003] The space radiation environment primarily consists of cosmic rays, solar flares, and radiation from the inner and outer Van Allen radiation belts surrounding the Earth. This radiation includes a large number of cosmic rays and high-energy particles originating from the Sun, the Milky Way, and secondary shower particles. In the space environment, without the protection of an atmosphere and magnetic field, semiconductor devices will experience single-event effects, total ionizing radiation dose effects, and displacement damage effects. Among these, single-event effects refer to the degradation or even failure of a device caused by a single high-energy particle incident on it, and are one of the main threats to power electronic devices in space applications.

[0004] To improve the device's resistance to single-event events, existing technologies employ a shallow trench combined with a gradient doping drift region design, with a low concentration of P at the bottom of the trench. - A buffer layer is formed, and step-type N-type doping is performed on the trench sidewalls, P - Hole injection in the buffer layer enhances the threshold current of the conductivity modulation effect, thus leading to an increase in the forward voltage drop (VF). Furthermore, existing technologies also introduce P into conventional trench TSDs (Transient Voltage Suppression Diodes). + Islands are formed to create a junction barrier Schottky structure by implanting aluminum into the surface of the epitaxial layer between the trenches to form periodic P-type structures. + Island, and make P + Island and N - The drift region forms a PN junction, which works in conjunction with the Schottky contact within the trench; however, P... + The presence of the island reduces the Schottky contact area, increases the current density at the same current, and causes VF to vary with P. + The island density increases linearly with increasing density.

[0005] Clearly, designing device structures that provide better single-event immunity while maintaining conductivity has become a pressing technical problem. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a cell structure for an anti-single-particle trench Schottky diode containing high-energy-level recombination centers and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a trench Schottky diode cell structure resistant to single-event effects, comprising: Substrate and an epitaxial layer located on one side surface of the substrate; The trench structure formed in the epitaxial layer includes a deep trench region and a V-shaped opening region above the deep trench region. A gate oxide layer is deposited on the inner surface of the deep trench region and a polysilicon layer covering the gate oxide layer is filled thereon. The top of the polysilicon layer is flush with the bottom of the V-shaped opening region. The Pbody region is formed on the sidewall of the V-shaped opening region; Deep-level recombination centers formed on the sidewalls of the V-shaped opening region are used to capture holes generated by the single-particle effect. Anode metal; Schottky metal is deposited on the inner surface of the V-shaped opening region, the exposed surface of the polysilicon layer, and the surface of the epitaxial layer away from the substrate. The Schottky metal forms a Schottky contact with the epitaxial layer and an ohmic contact with the polysilicon layer. The anode metal is located on the upper surface of the epitaxial layer covered by the Schottky metal and in the V-shaped opening region. The cathode metal located on the surface of the substrate away from the epitaxial layer.

[0007] In one embodiment of the present invention, the substrate is a heavily doped N-type Si substrate with a thickness of 715~735μm and a resistivity of 0.002~0.006Ω·cm.

[0008] In one embodiment of the present invention, the depth of the trench structure is 2~3μm, the depth of the V-shaped opening region is 1μm, and the angle between the sidewall of the V-shaped opening region and the first direction is 30~45°, wherein the first direction is a direction perpendicular to the plane of the substrate.

[0009] In a second aspect, the present invention also provides a method for preparing a trench Schottky diode cell structure resistant to single-event effects, for fabricating a trench Schottky diode cell structure resistant to single-event effects as described in the first aspect. The method includes: A substrate is provided, and an epitaxial layer is grown on one side surface of the substrate; A trench structure is formed in the epitaxial layer, the trench structure including a deep trench region and a V-shaped opening region above the deep trench region; A gate oxide layer is deposited on the inner surface of the deep trench region, and a polysilicon layer is filled in the deep trench region; A Pbody region is formed on the sidewall of the V-shaped opening region; Deep-level recombination centers are formed on the sidewalls of the V-shaped opening region; Schottky metal is deposited on the inner surface of the V-shaped opening region, the exposed surface of the polysilicon layer, and the surface of the epitaxial layer away from the substrate, so that the Schottky metal forms a Schottky contact with the epitaxial layer and an ohmic contact with the polysilicon layer. An anode metal is deposited on the upper surface of the epitaxial layer, and a cathode metal is deposited on the surface of the substrate on the side away from the epitaxial layer.

[0010] In one embodiment of the present invention, the step of forming a trench structure within the epitaxial layer includes: A silicon dioxide layer is deposited on the surface of the epitaxial layer away from the substrate as a hard mask. A photoresist pattern is formed on the surface of the silicon dioxide layer, and the photoresist pattern is transferred to the silicon dioxide layer by etching. Using a patterned silicon dioxide layer as a mask, a rectangular deep trench region is formed in the epitaxial layer by dry etching; By adjusting the etching selectivity, the upper half of the deep trench region is etched into a V-shaped opening region; The bottom of the deep trench region is rounded by wet isotropic etching to form an arc-shaped sidewall.

[0011] In one embodiment of the present invention, the steps of depositing a gate oxide layer on the inner surface of the deep trench region and filling the deep trench region with a polysilicon layer include: After growing a gate oxide layer on the inner surface of the trench structure by thermal oxidation, a polycrystalline silicon layer is deposited inside the trench structure. The gate oxide layer and the polysilicon layer are etched back to the bottom of the V-shaped opening region.

[0012] In one embodiment of the present invention, the step of forming a deep-level recombination center on the sidewall of the V-shaped opening region includes: Platinum is sputtered onto the sidewalls of the V-shaped opening region, the exposed surface of the polycrystalline silicon layer, and the surface of the epitaxial layer away from the substrate, and then subjected to high-temperature annealing to allow platinum atoms to diffuse and form deep-level recombination centers.

[0013] In one embodiment of the present invention, after the step of forming a deep-level recombination center on the sidewall of the V-shaped opening region, the method further includes: Undiffused platinum was etched using aqua regia, and platinum outside the sidewalls of the V-shaped opening region was removed by photolithography and etching.

[0014] In one embodiment of the present invention, the Schottky metal is Ti with a thickness of 300-1000 Å.

[0015] In one embodiment of the present invention, the anode metal is Al with a thickness of 4-6 μm; The cathode metal is Ti / Ni / Ag with a thickness of 5~10μm.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention provides a trench Schottky diode cell structure and its fabrication method that resist single-event effects. In this cell structure, the trench structure formed in the epitaxial layer consists of a deep trench region and a V-shaped opening region above it. The Pbody region and deep level recombination centers are formed on the sidewalls of the V-shaped opening region. This invention forms a closed-loop protection of "capture-transport-recombination" with the trench structure through the deep level recombination centers. Under reverse bias conditions, the deep level recombination centers can efficiently capture holes when single-event effects occur and eliminate charge accumulation through non-radiative recombination, so that the instantaneous charge generated by single particles is quickly cleared, thereby preventing avalanche breakdown or latch-up failure caused by charge accumulation.

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0018] Figure 1 This is a top view of the trench Schottky diode cell structure resistant to single-event effects provided in an embodiment of the present invention; Figure 2 This is a cross-sectional view of the trench Schottky diode cell structure provided in an embodiment of the present invention along the diagonal AA' direction; Figure 3 This is a schematic diagram of the arrangement of multiple trench Schottky diode cell structures provided in an embodiment of the present invention; Figure 4 This is a flowchart of a method for fabricating a trench Schottky diode cell structure resistant to single-event effects provided in an embodiment of the present invention; Figures 5-13 This is a schematic diagram illustrating the fabrication process of the trench Schottky diode cell structure resistant to single-event effects provided in an embodiment of the present invention. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0020] Figure 1 This is a top view of the cell structure of the trench Schottky diode resistant to single-event effects provided in an embodiment of the present invention. Figure 2This is a cross-sectional view of the trench Schottky diode cell structure provided in an embodiment of the present invention along the diagonal AA' direction. Figures 1-2 As shown, an embodiment of the present invention provides a trench Schottky diode cell structure resistant to single-event effects, comprising: Substrate 1 and epitaxial layer 2 located on one side surface of substrate 1; The trench structure 3 formed in the epitaxial layer 2 includes a deep trench region 31 and a V-shaped opening region 32 above the deep trench region 31. A gate oxide layer 4 is deposited on the inner surface of the deep trench region 31, and a polysilicon layer 5 covering the gate oxide layer 4 is filled thereon. The top of the polysilicon layer 5 is flush with the bottom of the V-shaped opening region 32. Pbody region 6 is formed on the sidewall of the V-shaped opening region 32; Deep-level recombination centers 7, formed on the sidewalls of the V-shaped opening region 32, are used to capture holes generated by the single-event effect. Anode metal 9; Schottky metal 8 is deposited on the inner surface of the V-shaped opening region 32, the exposed surface of the polysilicon layer 5, and the surface of the epitaxial layer 2 away from the substrate 1. The Schottky metal 8 forms a Schottky contact with the epitaxial layer 2 and an ohmic contact with the polysilicon layer 5. The anode metal 9 is located on the upper surface of the epitaxial layer 2 covered by the Schottky metal 8 and in the V-shaped opening region 32. The cathode metal 10 is located on the surface of the substrate 1 away from the epitaxial layer 2.

[0021] Specifically, the aforementioned trench Schottky diode cell structure includes a substrate 1 and an epitaxial layer 2 located on the substrate 1. The epitaxial layer 2 includes a trench structure 3 extending downward from the upper surface of the epitaxial layer 2. In this embodiment, the trench structure 3 consists of a deep trench region 31 and a V-shaped opening region 32. The V-shaped opening region 32 is located above the deep trench region 31, with its bottom connected to the top of the deep trench region 31 and its upper end flush with the upper surface of the epitaxial layer 2. The depth of the trench structure 3 is 2~3μm, the depth of the V-shaped opening region 32 is 1μm, and the angle between the sidewall of the V-shaped opening region 32 and the first direction is 30~45°, where the first direction is perpendicular to the plane of the substrate 1. A gate oxide layer 4 is deposited on the inner surface of the deep trench region 31 (including the sidewalls and bottom of the deep trench region 31), and a polysilicon layer 5 fills the deep trench region 31 and covers the gate oxide layer 4. It should be noted that the exposed surface of the polysilicon layer 5 (i.e., the...) Figure 2 The upper surface (as shown in the image) is flush with the bottom of the V-shaped opening region 32.

[0022] Furthermore, the Pbody region 6 is formed on the sidewall of the V-shaped opening region 32. The deep level recombination center 7 shares the sidewall region with the Pbody region 6 and can be formed by diffusion of platinum metal. Therefore, the deep level recombination center 7 is actually more biased towards the interior of the silicon mass. Schottky metal 8 is deposited on the inner surface of the sidewall of the V-shaped opening region 32, the exposed surface of the polysilicon layer 5 (i.e., the top of the polysilicon in the deep trench region 31), and the surface of the epitaxial layer 2 away from the substrate 1 (i.e., the upper surface of the epitaxial layer 2), forming a Schottky contact with the epitaxial layer 2 and an ohmic contact with the polysilicon layer 5. It should be understood that this embodiment forms a closed-loop protection system of "capture-transport-recombination" through the deep-level recombination center 7 and the trench structure 3. Specifically, under reverse bias conditions, the trench electric field is a gradient force field radiating outward from the trench with the interior of the trench as the low potential center, and a strong electric field focusing area is formed at the bottom corner. When a single particle, such as a space heavy ion or proton, is incident on the device, the direction of hole motion is completely determined by the direction of the electric field. The direction of the force in the electric field is consistent with the direction of the electric field, i.e., the V-shaped opening adopted in this embodiment. The shape design of the opening region combined with the deep trench allows the electric field on the sidewall of the trench structure 3 to "drive" holes toward the distribution region of the deep-level recombination center 7 (i.e., the V-shaped opening sidewall). The captured holes and free electrons complete non-radiative recombination through the deep-level recombination center 7, and the energy is dissipated in the form of lattice vibration, avoiding charge accumulation. At the same time, the Schottky anode rapidly collects free electrons, and the deep-level recombination center 7 efficiently captures holes. The two act on the two ends of the electron and hole pairs, respectively, to achieve "bidirectional rapid removal" of charge carriers.

[0023] In addition, the trench Schottky diode cell structure that resists single-event effects also includes an anode metal 9 and a cathode metal 10. The anode metal 9 is located on top of the Schottky metal 8, covering the entire upper surface of the epitaxial layer 2 and filling the V-shaped opening region 32. The cathode metal 10 is located on the side surface of the substrate 1 away from the epitaxial layer 2.

[0024] Optionally, the substrate 1 is a heavily doped N-type Si substrate 1 with a thickness of 715~735μm and a resistivity of 0.002~0.006Ω·cm, where Ω·cm represents the resistance of a conductor with a length of 1 cm and a cross-sectional area of ​​1 square centimeter, i.e., the resistance of the material per unit length and per unit cross-section.

[0025] Figure 4 This is a flowchart illustrating the method for fabricating a trench Schottky diode cell structure resistant to single-event effects provided in this embodiment of the invention. Figures 5-13 This is a schematic diagram illustrating the fabrication process of the trench Schottky diode cell structure resistant to single-event effects provided in this embodiment of the invention. Please refer to... Figure 2 as well as Figures 4-13The present invention also provides a method for fabricating a trench Schottky diode cell structure resistant to single-event effects, which is used to fabricate the above-mentioned trench Schottky diode cell structure resistant to single-event effects. The method includes: S1. Provide a substrate 1, and grow an epitaxial layer 2 on one side surface of the substrate 1.

[0026] like Figure 5 As shown, in step S1, a silicon substrate 1 is first selected, and then an epitaxial layer 2 with a certain doping concentration is grown on the upper surface of the substrate 1. For example, the resistivity of the epitaxial layer 2 is 0.1~5Ω·cm and the thickness is 3~30μm. Of course, the specific doping concentration and thickness can be determined according to the electrical properties of the required device.

[0027] S2. A trench structure 3 is formed in the epitaxial layer 2. The trench structure 3 includes a deep trench region 31 and a V-shaped opening region 32 above the deep trench region 31.

[0028] like Figures 6-9 As shown, in this embodiment, step S2 includes: S21. A silicon dioxide layer is deposited on the surface of the epitaxial layer 2 away from the substrate 1 as a hard mask. The thickness of the silicon dioxide layer is 4000-6000 Å.

[0029] S22. A photoresist pattern is formed on the surface of the silicon dioxide layer, and the photoresist pattern is transferred to the silicon dioxide layer by etching.

[0030] S23. Using a patterned silicon dioxide layer as a mask, a rectangular deep trench region 31 is formed in the epitaxial layer 2 by dry etching.

[0031] In steps S22-S23, after spin-coating photoresist on the upper surface of the sample, exposure and development are performed using a mask to obtain a trench etching window. First, a trench etching is performed to form a nearly rectangular deep trench region 31 with a width of 0.5-1 μm and a depth of 2-3 μm.

[0032] S24. By adjusting the etching selectivity, the upper half of the deep trench region 31 is etched into a V-shaped opening region 32.

[0033] In this step, the etching trench angle is adjusted by adjusting the etching selectivity ratio, and a V-shaped opening region 32 is formed in the upper half of the deep trench region 31. For example, the width of the V-shaped opening region 32 is 1~2μm, the depth is 1μm, and the angle between the sidewall of the V-shaped opening region 32 and the first direction is 30-45°. The first direction is defined as the direction perpendicular to the plane where the substrate 1 is located.

[0034] S25. The bottom of the deep trench region 31 is rounded by wet isotropic etching to form an arc-shaped sidewall.

[0035] Specifically, a bottom arc-shaped sidewall is formed by wet etching, followed by the growth of a 500 Å thick sacrificial oxide layer, which is then removed to repair the lattice damage caused by the etching, resulting in a smooth arc-shaped sidewall. It should be understood that this embodiment, by increasing the bottom curvature radius of the trench structure, can more effectively disperse the bottom electric field, while simultaneously using a gate oxide layer to improve the breakdown voltage.

[0036] S3. Deposit a gate oxide layer 4 on the inner surface of the deep trench region 31, and fill the deep trench region 31 with a polysilicon layer 5.

[0037] Please see Figure 10 In step S3, after a gate oxide layer 4 with a thickness of 1000~3000 Å is grown on the inner surface of the trench structure 3 by thermal oxidation, a polysilicon layer 5 with a thickness of 8000~10000 Å is deposited in the trench structure 3. Then, the gate oxide layer 4 and the polysilicon layer 5 are etched back to the bottom of the V-shaped opening region 32. The thickness of the gate oxide layer 4 and the polysilicon layer 5 after etching back is 1 μm. Finally, sacrificial oxidation and removal are performed.

[0038] S4. A Pbody region 6 is formed on the sidewall of the V-shaped opening region 32.

[0039] Specifically, photoresist is spin-coated onto the upper surface of the sample, and exposure and development are performed using a mask to obtain a P-type ion implantation window. Then, implantation is performed on the sidewall of the V-shaped opening region 32 to form... Figure 11 Pbody region 6 is shown. During the above process, the energy was 40–120 keV, and the injection dose was 1 × 10⁶. 12 ~9×10 13 ion·cm -2 .

[0040] By designing the Pbody region 6 in the V-shaped opening region 32, the uneven distribution of the reverse electric field caused by insufficient depletion during the reverse process due to the large distance between the trenches and the middle region of the trenches is avoided, which leads to premature breakdown.

[0041] S5. A deep-level recombination center 7 is formed on the sidewall of the V-shaped opening region 32.

[0042] Please see Figure 12 In step S5, platinum is sputtered onto the sidewalls of the V-shaped opening region 32, the exposed surface of the polysilicon layer 5, and the surface of the epitaxial layer 2 away from the substrate 1, and then subjected to high-temperature annealing to allow platinum atoms to diffuse and form deep-level recombination centers 7. After forming deep-level recombination centers 7 on the sidewalls of the V-shaped opening region 32, the undiffused platinum can be etched using aqua regia, and the platinum outside the sidewalls of the V-shaped opening region 32 can be removed by photolithography and etching.

[0043] Specifically, heavy metal platinum is sputtered onto the surface of a silicon wafer, followed by high-temperature annealing. The platinum thickness is 300 Å, the annealing temperature is 750~850℃, and the time is 10~20 min. Next, since platinum has a high work function, leaving it in the non-trap area will greatly increase the forward conduction voltage. Therefore, aqua regia etching is required to remove the remaining platinum. Then, photoresist is spin-coated onto the sample surface, and exposure and development are performed using a mask to form an etching window. The platinum silicon layer outside the sidewalls of the V-shaped opening region 32 is etched away. S6. Schottky metal 8 is deposited on the inner surface of the V-shaped opening region 32, the exposed surface of the polysilicon layer 5, and the surface of the epitaxial layer 2 away from the substrate 1, such as... Figure 13 As shown, the Schottky metal 8 is Ti with a thickness of 300~1000 Å, so that the Schottky metal 8 forms a Schottky contact with the epitaxial layer 2 and an ohmic contact with the polycrystalline silicon layer 5.

[0044] S7. An anode metal 9, such as Al, with a thickness of 4-6 μm is deposited on the surface of the epitaxial layer 2, and a cathode metal 10, such as Ti / Ni / Ag, with a thickness of 5-10 μm is deposited on the surface of the substrate 1 away from the epitaxial layer 2, finally obtaining... Figure 2 The shown is a trench Schottky diode cell structure resistant to single-event effects.

[0045] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows: This invention provides a trench Schottky diode cell structure and its fabrication method that resist single-event effects. In this cell structure, the trench structure formed in the epitaxial layer consists of a deep trench region and a V-shaped opening region above it. The Pbody region and deep level recombination centers are formed on the sidewalls of the V-shaped opening region. This invention forms a closed-loop protection of "capture-transport-recombination" with the trench structure through the deep level recombination centers. Under reverse bias conditions, the deep level recombination centers can efficiently capture holes when single-event effects occur and eliminate charge accumulation through non-radiative recombination, so that the instantaneous charge generated by single particles is quickly cleared, thereby preventing avalanche breakdown or latch-up failure caused by charge accumulation.

[0046] In the description of this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0047] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A trench Schottky diode cell structure resistant to single-event effects, characterized in that, include: Substrate and an epitaxial layer located on one side surface of the substrate; The trench structure formed in the epitaxial layer includes a deep trench region and a V-shaped opening region above the deep trench region. A gate oxide layer is deposited on the inner surface of the deep trench region and a polysilicon layer covering the gate oxide layer is filled thereon. The top of the polysilicon layer is flush with the bottom of the V-shaped opening region. The Pbody region is formed on the sidewall of the V-shaped opening region; Deep-level recombination centers formed on the sidewalls of the V-shaped opening region are used to capture holes generated by the single-particle effect. Anode metal; Schottky metal is deposited on the inner surface of the V-shaped opening region, the exposed surface of the polysilicon layer, and the surface of the epitaxial layer away from the substrate. The Schottky metal forms a Schottky contact with the epitaxial layer and an ohmic contact with the polysilicon layer. The anode metal is located on the upper surface of the epitaxial layer covered by the Schottky metal and in the V-shaped opening region. The cathode metal located on the surface of the substrate away from the epitaxial layer.

2. The trench Schottky diode cell structure resistant to single-event effects according to claim 1, characterized in that, The substrate is a heavily doped N-type Si substrate with a thickness of 715~735μm and a resistivity of 0.002~0.006Ω·cm.

3. The trench Schottky diode cell structure resistant to single-event effects according to claim 1, characterized in that, The trench structure has a depth of 2~3μm, the V-shaped opening region has a depth of 1μm, and the angle between the sidewall of the V-shaped opening region and the first direction is 30~45°, wherein the first direction is the direction perpendicular to the plane of the substrate.

4. A method for fabricating a trench Schottky diode cell structure resistant to single-event effects, characterized in that, Used to fabricate a trench Schottky diode cell structure resistant to single-event effects as described in any one of claims 1 to 3; The method includes: A substrate is provided, and an epitaxial layer is grown on one side surface of the substrate; A trench structure is formed in the epitaxial layer, the trench structure including a deep trench region and a V-shaped opening region above the deep trench region; A gate oxide layer is deposited on the inner surface of the deep trench region, and a polysilicon layer is filled in the deep trench region; A Pbody region is formed on the sidewall of the V-shaped opening region; Deep-level recombination centers are formed on the sidewalls of the V-shaped opening region; Schottky metal is deposited on the inner surface of the V-shaped opening region, the exposed surface of the polysilicon layer, and the surface of the epitaxial layer away from the substrate, so that the Schottky metal forms a Schottky contact with the epitaxial layer and an ohmic contact with the polysilicon layer. An anode metal is deposited on the upper surface of the epitaxial layer, and a cathode metal is deposited on the surface of the substrate on the side away from the epitaxial layer.

5. The method for fabricating the trench Schottky diode cell structure resistant to single-event effects according to claim 4, characterized in that, The step of forming a trench structure within the epitaxial layer includes: A silicon dioxide layer is deposited on the surface of the epitaxial layer away from the substrate as a hard mask. A photoresist pattern is formed on the surface of the silicon dioxide layer, and the photoresist pattern is transferred to the silicon dioxide layer by etching. Using a patterned silicon dioxide layer as a mask, a rectangular deep trench region is formed in the epitaxial layer by dry etching; By adjusting the etching selectivity, the upper half of the deep trench region is etched into a V-shaped opening region; The bottom of the deep trench region is rounded by wet isotropic etching to form an arc-shaped sidewall.

6. The method for fabricating the trench Schottky diode cell structure resistant to single-event effects according to claim 4, characterized in that, The steps of depositing a gate oxide layer on the inner surface of the deep trench region and filling the deep trench region with a polysilicon layer include: After growing a gate oxide layer on the inner surface of the trench structure by thermal oxidation, a polycrystalline silicon layer is deposited inside the trench structure. The gate oxide layer and the polysilicon layer are etched back to the bottom of the V-shaped opening region.

7. The method for fabricating the trench Schottky diode cell structure resistant to single-event effects according to claim 4, characterized in that, The step of forming deep-level recombination centers on the sidewall of the V-shaped opening region includes: Platinum is sputtered onto the sidewalls of the V-shaped opening region, the exposed surface of the polycrystalline silicon layer, and the surface of the epitaxial layer away from the substrate, and then subjected to high-temperature annealing to allow platinum atoms to diffuse and form deep-level recombination centers.

8. The method for fabricating the trench Schottky diode cell structure resistant to single-event effects according to claim 7, characterized in that, Following the step of forming deep-level recombination centers on the sidewalls of the V-shaped opening region, the method further includes: Undiffused platinum was etched using aqua regia, and platinum outside the sidewalls of the V-shaped opening region was removed by photolithography and etching.

9. The method for fabricating the trench Schottky diode cell structure resistant to single-event effects according to claim 4, characterized in that, The Schottky metal is Ti, with a thickness of 300-1000 Å.

10. The method for fabricating the trench Schottky diode cell structure resistant to single-event effects according to claim 9, characterized in that, The anode metal is Al, with a thickness of 4~6 μm; The cathode metal is Ti / Ni / Ag with a thickness of 5~10μm.

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