Image sensor and method of manufacturing the same

Abstract

The application discloses an image sensor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The image sensor comprises a substrate, a photoelectric sensing area and a logic area, the substrate comprises a front surface and a back surface arranged oppositely, a plurality of photodiodes are arranged at the photoelectric sensing area at intervals from the front surface of the substrate, a plurality of semiconductor devices are arranged at the logic area at intervals from the front surface of the substrate, at least one back surface transistor is arranged at the logic area from the back surface of the substrate, the back surface transistor comprises a pair of doped areas arranged at intervals in the substrate, a plurality of deep trench isolation structures are arranged at least on both sides of the photodiodes and the back surface transistor from the back surface of the substrate, and a plurality of metal grids are arranged at least on the deep trench isolation structures on both sides of the photodiodes and on the substrate between the pair of doped areas. The image sensor and the manufacturing method thereof provided by the application meet the requirement of high complexity of the logic area circuit, improve the flexibility of chip design, and reduce the occupied area of the logic area.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to an image sensor and its manufacturing method. Background Technology

[0002] In semiconductor devices, CMOS image sensors (Complementary Metal Oxide Semiconductor Image Sensors, CIS) can convert light signals into electrical signals and have advantages such as high integration, low power supply voltage, and low technical barriers. They are widely used in fields such as photography and videography, security systems, smartphones, fax machines, scanners, and medical electronics. Among these, back-illuminated CMOS image sensors are widely used due to their excellent imaging performance. The manufacturing process of back-illuminated CMOS image sensors generally includes forming photosensitive / logic region transistors, metal interconnects, back-side thinning, dielectric layers, metal grids, and pad fabrication. In the photosensitive and logic regions, transistors are located on the front side of the wafer, limiting chip design flexibility. Furthermore, when the logic region circuitry is complex, it occupies area in the photosensitive region or increases the die size, thereby reducing the fill factor of the image sensor or decreasing the effective number of dies produced on the wafer. Summary of the Invention

[0003] The purpose of this invention is to provide an image sensor and its manufacturing method. The image sensor and its manufacturing method provided by this invention can meet the requirements of high logic area circuit complexity, improve chip design flexibility, avoid the logic area occupying the photoelectric sensing area, reduce the die size, thereby improving the fill factor of the image sensor, increasing the effective number of dies produced on the wafer, and increasing production capacity. At the same time, the isolation structure serves as an isolation structure between adjacent back transistors, and the isolation structure does not require a separate process, thereby simplifying the manufacturing process and reducing production costs.

[0004] To address the aforementioned technical problems, the present invention provides an image sensor, comprising:

[0005] A substrate, the substrate including a photosensitive area and a logic area, the substrate including a front side and a back side disposed opposite to each other;

[0006] Multiple photodiodes are spaced apart on the front side of the substrate in the photosensitive area;

[0007] Multiple semiconductor devices are spaced apart on the front side of the substrate in the logic region;

[0008] At least one back-side transistor is disposed in the logic region by the back side of the substrate, the back-side transistor comprising a pair of doped regions spaced apart within the substrate;

[0009] Multiple deep trench isolation structures are disposed on at least both sides of the photodiode and the back transistor from the back side of the substrate;

[0010] Multiple metal grids are disposed at least on the deep trench isolation structure on both sides of the photodiode and on the substrate between the pair of doped regions.

[0011] In one embodiment of the present invention, the substrate is a silicon wafer with a homogeneous epitaxial layer, the epitaxial layer and the silicon wafer have the same doping type, and the doping type of the doped region is opposite to that of the substrate.

[0012] In one embodiment of the present invention, a dielectric layer is disposed between the metal grid and the substrate. The dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer stacked together. The first dielectric layer and the second dielectric layer are silicon oxide layers, and the material of the second dielectric layer is a high dielectric constant material.

[0013] In one embodiment of the present invention, an insulating layer is provided at least on the doped region, and the thickness of the insulating layer is equal to the thickness of the dielectric layer.

[0014] In one embodiment of the present invention, a first connection structure is provided on the back side of the substrate on the side of the photoelectric sensing area away from the logic area, and the first connection structure is in communication with the substrate.

[0015] The present invention also provides a method for manufacturing an image sensor, comprising:

[0016] A substrate is provided, the substrate including a photosensitive region and a logic region, the substrate including a front side and a back side disposed opposite to each other;

[0017] A plurality of photodiodes are formed at intervals on the front side of the substrate in the photosensitive area.

[0018] A plurality of semiconductor devices are formed at intervals in the logic region on the front side of the substrate;

[0019] At least one back-side transistor is formed in the logic region from the back side of the substrate, the back-side transistor comprising a pair of doped regions spaced apart within the substrate;

[0020] Multiple deep trench isolation structures are formed on the back side of the substrate, and the deep trench isolation structures are disposed on at least both sides of the photodiode and the back-side transistor;

[0021] A metal grid is formed on at least the deep trench isolation structure on both sides of the photodiode and on the substrate between the pair of doped regions.

[0022] In one embodiment of the present invention, the manufacturing method further includes:

[0023] After fabricating the photodiode and the semiconductor device on the front side of the substrate, a multilayer metal wiring layer is fabricated.

[0024] After the metal wiring layer is bonded to the carrier board, it forms a structural layer;

[0025] The substrate is flipped over, and thinning is performed on the back side of the substrate to form a sacrificial oxide layer on one side of the substrate opposite to the structural layer;

[0026] A first photoresist layer is formed on the sacrificial oxide layer, and at least two first openings are formed on the first photoresist layer, wherein the first openings are located in the logic region;

[0027] Using the first photoresist as a mask, an ion implantation process is performed on the substrate within the first opening to form at least one pair of doped regions.

[0028] In one embodiment of the present invention, the steps for forming the deep trench isolation structure include:

[0029] After the doped region is formed, a second photoresist layer is reformed on the sacrificial oxide layer. A plurality of second openings are formed on the second photoresist layer. The second openings are at least disposed between adjacent photodiodes and on both sides of a pair of doped regions.

[0030] Using the second photoresist layer as a mask, etching is performed in the direction of the structural layer to remove the sacrificial oxide layer exposed by the second opening and part of the substrate, forming a deep trench.

[0031] An insulating material is deposited in the deep trench and on the sacrificial oxide layer. A portion of the insulating material and the sacrificial oxide layer is removed by planarization until the insulating material is flush with the substrates on both sides, forming a deep trench isolation structure.

[0032] In one embodiment of the present invention, the manufacturing method further includes:

[0033] A dielectric layer is formed on the substrate and the deep trench isolation structure;

[0034] The dielectric layer is etched to form a plurality of recesses, the recesses being at least located on the doped region, on the side of the photodiode away from the logic region, and on the side of the doped region away from the photosensitive region;

[0035] An insulating material is deposited within the recess to form an insulating layer, which is flush with the dielectric layer.

[0036] In one embodiment of the present invention, the manufacturing method further includes:

[0037] A metal grid layer and a hard mask layer are formed on the insulating layer and the dielectric layer;

[0038] The hard mask layer and the metal grid layer are etched down to the dielectric layer and the insulating layer to form a plurality of the metal grids;

[0039] A dielectric layer is filled between the metal grids to flatten the dielectric layer;

[0040] The dielectric layer is etched to form multiple openings;

[0041] Conductive material is deposited within the opening to form multiple connection structures, which are connected to at least the doped region and the metal grid between a pair of doped regions.

[0042] In summary, this invention provides an image sensor and its fabrication method. The unexpected technical advantage of this application is that by forming semiconductor devices on both sides of the substrate in the logic region, it meets the requirements of high logic region circuit complexity, improves chip design flexibility, avoids the logic region occupying the photosensitive area, reduces die size, thereby improving the fill factor of the image sensor and increasing the effective number of dies produced on the wafer, thus increasing production capacity. Furthermore, in the fabrication process, a dielectric layer and a metal grid are used as the gate dielectric layer and gate, respectively, eliminating the need for separate gate processes and photomasks. A deep trench isolation structure is used as the isolation structure between adjacent back-side transistors, eliminating the need for a separate isolation structure process, thereby simplifying the fabrication process and reducing production costs. By selecting a substrate doped between doped regions as the channel region for the subsequently formed back-side transistors, the process of forming the well region can be reduced, and even the sidewall structure process can be omitted, thereby improving fabrication efficiency. By forming a dielectric layer and a metal grid with a high dielectric constant material, back-side transistors with metal gates can be formed, enabling the image sensor obtained in this application to advanced processes with faster response speeds. An air gap is formed within the deep trench isolation structure, improving the isolation strength between photodiodes, avoiding interference from parasitic light pollution, and enhancing the isolation effect of the formed deep trench isolation structure. Back-side transistor wiring connections are completed on the back side of the substrate, and a third pad is formed within the trench for direct contact with the metal layer, achieving back-side electrical interconnection, reducing space occupation, and optimizing the fill factor.

[0043] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0044] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram of the substrate and structural layer in one embodiment of the present invention.

[0046] Figure 2 This is a schematic diagram of a substrate thinning and forming a sacrificial oxide layer and a first photoresist layer on one side of the substrate relative to the structural layer, according to an embodiment of the present invention.

[0047] Figure 3 This is a schematic diagram of the formation of the doped region and the second photoresist layer in one embodiment of the present invention.

[0048] Figure 4 This is a schematic diagram of a deep trench isolation structure formed in one embodiment of the present invention.

[0049] Figure 5 This is a schematic diagram of the formation of a dielectric layer in one embodiment of the present invention.

[0050] Figure 6 This is a schematic diagram of the dielectric layer after etching in one embodiment of the present invention.

[0051] Figure 7 This is a schematic diagram of the formation of an insulating layer in one embodiment of the present invention.

[0052] Figure 8 This is a schematic diagram of the formation of a metal grid layer and a hard mask layer in one embodiment of the present invention.

[0053] Figure 9 This is a schematic diagram of forming a metal grid in one embodiment of the present invention.

[0054] Figure 10 This is a schematic diagram of the formation of a dielectric layer in one embodiment of the present invention.

[0055] Figure 11 This is a schematic diagram of a connection structure formed in one embodiment of the present invention.

[0056] Figure 12 This is a schematic diagram of the groove formed in one embodiment of the present invention.

[0057] Figure 13 This is a schematic diagram of an image sensor according to one embodiment of the present invention.

[0058] Label Explanation:

[0059] 100. Substrate; 101. Photosensitive area; 102. Logic area; 111. First isolation structure; 112. Second isolation structure; 12. Photodiode; 13. Transfer gate; 14. Semiconductor device; 15. Conductive plug; 16. Metal layer; 200. Structural layer; 110. Sacrificial oxide layer; 120. First photoresist layer; 121. First opening; 130. Doped region; 140. Second photoresist layer; 141. Second opening; 150. Deep trench isolation structure; 151. Air gap; 160, Dielectric layer; 161, First dielectric layer; 162, Second dielectric layer; 163, Third dielectric layer; 170, Insulating layer; 171, Recess; 180, Metal grid layer; 181, Metal grid; 190, Hard mask layer; 201, Back transistor; 210, Dielectric layer; 220, Connection structure; 221, First connection structure; 222, Second connection structure; 223, Third connection structure; 240, Groove; 251, First pad; 252, Second pad; 253, Third pad. Detailed Implementation

[0060] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0061] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0062] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0063] Please see Figure 13As shown, the present invention provides an image sensor, including a substrate 100, which includes a photosensitive region 101 and a logic region 102. The substrate 100 includes a front side and a back side disposed opposite to each other. A plurality of photodiodes 12 are disposed at intervals in the photosensitive region 101 on the front side of the substrate 100. A plurality of semiconductor devices 14 are disposed at intervals in the logic region 102 on the front side of the substrate 100. At least one back transistor is disposed in the logic region 102 on the back side of the substrate 100. The back transistor includes a pair of doped regions 130 disposed at intervals in the substrate 100. A plurality of deep trench isolation structures 150 are disposed at least on both sides of the photodiodes 12 and the back transistor on the back side of the substrate 100. A plurality of metal grids 181 are disposed at least on the deep trench isolation structures 150 on both sides of the photodiodes 12 and on the substrate 100 between the pair of doped regions 130. Semiconductor devices are formed on both sides of the substrate of the logic region to meet the requirements of high circuit complexity in the logic region, improve chip design flexibility, avoid the logic region occupying the area of ​​the photoelectric sensing region, reduce the die size, thereby improving the fill factor of the image sensor and increasing the number of effective dies produced on the wafer, thus increasing production capacity.

[0064] Please see Figure 1 As shown, in one embodiment of the present invention, a back-side illuminated (BSI) CMOS image sensor is used as an example to illustrate the structure and fabrication process of the image sensor. First, a substrate 100 is provided. The substrate 100 can be any suitable semiconductor material, specifically, for example, silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon-germanium (GeSi), sapphire, or a silicon wafer, etc., and also includes a stacked structure composed of these semiconductors, or silicon-on-insulator, silicon-on-insulator stacked, silicon-germanium-on-insulator, silicon-germanium-on-insulator, and germanium-on-insulator, etc., which can be selected according to the fabrication requirements of the image sensor. In this embodiment, the substrate 100 is, for example, a silicon wafer with an epitaxial structure (not shown in the figure), and the epitaxial structure is, for example, a homogeneous epitaxial layer, and the epitaxial structure and the silicon wafer are, for example, silicon materials of the same doping type. In other embodiments, the substrate 100 can be other semiconductor materials, and can be a doped or undoped semiconductor substrate.

[0065] Please see Figure 1As shown, in one embodiment of the present invention, the substrate 100 includes a front side and a back side disposed opposite to each other. A plurality of photodiodes 12 and a plurality of semiconductor devices are formed on the front side of the substrate 100. The substrate 100 includes a photosensitive region 101 and a logic region 102. The plurality of photodiodes 12 are spaced apart in the photosensitive region 101. A transfer gate 13 is disposed on the substrate 100 on one side of the photodiodes 12 to transfer photogenerated electrons within the photodiodes 12. A plurality of semiconductor devices 14, such as row drivers, column drivers, timing control logic, and AD converters, are disposed in the logic region 102. The semiconductor devices 14 may be, for example, MOS transistors. A first isolation structure 111 is disposed on the side of the logic region 102 away from the photosensitive region 101. A second isolation structure 112 is disposed between adjacent photodiodes 12, adjacent semiconductor devices 14, and between photodiodes 12 and semiconductor devices 14, to reduce mutual interference between the devices. During the operation of the CMOS image sensor, an object is focused onto the pixel array through an imaging lens. Each photodiode 12 converts light intensity into an electrical signal. The control circuit, electrically connected to the photodiode 12, selects the pixel to be used and reads the electrical signal from the pixel. After amplification and noise reduction processing, the electrical signal is output. The semiconductor devices in the logic area 102 are used to control reset, integration, and readout.

[0066] Please see Figure 1 As shown, in one embodiment of the present invention, after forming the photodiode 12 and the semiconductor device, a multilayer metal wiring layer is formed on the front side of the substrate 100. Only one metal layer 16 is shown in this application as an example, and does not represent the actual application of a single metal layer. The multiple metal layers 16 are connected to the semiconductor device via conductive plugs 15. The metal layers 16 are then bonded to a carrier plate to form a structural layer 200, which includes gates of multiple semiconductor devices, the multilayer metal wiring layer, and the carrier plate. The carrier plate can be, for example, a rigid packaging substrate, a flexible packaging substrate, or a ceramic packaging substrate, selected according to the manufacturing requirements.

[0067] Please see Figures 1 to 2As shown, in one embodiment of the present invention, after forming the structural layer 200, the substrate 100 is flipped, and thinning is performed on the back side of the substrate 100, that is, on the side of the substrate 100 opposite to the structural layer 200, the substrate 100 is thinned, and the remaining thickness of the substrate 100 is selected according to the fabrication requirements. In this embodiment, the thickness of the thinned substrate 100 meets the requirement of forming a transistor on the back side of the logic region 102. After thinning, a sacrificial oxide layer 110 is formed on the side of the substrate 100 opposite to the structural layer 200. The sacrificial oxide layer 110 is formed, for example, by a low-temperature process such as low-temperature plasma oxidation, to ensure the performance stability of the structural layer 200. Specifically, the substrate 100 is placed in a low-temperature plasma oxidation apparatus, and an oxygen-containing gas, such as a mixture of oxygen (O2) and hydrogen (H2), is introduced into the apparatus. At a temperature of, for example, 350°C to 450°C, the oxygen dissociates into oxygen plasma. The oxygen plasma reacts with the substrate 100 to form a sacrificial oxide layer 110, and the thickness of the sacrificial oxide layer 110 is, for example, 15 Å to 30 Å, or, for example, 20 Å. By dissociating oxygen into oxygen plasma, a sacrificial oxide layer 110 can be generated on the substrate surface at a low temperature. Furthermore, the sacrificial oxide layer 110 generated by low-temperature plasma oxidation has a dense structure, which is beneficial for subsequent operations.

[0068] Please see Figure 2 As shown, in one embodiment of the present invention, after forming the sacrificial oxide layer 110, a first photoresist layer 120 is formed on the sacrificial oxide layer 110, for example, by spin coating. The first photoresist layer 120 is exposed and developed to form at least two first openings 121 to locate the positions of the doped regions. The first openings 121 are located on the logic region 102, and are arranged in pairs to form the source and drain doped regions of the semiconductor device. The distance between the pairs of first openings 121 is set according to the gate size of the subsequent semiconductor device. This application does not limit the number of pairs of first openings 121, but sets them according to the number of semiconductor devices to be configured.

[0069] Please see Figure 2As shown, in one embodiment of the present invention, using a first photoresist layer 120 as a mask and a sacrificial oxide layer 110 as an ion implantation buffer layer, an ion implantation process is performed on the substrate 100 exposed by the first opening 121 to form at least one pair of doped regions 130. In this embodiment, two pairs of doped regions 130 are used as an example. In this embodiment, the implanted ions are, for example, N-type ions or P-type ions. N-type ions are, for example, phosphorus (P), arsenic (As), or antimony (Sb), etc., and P-type ions are, for example, boron (B), gallium (Ga), or indium (In), etc., which are opposite to the doping type of the substrate 100. Furthermore, the ion types implanted in a pair of doped regions 130 are the same, and the ion types implanted in different pairs of doped regions 130 are also the same. In other embodiments, the ion types implanted in different pairs of doped regions 130 may also be different. In this case, the substrate 100 between the doped regions 130 with the same doping type as the substrate 100 needs to be doped to form a well region with the opposite doping type to the substrate. Specifically, after forming the doped regions 130, a photoresist layer is re-formed for well region doping, which will not be elaborated here. This application does not limit the doping depth and doping concentration of the doped regions 130, etc., and the specific selection is based on the fabrication requirements. This embodiment, by selecting the substrate 100 between the doped regions 130 as the channel region of the subsequently formed back-side transistor, can reduce the process of forming the well region, and may even omit the sidewall structure process, thereby improving fabrication efficiency.

[0070] Please see Figures 2 to 3 As shown, in one embodiment of the present invention, after forming the doped region 130, the first photoresist layer 120 is removed, for example, by wet etching or ashing. A second photoresist layer 140 is then formed on one side of the substrate 100 relative to the structural layer 200. The second photoresist layer 140 is formed on the substrate 100, for example, by spin coating. The second photoresist layer 140 is then exposed and developed, and a plurality of second openings 141 are formed on the second photoresist layer 140. The second openings 141 are disposed between adjacent photodiodes and on both sides of a pair of doped regions 130 to locate the position of the deep trench isolation structure.

[0071] Please see Figures 3 to 4As shown, in one embodiment of the present invention, after the second opening 141 is formed, etching is performed in the direction of the structural layer 200 using the second photoresist layer 140 as a mask to remove the sacrificial oxide layer 110 and part of the substrate 100 exposed by the second opening 141, forming a deep trench (not shown in the figure). In this embodiment, for example, dry etching is selected to form the deep trench, and the etching gas includes, for example, one or a mixture of several of chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), or hydrogen bromide (HBr), or a combination of them and oxygen (O2). This application does not limit the depth of the deep trench. In one embodiment of this application, the depth of the deep trench within the substrate 100 is, for example, 1 μm to 1.5 μm.

[0072] Please see Figure 4 As shown, in one embodiment of the present invention, after forming a deep trench, the second photoresist layer 140 is removed by wet etching or ashing, and then an insulating material is deposited in the deep trench and on the sacrificial oxide layer 110. The insulating material is, for example, one or a multilayer structure of silicon oxide or a high-k dielectric material. The high-k dielectric material is, for example, one or a mixture of several of the following: aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), zirconium oxynitride (ZrON), hafnium silicate (HfSiO), hafnium oxynitride (HfSiON), or aluminum hafnium oxide (HfAlO). Insulating materials are deposited using methods such as plasma-enhanced atomic layer deposition (PEALD), high-density plasma chemical vapor deposition (HDP-CVD), or high-aspect-ratio process chemical vapor deposition (HARP-CVD). During the deposition process, the deposition is stopped once the insulating material in the deep trench protrudes from the surface of the substrate 100.

[0073] Please see Figures 3 to 4As shown, in one embodiment of the present invention, after depositing the insulating material, the insulating material is planarized, for example, by using a chemical mechanical polishing (CMP) process to planarize part of the insulating material and the sacrificial oxide layer 110 until the insulating material is flush with the substrates 100 on both sides, forming a deep trench isolation structure 150. During the deposition of the insulating material, for example, an air gap 151 is formed within the insulating material, and the top of the air gap 151 is, for example, lower than the surface of the substrate 100. By setting the air gap 151, the isolation strength between photodiodes is improved, interference from parasitic light pollution is avoided, and the isolation effect of the formed deep trench isolation structure is improved. In other embodiments, after the insulating material is deposited, a tempering process can be performed to increase the density and stress of the insulating material. By setting the sacrificial oxide layer, damage to the substrate can be reduced during the formation of the doped region and the deep trench isolation structure.

[0074] Please see Figures 4 to 5 As shown, in one embodiment of the present invention, after forming the deep trench isolation structure 150, a dielectric layer 160 is formed on the substrate 100 and the deep trench isolation structure 150. In this embodiment, starting from the surface of the substrate 100, the dielectric layer 160 includes a first dielectric layer 161, a second dielectric layer 162, and a third dielectric layer 163, etc., stacked sequentially. The first dielectric layer 161 and the third dielectric layer 163 are, for example, silicon oxide layers. The material of the second dielectric layer 162 is, for example, a high dielectric constant material, or, for example, one or a mixture of several of the following: aluminum oxide, tantalum pentoxide, hafnium oxide, hafnium oxynitride, zirconium oxide, zirconium oxynitride, hafnium silicate, hafnium oxynitride, or aluminum hafnium oxide. In this embodiment, the thickness of the first dielectric layer 161 is, for example, 10 Å to 20 Å, the thickness of the second dielectric layer 162 is, for example, 60 Å to 100 Å, and the thickness of the third dielectric layer 163 is, for example, 1600 Å to 2000 Å. This application does not limit the deposition method of the dielectric layer 160; the deposition method is selected according to the material of each layer.

[0075] Please see Figures 5 to 6As shown, in one embodiment of the present invention, after forming the dielectric layer 160, a portion of the dielectric layer 160 is etched down to the substrate 100, forming a plurality of recesses 171 within the dielectric layer 160. Specifically, a patterned photoresist layer (not shown in the figure) is formed on the dielectric layer 160 through processes such as spin coating, exposure, and development, exposing a portion of the dielectric layer 160. Using the patterned photoresist layer as a mask, the exposed dielectric layer 160 is etched using dry etching, wet etching, or a combination of dry and wet etching to form a plurality of recesses 171. The recesses 171 are, for example, located on the doped region 130, on the side of the photodiode 12 away from the logic region 102, and on the side of the doped region 130 away from the photosensitive region 101, and are located on the outer side of the deep trench isolation structure 150. The dielectric layer is etched to isolate different devices.

[0076] Please see Figures 6 to 7 As shown, in one embodiment of the present invention, after forming the recess 171, an insulating material such as silicon oxide is deposited in the recess 171 to form an insulating layer 170. The insulating layer 170 is deposited, for example, by a method such as chemical vapor deposition, and after deposition, a portion of the insulating material is planarized, for example, by a chemical mechanical polishing process, until the insulating material is flush with the dielectric layers 160 on both sides, thus forming the insulating layer 170.

[0077] Please see Figures 7 to 8 As shown, in one embodiment of the present invention, after forming the insulating layer 170, a metal grid layer 180 and a hard mask layer 190 are sequentially formed on the dielectric layer 160 and the insulating layer 170. The metal grid layer 180, for example, extends from the surface of the dielectric layer 160 and the insulating layer 170 and includes stacked layers of materials such as titanium nitride and aluminum. The thickness of each layer is designed according to fabrication requirements. The metal grid layer 180 is deposited, for example, using methods such as atomic layer deposition (ALD) or radio frequency sputtering physical vapor deposition (RFPVD). The hard mask layer 190 is disposed on the metal grid layer 180, and is, for example, titanium nitride, to reduce damage to the metal grid layer 180 during subsequent etching. This application does not limit the thickness of the hard mask layer 190; it is set according to fabrication requirements.

[0078] Please see Figures 8 to 9As shown, in one embodiment of the present invention, after forming the hard mask layer 190, a portion of the hard mask layer 190 and the metal grid layer 180 is etched down to the dielectric layer 160 and the insulating layer 170 to form a plurality of metal grids 181. Specifically, a patterned photoresist layer (not shown in the figure) is formed on the hard mask layer 190 through processes such as spin coating, exposure, and development, exposing a portion of the hard mask layer 190. Using the patterned photoresist layer as a mask, the exposed hard mask layer 190 and the metal grid layer 180 are etched by dry etching, wet etching, or a combination of dry and wet etching to form a plurality of metal grids 181. In this embodiment, the metal grid 181 is located, for example, at least on the deep trench isolation structure 150 on both sides of the photodiode 12 and on the dielectric layer 160 between a pair of doped regions 130. The metal grid 181 on both sides of the photodiode 12 improves anti-reflection and optical crosstalk performance, thereby enhancing imaging quality. The edge of the metal grid 181 between the pair of doped regions 130 is aligned with the edge of the adjacent doped region 130 to serve as the gate of the semiconductor device. Additionally, the metal grid 181 is also disposed on the side of the photodiode 12 away from the logic region 102, the side of the logic region 102 away from the photosensitive region 101, between two adjacent pairs of doped regions 130, and on the deep trench isolation structure 150 within the logic region 102 away from the photosensitive region 101.

[0079] Please see Figure 9 As shown, in one embodiment of the present invention, a back-side transistor 201 includes a pair of doped regions 130 and a metal grid 181 between the pair of doped regions 130. The metal grid 181 serves as the gate of the transistor, the dielectric layer 160 between the metal grid 181 and the substrate 100 serves as the gate dielectric layer, and the pair of doped regions 130 serve as the source and drain doped regions of the transistor, respectively. This allows semiconductor devices to be formed on both sides of the substrate 100 within the logic region 102, meeting the requirements of high logic region circuit complexity, improving chip design flexibility, avoiding the logic region occupying the photosensitive area, reducing die size, thereby improving the fill factor of the image sensor, increasing the effective number of dies produced on the wafer, and increasing production capacity. Furthermore, during the fabrication process, the dielectric layer and metal grid are used as the gate dielectric layer and gate, respectively, eliminating the need for separate gate processes and photomasks. The deep trench isolation structure 150 serves as the isolation structure between adjacent back-side transistors 201, eliminating the need for a separate isolation structure process, thus simplifying the fabrication process and reducing production costs. By forming a dielectric layer and a metal grid with a high dielectric constant, a back-side transistor 201 with a metal gate can be formed, enabling the image sensor obtained in this application to be applied to advanced processes with faster response speed.

[0080] Please see Figures 9 to 10As shown, in one embodiment of the present invention, after forming the metal grid 181, a dielectric layer 210 is filled between the metal grids 181. The dielectric layer 210 is, for example, silicon dioxide or a low-k dielectric material to improve the reliability of the image sensor. The dielectric layer 210 is deposited, for example, using a high aspect ratio process to improve its filling capacity. After forming the dielectric layer 210, a planarization process is performed on the dielectric layer 210, for example, by chemical mechanical polishing to remove a portion of the dielectric layer 210, ensuring that the surface of the dielectric layer 210 is planar and improving the convenience of the metal connection structure. In this embodiment, the remaining thickness of the dielectric layer 210 on the metal grid 181 is, for example, 60 nm to 100 nm. In other embodiments, the remaining thickness of the dielectric layer 210 on the metal grid 181 can be selected according to manufacturing requirements.

[0081] Please see Figures 10 to 11 As shown, in one embodiment of the present invention, after forming the dielectric layer 210, a plurality of openings (not shown) are formed within the dielectric layer 210 to form the connection structure 220. Specifically, a patterned photoresist layer (not shown) is formed on the dielectric layer 210 to locate the openings. Using the patterned photoresist layer as a mask and the substrate 100 or hard mask layer 190 as an etch stop layer, the dielectric layer 210 is etched by dry etching until the substrate 100 and hard mask layer 190 are etched to a stop. The etching gas can be, for example, one or a combination of several gases selected from trifluoromethane, difluoromethane, nitrogen trifluoride, sulfur hexafluoride, or nitrogen, or a mixture of these gases with oxygen. After forming the openings, conductive material is deposited within the openings to form the plurality of connection structures 220. When depositing the conductive material, a barrier layer can be deposited inside the opening first. This barrier layer can be a material with good adhesion, such as tantalum (Ta), titanium (Ti), tantalum nitride (TaN), or titanium nitride (TiN), and its thickness can be, for example, 1 nm to 5 nm. By setting the barrier layer, the adhesion between the conductive material and the sidewalls of the opening is enhanced. Simultaneously, the diffusion of the conductive material into the dielectric layer is reduced, electromigration is decreased, and the electrical performance of the image sensor is improved. The conductive material can be, for example, a low-resistance material such as metallic copper, metallic aluminum, or metallic tungsten. In this embodiment, the conductive material is, for example, metallic copper. The metallic copper is formed, for example, by physical vapor deposition or electroplating, and fills the opening until it covers the dielectric layer 210. Then, the metallic copper is planarized so that it is flush with the dielectric layers 210 on both sides of the opening to form the connection structure 220.

[0082] Please see Figure 11As shown, in one embodiment of the present invention, the connection structure 220 includes a first connection structure 221, a second connection structure 222, and a third connection structure 223. The first connection structure 221 is located on the side of the photosensitive region 101 away from the logic region 102, and penetrates the dielectric layer 210 and the insulating layer 170, connecting to the substrate 100 and the second dielectric layer 162 to ground, so that the second dielectric layer 162 and the substrate 100 are not charged. The second connection structure 222 penetrates the dielectric layer 210 and the insulating layer 170, communicating with the doped region 130 to expose the source and drain of the back transistor 201. The third connection structure 223 penetrates the dielectric layer 210, communicating with the hard mask layer 190 to expose the gate of the back transistor 201, thereby wiring the back transistor 201.

[0083] Please see Figures 11 to 12 As shown, in one embodiment of the present invention, after forming the connection structure 220, a patterned mask layer (not shown in the figure) is formed on the dielectric layer 210 and the connection structure 220 by processes such as spin-coating photoresist, exposure, and development. The patterned mask layer exposes a portion of the dielectric layer 210 on the first isolation structure 111. Using the patterned mask layer as a mask, the dielectric layer 210, insulating layer 170, substrate 100, first isolation structure 111, and structural layer 200 exposed by the patterned mask layer are etched by dry etching, wet etching, or a combination of dry and wet etching to expose the metal layer 16 and form a groove 240 for forming connection pads. After forming the groove 240, the patterned mask layer is removed by wet etching or ashing treatment.

[0084] Please see Figures 12 to 13 As shown, in one embodiment of the present invention, after the groove 240 is formed, conductive material is deposited on the groove 240 and the dielectric layer 210 until the conductive material in the groove 240 exceeds the first isolation structure 111, at which point the deposition stops. The conductive material is, for example, a metallic material such as aluminum, nickel, or copper, and is obtained, for example, by physical vapor deposition. After deposition stops, a portion of the conductive material on the dielectric layer 210 is removed by a planarization process such as chemical mechanical polishing, leaving a predetermined thickness of conductive material to form pads. The conductive material is then etched to retain the conductive material on the connection structure 220 and within the groove 240, thereby forming multiple pads. In this embodiment, a first pad 251 is formed on the first connection structure 221 to ground the substrate 100 and the second dielectric layer 162. A second pad 252 is formed on the second connection structure 222 and the third connection structure 223 to complete the wiring connection of the back transistor 201. A third pad 253 is formed in the groove 240 to directly contact the metal layer 16, thereby realizing electrical interconnection on the back side, reducing the space occupied, and optimizing the fill factor.

[0085] Please see Figure 10As shown, in one embodiment of the present invention, after forming the pads, structures such as filters and microlenses are formed between the metal grids 181 on the photodiode to form the final image sensor chip structure. The fabrication processes for the filters and microlenses can be any fabrication process, and will not be elaborated upon in this application.

[0086] In summary, this invention provides an image sensor and its fabrication method. The unexpected technical advantage of this application is that by forming semiconductor devices on both sides of the substrate in the logic region, it meets the requirements of high logic region circuit complexity, improves chip design flexibility, avoids the logic region occupying the photosensitive area, reduces die size, thereby improving the fill factor of the image sensor and increasing the effective number of dies produced on the wafer, thus increasing production capacity. Furthermore, in the fabrication process, a dielectric layer and a metal grid are used as the gate dielectric layer and gate, respectively, eliminating the need for separate gate processes and photomasks. A deep trench isolation structure is used as the isolation structure between adjacent back-side transistors, eliminating the need for a separate isolation structure process, thereby simplifying the fabrication process and reducing production costs. By selecting a substrate doped between doped regions as the channel region for the subsequently formed back-side transistors, the process of forming the well region can be reduced, and even the sidewall structure process can be omitted, thereby improving fabrication efficiency. By forming a dielectric layer and a metal grid with a high dielectric constant material, back-side transistors with metal gates can be formed, enabling the image sensor obtained in this application to advanced processes with faster response speeds. An air gap is formed within the deep trench isolation structure, improving the isolation strength between photodiodes, avoiding interference from parasitic light pollution, and enhancing the isolation effect of the formed deep trench isolation structure. Back-side transistor wiring connections are completed on the back side of the substrate, and a third pad is formed within the trench for direct contact with the metal layer, achieving back-side electrical interconnection, reducing space occupation, and optimizing the fill factor.

[0087] The embodiments of the present invention disclosed above are merely illustrative of the invention. These embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An image sensor, characterized in that, include: A substrate, the substrate including a photosensitive area and a logic area, the substrate including a front side and a back side disposed opposite to each other; Multiple photodiodes are spaced apart on the front side of the substrate in the photosensitive area; Multiple semiconductor devices are spaced apart on the front side of the substrate in the logic region; At least one back-side transistor is disposed in the logic region by the back side of the substrate, the back-side transistor comprising a pair of doped regions spaced apart within the substrate; Multiple deep trench isolation structures are disposed on at least both sides of the photodiode and the back transistor from the back side of the substrate; Multiple metal grids are disposed at least on the deep trench isolation structure on both sides of the photodiode and on the substrate between the pair of doped regions.

2. The image sensor according to claim 1, characterized in that, The substrate is a silicon wafer with a homogeneous epitaxial layer, the epitaxial layer and the silicon wafer have the same doping type, and the doping type of the doped region is opposite to that of the substrate.

3. The image sensor according to claim 1, characterized in that, A dielectric layer is disposed between the metal grid and the substrate. The dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer stacked together. The first dielectric layer and the second dielectric layer are silicon oxide layers, and the material of the second dielectric layer is a high dielectric constant material.

4. The image sensor according to claim 3, characterized in that, An insulating layer is provided at least on the doped region, and the thickness of the insulating layer is equal to the thickness of the dielectric layer.

5. The image sensor according to claim 1, characterized in that, On the side of the photoelectric sensing area away from the logic area, a first connection structure is provided on the back side of the substrate, and the first connection structure is in communication with the substrate.

6. A method for manufacturing an image sensor, characterized in that, include: A substrate is provided, the substrate including a photosensitive region and a logic region, the substrate including a front side and a back side disposed opposite to each other; A plurality of photodiodes are formed at intervals on the front side of the substrate in the photosensitive area. A plurality of semiconductor devices are formed at intervals in the logic region on the front side of the substrate; At least one back-side transistor is formed in the logic region from the back side of the substrate, the back-side transistor comprising a pair of doped regions spaced apart within the substrate; Multiple deep trench isolation structures are formed on the back side of the substrate, and the deep trench isolation structures are disposed on at least both sides of the photodiode and the back-side transistor; A metal grid is formed on at least the deep trench isolation structure on both sides of the photodiode and on the substrate between the pair of doped regions.

7. The method for manufacturing an image sensor according to claim 6, characterized in that, The manufacturing method further includes: After fabricating the photodiode and the semiconductor device on the front side of the substrate, a multilayer metal wiring layer is fabricated. After the metal wiring layer is bonded to the carrier board, it forms a structural layer; The substrate is flipped over, and thinning is performed on the back side of the substrate to form a sacrificial oxide layer on one side of the substrate opposite to the structural layer; A first photoresist layer is formed on the sacrificial oxide layer, and at least two first openings are formed on the first photoresist layer, wherein the first openings are located in the logic region; Using the first photoresist as a mask, an ion implantation process is performed on the substrate within the first opening to form at least one pair of doped regions.

8. The method for manufacturing an image sensor according to claim 7, characterized in that, The steps for forming the deep trench isolation structure include: After the doped region is formed, a second photoresist layer is reformed on the sacrificial oxide layer. A plurality of second openings are formed on the second photoresist layer. The second openings are at least disposed between adjacent photodiodes and on both sides of a pair of doped regions. Using the second photoresist layer as a mask, etching is performed in the direction of the structural layer to remove the sacrificial oxide layer exposed by the second opening and part of the substrate, forming a deep trench. An insulating material is deposited in the deep trench and on the sacrificial oxide layer. A portion of the insulating material and the sacrificial oxide layer is removed by planarization until the insulating material is flush with the substrates on both sides, forming a deep trench isolation structure.

9. The method for manufacturing an image sensor according to claim 8, characterized in that, The manufacturing method further includes: A dielectric layer is formed on the substrate and the deep trench isolation structure; The dielectric layer is etched to form a plurality of recesses, the recesses being at least located on the doped region, on the side of the photodiode away from the logic region, and on the side of the doped region away from the photosensitive region; An insulating material is deposited within the recess to form an insulating layer, which is flush with the dielectric layer.

10. The method for manufacturing an image sensor according to claim 9, characterized in that, The manufacturing method further includes: A metal grid layer and a hard mask layer are formed on the insulating layer and the dielectric layer; The hard mask layer and the metal grid layer are etched down to the dielectric layer and the insulating layer to form a plurality of the metal grids; A dielectric layer is filled between the metal grids to flatten the dielectric layer; The dielectric layer is etched to form multiple openings; Conductive material is deposited within the opening to form multiple connection structures, which are connected to at least the doped region and the metal grid between a pair of doped regions.

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