Task processing method and electronic device

Abstract

The application discloses a task processing method and an electronic device, and relates to the technical field of data processing, and comprises the following steps: a hardware logic processor can directly receive a concurrent data acquisition request initiated by a server state detection module, and quickly extracts function fields and command fields of each request through hardware-level analysis logic, compared with a traditional software analysis mode, and the delay problem of serial instruction execution is avoided. In addition, the hardware logic processor can perform mask matching and priority determination on the core fields of each request by means of the hardware parallel processing capability of a parallel comparator array, so that the priority of multiple requests is quickly defined, and the resource blockage of the priority determination link is reduced. Therefore, the task processing method provided by the application improves the processing efficiency of multiple data acquisition requests.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a task processing method and electronic device. Background Technology

[0002] A server includes hardware components such as a power supply module, hard drive, network interface card (NIC), and backplane. The status of these hardware components affects the server's operating efficiency. In some scenarios, it is necessary to monitor the operating data of each hardware component and determine its status based on this data.

[0003] In related technologies, the server includes a status detection module that can detect the operational data of each hardware component based on the Baseboard Management Controller (BMC). Specifically, the status detection module can send multiple data acquisition requests to the BMC to obtain the operational data of each hardware component. After receiving multiple data acquisition requests, the BMC processes them serially or through a simple queue to obtain the operational data of each hardware component and then sends the operational data of each hardware component to the status detection module. However, processing multiple data acquisition requests in this way is inefficient. Summary of the Invention

[0004] This application provides a task processing method and an electronic device to improve the processing efficiency of multiple data acquisition requests.

[0005] This application provides a task processing method applied to a hardware logic processor, the hardware logic processor including a parallel comparator array, comprising:

[0006] Receive multiple data acquisition requests. Each data acquisition request is used to request the operation data of the target component corresponding to the data acquisition request. The target component is at least one of multiple components in the server.

[0007] Parse multiple data retrieval requests to determine the function fields and command fields of each request.

[0008] For each data acquisition request among multiple data acquisition requests, the function field and command field of the data acquisition request are processed by a parallel comparator array to determine the priority of the data acquisition request;

[0009] Based on the priority of each data acquisition request, the requests are processed to determine the operating data of the target component corresponding to each data acquisition request.

[0010] This application also provides a task processing apparatus, including:

[0011] The receiving module is used to receive multiple data acquisition requests. Each data acquisition request is used to request the operation data of the target component corresponding to the data acquisition request. The target component is at least one of multiple components in the server.

[0012] The parsing module is used to parse multiple data retrieval requests and determine the function fields and command fields of each data retrieval request.

[0013] The priority determination module is used to process the function fields and command fields of the data acquisition requests among multiple data acquisition requests through a parallel comparator array to determine the priority of the data acquisition requests.

[0014] The processing module is used to process multiple data acquisition requests according to their respective priorities and determine the running data of the target component corresponding to each data acquisition request.

[0015] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the above-described task processing method.

[0016] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described task processing method.

[0017] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described task processing method.

[0018] This application enables a hardware logic processor to directly receive concurrent data acquisition requests initiated by the server status detection module. Through hardware-level parsing logic, it quickly extracts the functional and command fields of each request, avoiding the latency issues associated with serial instruction execution compared to traditional software parsing methods. Furthermore, leveraging the hardware parallel processing capabilities of the parallel comparator array, the hardware logic processor can simultaneously perform mask matching and priority determination on the core fields of each request, achieving rapid prioritization of multiple requests and reducing resource congestion in the priority determination process. Therefore, the task processing method provided in this application improves the efficiency of processing multiple data acquisition requests. Attached Figure Description

[0019] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram illustrating an application scenario provided in the embodiments of this application;

[0021] Figure 2 A flowchart illustrating a task processing method provided in an embodiment of this application;

[0022] Figure 3 A flowchart illustrating the process of determining the priority of a data acquisition request, provided as an embodiment of this application;

[0023] Figure 4 This is a schematic diagram illustrating how to determine the priority of a data acquisition request, as provided in an embodiment of this application.

[0024] Figure 5 A flowchart illustrating the process of determining the operating data of the target component corresponding to each of multiple data acquisition requests, provided in an embodiment of this application;

[0025] Figure 6 A flowchart illustrating another task processing method provided in an embodiment of this application;

[0026] Figure 7 A schematic diagram illustrating the processing state of a maintenance task processing unit provided in an embodiment of this application;

[0027] Figure 8 A schematic diagram illustrating the processing state of another maintenance task processing unit provided in an embodiment of this application;

[0028] Figure 9 This is a schematic diagram of the structure of a task processing device provided in an embodiment of this application;

[0029] Figure 10 A schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0031] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0032] First, let's explain the technical terms used in this application:

[0033] A Field-Programmable Gate Array (FPGA) is a semi-custom programmable logic integrated circuit. Unlike the serial instruction execution mode of a Central Processing Unit (CPU), an FPGA supports massively parallel logic operations. Multiple logic modules within the FPGA can synchronously complete different tasks within the same clock cycle, significantly improving data processing efficiency and real-time performance.

[0034] The BMC (Board Management Controller) is a dedicated embedded management chip integrated on the server motherboard. During server operation, the BMC needs to respond to data access requests initiated concurrently by multiple processes. These data access requests request access to the operational data of various components within the server. The BMC can use a software-level thread scheduling mechanism to queue, prioritize, and allocate resources for the sensor tasks corresponding to the concurrent data access requests. It then schedules the processing units within the BMC chip to execute the tasks, ultimately feeding the sensor data back to the corresponding processes to fulfill the multi-process monitoring requirements of the server hardware status.

[0035] During server operation, the server's operating status can be determined by monitoring the operating data of hardware components such as the power module, hard drive, network card, backplane, CPU, and graphics processing unit (GPU), including their temperature and voltage.

[0036] In related technologies, the server includes a status detection module that can detect the operational data of each hardware component based on the BMC (Body Control Controller). Specifically, the status detection module can send multiple data acquisition requests to the BMC to obtain the operational data of each hardware component. After receiving multiple data acquisition requests, the BMC processes them serially or through a simple queue to obtain the operational data of each hardware component and then sends the operational data of each hardware component to the status detection module.

[0037] However, when multiple processes make concurrent requests, the data acquisition requests are queued and processed sequentially in the BMC. Since operations such as sensor data reading involve hardware access and inherently involve latency, the BMC takes a long time to process each data acquisition request. Furthermore, the response time for multiple concurrent requests increases linearly with the number of concurrent data acquisition requests, making the aforementioned serial or simple queue-based approach inefficient for processing multiple data acquisition requests.

[0038] Based on this, this application provides a task processing method in which a hardware logic processor can directly receive concurrent data acquisition requests initiated by the server status detection module. Through hardware-level parsing logic, it quickly extracts the functional and command fields of each request, avoiding the latency problem of serial instruction execution compared to traditional software parsing methods. Furthermore, leveraging the hardware parallel processing capabilities of the parallel comparator array, the hardware logic processor can simultaneously perform mask matching and priority determination on the core fields of each request, enabling rapid prioritization of multiple requests and reducing resource congestion in the priority determination process. Therefore, the task processing method provided in this application improves the processing efficiency for multiple data acquisition requests.

[0039] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0040] This section describes the specific application environment architecture or hardware architecture upon which the task processing method depends. (References) Figure 1 , Figure 1 This is a schematic diagram illustrating an application scenario provided in an embodiment of this application. For example... Figure 1 As shown, it includes server 11, in which a status detection module, power module, hard disk, network card, backplane, CPU, etc. are deployed.

[0041] In practical applications, the status detection module needs to detect the operating data of each hardware component in server 11, such as the power module, hard disk, network card, backplane, and CPU, in order to determine the operating status of server 11 based on the operating data of each hardware component.

[0042] It should be noted that the execution subject in each embodiment of this application can be a processor, microprocessor, or a device integrating the aforementioned processor or microprocessor, such as a terminal device. The specific execution subject in each embodiment of this application is not limited and can be selected and set according to actual needs. In the following embodiments, a terminal device integrating the aforementioned processor or microprocessor is used as an example for description, which does not constitute a limitation on the actual execution subject.

[0043] It should be noted that, Figure 1 This is merely an example to illustrate one application scenario, and is not intended to limit the application scenario.

[0044] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0045] Figure 2 This is a flowchart illustrating a task processing method provided in an embodiment of this application. Figure 2 As shown, the method may include the following steps:

[0046] S201. Receive multiple data acquisition requests. Each data acquisition request is used to request the operation data of the target component corresponding to the data acquisition request. The target component is at least one of multiple components in the server.

[0047] In some embodiments, the server includes a status detection module for detecting the server's operating status during operation. The status detection module needs to acquire the operating data of multiple components within the server and determine the server's operating status based on the operating data of these components.

[0048] These components can include, for example, hardware components such as the power supply module, hard drive, network card, backplane, and CPU in a server. Taking the CPU as an example, CPU operating data can include data such as CPU temperature and voltage.

[0049] Multiple data acquisition requests are instruction packets with a specific protocol format initiated concurrently by the status detection module. Each data acquisition request requests the operational data of the target component corresponding to that request. For example, a data acquisition request could be an Intelligent Platform Management Interface (IPMI) request.

[0050] For example, assuming the target component of the data acquisition request is a hard drive, the data acquisition request is used to request the acquisition of the hard drive's operating data.

[0051] In some embodiments, the status detection module can concurrently send multiple data acquisition requests to the hardware logic processor. The hardware logic processor is a dedicated processing module with hardware circuitry at its core, capable of performing specific logical operations and task processing. Its core characteristic is that data processing is completed through fixed or programmable hardware logic, rather than relying on the serial execution of software instructions, offering advantages such as low latency, high parallelism, and high stability. The hardware logic processor can be, for example, an FPGA.

[0052] S202. Parse multiple data acquisition requests and determine the function fields and command fields of each data acquisition request.

[0053] For each data acquisition request among multiple data acquisition requests, the function field of the data acquisition request is used as a core identifier to macroscopically define the major business function category to which the request belongs. The function field can be represented by, for example, NetFn, and different function field values ​​correspond to different business domains. For example, assuming NetFn=0x04, it means that the data acquisition request belongs to the sensor data reading and equipment monitoring function category.

[0054] The command field of this data acquisition request is the core identifier under the business category defined by the function field, used to clarify the specific operation instruction for this data acquisition request. The command field can be represented by Cmd. The command field needs to be combined with the function field to determine the complete intent of the request. For example, if the function field is NetFn=0x04, then Cmd=0x2D represents the specific operation of "reading sensor data".

[0055] In some embodiments, the hardware logic processor determines the function fields and command fields of each of the multiple data acquisition requests as follows: For each data acquisition request among the multiple data acquisition requests, the data acquisition request is parsed according to the protocol format of the data acquisition request to determine the function fields and command fields of the data acquisition request.

[0056] S203. For each data acquisition request among multiple data acquisition requests, the function field and command field of the data acquisition request are processed by a parallel comparator array to determine the priority of the data acquisition request.

[0057] The hardware logic processor includes a parallel comparator array. In some embodiments, the parallel comparator array consists of N independent comparators, and its core capability is to synchronously perform mask matching operations on the function fields and command fields of multiple data acquisition requests within the same clock cycle. The parallel comparator array possesses hardware-level parallel processing characteristics and is a key hardware foundation for achieving fast priority determination.

[0058] The priority of a data acquisition request is used to indicate the business urgency of the request. In some embodiments, the priority of a data acquisition request can be represented as a positive integer, and the higher the priority, the higher the business urgency of the request; the lower the priority, the lower the business urgency.

[0059] In some embodiments, for each data acquisition request among multiple data acquisition requests, the hardware logic processor can input the function field and command field of the data acquisition request into a parallel comparator array. The parallel comparator array uses the function field and command field of the data acquisition request to determine the rules that the data acquisition request must satisfy. The hardware logic processor can then determine the priority of the data acquisition request based on the priority of the rule with the highest priority among the rules satisfied by the data acquisition request.

[0060] S204. Based on the priority of each of the multiple data acquisition requests, process the multiple data acquisition requests and determine the operating data of the target component corresponding to each of the multiple data acquisition requests.

[0061] In some embodiments, the hardware logic processor can determine the processing order of multiple data acquisition requests based on their respective priorities. Then, the hardware logic processor processes the multiple data acquisition requests sequentially to determine the operating data of the target component corresponding to each data acquisition request.

[0062] exist Figure 2 In the illustrated embodiment, the hardware logic processor can directly receive concurrent data acquisition requests initiated by the server status detection module. Through hardware-level parsing logic, it quickly extracts the functional and command fields of each request, avoiding the latency problem of serial instruction execution compared to traditional software parsing methods. Furthermore, leveraging the hardware parallel processing capabilities of the parallel comparator array, the hardware logic processor can simultaneously perform mask matching and priority determination on the core fields of each request, enabling rapid prioritization of multiple requests and reducing resource congestion in the priority determination process. Therefore, the task processing method provided in this application improves the processing efficiency for multiple data acquisition requests.

[0063] exist Figure 2 Based on the illustrated embodiment, the following section addresses each data acquisition request among multiple data acquisition requests, combining... Figure 3 The process by which the hardware logic processor determines the priority of the data acquisition request is further explained.

[0064] Figure 3 This is a flowchart illustrating a process for determining the priority of a data acquisition request, provided as an embodiment of this application. Figure 3 As shown, the process may include the following steps:

[0065] S301. The function field and command field of the data acquisition request are processed by at least one comparator to determine the matching vector of the data acquisition request; the matching vector is used to indicate at least one request rule that the data acquisition request satisfies.

[0066] The parallel comparator array includes at least one comparator, wherein each comparator is used to determine whether the data acquisition request meets the preset rule corresponding to that comparator, and the preset rules corresponding to each comparator are different.

[0067] In some embodiments, the hardware logic processor determines the matching vector as follows: for each comparator in at least one comparator, the function field and command field of the data acquisition request are processed by the comparator to determine the vector value corresponding to the comparator; the vector value corresponding to the comparator is used to indicate whether the data acquisition request meets the preset rules of the comparator; and the matching vector is determined according to the vector value corresponding to each of the at least one comparator.

[0068] In some embodiments, the vector value corresponding to the comparator can be determined as follows: by comparing the function field of the data acquisition request with the first preset field using the comparator, a first index value of the comparator is determined, the first index value being used to indicate whether the function field of the data acquisition request is consistent with the first preset field; by comparing the command field of the data acquisition request with the second preset field using the comparator, a second index value of the comparator is determined, the second index value being used to indicate whether the command field of the data acquisition request is consistent with the second preset field; and the vector value corresponding to the comparator is determined based on the first index value and the second index value.

[0069] Each comparator includes a first preset field and a second preset field. The first preset field is the baseline value of the function field of the comparator's preset rule, and the second preset field is the baseline value of the command field of the comparator's preset rule.

[0070] The first indicator value can be represented, for example, by 0 or 1. The second indicator value can be represented, for example, by 0 or 1.

[0071] For example, suppose that when the first indicator is 0, the function field indicating the data acquisition request is inconsistent with the first preset field; when the first indicator is 1, the function field indicating the data acquisition request is consistent with the first preset field. When the second indicator is 0, the command field indicating the data acquisition request is inconsistent with the second preset field; when the second indicator is 1, the command field indicating the data acquisition request is consistent with the second preset field.

[0072] After the hardware logic processor inputs the function field and command field of the data acquisition request into the comparator, it compares the function field of the data acquisition request with the first preset field, and then determines the first indicator value to be 1. At the same time, the comparator compares the command field of the data acquisition request with the second preset field, and then determines the second indicator value to be 0.

[0073] In some embodiments, the hardware logic processor determines the vector value corresponding to the comparator based on the first indicator value and the second indicator value as follows: when the first indicator value indicates that the function field of the data acquisition request is consistent with the first preset field, and the second indicator value indicates that the command field of the data acquisition request is consistent with the second preset field, the vector value corresponding to the comparator is determined to indicate that the data acquisition request meets the comparator's preset rules; when the first indicator value indicates that the function field of the data acquisition request is inconsistent with the first preset field, and / or the second indicator value indicates that the command field of the data acquisition request is inconsistent with the second preset field, the vector value corresponding to the comparator is determined to indicate that the data acquisition request does not meet the comparator's preset rules.

[0074] Vector values ​​can be represented, for example, by 0 or 1.

[0075] For example, suppose that when the vector value is 0, it means that the data acquisition request does not meet the comparator's preset rules; and when the vector value is 1, it means that the data acquisition request meets the comparator's preset rules. If the first indicator value indicates that the function field of the data acquisition request is consistent with the first preset field, and the second indicator value indicates that the command field of the data acquisition request is consistent with the second preset field, then the vector value corresponding to the comparator is determined to be 1.

[0076] The matching vector of the data acquisition request is a binary vector formed by sequentially integrating the rule matching results of each independent comparator in the parallel comparator array within the hardware logic processor. Its core is a quantitative representation of the matching situation between the data acquisition request and all rule entries in the preset rule table.

[0077] In some embodiments, the hardware logic processor may determine the vector position of at least one comparator and determine the matching vector of the data acquisition request based on the vector position of at least one comparator and the vector value corresponding to at least one comparator.

[0078] For example, suppose at least one comparator includes comparator 1, comparator 2, and comparator 3, and the vector position of comparator 1 is 0, the vector position of comparator 2 is 1, and the vector position of comparator 3 is 2. Simultaneously, the vector value corresponding to comparator 1 is 0, the vector value corresponding to comparator 2 is 1, and the vector value corresponding to comparator 3 is 1. In this case, the hardware logic processor determines the matching vector as [0, 1, 1].

[0079] S302. Determine the priority of the data retrieval request based on the matching vector.

[0080] In some embodiments, the hardware logic processor determines the priority of a data acquisition request in the following way: based on the matching vector, it determines the target rule that the data acquisition request must satisfy, wherein the target rule is the request rule with the highest priority among at least one request rule that the data acquisition request must satisfy; and the priority of the target rule is determined as the priority of the data acquisition request.

[0081] For example, suppose the matching vector is [0,1,1]. The matching vector indicates at least one request rule that the data retrieval request satisfies, including request rule 1 and request rule 2, where request rule 1 has a priority of 1 and request rule 2 has a priority of 2. Therefore, the target rule is determined to be request rule 2. Since request rule 2 has a priority of 2, the priority of the data retrieval request is determined to be 2.

[0082] In summary, it can be combined with Figure 4 Understand the process of prioritizing data retrieval requests. Figure 4 This is a schematic diagram illustrating how to determine the priority of a data acquisition request, as provided in an embodiment of this application. Figure 4 As shown, after the input register of the hardware logic processor receives multiple data acquisition requests, the hardware logic processor parses the multiple data acquisition requests and determines the function fields and command fields of each of the multiple data acquisition requests.

[0083] For each data acquisition request among multiple data acquisition requests, the hardware logic processor inputs the function field and command field of the data acquisition request to N comparators in the parallel comparator array, respectively.

[0084] N comparators perform mask matching operations on the function field and command field of the data acquisition request, respectively, to determine the vector value corresponding to each of the N comparators. The hardware logic processor determines the matching vector for the data acquisition request based on the vector values ​​corresponding to the N comparators.

[0085] The hardware logic processor includes a priority classifier. The hardware logic processor can input the matching vectors of multiple data acquisition requests into the priority classifier. For each data acquisition request among the multiple data acquisition requests, the priority classifier determines the priority of that data acquisition request based on its matching vector.

[0086] exist Figure 3In the illustrated embodiment, the hardware logic processor, based on a parallel comparator array-based request priority determination process, achieves accurate determination of request rule matching and priority definition through phased dual-index value verification, matching vector generation, and highest-priority target rule filtering. Simultaneously, relying on hardware-level parallel processing logic, it ensures both the rigor and accuracy of priority determination and improves the scheduling efficiency of multiple data acquisition requests.

[0087] Based on the above embodiments, the following, in conjunction with Figure 5 The process of determining the operating data of the target component corresponding to each of the multiple data acquisition requests provided in the embodiments of this application will be further explained.

[0088] Figure 5 This is a flowchart illustrating a process for determining the operational data of a target component corresponding to each of multiple data acquisition requests, as provided in an embodiment of this application. Figure 5 As shown, the process may include the following steps:

[0089] S501. Determine the priority of at least one task queue.

[0090] The hardware logic processor includes at least one task queue. The task queue is a hardware storage module within the hardware logic processor used to cache and manage data fetch requests. For example, the task queue can be constructed as a separate First-In-First-Out (FIFO) storage structure from the FPGA's built-in Block Random Access Memory (BRAM).

[0091] The priority of a task queue is a level identifier used to distinguish the order in which tasks are scheduled. The priority level is related to the urgency of the data retrieval request within the queue.

[0092] S502. For each data acquisition request among multiple data acquisition requests, at least one task queue with the same priority as the data acquisition request is determined as the task queue for the data acquisition request.

[0093] The priority of the task queue corresponds one-to-one with the priority of the data retrieval request.

[0094] For example, suppose the priority of the data acquisition request is 2, and at least one task queue includes task queue A, task queue B, and task queue C. Task queue A has a priority of 1, task queue B has a priority of 2, and task queue C has a priority of 3. Then, the hardware logic processor determines that the task queue for this data acquisition request is task queue B.

[0095] In some embodiments, each task queue aggregates multiple data acquisition requests of the same priority according to rules. Its core function is to achieve classified caching and orderly scheduling of requests, avoiding chaotic backlog of data acquisition requests of different priorities.

[0096] S503. Based on the priority of each data acquisition request's task queue, process the multiple data acquisition requests and determine the running data of the target component corresponding to each of the multiple data acquisition requests.

[0097] In some embodiments, the hardware logic processor determines the running data of the target component corresponding to each of the multiple data acquisition requests in the following manner: performing a first operation, the first operation including: determining the task queue with priority i in the task queue of each of the multiple data acquisition requests as the target queue; processing the data acquisition requests in the target queue to determine the running data of the target component corresponding to the data acquisition requests in the target queue; updating i to i-1, and repeating the first operation until i=0; wherein i is a positive integer greater than or equal to 0.

[0098] The target queue is the queue of data retrieval requests that the hardware logic processor currently needs to process.

[0099] In some embodiments, the hardware logic processor will prioritize processing requests in the highest priority queue. Only when the queue is empty will requests in the next level queue be scheduled in sequence. Requests in the high priority queue can preempt the processing resources of requests in the low priority queue, thereby ensuring that requests corresponding to core server management commands (such as power supply alarms and device power-on / off) can be responded to first, and improving the business adaptability of overall task processing.

[0100] For example, suppose there are multiple data retrieval requests, including data retrieval request a, data retrieval request b, and data retrieval request c, and the task queue for data retrieval request a is task queue A, the task queue for data retrieval request b is task queue A, and the task queue for data retrieval request c is task queue B. The priority of task queue A is 2, and the priority of task queue B is 1.

[0101] The hardware logic processor first designates task queue A as the target queue and processes data acquisition requests a and b within task queue A to determine the operating data of the target component corresponding to data acquisition request a, and the operating data of the target component corresponding to data acquisition request b. Then, the hardware logic processor designates task queue B as the target queue and processes data acquisition request c within task queue B to determine the operating data of the target component corresponding to data acquisition request c.

[0102] In some embodiments, the hardware logic processor processes data acquisition requests in the target queue as follows: determining the processing state of at least one task processing unit, wherein the processing state of each task processing unit is either idle or working; determining a target processing unit in the at least one task processing unit based on the processing state of each task processing unit, wherein the processing state of the target processing unit is idle; and processing the data acquisition requests in the target queue through the target processing unit to determine the running data of the target component corresponding to the data acquisition requests in the target queue.

[0103] The server includes at least one task processing unit. The task processing unit is a dedicated data processing hardware module integrated within the hardware logic processor. The core of the task processing unit consists of an arithmetic logic unit, an Inter-Integrated Circuit (I2C) interaction submodule, and a cache access interface, possessing the ability to independently execute data acquisition request processing. Each task processing unit can independently complete operations such as reading data from the cache or accessing the I2C bus, and data verification, serving as the core hardware carrier for realizing parallel processing of multiple requests.

[0104] A task processing unit in an idle state indicates that it is not currently processing any tasks; a task processing unit in a working state indicates that it is currently processing any tasks.

[0105] In some embodiments, the hardware logic processor may identify at least one task processing unit that is in an idle state as a candidate processing unit. If there is only one candidate processing unit, the hardware logic processor identifies that candidate processing unit as the target processing unit. If there are multiple candidate processing units, the hardware logic processor may identify any one of the candidate processing units as the target processing unit.

[0106] In some embodiments, if at least one task processing queue is in a working state, the hardware logic processor can determine the priority of the data acquisition request being processed by each of the at least one task processing unit, identify data acquisition requests with priorities lower than the current pending data acquisition request, and designate the task processing unit processing the data acquisition request as a candidate processing unit. If there is only one candidate processing unit, the hardware logic processor designates that candidate processing unit as the target processing unit. If there are multiple candidate processing units, the hardware logic processor can designate any one of the candidate processing units as the target processing unit.

[0107] The hardware logic processor terminates the current processing task of the target processing unit and saves the context of the processing task. Then, the hardware logic processor inputs the current task acquisition request to the target processing unit, and after the target processing unit completes the processing of the data acquisition request, it continues to process the previous processing task.

[0108] For example, assuming the data acquisition request in the target queue is data acquisition request a, the target processing unit can process data acquisition request a to determine the running data of the target component corresponding to data acquisition request a.

[0109] exist Figure 5 In the illustrated embodiment, the hardware logic processor first defines the priority of the task queue and completes the priority matching and classification of data acquisition requests. Then, it processes the requests one by one in descending order of priority, while simultaneously selecting idle task processing units to take on the tasks. This achieves orderly management of data acquisition requests, ensuring priority response to high-priority data acquisition requests, and maximizes the utilization of hardware processing resources, avoiding idle or blocked task processing units. The task processing method provided in this application, relying on hardware-level scheduling and execution logic, improves the processing efficiency and stability of multiple data acquisition requests, ensuring timely acquisition of the corresponding running data.

[0110] Based on the above embodiments, the following, in conjunction with Figure 6 The task processing method provided in the embodiments of this application will be further described.

[0111] Figure 6 This is a flowchart illustrating another task processing method provided in an embodiment of this application. Figure 6 As shown, the task processing method may include the following steps:

[0112] S601, the status detection module sends multiple data acquisition requests to the hardware logic processor.

[0113] S602, the hardware logic processor receives multiple data acquisition requests.

[0114] The S603 hardware logic processor parses multiple data acquisition requests and determines the function fields and command fields of each data acquisition request.

[0115] S604 and the hardware logic processor process the function fields and command fields of each of the multiple data acquisition requests through at least one comparator to determine the matching vectors of each of the multiple data acquisition requests.

[0116] S605: The hardware logic processor determines the priority of each data acquisition request based on its matching vector.

[0117] S606. For each data acquisition request among multiple data acquisition requests, the hardware logic processor determines at least one task queue with the same priority as the data acquisition request as the task queue for the data acquisition request.

[0118] S607 The hardware logic processor processes multiple data acquisition requests according to the priority of their respective task queues, and determines the running data of the target component corresponding to each of the multiple data acquisition requests.

[0119] exist Figure 6 In the illustrated embodiment, the hardware logic processor can directly receive concurrent data acquisition requests initiated by the server status detection module. Through hardware-level parsing logic, it quickly extracts the functional and command fields of each request, avoiding the latency problem of serial instruction execution compared to traditional software parsing methods. Furthermore, leveraging the hardware parallel processing capabilities of the parallel comparator array, the hardware logic processor can simultaneously perform mask matching and priority determination on the core fields of each request, enabling rapid prioritization of multiple requests and reducing resource congestion in the priority determination process. Therefore, the task processing method provided in this application improves the processing efficiency for multiple data acquisition requests. In addition, the task processing method provided in this application does not require BMC intervention, reducing the BMC's operating pressure and CPU utilization.

[0120] In the above embodiments, the task processing method provided by this application further includes maintaining the processing state of each of the at least one task processing unit. Specifically, taking any one of the at least one task processing units as an example, it can be combined with... Figure 7 To understand, Figure 7 This is a schematic diagram illustrating the processing state of a maintenance task processing unit provided in an embodiment of this application. Figure 7 As shown, assume the task processing unit is currently in an idle state. After the hardware logic processor inputs a data acquisition request into the task processing unit, the task processing unit's processing state is updated to an active state. At this time, the hardware logic processor monitors the processing time of the task processing unit in processing the data acquisition request.

[0121] If the processing time is greater than or equal to the preset time, and the task processing unit has not yet completed processing the data acquisition request, then the processing status of the task processing unit is updated to the timeout state. At this time, the hardware logic processor resets the task processing unit, puts the data acquisition request back into the task queue for data acquisition requests, and finally updates the processing status of the task processing unit to the idle state.

[0122] If the processing time is less than the preset time and the task processing unit has completed processing the data acquisition request, then the processing status of the task processing unit will be updated to idle status.

[0123] In some embodiments, the hardware logic processor can also monitor whether there are any abnormalities in the processing of the data acquisition request by the task processing unit. If there is an abnormality in the processing of the data acquisition request by the task processing unit, the processing status of the task processing unit is updated to an abnormal status. At this time, the hardware logic processor resets the task processing unit, puts the data acquisition request back into the task queue of the data acquisition request, and finally updates the processing status of the task processing unit to an idle status.

[0124] Specifically, it can be combined with Figure 8 To understand, Figure 8 This is a schematic diagram illustrating the processing state of another maintenance task processing unit provided in an embodiment of this application. For example... Figure 8 As shown, the hardware logic processor includes a status monitoring module, which monitors the processing status of at least one task processing unit. The status monitoring module includes a status register, a hardware monitoring counter, and a hardware timeout counter.

[0125] The status register includes the processing status of at least one task processing unit at the current moment. A hardware monitoring counter is used to detect the status of each of the at least one task processing unit. For example, for each task processing unit among the at least one task processing unit, the hardware monitoring counter is used to detect whether the task processing unit is blocked, and if the task processing unit is blocked, the data acquisition request in the task processing unit is routed to the task processing unit whose processing status is idle.

[0126] For each task processing unit in at least one task processing unit, a hardware timeout counter is used to detect the processing time of the data acquisition request. If the processing time is greater than or equal to a preset time and the task processing unit has not yet completed processing the data acquisition request, a timeout message is triggered. At this time, the status monitoring module can reset the task processing unit, put the data acquisition request back into the task queue for data acquisition requests, and finally update the processing status of the task processing unit to idle status.

[0127] In some embodiments, the hardware logic processor includes a storage area for runtime data, which may, for example, use the BRAM built into the FPGA as the core storage medium, and define a data table in the FPGA's BRAM, with each entry containing: part number, runtime data, runtime status, and update timestamp.

[0128] The hardware storage processor can acquire the operating data of multiple components in the server according to a preset period and store the operating data of each component in the storage area.

[0129] Specifically, upon BMC startup or after the operating system boots up, the hardware logic processor begins acquiring operational data from multiple components. The hardware logic processor includes a data acquisition timer to acquire operational data from each component in the server at preset intervals. In some embodiments, the preset interval can be configured via registers.

[0130] For example, the hardware logic processor triggers an acquisition signal, starting the I2C host controller. The I2C host accesses the sensors of all components in a predefined order, reading the latest operational data. After verifying the acquired operational data, it is directly written to the storage area. The verification method can be, for example, Cyclic Redundancy Check (CRC). Then, the old data is overwritten and the timestamp is updated; if the read fails (e.g., I2C bus timeout), the corresponding entry's "status" is set to data expired, and the last valid data is retained.

[0131] In some embodiments, different preset periods can be configured based on the characteristics of different sensors on the component. For example, it is assumed that the preset period for acquiring the temperature data of the power module is 1 second, and the preset period for acquiring the fan speed data is 100 ms.

[0132] In this way, when processing data acquisition requests, the task processing unit does not need to rely on the BMC to access the slow I2C bus or for the BMC to poll and read the Redis database, but can directly read the required running data from the storage area.

[0133] Figure 9 This is a schematic diagram of a task processing device provided in an embodiment of this application. Figure 9 As shown in the figure, this application embodiment also provides a task processing device 90, which includes a receiving module 91, a parsing module 92, a determining module 93, and a processing module 94, wherein:

[0134] The receiving module 91 is used to receive multiple data acquisition requests. Each data acquisition request is used to request the operation data of the target component corresponding to the data acquisition request. The target component is at least one of multiple components in the server.

[0135] Parsing module 92 is used to parse multiple data acquisition requests and determine the function fields and command fields of each data acquisition request.

[0136] The determination module 93 is used to process the function fields and command fields of the data acquisition requests among multiple data acquisition requests through a parallel comparator array to determine the priority of the data acquisition requests.

[0137] The processing module 94 is used to process multiple data acquisition requests according to their respective priorities, and determine the running data of the target component corresponding to each of the multiple data acquisition requests.

[0138] In one possible implementation, the parallel comparator array includes at least one comparator, and the determining module 93 is specifically used for:

[0139] The function field and command field of the data retrieval request are processed by at least one comparator to determine the matching vector of the data retrieval request; the matching vector is used to indicate at least one request rule that the data retrieval request satisfies.

[0140] The priority of data retrieval requests is determined based on the matching vector.

[0141] In one possible implementation, the determining module 93 is specifically used for:

[0142] For each comparator in at least one comparator, the function field and command field of the data acquisition request are processed by the comparator to determine the vector value corresponding to the comparator; the vector value corresponding to the comparator is used to indicate whether the data acquisition request meets the preset rules of the comparator.

[0143] The matching vector is determined based on the vector values ​​corresponding to at least one comparator.

[0144] In one possible implementation, the determining module 93 is specifically used for:

[0145] The comparator compares the functional field of the data acquisition request with the first preset field to determine the first index value of the comparator. The first index value is used to indicate whether the functional field of the data acquisition request is consistent with the first preset field.

[0146] The comparator compares the command field of the data retrieval request with the second preset field to determine the second index value of the comparator. The second index value is used to indicate whether the command field of the data retrieval request is consistent with the second preset field.

[0147] The vector value corresponding to the comparator is determined based on the first index value and the second index value.

[0148] In one possible implementation, the determining module 93 is specifically used for:

[0149] When the function field of the first indicator value used to indicate the data acquisition request is consistent with the first preset field, and the command field of the second indicator used to indicate the data acquisition request is consistent with the second preset field, the vector value corresponding to the comparator is determined to indicate that the data acquisition request meets the comparator's preset rules.

[0150] If the function field of the first indicator used to indicate the data acquisition request is inconsistent with the first preset field, and / or the command field of the second indicator used to indicate the data acquisition request is inconsistent with the second preset field, the vector value corresponding to the comparator is determined to indicate that the data acquisition request does not meet the comparator's preset rules.

[0151] In one possible implementation, the determining module 93 is specifically used for:

[0152] Based on the matching vector, the target rule that the data acquisition request must satisfy is determined. The target rule is the request rule with the highest priority among at least one request rule that the data acquisition request must satisfy.

[0153] The priority of the target rule is determined as the priority of the data retrieval request.

[0154] In one possible implementation, the processing module 94 is specifically used for:

[0155] Determine the priority of at least one task queue;

[0156] For each data acquisition request among multiple data acquisition requests, at least one task queue with the same priority as the data acquisition request is identified as the task queue for the data acquisition request.

[0157] Based on the priority of each data acquisition request's task queue, the multiple data acquisition requests are processed to determine the running data of the target component corresponding to each data acquisition request.

[0158] In one possible implementation, the processing module 94 is specifically used for:

[0159] Perform the first operation, which includes: determining the task queue with priority i from the task queues of multiple data acquisition requests as the target queue; processing the data acquisition requests in the target queue to determine the running data of the target component corresponding to the data acquisition requests in the target queue;

[0160] Update i to i-1, and repeat the first operation until i is 0; where i is a positive integer greater than or equal to 0.

[0161] In one possible implementation, the processing module 94 is specifically used for:

[0162] Determine the processing state of at least one task processing unit, where the processing state of each task processing unit is either idle or working.

[0163] Based on the processing state of each of the at least one task processing unit, a target processing unit is determined in the at least one task processing unit; wherein the processing state of the target processing unit is an idle state.

[0164] The target processing unit processes the data acquisition requests in the target queue and determines the operating data of the target component corresponding to the data acquisition request in the target queue.

[0165] For a description of the features in the embodiment corresponding to the task processing device 90, please refer to the relevant description in the embodiment corresponding to the task processing method, which will not be repeated here.

[0166] Figure 10 A schematic diagram of the structure of the electronic device provided in this application. Figure 10 As shown, the electronic device 100 provided in this embodiment includes at least one processor 1001 and a memory 1002. Optionally, the electronic device 100 further includes a communication component 1003. The processor 1001, memory 1002, and communication component 1003 are connected via a bus.

[0167] In a specific implementation, at least one processor 1001 executes computer execution instructions stored in memory 1002, causing at least one processor 1001 to execute the above-described task processing method embodiment.

[0168] The specific implementation process of the task processing method executed by the processor 1001 can be found in the above method embodiment. The implementation principle and technical effect are similar, and will not be repeated here.

[0169] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0170] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0171] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0172] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described task processing method embodiments at runtime.

[0173] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0174] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described task processing method embodiments.

[0175] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described task processing method embodiments.

[0176] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0177] The foregoing has provided a detailed description of a task processing method and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A task processing method, characterized in that, Applied to a hardware logic processor, wherein the hardware logic processor includes a parallel comparator array, the method includes: Receive multiple data acquisition requests, each data acquisition request is used to request the acquisition of the operation data of the target component corresponding to the data acquisition request, and the target component is at least one of multiple components in the server; The multiple data acquisition requests are parsed to determine the function fields and command fields of each data acquisition request. For each of the multiple data acquisition requests, the function field and command field of the data acquisition request are processed by the parallel comparator array to determine the priority of the data acquisition request; Based on the priority of each of the multiple data acquisition requests, the multiple data acquisition requests are processed to determine the operating data of the target component corresponding to each of the multiple data acquisition requests; The parallel comparator array includes at least one comparator. For each of the plurality of data acquisition requests, the parallel comparator array processes the function field and command field of the data acquisition request to determine the priority of the data acquisition request, including: The function field and command field of the data acquisition request are processed by the at least one comparator to determine the matching vector of the data acquisition request; the matching vector is used to indicate at least one request rule that the data acquisition request satisfies. The priority of the data acquisition request is determined based on the matching vector. The step of processing the function field and command field of the data acquisition request through the at least one comparator to determine the matching vector of the data acquisition request includes: For each of the at least one comparators, the function field and command field of the data acquisition request are processed by the comparator to determine the vector value corresponding to the comparator; the vector value corresponding to the comparator is used to indicate whether the data acquisition request meets the preset rules of the comparator. The matching vector is determined based on the vector values ​​corresponding to each of the at least one comparator.

2. The method according to claim 1, characterized in that, The step of processing the function field and command field of the data acquisition request through the comparator for each of the at least one comparator to determine the vector value corresponding to the comparator includes: The comparator compares the functional field of the data acquisition request with the first preset field to determine the first index value of the comparator. The first index value is used to indicate whether the functional field of the data acquisition request is consistent with the first preset field. The comparator compares the command field of the data acquisition request with the second preset field to determine a second index value of the comparator. The second index value is used to indicate whether the command field of the data acquisition request is consistent with the second preset field. The vector value corresponding to the comparator is determined based on the first index value and the second index value.

3. The method according to claim 2, characterized in that, Determining the vector value corresponding to the comparator based on the first index value and the second index value includes: When the first indicator value indicates that the function field of the data acquisition request is consistent with the first preset field, and the second indicator indicates that the command field of the data acquisition request is consistent with the second preset field, the vector value corresponding to the comparator is determined to indicate that the data acquisition request meets the preset rule of the comparator. If the first indicator value is inconsistent with the first preset field for indicating the data acquisition request, and / or the second indicator is inconsistent with the second preset field for indicating the command field for indicating the data acquisition request, the vector value corresponding to the comparator is determined to indicate that the data acquisition request does not meet the preset rule of the comparator.

4. The method according to any one of claims 1-3, characterized in that, Determining the priority of the data acquisition request based on the matching vector includes: Based on the matching vector, the target rule to be satisfied by the data acquisition request is determined. The target rule is the request rule with the highest priority among at least one request rule to be satisfied by the data acquisition request. The priority of the target rule is determined as the priority of the data acquisition request.

5. The method according to any one of claims 1-3, characterized in that, The step of processing the multiple data acquisition requests according to their respective priorities and determining the operating data of the target component corresponding to each of the multiple data acquisition requests includes: Determine the priority of at least one task queue; For each of the plurality of data acquisition requests, the task queue with the same priority as the data acquisition request in the at least one task queue is determined as the task queue for the data acquisition request. Based on the priority of each data acquisition request's task queue, the data acquisition requests are processed to determine the running data of the target component corresponding to each data acquisition request.

6. The method according to claim 5, characterized in that, The step of processing the multiple data acquisition requests according to the priority of their respective task queues, and determining the running data of the target component corresponding to each of the multiple data acquisition requests, includes: Perform a first operation, which includes: determining the task queue with priority i in the task queues of the plurality of data acquisition requests as the target queue; processing the data acquisition requests in the target queue to determine the running data of the target component corresponding to the data acquisition requests in the target queue; Update i to i-1, and repeat the first operation until i is 0; where i is an integer greater than or equal to 0.

7. The method according to claim 6, characterized in that, The process of processing data acquisition requests in the target queue and determining the operating data of the target component corresponding to the data acquisition request in the target queue includes: Determine the processing state of at least one task processing unit, where the processing state of each task processing unit is either idle or working. Based on the processing state of each of the at least one task processing unit, a target processing unit is determined among the at least one task processing unit; wherein the processing state of the target processing unit is the idle state; The target processing unit processes the data acquisition requests in the target queue to determine the operating data of the target component corresponding to the data acquisition requests in the target queue.

8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the task processing method as described in any one of claims 1 to 7.

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