A / D converter and A / D conversion method

Abstract

This A / D converter performs A / D conversion including folding integration. The A / D converter includes: a gain stage that generates an operation value based on an input value; and an A / D conversion circuit that outputs an operation value usable for the generation of a digital value by comparing the operation value generated by the gain stage and the conversion reference voltage. The gain stage generates a calculation value VO (M-1) by using the integration gain G (M-1) in the (M-1)-th integration operation during the M-th integration operation, and generates a calculation value VO (M) by using the integration gain G (M) in the M-th integration operation. The integral gain G (M-1) is greater than the integral gain G (M).

Description

Technical Field

[0001] This disclosure relates to A / D converters and A / D conversion methods. Background Technology

[0002] Patent documents 1-6 disclose A / D converters that generate digital values ​​from analog signals. For example, the A / D converters disclosed in patent documents 1-4 perform folded integral type A / D conversion and cyclic type A / D conversion by switching a switch. Specifically, the A / D converter first performs a folded integral type A / D conversion. Then, the A / D converter performs a cyclic type A / D conversion on the analog signal, which is the result of the folded integral type A / D conversion.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: International Publication No. 2018 / 088476

[0006] Patent Document 2: Japanese Patent Application Publication No. 2017-201751

[0007] Patent Document 3: Japanese Patent Application Publication No. 2017-139583

[0008] Patent Document 4: International Publication No. 2012 / 111821

[0009] Patent Document 5: Japanese Patent Application Publication No. 2017-55174

[0010] Patent Document 6: Japanese Patent Application Publication No. 2007-49637 Summary of the Invention

[0011] The problem that the invention aims to solve

[0012] As with the A / D converters disclosed in Patent Documents 1-4, when switching between folded integral and cyclic modes, the result (analog signal) of the folded integral mode, which is the preceding operation, is controlled within an acceptable range for the cyclic mode, which is the following operation. Therefore, in the folded integral mode operation, an integral gain is employed to control the result of the integral operation within a desired range.

[0013] Integral gain affects the noise reduction effect during integration. A higher integral gain results in greater noise reduction, while a lower integral gain results in less noise reduction. In other words, to keep the integration result within the desired range, the integral gain must be reduced. Consequently, the noise reduction effect decreases.

[0014] This disclosure describes an A / D converter and A / D conversion method that controls the calculation result of the integral operation within the desired range and achieves good noise reduction effect.

[0015] Technical means to solve the problem

[0016] One aspect of this disclosure is an A / D converter that performs A / D conversion including folded integration, which obtains a digital value from an analog signal by repeatedly sampling the input signal and integrating the sampled values. The A / D converter has: a gain stage that outputs an operational value based on the analog signal; and an A / D conversion circuit that compares the operational value output by the gain stage with a conversion reference voltage to output a result usable for generating a digital value. In M operations (M being an integer greater than or equal to 2), the gain stage uses a first integral gain to generate the operational value based on the analog signal in the k-th operation (k being an integer less than or equal to M-1). In the (k+1)-th operation, the gain stage uses a second integral gain to generate the operational value based on the analog signal. The second integral gain is less than the first integral gain.

[0017] In multiple integration operations, the A / D converter ensures that the integration gain of the k-th integration operation corresponding to the next integration operation is smaller than the integration gain of the (k-1)-th operation. That is, to keep the calculated value obtained from M integration operations within a specified range, the A / D converter does not suppress the integration gain of all operations in the M integration operations, but only suppresses the integration gain of subsequent integration operations where the calculated value increases. As a result, sufficient integration gain can be obtained in the (k-1)-th integration operation where integration gain is not suppressed. Consequently, sufficient noise reduction effect can be ensured. Suppressing the integration gain of subsequent integration operations prevents the calculated value obtained as a result of M integration operations from exceeding the specified value. In other words, the A / D converter can control the calculated value of the integration operations within the desired range and achieve good noise reduction effect.

[0018] In one approach, the gain stage can also use a third integral gain to generate the calculated value based on the analog signal during the first operation. The third integral gain can also be greater than the first integral gain. Based on this structure, a better noise reduction effect can be achieved.

[0019] In one approach, the first integral gain can be used in the second through the (M-1)th actions. The second integral gain can also be used in the Mth action. This structure further enhances noise reduction.

[0020] In one approach, the first integral gain can be greater than or equal to 1. The second integral gain can also be greater than or equal to 0 and less than 1. This structure can further achieve good noise reduction.

[0021] Another aspect of this disclosure is an A / D converter that performs A / D conversion including folded integration, which obtains a digital value from an analog signal by repeatedly sampling the input signal and integrating the sampled values. The A / D converter of this other aspect has: a gain stage that outputs an operational value based on the analog signal; and an A / D conversion circuit that compares the operational value output by the gain stage with a conversion reference voltage to output a result usable for generating a digital value. The gain stage has: a stage input that receives the analog signal; an operational amplifier circuit that generates the operational value based on the analog signal; a stage output that outputs the operational value to the A / D conversion circuit; a pre-stage capacitor section that can be connected to the stage input and the input of the operational amplifier circuit, including at least one pre-stage capacitor; and a feedback capacitor section that can be connected to the stage input and the output of the operational amplifier circuit, including a feedback capacitor. The gain stage selectively constitutes a first circuit and a second circuit different from the first circuit in the sampling of the input signal. The first circuit, in order to set a predetermined capacitance ratio between the pre-stage capacitor and the feedback capacitor, stores the analog signal in at least one pre-stage capacitor by connecting the pre-stage capacitor to the stage input, and stores the analog signal in a feedback capacitor by connecting the feedback capacitor to the stage input. The second circuit, in order to set a capacitance ratio between the pre-stage capacitor and the feedback capacitor that is smaller than that of the first circuit, stores the analog signal in at least one pre-stage capacitor by connecting the pre-stage capacitor to the stage input, and does not store the analog signal in the feedback capacitor by disconnecting the feedback capacitor from the stage input.

[0022] This A / D converter, like the A / D converter of one embodiment of the present disclosure, is also able to control the result of the integration operation within the desired range and achieve good noise reduction.

[0023] In another approach, the ratio of the capacitance of the pre-amplifier capacitor to the capacitance of the feedback capacitor can also correspond to the magnitude of the integral gain. Based on this structure, further good noise reduction can be achieved.

[0024] In another approach, the action can be performed M times (M being an integer greater than or equal to 2). In sampling the input signal during the first action, a first circuit can be used to set the capacitance ratio of the pre-amplifier capacitor to the feedback capacitor capacitor to a predetermined ratio. Based on this structure, a further good noise reduction effect can be obtained.

[0025] In another approach, the action can be performed M times (M being an integer greater than or equal to 2). During the sampling of the input signal in the 2nd to M-1th actions, a second circuit can be used to set the capacitance ratio of the pre-stage capacitor to the feedback capacitor to be smaller than the ratio specified in the first circuit. Based on this structure, a further good noise reduction effect can be obtained.

[0026] In another approach, the action can also be executed M times (M being an integer greater than 2).

[0027] In the sampling of the input signal during the 2nd to M-1th operations, in order to set a first capacitance ratio (smaller than the specified capacitance ratio in the first circuit) for the ratio of the capacitance of the pre-stage capacitor to the capacitance of the feedback capacitor, the number of pre-stage capacitors storing the analog signal in the second circuit can be set to 2 or more. In the sampling of the input signal during the Mth operation, in order to set a second capacitance ratio (smaller than the first capacitance ratio) for the ratio of the capacitance of the pre-stage capacitor to the capacitance of the feedback capacitor, the number of pre-stage capacitors storing the analog signal in the second circuit can be set to 0 or 1. Based on this structure, a better noise reduction effect can be further obtained.

[0028] In another approach, the capacitance of the feedback capacitor can also be greater than that of the preceding capacitor. This structure also allows for further improvement in noise reduction.

[0029] In another approach, the capacitance of the feedback capacitor can also be greater than the capacitance of the first pre-stage capacitor. The capacitance of the first pre-stage capacitor can also differ from the capacitance of the second pre-stage capacitor, which is different from the first pre-stage capacitor. Based on this structure, further good noise reduction can be achieved.

[0030] Another aspect of this disclosure is an A / D conversion method that performs A / D conversion including folded integration, which obtains a digital value from an analog signal by repeatedly sampling the input signal and integrating the sampled values. Yet another aspect of the A / D conversion method includes: a step of generating a first calculated value based on the analog signal by performing an operation using a first integral gain; and a step of generating a second calculated value based on the analog signal after the step of generating the first calculated value by performing an operation using a second integral gain. The second integral gain is less than the first integral gain.

[0031] This A / D conversion method, like the A / D converter of one embodiment of the present disclosure, can control the calculation result of the integration operation within the desired range and achieve good noise reduction.

[0032] In another approach, the method may also include a step of generating a third operational value based on the analog signal by performing an action using a third integral gain before generating the first operational value. The third integral gain may also be greater than the first integral gain. This approach can further achieve better noise reduction.

[0033] In another approach, the action can be performed M times (M being an integer greater than or equal to 2). The step of generating the first calculated value can also be performed in the 2nd to M-1th actions. The step of generating the second calculated value can also be performed in the Mth action. This approach can further achieve a good noise reduction effect.

[0034] In another approach, the first integral gain can be greater than or equal to 1, and the second integral gain can be greater than or equal to 0 and less than 1. This approach also allows for further improvement in noise reduction.

[0035] Another aspect of this disclosure is an A / D conversion method that performs A / D conversion including folded integration, which obtains a digital value from an analog signal by repeatedly sampling the input signal and integrating the sampled values. Another aspect of the A / D conversion method includes: a sampling step of the input signal, wherein the analog signal is stored at least in a pre-stage capacitor section and a feedback capacitor section connected to the stage input of a gain stage for outputting an operational value based on the analog signal; the pre-stage capacitor section includes at least one pre-stage capacitor, and the feedback capacitor section includes a feedback capacitor; and an integration step of the sampled values, wherein the operational value is generated at the output of the operational amplifier circuit by connecting at least the pre-stage capacitor section to the input of an operational amplifier circuit having the gain stage. In the input signal sampling step, either a first storage or a second storage different from the first storage is performed. The first storage method, in order to set a predetermined capacitance ratio between the capacitors of the pre-stage capacitor section and the feedback capacitor section, stores the analog signal in at least one pre-stage capacitor by connecting the pre-stage capacitor section to the stage input, and stores the analog signal in a feedback capacitor by connecting the feedback capacitor section to the stage input. The second storage method, in order to set a capacitance ratio between the pre-stage capacitor section and the feedback capacitor section that is smaller than the predetermined capacitance ratio in the first storage method, stores the analog signal in at least one pre-stage capacitor by connecting the pre-stage capacitor section to the stage input, and does not store the analog signal in the feedback capacitor by disconnecting the feedback capacitor section from the stage input.

[0036] This A / D conversion method, like the A / D converter of one embodiment of the present disclosure, can control the calculation result of the integration operation within the desired range and achieve good noise reduction.

[0037] In another approach, the ratio of the capacitance of the pre-amplifier capacitor to the capacitance of the feedback capacitor can also correspond to the magnitude of the integral gain. This approach further enables the achievement of good noise reduction.

[0038] In another approach, the action can be performed M times (M being an integer greater than or equal to 2). During the input signal sampling step of the first action, a first storage operation can be performed to set the capacitance ratio of the preceding capacitor section to the feedback capacitor section to a predetermined ratio. According to this approach, a further good noise reduction effect can be obtained.

[0039] In another approach, the action can be performed M times (M being an integer greater than or equal to 2). During the sampling steps of the input signal in the 2nd to M-1th actions, a second storage operation can be performed to set the ratio of the capacitance of the preceding capacitor section to the capacitance of the feedback capacitor section to be smaller than the capacitance ratio specified in the first storage. According to this approach, a further good noise reduction effect can be obtained.

[0040] In another way, the action can also be performed M times (M is an integer greater than 2).

[0041] In the sampling of the input signal during the 2nd to M-1th operations, in order to set a first capacitance ratio (smaller than the specified capacitance ratio during the first storage) to be a first capacitance ratio, the number of pre-stage capacitors storing the analog signal can be set to 2 or more in the second storage. In the sampling of the input signal during the Mth operation, in order to set a second capacitance ratio (smaller than the first capacitance ratio) to be a second capacitance ratio, the number of pre-stage capacitors storing the analog signal can be set to 0 or 1 in the second storage. This method further improves noise reduction.

[0042] Invention Effects

[0043] According to this disclosure, an A / D converter and an A / D conversion method are described that control the calculation result of the integral operation within the desired range and achieve good noise reduction effect. Attached Figure Description

[0044] Figure 1 This is a circuit diagram showing the structure of the A / D converter in the first embodiment.

[0045] Figure 2 It is used for explanation Figure 1 A graph showing the integral gain during the operation of an A / D converter.

[0046] Figure 3 of (a) Figure 3 of (b) Figure 3 (c) Figure 3 of (d), Figure 3 (e) and Figure 3 (f) represents Figure 1 A diagram illustrating the operation of a folded integral type A / D converter in the A / D converter shown.

[0047] Figure 4 This is an example of the input / output characteristics of an A / D converter.

[0048] Figure 5 of (a) Figure 5 (b) and Figure 5 (c) represents Figure 1 The diagram shows the operation of a cyclic A / D conversion in an A / D converter.

[0049] Figure 6 This is a circuit diagram showing the structure of the A / D converter in the second embodiment.

[0050] Figure 7 It is used for explanation Figure 6 A graph showing the integral gain during the operation of an A / D converter.

[0051] Figure 8 of (a) Figure 8 of (b) Figure 8 (c) Figure 8 of (d), Figure 8 of (e) Figure 8 (f) represents Figure 6 A diagram illustrating the operation of a folded integral type A / D converter in the A / D converter shown.

[0052] Figure 9 of (a) Figure 9 (b) and Figure 9 (c) represents Figure 6 The diagram shows the operation of a cyclic A / D conversion in an A / D converter.

[0053] Figure 10 This is a diagram illustrating the integral gain during the operation of the A / D converter in Modified Example 1.

[0054] Figure 11 of (a) Figure 11 of (b) Figure 11 (c) Figure 11 of (d), Figure 11 (e) and Figure 11 (f) is a diagram showing the operation of the folded integral type A / D conversion in the A / D converter of Modified Example 1.

[0055] Figure 12 (a) is a graph used to illustrate the integral gain in the operation of the A / D converter in Modified Example 2. Figure 12 (b) is a graph used to illustrate the integral gain in the operation of the A / D converter in Modified Example 3.

[0056] Figure 13 This is a diagram showing the structure of an image sensor unit.

[0057] Figure 14 (a) is the result of Analytical Example 1, which represents the characteristics of A / D conversion. Figure 14 (b) is the result of analytic example 1 representing nonlinearity.

[0058] Figure 15 (a) is the result of analytical example 2, which represents the characteristics of A / D conversion. Figure 15 (b) is the result of analytic example 2 representing nonlinearity.

[0059] Figure 16 (a) is the result of analytical example 3 representing the characteristics of A / D conversion. Figure 16 (b) represents the result of analytic example 3, which indicates nonlinearity. Detailed Implementation

[0060] The insights of this disclosure can be readily understood by considering the following detailed description with reference to the accompanying drawings, which are shown as examples. Hereinafter, an embodiment of an A / D converter and A / D conversion method of this disclosure will be described with reference to the accompanying drawings. Where possible, the same reference numerals will be used to label the same parts, and repeated descriptions will be omitted.

[0061] <First Implementation>

[0062] Figure 1 This is a circuit diagram of an A / D converter 11 according to one embodiment of the present disclosure. The A / D converter 11 uses the same circuit structure to implement a so-called folded integration type A / D conversion, i.e., the first A / D conversion operation, and a cyclic type A / D conversion, i.e., the second A / D conversion operation. The A / D converter 11 achieves both the first and second A / D conversion operations by changing the control mode of the timing of the switches it possesses.

[0063] Figure 1 As shown, the A / D converter 11 includes a gain stage 15, an A / D conversion circuit 17, a logic circuit 19, a D / A conversion circuit 21, a clock generator 61, and a reference voltage generator 70.

[0064] Gain stage 15 includes receiving and converting the analog signal into a digital value, i.e., the input value V. INInput 15a (level input) and output operation value V O Output 15b (stage output). Gain stage 15 includes operational amplifier circuit 23, first capacitor 25 (first pre-stage capacitor), second capacitor 27 (second pre-stage capacitor), and third capacitor 29 (feedback capacitor).

[0065] Operational amplifier circuit 23 includes a first input 23a, an output 23b, and a second input 23c. The phase of the signal output from output 23b is out of phase with respect to the phase of the signal supplied to first input 23a. For example, first input 23a is an inverting input terminal. Second input 23c is a non-inverting input terminal. For example, the second input 23c of operational amplifier circuit 23 is connected to a first reference potential GND1. Second input 23c receives a reference potential V. COM .

[0066] The first capacitor 25, the second capacitor 27, and the third capacitor 29 are capacitors used to store and process various signal values.

[0067] The first capacitor 25 and the second capacitor 27 constitute the pre-amplifier section 41. The pre-amplifier section 41 can be connected to the input 15a via a plurality of switches 43, 82, and 83. The pre-amplifier section 41 can also be disconnected from the input 15a via a plurality of switches 43, 82, and 83. The pre-amplifier section 41 is also connected to the D / A conversion circuit 21.

[0068] The third capacitor 29 constitutes the feedback capacitor section 42. The feedback capacitor section 42 is connected to the input 23a of the operational amplifier circuit 23. The feedback capacitor section 42 can be connected to the input 15a using switches 43 and 51. The feedback capacitor section 42 can also be disconnected from the input 15a using switches 43 and 51. The feedback capacitor section 42 can be connected to the output 23b of the operational amplifier circuit 23 using switch 81. The feedback capacitor section 42 can be disconnected from the output 23b of the operational amplifier circuit 23 using switch 81.

[0069] The capacitance C2 of the third capacitor 29 (the third capacitor) is greater than the capacitance C of the first capacitor 25. 1a (First capacitor). Additionally, the capacitance C2 of the third capacitor 29 is greater than the capacitance C of the second capacitor 27. 1b (Second capacitor). Based on these capacitances C 1a and capacitor C 1b In the folded integral type A / D conversion, i.e., the first A / D conversion action, the input value V is... IN According to the capacitance ratio (C) 1a / C2、C 1b / C2) attenuation. Therefore, in the folded integral type A / D conversion, the output calculated value V OThe voltage range decreases according to the capacitance ratio of the capacitor. Based on this structure, the A / D converter 11 can be configured as a single-ended converter.

[0070] More specifically, the capacitance C2 of the third capacitor 29 is the same as the capacitance C of the first capacitor 25. 1a Twice that of the second capacitor. The capacitance C2 of the third capacitor 29 is twice that of the second capacitor 27. 1b 2 times. C 1a =1 / 2×C2 and C 1b The relationship V = 1 / 2 × C2 holds true. According to the A / D converter 11 with such a capacitor, the input value V in the folded integral type A / D conversion... IN The attenuation is 1 / 2. The attenuated input value V IN The sampled signal is integrated. Therefore, in a folded integral-type A / D converter, the output analog signal is the calculated value V. O The voltage range is halved according to the capacitance ratio of the capacitor. Therefore, in the cyclic A / D conversion, i.e., the second A / D conversion operation, an input voltage suitable for a single-ended A / D converter is provided.

[0071] Gain stage 15 includes a plurality of switches 43, 47, 49, 51, 53, 81, 82, and 83. These switches connect or disconnect the input 15a of gain stage 15 to the first capacitor 25, the second capacitor 27, and the third capacitor 29. These switches also connect or disconnect the first capacitor 25, the second capacitor 27, and the third capacitor 29 to the operational amplifier circuit 23. Figure 1 The configuration of switches 43, 47, 49, 51, 53, 81, 82, and 83 shown is an example. Switches 43, 47, 49, 51, 53, 81, 82, and 83 are controlled by control signals generated in clock generator 61. sa , sb , 1. 2. F , I , T , R control.

[0072] The A / D converter 11 repeatedly performs integration operations from the 1st to the Mth time. During these integration operations, the gain stage 15 will adjust the input value V. IN The value obtained by multiplying by the specified integral gain is used as the operation value V. OOutput the integral gain for each integral action as G(k). The letter "k" in parentheses refers to the number of integral actions (loop number), k = 1 to M. These integral gains G(k) are not constant. For example, the integral gain G(k) can be set as follows.

[0073] Integral gain G(1) = 1.5 (third integral gain)

[0074] Integral gain G(2) ~ G(M-1) = 1.0 (first integral gain)

[0075] Integral gain G(M) = 0.5 (second integral gain)

[0076] The integral gain G(1) is maximum for the first (initial) integration action. The integral gain G(M) is minimum for the Mth (final) integration action. The integral gains G(2) to G(M-1) for the second to M-1th integration actions are constant. The integral gain G is determined by storing the input value V. IN The state of the capacitor determines the input value V. IN The capacitor can be selected using the multiple switches provided by gain stage 15. The specific operation will be explained in detail later.

[0077] A / D conversion circuit 17 is based on the calculated value V provided by the output 15b of gain stage 15. O According to the first conversion reference voltage V RCH and / or the second conversion reference voltage V RCL Generate a numeric value D.

[0078] The A / D conversion circuit 17 includes comparator 17a (first comparator) and comparator 17b (second comparator). The A / D conversion circuit 17 uses both comparators 17a and 17b to generate a 1.5-bit digital value D. The digital value D represents the A / D conversion value. The A / D conversion circuit 17 can also use either comparator 17a or 17b to generate a 1-bit digital value D.

[0079] The first input of comparator 17a is connected to the output 15b of gain stage 15. The first input of comparator 17a receives the calculated value V from gain stage 15. O The second input of comparator 17a is connected to the reference voltage generator 70 via switches 17a1 and 17a2. The second input of comparator 17a receives the first converted reference voltage V from the reference voltage generator 70 (described later) under the control of switches 17a1 and 17a2. RCH Or the first conversion reference voltage V RCCH Either of the two. Switches 17a1 and 17a2 are controlled by the control signal S output from the clock generator 61. F S C control.

[0080] When performing a folded integral type A / D conversion, comparator 17a receives the first conversion reference voltage V. RCH At this time, switch 17a1 is turned on, and switch 17a2 is turned off. During cyclic A / D conversion, comparator 17a receives the first conversion reference voltage V. RCCH At this time, switch 17a2 is turned on, and switch 17a1 is turned off. Comparator 17a compares the calculated value V. O and the first conversion reference voltage V RCH Or compare the operand V O and the first conversion reference voltage V RCCH This generates bit (B1) as the comparison result signal.

[0081] In comparator 17a, a first conversion reference voltage V is provided. RCH The input can be obtained via a capacitor (not shown) and a reference potential V. COM Connection. Based on this structure, filtering for high-frequency noise can be performed.

[0082] The first input of comparator 17b is connected to the output 15b of gain stage 15. The first input of comparator 17b receives the calculated value V. O The second input of comparator 17b is connected to the reference voltage generator 70 via switches 17b1 and 17b2. The second input of comparator 17a receives the second converted reference voltage V from the reference voltage generator 70 (described later) under the control of switches 17b1 and 17b2. RCL Or the second conversion reference voltage V RCCL Either of the two. Switches 17b1 and 17b2 are controlled by the control signal S output from the clock generator 61. F S C control.

[0083] When in the folded integral type A / D conversion operation, comparator 17b receives the second conversion reference voltage V. RCL At this time, switch 17b1 is turned on, and switch 17b2 is turned off. During cyclic A / D conversion, comparator 17b receives the second conversion reference voltage V. RCCL At this time, switch 17b2 is turned on, and switch 17b1 is turned off. Comparator 17b compares the calculated value V. O Second conversion reference voltage V RCL Or compare the operation value V O Second conversion reference voltage V RCCL This generates bit (B0) as the comparison result signal.

[0084] When the A / D conversion circuit 17 generates a 1.5-bit digital value D, the digital value D can take three values ​​(D=0, D=1, D=2) for each integration operation or each cycle by combining bits (B0, B1). In this case, comparators 17a and 17b operate as follows.

[0085] V O >V RCH When D = 2 (B1 = 1, B0 = 1)

[0086] V RCL <V O ≤V RCH When D = 1 (B1 = 0, B0 = 1)

[0087] V O ≤V RCL When D = 0 (B1 = 0, B0 = 0)

[0088] Furthermore, when the A / D conversion circuit 17 generates a 1-bit digital value D, the value of D can take two values ​​(D=0 or D=1) for each integration operation or each cycle, depending on the value of bit (B1). At this time, the comparator 17a operates in the A / D conversion circuit 17. Therefore, when generating a 1-bit digital value D, the signal used as the reference is the first conversion reference voltage V. RCH In this case, comparator 17a operates as follows.

[0089] V O ≥V RCH When B1 = 1

[0090] V O <V RCH When B1 = 0

[0091] The reference voltage generator 70 is connected to the reference voltage sources 33 and 35. The reference voltage generator 70 receives the reference reference voltage V from the reference voltage source 33. RH Additionally, the reference voltage generator 70 receives the reference reference voltage V from the quasi-voltage source 35. RL The reference voltage generator 70 is connected to the A / D conversion circuit 17. The reference voltage generator 70 outputs a first conversion reference voltage V to the comparator 17a of the A / D conversion circuit 17. RCH V RCCH The reference voltage generator 70 outputs a second conversion reference voltage V to the comparator 17b of the A / D conversion circuit 17. RCL V RCCL First conversion reference voltage V RCH Second conversion reference voltage V RCL Used for folded integrating A / D conversion operation. First conversion reference voltage V RCCHSecond conversion reference voltage V RCCL Used for cyclic A / D conversion operations.

[0092] In addition, the first conversion reference voltage V RCH V RCCH Second conversion reference voltage V RCL V RCCL These can also be fixed values. Additionally, the first conversion reference voltage V... RCH V RCCH Second conversion reference voltage V RCL V RCCL It can also be a variable value. For example, in a folded integral type A / D conversion operation, the reference voltage generator 70 can also be based on the input value V received by the input 15a of the gain stage 15. IN To control the first conversion reference voltage V RCH Second conversion reference voltage V RCL Additionally, the reference voltage generator 70 can also use the calculated value V generated in the output 15b of the gain stage 15. O To control the first conversion reference voltage V RCH Second conversion reference voltage V RCL .

[0093] Logic circuit 19 is connected to D / A conversion circuit 21. Logic circuit 19 outputs a control signal V to D / A conversion circuit 21. CONT Logic circuit 19 is connected to the outputs of comparators 17a and 17b. Logic circuit 19 receives the operand value B1 from comparator 17a and the operand value B0 from comparator 17b. Logic circuit 19 can generate a control signal V corresponding to the digital value D. CONT (For example DHa , DHb , DLa , DLb ).

[0094] D / A conversion circuit 21 receives the first reference voltage V from reference voltage sources 33 and 35. RH Second reference voltage V RL The D / A conversion circuit 21 operates according to the control signal V. CONT The first reference voltage V RH Second reference voltage V RL Output to gain stage 15. D / A conversion circuit 21 has four outputs 21a1, 21a2, 21b1, 21b2 and switching circuit 31.

[0095] Output 21a1 is connected to the first capacitor 25. Output 21a1 operates according to the control signal. DHa Output the first reference voltage V to the first capacitor 25 RH Output 21b1 is connected to the second capacitor 27. Output 21b1 operates according to the control signal. DHb Output the first reference voltage V to the second capacitor 27 RH Output 21a2 is connected to the first capacitor 25. Output 21a2 operates according to the control signal. DLa Output the second reference voltage V to the first capacitor 25 RL Output 21b2 is connected to the second capacitor 27. Output 21b2 operates according to the control signal. DLb Output the second reference voltage V to the second capacitor 27 RL .

[0096] The switching circuit 31 includes switches 31a1, 31a2, 31b1, and 31b2. Switch 31a1 is connected to output 21a1 and is controlled by a control signal. DHa Switching the first reference voltage V for output 21a1 RH The supply and stop of [something]. Switch 31b1 is connected to output 21b1, and is controlled by a control signal. DHb Switching the first reference voltage V for output 21b1 RH The supply and stop. Switch 31a2 is connected to output 21a2, and is controlled by a control signal. DLa Switching the second reference voltage V for output 21a2 RL The supply and stop. Switch 31b2 is connected to output 21b2, and is controlled by a control signal. DLb Switching the second reference voltage V for output 21b2 RL The provision and cessation of [the provision / cessation of the service / service].

[0097] Next, regarding Figure 1 The first A / D conversion operation in the A / D converter 11 shown will be explained. The first A / D conversion operation is a folded integration type operation, which repeatedly samples the input signal and integrates the sampled values ​​to obtain the analog input value V. IN The output value is obtained as a digital value D. For example... Figure 2 As shown, the folded integral action includes a first storage action P1A, a first operation action P1B, a second storage action P2A, a second operation action P2B, a third storage action P3A, and a third operation action P3B.

[0098] First, the A / D converter 11 performs a first storage operation P1A and a first operation P1B. These first storage operations P1A and P1B correspond to the first (k=1) integration operation out of M integration operations. The integration gain G(1) in the first storage operation P1A and the first operation P1B is 1.5.

[0099] A / D converter 11 performs the first storage operation P1A. Figure 3 (a) represents the circuit structure in the first storage operation P1A. This circuit structure is controlled by the control signal output from the clock generator 61. DHa =0、 DHb =0、 DLa =0、 DLb =1) and control signals ( sa =1、 sb =0、 1 = 1 2 = 0 F =1、 I =1、 T =0、 R =0, S F =1, S C =0) to achieve.

[0100] according to Figure 3 In the circuit structure of (a), the first capacitor 25 is connected to the input 15a of the gain stage 15 and the second reference potential GND2. As a result, the first capacitor 25 receives the input value V. IN The second capacitor 27 is connected to the output 21b2 of the D / A conversion circuit 21 and the second reference potential GND2. As a result, the second capacitor 27 receives the second reference voltage V. RL The third capacitor 29 is connected to the input 15a of the gain stage 15 and the operational amplifier circuit 23. Specifically, one end of the third capacitor 29 is connected to the first input 23a and the output 23b of the operational amplifier circuit 23. As a result, the third capacitor 29 receives the input value V. IN That is, when the integral gain G is set to 1.5, the input value V IN It is stored in the first capacitor 25 and the third capacitor 29.

[0101] Following the first storage operation P1A, the A / D converter 11 performs the first operation P1B (see reference). Figure 2 ). Figure 3 (b) represents the circuit structure in the first operational action P1B. This circuit structure is controlled by the control signal output from the clock generator 61. DHa =1、 DHb =0、 DLa =0、 DLb =1) and control signals ( sa =0、 sb =0、 1 = 0 2 = 1 F =0、 I =0、 T =1、 R =0, S F =1, S C =0) to achieve.

[0102] according to Figure 3 In the circuit structure of (b), the first capacitor 25 is connected to the output 21a1 of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. As a result, the first capacitor 25 receives the first reference voltage V. RH The second capacitor 27 is connected to the output 21b2 of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. As a result, the second capacitor 27 receives the second reference voltage V. RL The third capacitor 29 is connected to the first input 23a and the output 23b of the operational amplifier circuit 23.

[0103] Furthermore, comparator 17a receives the first conversion reference voltage V. RCH Comparator 17a will operate on the value V. O (1) with the first conversion reference voltage V RCH The comparison is performed, and the output is the calculated value B1(1) corresponding to the comparison result. Furthermore, comparator 17b receives the second conversion reference voltage V. RCL Comparator 17b will operate on the value V. O (1) with the second conversion reference voltage V RCL Compare and output the operand B0(1) corresponding to the comparison result.

[0104] Specifically, the output (digital value D) of the A / D conversion circuit 17 is as follows.

[0105]

Mathematical Formula 1

[0106] Based on these connection structures, the operational value V is generated in the output 23b of the operational amplifier circuit 23. O (1).

[0107]

Mathematical Formula 2

[0108]

Mathematical Expression 3

[0109] Next, the A / D converter 11 alternately performs multiple second storage operations P2A and second operation operations P2B (refer to...). Figure 2 The second storage action P2A and the second operation action P2B correspond to the 2nd to the (M-1)th integration actions in the M integration actions. The integration gains G(2) to G(M-1) in the second storage action P2A and the second operation action P2B are 1.0. That is, the integration gains G(2) to G(M-1) are less than the integration gains G(1).

[0110] Figure 3 (c) represents the circuit structure in the second storage operation P2A. This circuit structure is controlled by the control signal output from the clock generator 61. DHa =0、 DHb =0、 DLa =0、 DLb =0) and control signals ( sa =1、 sb =1、 1 = 1 2 = 0 F =0、 I =0、 T =1、 R =0, S F =1, S C =0) to achieve.

[0111] according to Figure 3In the circuit structure of (c), the first capacitor 25 is connected to the input 15a of the gain stage 15 and the second reference potential GND2. As a result, the first capacitor 25 receives the input value V. IN The second capacitor 27 is connected to input 15a of gain stage 15 and the second reference potential GND2. As a result, the second capacitor 27 receives the input value V. IN The third capacitor 29 is connected to the first input 23a and the output 23b of the operational amplifier circuit 23. That is, when the integral gain G is set to 1.0, the input value V IN It is stored in the first capacitor 25 and the second capacitor 27.

[0112] Following the second storage operation P2A, the A / D converter 11 performs the second arithmetic operation P2B. For example... Figure 3 As shown in (d), the second operation P2B has the same circuit structure as the first operation P1B described above (refer to...). Figure 3 (b) is executed. Therefore, the detailed description of the second operation P2B is omitted.

[0113] In the second operation P2B, the output of the A / D conversion circuit 17 is as follows.

[0114]

Mathematical Expression 4

[0115] Based on these connection structures, the operational value V is generated in the output 23b of the operational amplifier circuit 23. O (k).

[0116]

Mathematical Expression 5

[0117]

Mathematical Expression 6

[0118] Furthermore, in the first operation P1B, the second operation P2B, and the third operation P3B (described later), a second reference voltage V may also be provided to the first capacitor 25, for example. RL Provides a first reference voltage V to the second capacitor 27 RH Furthermore, when repeating the second operational action P2B with an integral gain G of 1.0 multiple times, the following two circuit structures can be alternated: providing the first reference voltage V to the first capacitor 25. RH A second reference voltage V is provided to the second capacitor 27. RL The first circuit structure; and providing a second reference voltage V to the first capacitor 25. RL Provides a first reference voltage V to the second capacitor 27RH The second circuit structure.

[0119] Next, the A / D converter 11 performs a third storage operation P3A and a third operation P3B. These third storage operations P3A and P3B correspond to the Mth integration operation out of a total of M integration operations. The integration gain G(M) in the third storage operation P3A and P3B is 0.5. That is, the integration gain G(M) = 0.5 is less than the integration gain G(1) = 1.5. Furthermore, the integration gain G(M) = 0.5 is less than the integration gains G(2) ~ G(M-1) = 1.0.

[0120] Figure 3 (e) represents the circuit structure in the third storage operation P3A. This circuit structure is controlled by the control signal output from the clock generator 61. DHa =0、 DHb =0、 DLa =0、 DLb =1) and control signals ( sa =1、 sb =0、 1 = 1 2 = 0 F =0、 I =0、 T =1、 R =0, S F =1, S C =0) to achieve.

[0121] according to Figure 3 In the circuit structure of (e), the first capacitor 25 is connected to the input 15a of the gain stage 15 and the second reference potential GND2. As a result, the first capacitor 25 receives the input value V. IN The second capacitor 27 is connected to the output 21b2 of the D / A conversion circuit 21 and the second reference potential GND2. As a result, the second capacitor 27 receives the second reference voltage V. RL The third capacitor 29 is connected to the first input 23a and the output 23b of the operational amplifier circuit 23. That is, when the integral gain G is set to 0.5, the input value V IN It is stored only in the first capacitor 25.

[0122] Next, following the third storage operation P3A, the A / D converter 11 performs the third arithmetic operation P3B. For example... Figure 3 As shown in (f), the third operation P3B is executed by the same circuit as the first operation P1B described above. Therefore, a detailed description of the third operation P3B is omitted.

[0123] In the third operation P3B, the output of the A / D conversion circuit 17 is as follows.

[0124]

Mathematical Expression 7

[0125] Based on these connection structures, the operational value V is generated in the output 23b of the operational amplifier circuit 23. O (M).

[0126]

Mathematical Expression 8

[0127]

Mathematical Expression 9

[0128] However, when using V RCH V RCL In both cases where the reference voltage is used for conversion, a log2 (2M) bit A / D conversion can be performed through M integration operations. For example, for an input value V with an amplitude of 1V... IN , operation value V O The amplitude is 1.5V, which exceeds the 1.0V input range of the subsequent cyclic type. In this case, by reducing the stored input value V... IN The capacitance of the capacitor is used to reduce the integral gain G. By reducing this integral gain G, the calculated value V can be reduced. O The amplitude is controlled within the desired range. However, suppressing the integral gain G presents two problems.

[0129] The first problem is the decrease in the number of output bits. When using the first conversion reference voltage V... RCH Second conversion reference voltage V RCL In principle, M integrals would produce 2M (more precisely, 2M-2 or 2M-3) folds. However, to prevent the integral from diverging, if the input amplitude is set to 1V, the sum of the integral voltage (1×M×G) without folding and the folded voltage (2×M×V) needs to be equalized. R They are equal. That is, V R = (1×M×G) / (2×M) = 0.5×G. However, due to the need to share circuitry with the subsequent cyclic A / D converter, there is a V RThe relationship is equal to G, therefore the number of folds n = (M × G) / V R = (M×G) / G = M (log2(M) bits), which is 1 bit less than the original number of bits, i.e., log2(2M).

[0130] The second problem is the degradation of noise reduction performance. By changing the integral gain to 1 / 2, the noise reduction performance based on the integral decreases to 1 / √2.

[0131] Therefore, in multiple integration operations, the A / D converter 11 ensures that the number of capacitors storing the analog signal in the k-th integration operation corresponding to the next integration operation is less than the number of capacitors storing the analog signal in the (k-1)-th integration operation. According to this structure, it is possible to ensure that the integration gain G corresponding to the k-th integration operation is less than the integration gain G in the (k-1)-th integration operation in multiple integration operations. In other words, in multiple integration operations, the number of capacitors storing the input value V is not less than the number of capacitors storing the analog signal in the (k-1)-th integration operation. IN The capacitance of the capacitor is constant, but it varies according to the number of integration operations. To obtain the calculated value V through M integration operations... O Within a specified value, it is possible to achieve the calculated value V without suppressing the integral gain G for all M integral operations. O The increased integration action of the subsequent stage suppresses the integration gain G. As a result, in the (k-1)th integration action without suppressing the integration gain G, a sufficient integration gain G can be obtained, thus ensuring adequate noise reduction. On the other hand, since the integration gain G is suppressed for the subsequent integration action, it is possible to prevent the calculated value V obtained as a result of the Mth integration action from being corrupted. O Greater than the specified value.

[0132] For example, Figure 4 This is an example of the conversion characteristics of the A / D converter 11. In this example, the number of integrations is set to 5 (M=5), the integration gain G(k) is set to G(1)=1.5, G(2)=1.0, G(3)=1.0, G(4)=1.0, G(5)=0.5, and the first conversion reference voltage V is set to... RCH Set it to 1.0V, and set the second conversion reference voltage V. RCL Set to 0.5V. Curve P5a corresponds to the first integration operation, curve P5b to the second integration operation, curve P5c to the third integration operation, curve P5d to the fourth integration operation, and curve P5e to the fifth integration operation. In particular, as shown in curve P5e, even in the fifth integration operation, the calculated value V can be... OThe voltage is controlled within the desired range (1.0V in this case). Therefore, the A / D converter 11 of this embodiment can control the calculation result of the integration operation within the desired range, and can obtain good noise reduction and high resolution.

[0133] In summary, in the A / D converter 11 employing folded integration for an image sensor, the integration gain G is made variable during multiple integration operations. As a result, the A / D converter 11 according to the first embodiment can improve the resolution by 1 bit and can increase the integration gain by 2 times (S / N is √2 times). Therefore, the A / D converter 11 of the first embodiment has the characteristics of high resolution and low noise.

[0134] Next, regarding Figure 1 The second A / D conversion operation in the A / D converter 11 shown will be explained. The second A / D conversion operation is a cyclic A / D conversion operation Y. Hereinafter, the cyclic A / D conversion operation Y in the A / D converter 11 will be explained.

[0135] Figure 5 of (a) Figure 5 (b) and Figure 5 (c) is a circuit diagram illustrating the second A / D conversion operation. In the second A / D conversion operation, the A / D conversion circuit 17 uses two comparators 17a and 17b to generate the digital value D.

[0136] First, such as Figure 5 As shown in (a), gain stage 15 performs a second initial storage operation Y1A. In the second initial storage operation Y1A, the calculated value V in the folded integral-type A / D conversion operation P is... O (M) is stored in the first capacitor 25, the second capacitor 27, and the third capacitor 29. In the second initial storage operation Y1A, the gain stage 15 receives the control signal ( sa =0、 sb =0、 1 = 1 2 = 0 F =1、 I =0、 T =1、 R =1, S F =0, S C =1). Additionally, the D / A conversion circuit 21 receives control signals ( DHa =0、 DHb =0、 DLa =0、 DLb =0). Additionally, in the second initial storage action Y1A, the calculated value V in the folded integral-type A / D conversion action is... O (M) is provided to comparators 17a and 17b. Comparators 17a and 17b are based on the provided operand value V. O (M), generate the numeric value D.

[0137] Next, as Figure 5 (b) or Figure 5 As shown in (c), after the second initial storage operation Y1A, gain stage 15 performs the second operation Y1B according to the value of the digital value D (=B1+B0). In the second operation Y1B, gain stage 15 generates the operation value V from operational amplifier circuit 23, first capacitor 25, second capacitor 27 and third capacitor 29. O .

[0138] In the second operation Y1B, gain stage 15 receives the control signal ( sa =0、 sb =0、 1 = 0 2 = 1 F =0、 I =0、 T =1、 R =0, S F =0, S C =1). In the second operational operation Y1B, the third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a. The first capacitor 25 and the second capacitor 27 are connected to the D / A conversion circuit 21, but the voltage supplied to the first capacitor 25 and the second capacitor 27 is controlled according to the digital value D (=B1+B0).

[0139] When D=2, the switching circuit 31 receives the control signal ( DHa =1、 DHb =1、 DLa =0、 DLb =0). As a result, when D=2, the first reference voltage V RHThe outputs 21a1 and 21b1 of the D / A conversion circuit 21 are provided. In this case, the first capacitor 25 and the second capacitor 27 respectively receive the first reference voltage V. RH .

[0140] When D=0, the switching circuit 31 receives the control signal ( DHa =0、 DHb =0、 DLa =1、 DLb =1). As a result, when D=0, the second reference voltage V RL The outputs 21a2 and 21b2 of the D / A conversion circuit 21 are provided. In this case, the first capacitor 25 and the second capacitor 27 respectively receive the second reference voltage V. RL .

[0141] When D=1, the switching circuit 31 receives the control signal ( DHa =1、 DHb =0、 DLa =0、 DLb =1). As a result, when D=1, the first reference voltage V RH The output 21a1 is provided to the D / A conversion circuit 21. The second reference voltage V... RL It is supplied to output 21b2. In this case, the first capacitor 25 receives the first reference voltage V. RH The second capacitor 27 receives the second reference voltage V. RL .

[0142] Next, as Figure 5 As shown in (a), after the second operation Y1B, gain stage 15 performs the second storage operation Y1A. In the second storage operation Y1A, the operation value V from the second operation Y1B is stored... O The storage in the first capacitor 25, the second capacitor 27, and the third capacitor 29 is different from the second initial storage action Y1A.

[0143] Then, gain stage 15, acting as a cyclic A / D conversion operation, repeatedly performs the second operation Y1B and the second storage operation Y1A a predetermined number of times. Let D(j) represent the calculated value V after M integration operations. O (M) The numerical value obtained after the j-th iteration is the calculated value V. O (M)-V COMThe relationship between the numerical value D(j) and the numerical value is represented by equation (10).

[0144]

Mathematical Formula 10

[0145] <Second Implementation>

[0146] Furthermore, the integration gain G that can be set in the A / D converter 11 of the first embodiment is, for example, 1.5, 1.0, and 0.5. As shown in the following variations, in addition to these, the A / D converter 11A can also be set to 2.0 or 0 as the integration gain G. That is, the scale of the integration gain G that can be set in the A / D converter 11A of the first embodiment is 0.5. The A / D converter of the second embodiment can be set to have a finer scale interval for the integration gain G than the A / D converter of the first embodiment.

[0147] Figure 6 This is a circuit diagram of the A / D converter 11A according to the second embodiment. Figure 1 The difference in the first embodiment of the A / D converter 11 is that the second capacitor 27 of the A / D converter 11 is divided into two capacitors (second capacitor 28A and fourth capacitor 28B). That is, the A / D converter 11A of the second embodiment has a first capacitor 25, a second capacitor 28A, a third capacitor 29, and a fourth capacitor 28B. Moreover, when the capacitance of the third capacitor 29 is set to C, the capacitance relationship of each capacitor is as follows.

[0148] The capacitance C of the first capacitor 25 1a C / 2

[0149] The capacitance C of the second capacitor is 28A. 1ba C / 4

[0150] The capacitance C2 of the third capacitor 29: C

[0151] The capacitance C of the fourth capacitor 28B 1bb C / 4 (Fourth capacitor)

[0152] The fourth capacitor 28B is connected in parallel with the second capacitor 28A. Therefore, the combined capacitance of the second capacitor 28A and the fourth capacitor 28B in the second embodiment is equivalent to the capacitance C of the second capacitor 27 in the first embodiment. 1b In other words, it can also be said that the portion of the second capacitor 27 in the first embodiment after being divided is the second capacitor 28A and the fourth capacitor 28B in the second embodiment.

[0153] For example, the integral gain G(k) can be set as follows. That is, in the A / D converter 11A, the integral gain G can be set to 0.25 scale intervals.

[0154] Integral gain G(1) = 1.75

[0155] The integral gain G(2) ~ G(M-1) = 1.0

[0156] Integral gain G(M) = 0.25

[0157] Furthermore, the value of the integral gain G(k) mentioned above is an example.

[0158] Furthermore, the combined capacitance of the second capacitor 28A and the fourth capacitor 28B only needs to be the same as the capacitance of the second capacitor 27. Therefore, the capacitance C of the second capacitor 28A is... 1ba And the capacitance C of the fourth capacitor 28B 1bb Not limited to the same as above (=C / 4). For example, the capacitance C of the second capacitor 28A can also be... 1ba Set the capacitance C of the fourth capacitor 28B to 0.1×C. 1bb Set it to 0.4 × C.

[0159] Furthermore, two switches 84 and 85 are added to the A / D converter 11A. Switch 84 connects the reference voltage source 35 to the fourth capacitor 28B. Switch 85 connects the input 15a of the gain stage 15A to the fourth capacitor 28B.

[0160] The operation of the A / D converter 11A is explained. For example... Figure 7 As shown, the A / D converter 11A performs a first storage operation P1A and a first operation P1B. These first storage operation P1A and first operation P1B correspond to the first integration operation in an M-fold integration process (see reference). Figure 7 The integral gain G(1) in the first storage action P1A and the first operation action P1B is 1.75.

[0161] A / D converter 11A performs the first storage operation P1A. Figure 8 (a) represents the circuit structure in the first storage operation P1A. This circuit structure is controlled by the control signal output from the clock generator 61. DHa =0、 DHb =0、 DLa =0、 DLb =0) and control signals ( sa =1、 sb =1、 1 = 1 2 = 0 3 = 0 4 = 1 F =1、 I =1、 T =0、 R =0, S F =1, S C =0) to achieve.

[0162] according to Figure 8 In the circuit structure of (a), the first capacitor 25 is connected to the input 15a of the gain stage 15A and the second reference potential GND2. As a result, the first capacitor 25 receives the input value V. IN The second capacitor 28A is connected to input 15a of the gain stage 15A and the second reference potential GND2. As a result, the second capacitor 28A also receives the input value V. IN The third capacitor 29 is connected to input 15a of gain stage 15A and operational amplifier circuit 23. Specifically, one end of the third capacitor 29 is connected to the first input 23a and output 23b of operational amplifier circuit 23. As a result, the third capacitor 29 also receives the input value V. IN The fourth capacitor 28B is connected to the reference voltage source 35 and the second reference potential GND2. As a result, the fourth capacitor 28B receives the second reference voltage V. RL That is, with the integral gain G set to 1.75, the input value V... IN It is stored in the first capacitor 25, the second capacitor 28A and the third capacitor 29.

[0163] Following the first storage operation P1A, the A / D converter 11A performs the first operation P1B. Figure 8 (b) represents the circuit structure in the first operational action P1B. This circuit structure is controlled by the control signal output from the clock generator 61. DHa =1、 DHb =0、 DLa =0、 DLb =1) and control signals ( sa =0、 sb =0、 1 = 0 2 = 1 3 = 0 4 = 1 F =0、 I =0、 T =1、 R =0, S F =1, S C =0) to achieve.

[0164] according to Figure 8 In the circuit structure of (b), the first capacitor 25 is connected to the output 21a1 of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. As a result, the first capacitor 25 receives the first reference voltage V. RH The second capacitor 28A is connected to the output 21b2 of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. As a result, the second capacitor 28A receives the second reference voltage V. RL The third capacitor 29 is connected to the first input 23a and the output 23b of the operational amplifier circuit 23. The fourth capacitor 28B is connected to the reference voltage source 35 and the first input 23a of the operational amplifier circuit 23. As a result, the fourth capacitor 28B receives the second reference voltage V. RL .

[0165] Furthermore, comparator 17a receives the first conversion reference voltage V. RCH Comparator 17a will operate on the value V. O (1) with the first conversion reference voltage V RCH The comparison is performed, and the output is the calculated value B1(1) corresponding to the comparison result. Furthermore, comparator 17b receives the second conversion reference voltage V. RCL Comparator 17b will operate on the value V. O (1) with the second conversion reference voltage V RCL Compare and output the operand B0(1) corresponding to the comparison result.

[0166] Specifically, the output (digital value D) of the A / D conversion circuit 17 is as follows.

[0167]

Mathematical Expression 11

[0168] Based on this connection structure, the operational value V is generated in the output 23b of the operational amplifier circuit 23. O (1).

[0169]

Mathematical Expression 12

[0170]

Mathematical Expression 13

[0171] Next, the A / D converter 11A performs the second storage operation P2A and the second operation P2B. The integral gain G(2) in the second storage operation P2A and the second operation P2B is 1.0.

[0172] Figure 8 (c) represents the circuit structure in the second storage action P2A where the integral gain G(2) = 1.0. This circuit structure is controlled by the control signal output from the clock generator 61. DHa =0、 DHb =0、 DLa =0、 DLb =0) and control signals ( sa =1、 sb =1、 1 = 1 2 = 0 3 = 1 4 = 0 F =0、 I =0、 T =1、 R =0, S F =1, S C =0) to achieve.

[0173] according to Figure 8 In the circuit structure of (c), the first capacitor 25 is connected to the input 15a of the gain stage 15A and the second reference potential GND2. As a result, the first capacitor 25 receives the input value V. IN The second capacitor 28A is connected to input 15a of the gain stage 15A and the second reference potential GND2. As a result, the second capacitor 28A also receives the input value V. IN The third capacitor 29 is connected to the first input 23a and the output 23b of the operational amplifier circuit 23. The fourth capacitor 28B is connected to the input 15a of the gain stage 15A and the second reference potential GND2. As a result, the fourth capacitor 28B also receives the input value V. IN .

[0174] That is, when the integral gain G is set to 1.0, the input value V INIt is stored in the first capacitor 25, the second capacitor 28A and the fourth capacitor 28B.

[0175] Following the second storage action P2A, such as Figure 8 As described in (d), the A / D converter 11A performs a second operation P2B. The second operation P2B has the same circuit structure as the first operation P1B described above (see [reference]). Figure 8 (b) is executed. Therefore, the detailed description of the second operation P2B is omitted.

[0176] In the second operation P2B, the output of the A / D conversion circuit 17 is as follows.

[0177]

Mathematical Expression 14

[0178] Based on these connection structures, the operational value V is generated in the output 23b of the operational amplifier circuit 23. O (k).

[0179]

Mathematical Expression 15

[0180]

Mathematical Expression 16

[0181] Next, the A / D converter 11A performs the third storage operation P3A and the third operation P3B. The integral gain G(M) in the third storage operation P3A and the third operation P3B is 0.25. Figure 8 (e) represents the circuit structure in the third storage operation P3A. This circuit structure is controlled by the control signal output from the clock generator 61. DHa =0、 DHb =0、 DLa =1、 DLb =0) and control signals ( sa =0、 sb =1、 1 = 1 2 = 0 3 = 0 4 = 1 F =0、 I =0、 T =1、 R =0, S F =1, S C =0) to achieve.

[0182] according to Figure 8 In the circuit structure of (e), the first capacitor 25 is connected to the output 21a2 of the D / A conversion circuit 21 and the second reference potential GND2. As a result, the first capacitor 25 receives the second reference voltage V. RL The second capacitor 28A is connected to input 15a of the gain stage 15A and the second reference potential GND2. As a result, the second capacitor 28A receives the input value V. IN The third capacitor 29 is connected to the first input 23a and the output 23b of the operational amplifier circuit 23. The fourth capacitor 28B is connected to the reference voltage source 35 and the second reference potential GND2. As a result, the fourth capacitor 28B also receives the second reference voltage V. RL .

[0183] That is, when the integral gain G is set to 0.25, the input value V IN It is stored only in the second capacitor 28A.

[0184] Following the third storage action P3A, such as Figure 8 As shown in (f), the A / D converter 11A performs the third operation P3B. The third operation P3B has the same circuit structure as the first operation P1B described above (see reference). Figure 8 (b) is executed. Therefore, the detailed description of the third operation P3B is omitted.

[0185] In the third operation P3B, the output of the A / D conversion circuit 17 is as follows.

[0186]

Mathematical Expression 17

[0187] Based on these connection structures, the operational value V is generated in the output 23b of the operational amplifier circuit 23. O (M).

[0188]

Mathematical Expression 18

[0189]

Mathematical Expression 19

[0190] Next, regarding Figure 6 The second A / D conversion operation in the A / D converter 11A shown will be explained. The cyclic A / D conversion operation in the A / D converter 11A will be explained below.

[0191] Figure 9 of (a) Figure 9 (b) and Figure 9 (c) is a circuit diagram used to illustrate the second A / D conversion operation.

[0192] First, such as Figure 9 As shown in (a), gain stage 15A performs a second initial storage operation Y1A. In the second initial storage operation Y1A, the calculated value V in the folded integral-type A / D conversion operation P is... O (M) is stored in the first capacitor 25, the second capacitor 28A, the third capacitor 29, and the fourth capacitor 28B. In the second initial storage operation Y1A, the gain stage 15A receives the control signal ( sa =0、 sb =0、 1 = 1 2 = 0 3 = 1 4 = 0 F =1、 I =0、 T =1、 R =1, S F =0, S C =1). Additionally, the D / A conversion circuit 21 receives control signals ( DHa =0、 DHb =0、 DLa =0、 DLb =0). Additionally, in the second initial storage action Y1A, the calculated value V in the folded integral-type A / D conversion action is... O (M) is provided to comparators 17a and 17b. Comparators 17a and 17b are based on the provided operand value V. O (M) Generates the numeric value D.

[0193] Next, as Figure 9 (b) or Figure 9 As shown in (c), after the second initial storage operation Y1A, the gain stage 15A performs the second operation Y1B according to the value of the digital value D (=B1+B0). In the second operation Y1B, the gain stage 15A generates the operation value V through the operational amplifier circuit 23, the first capacitor 25, the second capacitor 28A, the third capacitor 29, and the fourth capacitor 28B.O .

[0194] When the output of A / D conversion circuit 17 is D=2, switching circuit 31 receives control signal ( DHa =1、 DHb =1、 DLa =0、 DLb =0). Additionally, when the output of the A / D conversion circuit 17 is D=2, the gain stage 15A receives the control signal ( sa =0、 sb =0、 1 = 0 2 = 1 3 = 1 4 = 0 F =0、 I =0、 T =1、 R =0, S F =0, S C =1). The result is that... Figure 9 The operation of the circuit shown in (b). That is, the first capacitor 25, the second capacitor 28A, and the fourth capacitor 28B respectively receive the first reference voltage V. RH .

[0195] When the output of A / D conversion circuit 17 is D=0, switching circuit 31 receives control signal ( DHa =0、 DHb =0、 DLa =1、 DLb =1). Additionally, when the output of the A / D conversion circuit 17 is D=0, the gain stage 15A receives the control signal ( sa =0、 sb =0、 1 = 0 2 = 1 3 = 0 4 = 1 F =0、 I =0、 T =1、 R =0, S F =0, S C =1). The result is that... Figure 9 The operation of the circuit shown in (b). That is, the first capacitor 25, the second capacitor 28A, and the fourth capacitor 28B respectively receive the second reference voltage V. RL .

[0196] When the output of A / D conversion circuit 17 is D=1, switching circuit 31 receives control signal ( DHa =1、 DHb =0、 DLa =0、 DLb =1). Additionally, when the output of the A / D conversion circuit 17 is D=1, the gain stage 15A receives the control signal ( sa =0、 sb =0、 1 = 0 2 = 1 3 = 0 4 = 1 F =0、 I =0、 T =1、 R =0, S F =0, S C =1). The result is that... Figure 9 The operation of the circuit shown in (c). That is, the first capacitor 25 receives the first reference voltage V. RH The second capacitor 28A and the fourth capacitor 28B respectively receive the second reference voltage V. RL .

[0197] Then, gain stage 15A, acting as a cyclic A / D conversion operation, repeatedly performs the second storage operation Y1A and the second operation Y1B a predetermined number of times. As a result, an output value as a digital value is obtained from the input value, which is an analog value.

[0198] Even with the A / D converter 11A of the second embodiment, the result of the integration operation can be controlled within the desired range in the same way as the A / D converter 11 of the first embodiment, and a good noise reduction effect can be obtained. Furthermore, by dividing the second capacitor 27 in the first embodiment into a second capacitor 28A and a fourth capacitor 28B, that is, increasing the number of capacitors storing analog signals, the A / D converter 11A of the second embodiment can set the integration gain G more precisely than the A / D converter 11 of the first embodiment.

[0199] The A / D converter and A / D conversion method of this disclosure have been described above. The A / D converter and A / D conversion method of this disclosure are not limited to the embodiments described above.

[0200] <Variation Example 1>

[0201] In the M-fold integral-type A / D conversion operation, the setting of the integral gain G is not limited to the method described in the first embodiment. In Variation 1, as... Figure 10 As shown, the integral gain G(k) can be set as follows.

[0202] Integral gain G(1) = 2.0

[0203] The integral gain G(2) ~ G(M-1) = 1.0

[0204] Integral gain G(M) = 0

[0205] That is, in Modification 1, the integral gain G(1) in the first integration operation is set to 2. Then, the integral gain G(M) in the Mth integration operation is set to 0. Furthermore, the integral gains G(2) to G(M-1) in the second to the (M-1)th integration operations are the same as those in the first embodiment (=1).

[0206] Figure 11 (a) represents the circuit structure in the first storage action P1A where the integral gain G(1) = 2.0. Figure 11 (e) represents the circuit structure in the third stored action PNA where the integral gain G(M) = 0. Furthermore, Figure 11 of (b) Figure 11 (c) Figure 11 of (d), Figure 11 The circuit structure shown in (f) is respectively the same as that described in the first embodiment. Figure 3 of (b) Figure 3 (c) Figure 3 of (d), Figure 3 The same as (f).

[0207] Figure 11The circuit structure shown in (a) is controlled by the control signal output from the clock generator 61. DHa =0、 DHb =0、 DLa =0、 DLb =0) and control signals ( sa =1、 sb =1、 1 = 1 2 = 0 F =1、 I =1、 T =0、 R =0, S F =1, S C =0) to achieve.

[0208] according to Figure 11 In the circuit structure of (a), the first capacitor 25 is connected to the input 15a of the gain stage 15 and the second reference potential GND2. As a result, the first capacitor 25 receives the input value V. IN The second capacitor 27 is connected to input 15a of gain stage 15 and the second reference potential GND2. As a result, the second capacitor 27 also receives the input value V. IN The third capacitor 29 is connected to input 15a of gain stage 15 and operational amplifier circuit 23. As a result, the third capacitor 29 also receives the input value V. IN That is, when the integral gain G is set to 2.0, the input value V IN It is stored in the first capacitor 25, the second capacitor 27 and the third capacitor 29.

[0209] Figure 11 The circuit structure shown in (e) consists of control signals output from clock generator 61. DHa =0、 DHb =0、 DLa =1、 DLb =1) and control signals ( sa =0、 sb =0、 1 = 1 2 = 0 F =0、 I =0、 T =1、 R =0, S F =1, S C =0) to achieve.

[0210] according to Figure 11 In the circuit structure of (e), the first capacitor 25 is connected to the output 21a2 of the D / A conversion circuit 21 and the second reference potential GND2. As a result, the first capacitor 25 receives the second reference voltage V. RL The second capacitor 27 is connected to the output 21b2 of the D / A conversion circuit 21 and the second reference potential GND2. Consequently, the second capacitor 27 also receives the second reference voltage V. RL The third capacitor 29 is connected to the first input 23a and the output 23b of the operational amplifier circuit 23. That is, when the integral gain G is set to 0, the input value V IN It is not stored in any capacitor.

[0211] <Variation Example 2>

[0212] Furthermore, in variation example 2, such as Figure 12 As shown in (a), the integral gain G(k) can be set as follows.

[0213] Integral gain G(1) = 0.5

[0214] Integral gain G(2) ~ G(M) = 1.0

[0215] Integral gain G(M+1) = 0.5

[0216] That is, in variation example 2, the integral gain G(1) in the first integral action is set to 0.5. The integral gains G(2) to G(M) in the second to the Mth integral actions are 1.0, and the integral gain G(M+1) in the (M+1)th integral action is 0.5.

[0217] <Variation Example 3>

[0218] Furthermore, in variation example 3, such as Figure 12 As described in (b), the integral gain G(k) can be set as follows.

[0219] Integral gain G(1)~G(M)=1.0

[0220] Integral gain G(M+1) = 0

[0221] That is, in variation 3, the integral gain G(1) to G(M) for the first to the Mth integral actions is set to 1. Moreover, the integral gain G(M+1) for the (M+1)th integral action is set to 0.

[0222] The A / D converters exemplified above can be applied to image sensor devices. Figure 13 This is an attached diagram showing the pixels of an image sensor. The image sensor device has a cell array and a converter array. The cell array includes a plurality of image sensor cells 2a arranged in a two-dimensional configuration. The converter array is connected to the cell array and includes a plurality of A / D converters 11. The A / D converters 11 are connected to the image sensor cells 2a via column lines 8 of the cell array.

[0223] Image sensor unit 2a is, for example, a CMOS image sensor unit. Photodiode DF receives light L from a pixel associated with the image. Selection transistor M... S The gate of the transistor is connected to the row select line S extending along the row direction. The reset transistor M... R The gate of the transfer transistor M is connected to the reset line R. T The gate of the photodiode DF is connected to the transmission selection line TX, which extends along the row direction. One end of the photodiode DF is connected to the transfer transistor M. T It is connected to the floating diffusion layer FD. The floating diffusion layer FD is connected via the reset transistor M. R Connected to the reset potential line Reset, and to transistor M A The gate connection. Transistor M A A current terminal (e.g., drain) is connected via a select transistor M S Connected to column line 8. Transistor M A Based on the charge amount of the floating diffusion layer FD, via the selection transistor M S Provide potential to the column lines.

[0224] The image sensor unit 2a of this structure generates a first signal representing a reset level and a second signal superimposed on the reset level, representing the signal level. That is, in the image sensor unit 2a, firstly, a control signal provided to the reset line R is provided to the reset transistor M. R The floating diffusion layer FD is reset. This is achieved via transistor M. A The reset level is read. Then, the charge transfer control signal is provided to the transfer transistor M. T The photosensitive signal charge is transferred from the photodiode DF to the floating diffuser layer FD. Then, it is transmitted via transistor M. A The signal level is read out. In this way, the image sensor unit 2a can generate a first signal S1 representing the reset level and a second signal S2 representing the signal level superimposed on the reset level.

[0225] <Analysis Example 1>

[0226] Figure 14 (a) represents the relationship between the input and output of gain stage 15. Figure 14 (a) shows the simulation results. The horizontal axis represents the input value V. IN The vertical axis represents the calculated value V. O Furthermore, in this simulation, the number of integration operations is set to 16 (M = 16, 5 bits). Moreover, in the 16 integration operations, the integration gain G(1) for the first operation is set to 1.5, the integration gains G(2) to G(15) for the second to fifteenth operations are set to 1.0, and the integration gain G(16) for the sixteenth operation is set to 0.5. Furthermore, the following values ​​are used for simulation.

[0227] First reference voltage / V RH 2.0V

[0228] Second reference voltage / V RL 1.0V

[0229] First conversion reference voltage / Folded integral type / V RCH 1.95V

[0230] Second conversion reference voltage / Folded integral type / V RCL 1.55V

[0231] In addition, the values ​​used for cyclic actions are as follows.

[0232] First conversion reference voltage / cyclic type / V RCCH 1.625V

[0233] Second conversion reference voltage / cyclic type / V RCCL 1.375V

[0234] like Figure 14 As shown in (a), the operand V, which is output, can be... O The range is controlled within +1V to +2V. Furthermore, based on the aforementioned integral gain G setting, the average integral gain over 16 integration operations is 1. That is, it can be seen that although the average integral gain is set to 1, the calculated value V can still be... O The integral gain is controlled within the desired range (+1V to +2V). In this case, the integral gain is twice that of the case where the integral gain from the 1st to the 16th iteration is set to 0.5. As a result, it can be confirmed that the S / N ratio for random noise is improved by √2 times. Moreover, by setting the integral gain G(2) to G(15) to 1.0, a match with the folding voltage (0.5V) is achieved. As a result, it can be confirmed that log2 (2M) bits are obtained as the resolution.

[0235] in addition, Figure 14 (b) is a graph evaluating the integral nonlinearity of the above-mentioned configuration combined with 7-cycle A / D conversion (8-bit) in the overall A / D conversion operation. Based on this... Figure 14 (b) confirms that the nonlinearity is controlled within a width of ±0.5 bits. Based on this range, it can also be confirmed that there is no significant impact on the required number of bits.

[0236] <Analysis of Example 2>

[0237] Figure 15 (a) is another simulation result showing the relationship between the input and output of gain stage 15. In this simulation, the number of integrations was set to 17 (M = 17, 5 bits). Moreover, in the 17 integration operations, the integration gain G(1) of the first integration was set to 0.5, the integration gains G(2) to G(16) of the second to the 16th integrations were set to 1.0, and the integration gain G(17) of the 17th integration was set to 0.5. Furthermore, for the simulation, the same values ​​as in analytical example 1 were used.

[0238] First reference voltage / V RH 2.0V

[0239] Second reference voltage / V RL 1.0V

[0240] First conversion reference voltage / Folded integral type / V RCH 1.95V

[0241] Second conversion reference voltage / Folded integral type / V RCL 1.55V

[0242] In addition, the values ​​used for cyclic actions are as follows.

[0243] First conversion reference voltage / cyclic type / V RCCH 1.625V

[0244] Second conversion reference voltage / cyclic type / V RCCL 1.375V

[0245] like Figure 15 As shown in (a), by setting the above-mentioned integral gain G, the calculated output value V can be confirmed. O The range is also controlled within +1V to +2V. Additionally, Figure 15 (b) is a graph evaluating the integral nonlinearity of the above-mentioned configuration combined with 7-cycle A / D conversion (8-bit) in the overall A / D conversion operation. Based on this... Figure 15As with analytical example 1, (b) confirms that the nonlinearity is controlled within a width of ±0.5 bits. Based on this range, it can be confirmed that there is no significant impact on the required number of bits.

[0246] <Analysis of Example 3>

[0247] Figure 16 (a) shows the simulation results of the input-output relationship considering the cyclic action in addition to the folded integral type A / D conversion action. In this simulation, the number of integrations was set to 16 (M = 16, 5 bits). Moreover, in the 16 integration actions, the first integration gain G(1) was set to 2.0, the second to the 15th integration gains G(2) to G(15) were set to 1.0, and the 16th integration gain G(16) was set to 0. Furthermore, the following values ​​were used for the simulation.

[0248] First reference voltage / V RH 2.0V

[0249] Second reference voltage / V RL 1.0V

[0250] First conversion reference voltage / Folded integral type / V RCH 2.1V

[0251] Second conversion reference voltage / Folded integral type / V RCL 1.6V

[0252] In addition, the values ​​used for cyclic actions are as follows.

[0253] First conversion reference voltage / cyclic type / V RCCH 1.625V

[0254] Second conversion reference voltage / cyclic type / V RCCL 1.375V

[0255] like Figure 16 As shown in (a), it can be confirmed that the output range can be controlled within the range of +1.0V to +1.6V (0.6V). Furthermore, Figure 16 (b) is a graph evaluating the integral nonlinearity of the overall A / D conversion operation under the aforementioned voltage setting, comparing the folded integral type A / D conversion operation with 8 integration cycles (M=8, 4 bits) and the cyclic type A / D conversion operation with 8 integration cycles (9 bits). Based on this... Figure 16 (b) When the amplifier gain is 85dB, it can be confirmed that the mismatch error, representing nonlinearity, is 0.1%.

[0256] [nearby]

[0257] The A / D converter and A / D conversion method described above are as follows [1] to

[11] . They are described in detail based on the above embodiments and variations.

[0258] [1] The first example is an A / D converter that performs A / D conversion including folded integration, wherein the folded integration obtains a digital value from an analog signal by repeatedly sampling the input signal and integrating the sampled values. The A / D converter has: a gain stage that outputs an operational value based on the analog signal; and an A / D conversion circuit that outputs a result that can be used to generate the digital value by comparing the operational value output by the gain stage with a conversion reference voltage; wherein in the M operations (M is an integer greater than or equal to 2), the gain stage uses a first integral gain to generate the operational value based on the analog signal in the kth operation (k is an integer less than or equal to M-1), and uses a second integral gain to generate the operational value based on the analog signal in the (k+1)th operation, wherein the second integral gain is less than the first integral gain.

[0259] [2] In the second example, according to the A / D converter of the first example, the gain stage generates the calculated value based on the analog signal using a third integral gain in the first operation, the third integral gain being greater than the first integral gain.

[0260] [3] In the third example, according to the A / D converter of the first or second example, the third A / D converter uses the first integral gain in the second to the (M-1)th operations of the first A / D converter or the second A / D converter, and uses the second integral gain in the (M)th operation.

[0261] [4] In the fourth example, the A / D converter selected from the first, second and third examples has a first integral gain of 1 or more and a second integral gain of 0 or more and less than 1.

[0262] [5] The fifth example is an A / D converter that performs A / D conversion including folded integration, wherein the folded integration obtains a digital value from an analog signal by repeatedly sampling the input signal and integrating the sampled values. The A / D converter has: a gain stage that outputs an operational value based on the analog signal; and an A / D conversion circuit that compares the operational value output by the gain stage with a conversion reference voltage and outputs a result that can be used to generate the digital value. The gain stage has: a stage input that receives the analog signal; an operational amplifier circuit that generates the operational value based on the analog signal; a stage output that outputs the operational value to the A / D conversion circuit; a pre-stage capacitor section that can be connected to the stage input and the input of the operational amplifier circuit, including at least one pre-stage capacitor; and a feedback capacitor section that can be connected to the stage input and the output of the operational amplifier circuit, including a feedback capacitor; the gain stage selectively constitutes a first circuit and a second circuit different from the first circuit in the sampling of the input signal. The first circuit, in order to set the ratio of the capacitance of the pre-stage capacitor to the capacitance of the feedback capacitor to a predetermined capacitance ratio, stores the analog signal in at least one pre-stage capacitor by connecting the pre-stage capacitor to the stage input, and stores the analog signal in the feedback capacitor by connecting the feedback capacitor to the stage input; the second circuit, in order to set the ratio of the capacitance of the pre-stage capacitor to the capacitance of the feedback capacitor to a capacitance ratio smaller than that of the first circuit, stores the analog signal in at least one pre-stage capacitor by connecting the pre-stage capacitor to the stage input, and does not store the analog signal in the feedback capacitor by disconnecting the feedback capacitor from the stage input.

[0263] [6] In the sixth example, according to the A / D converter of the fifth example, the ratio of the capacitance of the front stage capacitor section to the capacitance of the feedback capacitor section corresponds to the magnitude of the integral gain.

[0264] [7] In the seventh example, according to the A / D converter of the fifth or sixth example, the operation is performed M times (M is an integer greater than or equal to 2). In the sampling of the input signal in the first operation, the first circuit is used in order to set the ratio of the capacitance of the front capacitor section to the capacitance of the feedback capacitor section to the predetermined capacitance ratio.

[0265] [8] In the eighth example, according to the A / D converter selected from the fifth, sixth and seventh examples, the operation is performed M times (M is an integer greater than 2). In the sampling of the input signal in the second to the M-1th operation, in order to set the ratio of the capacitance of the front stage capacitor to the capacitance of the feedback capacitor to be smaller than the predetermined capacitance ratio in the first circuit, the second circuit is used.

[0266] [9] Ninth Example: According to the A / D converter selected from the fifth, sixth, seventh, and eighth examples, the operation is performed M times (M is an integer greater than or equal to 2). In the sampling of the input signal in the second to the (M-1)th operation, in order to set the ratio of the capacitance of the front-stage capacitor to the capacitance of the feedback capacitor to a first capacitance ratio smaller than the predetermined capacitance ratio in the first circuit, in the second circuit, the number of the front-stage capacitor storing the analog signal is set to 2 or more. In the sampling of the input signal in the Mth operation, in order to set the ratio of the capacitance of the front-stage capacitor to the capacitance of the feedback capacitor to a second capacitance ratio smaller than the first capacitance ratio, in the second circuit, the number of the front-stage capacitor storing the analog signal is set to 0 or 1.

[0267]

[10] In the tenth example, according to the A / D converter selected from the fifth, sixth, seventh, eighth and ninth examples, the capacitance of the feedback capacitor is greater than the capacitance of the preceding capacitor.

[0268]

[11] In the eleventh example, according to the A / D converter selected from the fifth, sixth, seventh, eighth and ninth examples, the capacitance of the feedback capacitor is greater than the capacitance of the first pre-stage capacitor, and the capacitance of the first pre-stage capacitor is different from the capacitance of the second pre-stage capacitor, which is different from the first pre-stage capacitor.

[0269]

[12] The twelfth example is an A / D conversion method that performs A / D conversion including folded integration, wherein the folded integration obtains a digital value from an analog signal by repeatedly sampling the input signal and integrating the sampled values. The A / D conversion method includes: generating a first operational value based on the analog signal by performing the action using a first integral gain; and after generating the first operational value, generating a second operational value based on the analog signal by performing the action using a second integral gain; wherein the second integral gain is less than the first integral gain.

[0270]

[13] The thirteenth example, according to the A / D conversion method of the twelfth example, further includes: before the step of generating the first operational value, a step of generating a third operational value based on the analog signal by performing the action using a third integral gain, wherein the third integral gain is greater than the first integral gain.

[0271]

[14] In the fourteenth example, according to the A / D conversion method of the twelfth or thirteenth example, the action is performed M times (M is an integer greater than 2). In the second action to the (M-1)th action, the step of generating the first operation value is performed. In the Mth action, the step of generating the second operation value is performed.

[0272]

[15] In the fifteenth case, the A / D conversion method selected from the twelfth, thirteenth and fourteenth cases is such that the first integral gain is greater than or equal to 1 and the second integral gain is greater than or equal to 0 and less than 1.

[0273]

[16] The sixteenth example is an A / D conversion method that performs A / D conversion including folded integration, wherein the folded integration obtains a digital value from an analog signal by repeatedly sampling the input signal and integrating the sampled values. The A / D conversion method includes: a sampling step of the input signal, wherein the analog signal is stored at least in a pre-stage capacitor section and a feedback capacitor section connected to the stage input of a gain stage for outputting an operational value based on the analog signal; the pre-stage capacitor section includes at least one pre-stage capacitor, and the feedback capacitor section includes a feedback capacitor; and an integration step of the sampled values, wherein the operational value is generated at the output of the operational amplifier circuit by connecting at least the pre-stage capacitor section to the input of the operational amplifier circuit of the gain stage. In the input signal sampling step, either a first storage or a second storage different from the first storage is performed. The first storage method, in order to set a predetermined capacitance ratio between the capacitance of the pre-stage capacitor and the capacitance of the feedback capacitor, stores the analog signal in at least one pre-stage capacitor by connecting the pre-stage capacitor to the stage input, and stores the analog signal in the feedback capacitor by connecting the feedback capacitor to the stage input. The second storage method, in order to set a capacitance ratio between the capacitance of the pre-stage capacitor and the capacitance of the feedback capacitor that is smaller than the predetermined capacitance ratio in the first storage method, stores the analog signal in at least one pre-stage capacitor by connecting the pre-stage capacitor to the stage input, and does not store the analog signal in the feedback capacitor by disconnecting the feedback capacitor from the stage input.

[0274]

[17] In the seventeenth example, according to the A / D conversion method of the sixteenth example, the ratio of the capacitance of the front-stage capacitor section to the capacitance of the feedback capacitor section corresponds to the magnitude of the integral gain.

[0275]

[18] In the eighteenth example, according to the A / D conversion method of the sixteenth or seventeenth example, the operation is performed M times (M is an integer greater than or equal to 2). In the sampling step of the input signal in the first operation, in order to set the ratio of the capacitance of the front capacitor section to the capacitance of the feedback capacitor section to the predetermined capacitance ratio, the first storage is performed.

[0276]

[19] In the nineteenth example, according to the A / D conversion method selected from the sixteenth, seventeenth and eighteenth examples, the operation is performed M times (M is an integer greater than 2). In the sampling step of the input signal in the second to the (M-1)th operation, in order to set the ratio of the capacitance of the front capacitor section to the capacitance of the feedback capacitor section to a capacitance ratio smaller than the predetermined capacitance ratio at the time of the first storage, the second storage is performed.

[0277]

[20] In the twentieth example, according to the A / D conversion method selected in the sixteenth, seventeenth, eighteenth and nineteenth examples, the operation is performed M times (M is an integer greater than or equal to 2). In the sampling of the input signal in the second to the (M-1)th operation, in order to set the ratio of the capacitance of the pre-stage capacitor to the capacitance of the feedback capacitor to a first capacitance ratio smaller than the predetermined capacitance ratio in the first storage, in the second storage, the number of the pre-stage capacitor storing the analog signal is set to 2 or more. In the sampling of the input signal in the Mth operation, in order to set the ratio of the capacitance of the pre-stage capacitor to the capacitance of the feedback capacitor to a second capacitance ratio smaller than the first capacitance ratio, in the second storage, the number of the pre-stage capacitor storing the analog signal is set to 0 or 1.

[0278] Explanation of reference numerals in the attached figures

[0279] 2a: Image sensor unit; 11: A / D converter; 15: Gain stage; 15a: Input; 15b: Output; 17: A / D conversion circuit; 17a, 17b: Comparators; 19: Logic circuit; 21: D / A conversion circuit; 23: Operational amplifier circuit; 23a: First input; 23b: Second input; 25: First capacitor; 27: Second capacitor; 29: Third capacitor; 31: Switching circuit; 43, 49, 51, 53: Switches; 33, 35: Reference voltage source; 61: Clock generator; 70: Reference voltage generator; B1, B0: Calculated values; C 1a C 1b C2: Capacitor; D: Digital value; V COM Reference potential; V CONT : Control signal; V IN : Input value; V O : Operational value; V RCHFirst conversion reference voltage; V RCL Second conversion reference voltage; V RH First reference voltage; V RL Second reference voltage.

Claims

1. An A / D converter that performs A / D conversion including folding integration that obtains a digital value from an analog signal by repeatedly performing an operation including sampling of an input signal and integration of a sampled value, wherein the A / D converter has: a gain stage that outputs an operation value based on the analog signal; and an A / D conversion circuit that outputs a result that can be used to generate the digital value by comparing the operation value output by the gain stage with a conversion reference voltage; the gain stage, in performing the operation M times, in the kth time of the operation, generates the operation value based on the analog signal using a first integration gain, in the (k+1)th time of the operation, generates the operation value based on the analog signal using a second integration gain, the second integration gain is smaller than the first integration gain, M is an integer of 2 or more, and k is an integer of M-1 or less.

2. The A / D converter according to claim 1, wherein the gain stage, in the first time of the operation, generates the operation value based on the analog signal using a third integration gain, and the third integration gain is larger than the first integration gain.

3. The A / D converter according to claim 1, wherein in the second time to the (M-1)th time of the operation, the first integration gain is used, and in the Mth time of the operation, the second integration gain is used.

4. The A / D converter according to claim 1, wherein the first integration gain is 1 or more, and the second integration gain is 0 or more and less than 1.

5. An A / D converter that performs A / D conversion including folding integration that obtains a digital value from an analog signal by repeatedly performing an operation including sampling of an input signal and integration of a sampled value, wherein the A / D converter has: a gain stage that outputs an operation value based on the analog signal; and an A / D conversion circuit that outputs a result that can be used to generate the digital value by comparing the operation value output by the gain stage with a conversion reference voltage; the gain stage has: a stage input that receives the analog signal; an operational amplifier circuit that generates the operation value based on the analog signal; a stage output that outputs the operation value to the A / D conversion circuit; a pre-stage capacitor section that can be connected to the stage input and an input of the operational amplifier circuit, and includes at least one pre-stage capacitor; and a feedback capacitor section that can be connected to the stage input and an output of the operational amplifier circuit, and includes one feedback capacitor; the gain stage selectively constitutes a first circuit and a second circuit different from the first circuit in the sampling of the input signal, the first circuit, in order to set a ratio of a capacitance of the pre-stage capacitor section to a capacitance of the feedback capacitor section to a prescribed capacitance ratio, stores the analog signal in the at least one pre-stage capacitor by connecting the pre-stage capacitor section to the stage input, and stores the analog signal in the feedback capacitor by connecting the feedback capacitor section to the stage input, and the second circuit, in order to set the ratio of the capacitance of the pre-stage capacitor section to the capacitance of the feedback capacitor section to a capacitance ratio different from the prescribed capacitance ratio, stores the analog signal in the at least one pre-stage capacitor by connecting the pre-stage capacitor section to the stage input, and stores the analog signal in the feedback capacitor by connecting the feedback capacitor section to the stage input. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The second circuit sets the ratio of the capacitance of the pre-stage capacitor section to the capacitance of the feedback capacitor section to a capacitance ratio smaller than the capacitance ratio when the first circuit is used, stores the analog signal in at least one of the pre-stage capacitors by connecting the pre-stage capacitor section to the stage input, and does not store the analog signal in the feedback capacitor by disconnecting the feedback capacitor section from the stage input.

6. The A / D converter according to claim 5, wherein The ratio of the capacitance of the pre-stage capacitor section to the capacitance of the feedback capacitor section corresponds to the size of the integration gain.

7. The A / D converter according to claim 5, wherein The operation is performed M times, M being an integer of 2 or more, In the sampling of the input signal in the first operation, the first circuit is used to set the ratio of the capacitance of the pre-stage capacitor section to the capacitance of the feedback capacitor section to the prescribed capacitance ratio.

8. The A / D converter according to claim 5, wherein The operation is performed M times, M being an integer of 2 or more, In the sampling of the input signal in the second to (M-1)th operations, the second circuit is used to set the ratio of the capacitance of the pre-stage capacitor section to the capacitance of the feedback capacitor section to a capacitance ratio smaller than the prescribed capacitance ratio when the first circuit is used.

9. The A / D converter according to claim 5, wherein The operation is performed M times, M being an integer of 2 or more, In the sampling of the input signal in the second to (M-1)th operations, the number of pre-stage capacitors storing the analog signal is set to 2 or more in the second circuit to set the ratio of the capacitance of the pre-stage capacitor section to the capacitance of the feedback capacitor section to a first capacitance ratio smaller than the prescribed capacitance ratio when the first circuit is used, In the sampling of the input signal in the Mth operation, the number of pre-stage capacitors storing the analog signal is set to 0 or 1 in the second circuit to set the ratio of the capacitance of the pre-stage capacitor section to the capacitance of the feedback capacitor section to a second capacitance ratio smaller than the first capacitance ratio.

10. The A / D converter according to claim 5, wherein The capacitance of the feedback capacitor is larger than the capacitance of the pre-stage capacitor.

11. The A / D converter according to claim 5, wherein The capacitance of the feedback capacitor is larger than the capacitance of a first pre-stage capacitor, The capacitance of the first pre-stage capacitor is different from the capacitance of a second pre-stage capacitor different from the first pre-stage capacitor.

12. An A / D conversion method of performing A / D conversion including folding integration that obtains a digital value from an analog signal by repeatedly performing an operation including sampling of an input signal and integration of a sampled value, wherein The A / D conversion method includes: generating a first operation value based on the analog signal by performing the operation using a first integration gain, and generating a second operation value based on the analog signal by performing the operation using a second integration gain smaller than the first integration gain. generating a second operation value based on the analog signal by performing the action using a second integral gain after the step of generating the first operation value; the second integral gain is smaller than the first integral gain.

13. The A / D conversion method according to claim 12, wherein further comprising: generating a third operation value based on the analog signal by performing the action using a third integral gain before the step of generating the first operation value, the third integral gain is larger than the first integral gain.

14. The A / D conversion method according to claim 12, wherein the action is performed M times, M being an integer of 2 or more, in the 2nd to (M-1)th actions, the step of generating the first operation value is performed, in the Mth action, the step of generating the second operation value is performed.

15. The A / D conversion method according to claim 12, wherein the first integral gain is 1 or more, the second integral gain is 0 or more and smaller than 1.

16. An A / D conversion method of performing A / D conversion including a folding integral that obtains a digital value from an analog signal by repeatedly performing an action including sampling of an input signal and integration of a sample value, wherein the A / D conversion method has: a sampling step of the input signal that stores the analog signal in at least a front-stage capacitor section among a front-stage capacitor section and a feedback capacitor section that can be connected to a stage input of a gain stage for outputting an operation value based on the analog signal, the front-stage capacitor section including at least one front-stage capacitor, the feedback capacitor section including one feedback capacitor; and an integration step of the sample value that generates the operation value in an output of an operational amplifier circuit possessed by the gain stage by connecting at least the front-stage capacitor section to an input of the operational amplifier circuit; in the sampling step of the input signal, either a first storage or a second storage different from the first storage is performed, the first storage stores the analog signal in at least one of the front-stage capacitor by connecting the front-stage capacitor section to the stage input and in the feedback capacitor by connecting the feedback capacitor section to the stage input so as to set a ratio of a capacitance of the front-stage capacitor section to a capacitance of the feedback capacitor section to a prescribed capacitance ratio, the second storage stores the analog signal in at least one of the front-stage capacitor by connecting the front-stage capacitor section to the stage input and does not store the analog signal in the feedback capacitor by disconnecting the feedback capacitor section from the stage input so as to set the ratio of the capacitance of the front-stage capacitor section to the capacitance of the feedback capacitor section to a capacitance ratio smaller than the prescribed capacitance ratio at the time of the first storage.

17. The A / D conversion method according to claim 16, wherein the ratio of the capacitance of the front-stage capacitor section to the capacitance of the feedback capacitor section corresponds to a size of an integral gain.

18. The A / D conversion method according to claim 16, wherein ​ The action is performed M times, M being an integer of 2 or more, In the sampling step of the input signal in the first of the actions, the first storage is performed so as to set the ratio of the capacitance of the preceding-stage capacitor section to the capacitance of the feedback capacitor section to the prescribed capacitance ratio.

19. The A / D conversion method according to claim 16, wherein The action is performed M times, M being an integer of 2 or more, In the sampling step of the input signal in the second to (M-1)th of the actions, the second storage is performed so as to set the ratio of the capacitance of the preceding-stage capacitor section to the capacitance of the feedback capacitor section to a capacitance ratio smaller than the prescribed capacitance ratio at the time of the first storage.

20. The A / D conversion method according to claim 16, wherein The action is performed M times, M being an integer of 2 or more, In the sampling of the input signal in the second to (M-1)th of the actions, the ratio of the capacitance of the preceding-stage capacitor section to the capacitance of the feedback capacitor section is set to a first capacitance ratio smaller than the prescribed capacitance ratio at the time of the first storage, and in the second storage, the number of preceding-stage capacitors storing the analog signal is set to 2 or more, In the sampling of the input signal in the Mth of the actions, the ratio of the capacitance of the preceding-stage capacitor section to the capacitance of the feedback capacitor section is set to a second capacitance ratio smaller than the first capacitance ratio, and in the second storage, the number of preceding-stage capacitors storing the analog signal is set to 0 or 1.

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