Deposition method, deposition apparatus, and electronic device manufacturing by using the deposition apparatus

Abstract

A deposition method, a deposition apparatus, and an electronic device manufactured by using the deposition apparatus are provided. The deposition method includes: forming a plurality of sensors on a substrate or a deposition mask to measure a gap between the substrate and the deposition mask; positioning the substrate on the deposition mask; measuring a gap between the substrate and the deposition mask using a plurality of sensors; adjusting the parallelism between the substrate and the deposition mask based on the gap between the substrate and the deposition mask; and providing a deposition material onto the substrate through the deposition mask, where providing the deposition material forms a deposition material layer on the substrate.

Description

[0001] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0115679, filed on August 28, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to deposition methods, deposition apparatus, and electronic devices manufactured using deposition apparatus. Background Technology

[0003] Wearable devices in the form of glasses or helmets, in which the focal point is formed at a distance close to the user's eyes, have been developed. For example, wearable devices can be head-mounted display (HMD) devices or augmented reality (hereinafter referred to as "AR") glasses. Wearable devices can provide users with AR or virtual reality (hereinafter referred to as "VR") visuals.

[0004] In the case of wearable devices such as HMD devices or AR glasses, providing high-resolution images (e.g., images with a resolution of approximately 3000 PPI (pixels per inch) or higher) allows users to use the wearable device for extended periods without experiencing dizziness. For this purpose, organic light-emitting diode-on-silicon (OLEDoS) technology for high-resolution, small organic light-emitting display devices has attracted attention. OLEDoS is a technology in which organic light-emitting diodes (OLEDs) are disposed on a semiconductor substrate on which complementary metal-oxide-semiconductor (CMOS) elements are disposed.

[0005] Some methods for manufacturing display panels with a resolution of approximately 3000 PPI or higher can use high-resolution deposition masks. For example, a deposition mask can be manufactured by forming a film with multiple pixel openings on a substrate, such as a silicon wafer, and partially removing the substrate to form cell openings that expose the pixel openings.

[0006] Deposition masks are used in deposition processes for forming emissive layers of sub-pixels on a backplane substrate. While the deposition process is being performed, the backplane substrate can be positioned on the deposition mask, and the deposition source for providing the vapor deposition material can be positioned below the deposition mask. However, if warping occurs during the fabrication of the deposition mask, the parallelism between the backplane substrate and the deposition mask may deteriorate, potentially worsening the pixel position accuracy (PPA) of the emissive layer formed on the backplane substrate and causing color mixing between sub-pixels. Summary of the Invention

[0007] The aspects and features of embodiments of this disclosure provide deposition methods and deposition apparatus capable of improving the parallelism between a substrate and a deposition mask, as well as electronic devices manufactured using the deposition apparatus.

[0008] However, the embodiments of this disclosure are not limited to those set forth herein. The above and other embodiments of this disclosure will become more apparent to those skilled in the art from the following detailed description of this disclosure.

[0009] According to aspects of this disclosure, the deposition method may include: forming a plurality of sensors on a substrate or deposition mask for measuring the gap between the substrate and the deposition mask; positioning the substrate on the deposition mask; measuring the gap between the substrate and the deposition mask using the plurality of sensors; adjusting the parallelism between the substrate and the deposition mask based on the gap between the substrate and the deposition mask; and providing a deposition material onto the substrate through the deposition mask, wherein providing the deposition material forms a deposition material layer on the substrate.

[0010] According to some embodiments of this disclosure, the substrate may include a plurality of display unit areas, an edge area, and a scribe area disposed between the plurality of display unit areas. Each of the plurality of sensors may include: a measurement electrode formed on the scribe area; a contact pad formed on the edge area; and wiring formed on the scribe area and connecting the measurement electrode and the contact pad.

[0011] According to some embodiments of this disclosure, each of the gaps between the substrate and the deposition mask can be measured based on the capacitance between the measuring electrode and the deposition mask.

[0012] According to some embodiments of this disclosure, the deposition method may further include forming a plurality of spacers on a deposition mask. Each of the gaps between the substrate and the deposition mask can be measured based on the capacitance between a measuring electrode and a corresponding spacer included among the plurality of spacers.

[0013] According to some embodiments of this disclosure, the substrate may include a plurality of display unit areas, an edge area, and a scribe line area disposed between the plurality of display unit areas. Each of the plurality of sensors may include: a first contact electrode and a second contact electrode formed on the scribe line area; a first contact pad and a second contact pad formed on the edge area; and a first wiring and a second wiring formed on the scribe line area, wherein the first wiring connects the first contact electrode and the first contact pad, and the second wiring connects the second contact electrode and the second contact pad.

[0014] According to some embodiments of this disclosure, the deposition method may further include forming a plurality of spacers on a deposition mask. Each of the gaps between the substrate and the deposition mask can be measured by the presence or absence of electrical connections between a first contact electrode and a second contact electrode and the plurality of spacers.

[0015] According to some embodiments of this disclosure, the deposition mask may include a plurality of mask unit regions, an edge region, and a grid region disposed between the plurality of mask unit regions. Each of the plurality of sensors may include a measurement electrode formed on the grid region, a contact pad formed on the edge region, and wiring formed on the grid region and connecting the measurement electrode and the contact pad.

[0016] According to some embodiments of this disclosure, each of the gaps between the substrate and the deposition mask can be measured based on the capacitance between the measuring electrode and the substrate.

[0017] According to some embodiments of this disclosure, positioning the substrate on the deposition mask may include: loading the substrate and the deposition mask onto a substrate chuck and a mask chuck, respectively, such that the substrate and the deposition mask face each other; adjusting the parallelism between the substrate chuck and the mask chuck; aligning the substrate and the deposition mask with each other; and adjusting the gap between the substrate chuck and the mask chuck so that the substrate is positioned on the deposition mask.

[0018] According to some embodiments of this disclosure, adjusting the parallelism between the substrate chuck and the mask chuck may include: measuring the gap between the substrate chuck and the mask chuck using a gap sensor disposed on the substrate chuck; and adjusting the tilt of the substrate chuck based on the gap between the substrate chuck and the mask chuck.

[0019] According to some embodiments of this disclosure, adjusting the parallelism between the substrate chuck and the mask chuck may include: first measuring the gap between the substrate chuck and the mask chuck using a first gap sensor; first adjusting the tilt of the substrate chuck based on the first measurement of the gap; second measuring the gap between the substrate chuck and the mask chuck using a second gap sensor having a higher resolution than the plurality of first gap sensors; and second adjusting the tilt of the substrate chuck based on the second measurement of the gap.

[0020] According to some embodiments of this disclosure, adjusting the parallelism between the substrate chuck and the mask chuck may further include: adjusting the gap between the substrate and the deposition mask to a first gap; and adjusting the gap between the substrate and the deposition mask to a second gap smaller than the first gap. After adjusting the gap between the substrate and the deposition mask to the first gap, a first measurement of the gap between the substrate chuck and the mask chuck can be performed, and after adjusting the gap between the substrate and the deposition mask to the second gap, a second measurement of the gap between the substrate chuck and the mask chuck can be performed.

[0021] According to some embodiments of this disclosure, the parallelism between the substrate and the deposition mask can be adjusted by adjusting the tilt of the substrate chuck on which the substrate is mounted.

[0022] According to another aspect of this disclosure, the deposition apparatus may include: a deposition source for providing deposition material onto a substrate; a mask chuck disposed above the deposition source and supporting a deposition mask; a substrate chuck disposed above the mask chuck and supporting a substrate such that the substrate faces the deposition mask; and a substrate chuck driver for adjusting the position and tilt of the substrate chuck to position the substrate on the deposition mask and adjust the parallelism between the substrate and the deposition mask. Multiple sensors for measuring the gap between the substrate and the deposition mask may be disposed on the substrate or the deposition mask, and the substrate chuck driver may adjust the tilt of the substrate chuck based on the measurement results of the gap between the substrate and the deposition mask provided by the multiple sensors.

[0023] According to some embodiments of this disclosure, the substrate may include display unit areas, edge areas, and scribe lines disposed between the display unit areas. Each of the plurality of sensors may include a measurement electrode formed on the scribe line, a contact pad formed on the edge area, and wiring disposed on the scribe line and connecting the measurement electrode and the contact pad.

[0024] According to some embodiments of this disclosure, the deposition apparatus may further include: a signal detector including a plurality of probes that contact contact pads of a plurality of sensors.

[0025] According to some embodiments of this disclosure, a signal detector may be disposed in a mask chuck, and the deposition mask may have through-holes or grooves through which multiple probes pass.

[0026] According to some embodiments of this disclosure, the signal detector can detect the capacitance between the measurement electrodes of multiple sensors and the deposition mask, and measure the gap between the substrate and the deposition mask based on the detected capacitance.

[0027] According to some embodiments of this disclosure, multiple spacers can be disposed on a deposition mask and face the measurement electrodes of multiple sensors, and a signal detector can detect the capacitance between the measurement electrodes of multiple sensors and the spacers respectively, and measure the gap between the substrate and the deposition mask based on the detected capacitance.

[0028] According to some embodiments of this disclosure, the substrate may include a plurality of display unit areas, an edge area, and a scribe line area disposed between the plurality of display unit areas. Each of the plurality of sensors may include a first contact electrode and a second contact electrode disposed on the scribe line area, a first contact pad and a second contact pad disposed on the edge area, and a first wiring and a second wiring disposed on the scribe line area, wherein the first wiring connects the first contact electrode and the first contact pad, and the second wiring connects the second contact electrode and the second contact pad.

[0029] According to some embodiments of this disclosure, the deposition apparatus may further include: a signal detector comprising a plurality of probes in contact with a first contact pad and a second contact pad of a plurality of sensors.

[0030] According to some embodiments of this disclosure, a plurality of spacers can be disposed on a deposition mask and face a first contact electrode and a second contact electrode, and a signal detector can detect whether the first contact electrode and the second contact electrode are in contact with the plurality of spacers, and measure the gap between the substrate and the deposition mask based on the detection of whether the first contact electrode and the second contact electrode are in contact with the spacers.

[0031] According to some embodiments of this disclosure, the deposition mask may include a plurality of mask unit regions, an edge region, and a grid region disposed between the plurality of mask unit regions. Each of the plurality of sensors may include: a measurement electrode disposed on the grid region; a contact pad disposed on the edge region; and wiring disposed on the grid region and connecting the measurement electrode and the contact pad.

[0032] According to some embodiments of this disclosure, the deposition apparatus may further include: a signal detector including a plurality of probes that contact contact pads of a plurality of sensors.

[0033] According to some embodiments of this disclosure, a signal detector can be disposed in a mask chuck. The deposition mask can have sensor openings that expose contact pads, and multiple probes can be made to contact the contact pads through the sensor openings.

[0034] According to some embodiments of this disclosure, the signal detector can detect the capacitance between the measurement electrodes of multiple sensors and the substrate, and measure the gap between the substrate and the deposition mask based on the detected capacitance.

[0035] According to some embodiments of this disclosure, the substrate chuck driver may include a hexapod actuator that provides six degrees of freedom of motion to adjust the position and tilt of the substrate chuck.

[0036] According to some embodiments of this disclosure, the deposition apparatus may further include: a plurality of gap sensors for measuring the gap between the substrate chuck and the mask chuck. The substrate chuck driver may adjust the tilt of the substrate chuck based on the measurement results of the gap between the substrate chuck and the mask chuck provided by the plurality of gap sensors, thereby adjusting the parallelism between the substrate chuck and the mask chuck.

[0037] According to some embodiments of this disclosure, the deposition apparatus may further include: a plurality of first gap sensors for measuring the gap between a substrate chuck and a mask chuck. A substrate chuck driver can adjust the position of the substrate chuck such that the gap between the substrate and the deposition mask becomes a first gap, and can then adjust the tilt of the substrate chuck based on the measurement results of the gap between the substrate chuck and the mask chuck provided by the plurality of first gap sensors to adjust the parallelism between the substrate chuck and the mask chuck.

[0038] According to some embodiments of this disclosure, the deposition apparatus may further include: a plurality of second gap sensors for measuring the gap between the substrate chuck and the mask chuck, and having a higher resolution than the plurality of first gap sensors. A substrate chuck driver can adjust the position of the substrate chuck such that the gap between the substrate and the deposition mask becomes a second gap smaller than the first gap, and can then adjust the tilt of the substrate chuck based on the measurement results of the gap between the substrate chuck and the mask chuck provided by the plurality of second gap sensors to adjust the parallelism between the substrate chuck and the mask chuck.

[0039] According to another aspect of this disclosure, the electronic device may include a display panel comprising a substrate and a light-emitting material layer formed on the substrate using a deposition apparatus. The deposition apparatus may include: a deposition source for supplying deposition material onto the substrate; a mask chuck disposed above the deposition source and supporting a deposition mask; a substrate chuck disposed above the mask chuck and supporting the substrate such that the substrate faces the deposition mask; and a substrate chuck driver for adjusting the position and tilt of the substrate chuck to position the substrate on the deposition mask and adjust the parallelism between the substrate and the deposition mask. In this case, multiple sensors for measuring the gap between the substrate and the deposition mask may be disposed on the substrate or the deposition mask, and the substrate chuck driver may adjust the tilt of the substrate chuck based on the measurement results of the gap between the substrate and the deposition mask provided by the multiple sensors.

[0040] According to embodiments of the present disclosure as described herein, a sensor for measuring the gap can be disposed on a substrate or a deposition mask, and the sensor can be used to measure the gap between the substrate and the deposition mask. Furthermore, the parallelism between the substrate and the deposition mask can be adjusted based on the gap measurement results provided by the sensor, thereby improving the pixel position accuracy of the deposited material layer formed on the substrate and reducing color mixing between sub-pixels.

[0041] Other features and embodiments may be apparent from the following detailed description and accompanying drawings. Attached Figure Description

[0042] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0043] Figure 1 This is a block diagram of an electronic device according to embodiments of the present disclosure;

[0044] Figure 2 These are schematic diagrams of electronic devices according to various embodiments of the present disclosure;

[0045] Figure 3 This is an exploded perspective view illustrating a display device according to an embodiment of the present disclosure;

[0046] Figure 4 It is a diagram. Figure 3 The block diagram of the display device shown in the figure;

[0047] Figure 5 It is a diagram. Figure 4 The equivalent circuit diagram of the example of the first sub-pixel shown in the figure;

[0048] Figure 6 It is a diagram. Figure 3 A schematic floor plan of an example display panel shown in the figure;

[0049] Figure 7 It is a diagram. Figure 6 A schematic enlarged plan view of an example of the display area shown in the diagram;

[0050] Figure 8 It is a diagram. Figure 6 A schematic enlarged plan view of another example of the display area shown in the diagram;

[0051] Figure 9 The diagram is along Figure 7 The diagram shows a schematic cross-sectional view of an example display panel, taken by line I1-I1'.

[0052] Figure 10 The diagram is along Figure 7 A schematic cross-sectional view of another example of a display panel, taken by line I1-I1' in the diagram.

[0053] Figure 11 This is a schematic perspective view illustrating an example of a head-mounted display;

[0054] Figure 12 It is a diagram. Figure 11 The diagram shows a schematic exploded perspective view of a head-mounted display.

[0055] Figure 13 This is a schematic perspective view illustrating another example of a head-mounted display;

[0056] Figure 14 This is a schematic diagram illustrating a deposition apparatus according to an embodiment of the present disclosure;

[0057] Figure 15 This is a schematic bottom view of a backplane substrate according to an embodiment of the present disclosure;

[0058] Figure 16 This is a schematic plan view illustrating a deposition mask according to an embodiment of the present disclosure;

[0059] Figure 17 It is a diagram. Figure 16 A schematic enlarged plan view of the mask unit area shown in the figure;

[0060] Figure 18 It is along Figure 17 The diagram shows a schematic enlarged cross-section taken by line I2-I2'.

[0061] Figure 19 It is a diagram. Figure 15 A schematic enlarged bottom view of another example of the sensor illustrated in the diagram;

[0062] Figure 20 It is a diagram. Figure 14 A schematic plan view of the mask chuck shown in the figure;

[0063] Figure 21 It is a diagram. Figure 14 The diagram shows a schematic cross-sectional view of the substrate chuck and mask chuck.

[0064] Figure 22 It is a diagram. Figure 21 The diagram shows a schematic cross-sectional view of the signal detector.

[0065] Figure 23 It is a diagram. Figure 22 The diagram shows a schematic enlarged cross-sectional view of the through-hole opening of the deposition mask.

[0066] Figure 24 This is a schematic plan view of a deposition mask according to another embodiment of the present disclosure;

[0067] Figure 25 This is a schematic plan view illustrating a deposition mask according to yet another embodiment of the present disclosure;

[0068] Figure 26 It is along Figure 25 The diagram shows a schematic enlarged cross-section taken by line I3-I3'.

[0069] Figure 27 This is a flowchart illustrating a deposition method according to yet another embodiment of the present disclosure;

[0070] Figure 28It is a diagram. Figure 27 The flowchart of step S200 shown in the figure; and

[0071] Figure 29 It is a diagram. Figure 28 The flowchart of step S240 is shown in the figure. Detailed Implementation

[0072] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments of the present disclosure are illustrated. However, aspects supported by this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, exemplary embodiments are provided so that this disclosure will be thorough and complete, and the exemplary embodiments will fully convey the scope of exemplary aspects of the disclosure to those skilled in the art.

[0073] It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on that other element or layer, or there may be an intervening element or layer. Throughout the specification, the same reference numerals indicate the same parts.

[0074] It will be understood that although the terms “first” and “second” may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the invention. Similarly, the second element may also be referred to as the first element.

[0075] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, “a,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” should not be construed as a limiting “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that when the terms “comprising” or “including” are used in this specification, they indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0076] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another as illustrated in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the relative terms are also intended to cover different orientations of the device. For example, if the device in one of the drawings is flipped, the element described as being “below” the other element will be oriented “above” that other element. Thus, depending on the specific orientation of the figure, the term “below” can cover both “below” and “above” orientations. Similarly, if the device in one of the drawings is flipped, the element described as being “below” or “under” the other element will be oriented “above” that other element. Thus, the term “below” or “under” can cover both “above” and “below” orientations.

[0077] Features of each of the various embodiments of this disclosure may be combined with each other in part or in whole and may cooperate with each other in various ways technically, and the various embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0078] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “approximately” or “about” as used herein include the stated value and mean within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0079] As used herein, the term "substantially" means approximately or actually. The term "substantially equal" means approximately or actually equal. The term "substantially identical" means approximately or actually identical. The term "substantially perpendicular" means approximately or actually perpendicular. The term "substantially parallel" means approximately or actually parallel.

[0080] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (e.g., those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0081] The embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Therefore, variations in the shape of the illustrations are expected, for example, due to manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but should include deviations in shape due to, for example, manufacturing processes. For example, regions illustrated or described as flat may generally have rough and / or non-linear characteristics. Additionally, sharp corners in the illustrations may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0082] In the following description, embodiments will be described in detail with reference to the accompanying drawings.

[0083] The display device according to embodiments of this disclosure can be applied to various electronic devices. Electronic devices according to embodiments of this disclosure include the display device described herein, and may further include modules or devices with additional functions in addition to the display device.

[0084] Figure 1 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0085] refer to Figure 1 The electronic device 10 according to embodiments of the present disclosure may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0086] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0087] The memory 13 can store data information that supports the operation of the processor 12 or the display module 11. In an example where the processor 12 executes an application stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0088] The power module 14 may include a power module such as a power adapter or battery, and a power conversion module that converts the power supplied by the power module to generate power to support the operation of the electronic device 10.

[0089] At least one component of the electronic device 10 according to an embodiment of the present disclosure may be included in the display device 20 according to an embodiment of the present disclosure (see Figure 3In some aspects, some modules that are functionally included in a single module may be included in the display device 20, while other modules may be provided separately from the display device 20. For example, the display device 20 may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided as other devices within the electronic device 10 besides the display device 20.

[0090] Figure 2 This is a schematic diagram of an electronic device according to various embodiments of the present disclosure.

[0091] refer to Figure 2 The various electronic devices that apply to the display device 20 according to the embodiments of this disclosure may include not only image display electronic devices such as smartphones 10_1a, tablet PCs (personal computers) 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e, but also wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c, and vehicle electronic devices 10_3 including display modules such as interior mirror displays and CIDs (central information displays) arranged on the instrument panel, central dashboard, and dashboard of a car.

[0092] Figure 3 This is an exploded perspective view illustrating a display device according to an embodiment of the present disclosure. Figure 4 It is a diagram. Figure 3 The block diagram of the display device shown in the figure.

[0093] refer to Figure 3 and Figure 4 The display device 20 according to the embodiment can be a device for displaying moving or still images. The display device 20 according to the embodiment can be used as an electronic device 10 or a display module 11 of an electronic device 10. For example, the display device 20 according to the embodiment can be applied to portable electronic devices 10, such as mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs). The display device 20 according to the embodiment can be applied as a display module 11 of an electronic device 10, such as a television, laptop computer, monitor, billboard, and Internet of Things (IoT) terminal. The display device 20 according to the embodiment can be applied to electronic devices 10, such as smartwatches, smartwatch phones, and head-mounted displays (HMDs) for realizing virtual and augmented reality.

[0094] The display device 20 according to the embodiment may include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0095] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a right angle or rounded with a predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 20 may conform to the planar shape of the display panel 100, but the embodiments of this disclosure are not limited thereto.

[0096] The display panel 100 may include multiple pixels PX, multiple scan lines SL, multiple emission control lines EL, multiple data lines DL, a scan driver 610, an emission driver 620, and a data driver 700. For example... Figure 4 As shown in the diagram, the display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0097] Multiple pixels (PX) can be set in the display area (DAA). Multiple pixels (PX) can be arranged in a matrix along the first direction (DR1) and the second direction (DR2). Multiple scan lines (SL) and multiple emission control lines (EL) can be arranged along the second direction (DR2) while extending along the first direction (DR1). Multiple data lines (DL) can be arranged along the first direction (DR1) while extending along the second direction (DR2).

[0098] Multiple scan lines SL can include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. Multiple emit control lines EL include multiple first emit control lines ECL1 and multiple second emit control lines ECL2.

[0099] Multiple pixels PX can include multiple sub-pixels SP1, SP2, and SP3. The multiple sub-pixels SP1, SP2, and SP3 can include, for example... Figure 5 The diagram shows multiple pixel transistors, which can be formed and disposed on a semiconductor substrate SSUB using semiconductor processes (see [reference]). Figure 9 For example, multiple pixel transistors can be formed of complementary metal-oxide-semiconductor (CMOS), but embodiments of this disclosure are not limited thereto.

[0100] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line GBL, a first emitt control line ECL1, a second emitt control line ECL2, and a data line DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage from the data line DL in response to a write scan signal from the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0101] The scan driver 610, transmit driver 620, and data driver 700 can be located in the non-display area NDA.

[0102] The scan driver 610 includes multiple scan transistors, and the emitter driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed on a semiconductor substrate SSUB (see [reference needed]) using semiconductor processes. Figure 9 For example, multiple scanning transistors and multiple light-emitting transistors can be formed by CMOS, but the embodiments of this disclosure are not limited thereto.

[0103] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit (or timing controller) 400. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS from the timing control circuit 400 and output them sequentially to the write scan line GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS and output them sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate bias scan signals according to the scan timing control signal SCS and output them sequentially to the bias scan line GBL.

[0104] The transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 can generate a first transmit control signal based on the transmit timing control signal ECS and outputs it sequentially to a first transmit control line ECL1. The second transmit control driver 622 can generate a second transmit control signal based on the transmit timing control signal ECS and outputs it sequentially to a second transmit control line ECL2.

[0105] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed on a semiconductor substrate SSUB (see [reference needed]) using semiconductor processes. Figure 9 For example, multiple data transistors can be formed by CMOS, but embodiments of this disclosure are not limited thereto.

[0106] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0107] The heat dissipation layer 200 may overlap the display panel 100 on a third direction DR3 in the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on the surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include graphite or a metal layer with high thermal conductivity, such as silver (Ag), copper (Cu), or aluminum (Al).

[0108] Circuit board 300 can be electrically connected to the first pad portion of display panel 100 PDA1 (see [reference]) using conductive adhesive components such as anisotropic conductive film. Figure 6 Multiple first pads PD1 (see) Figure 6 Circuit board 300 can be a flexible film or a flexible printed circuit board with flexible materials. Although circuit board 300 is in Figure 3 The circuit board 300 is shown unfolded, but it can be bent. In this case, one end of the circuit board 300 can be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 can be connected to the first pad portion PDA1 of the display panel 100 (see Figure 1) using conductive adhesive. Figure 6 Multiple first pads PD1 (see) Figure 6 One end of the circuit board 300 may be the opposite end of the other end of the circuit board 300.

[0109] The timing control circuit 400 can receive digital video data DATA and timing signals input from an external source. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0110] The power supply circuit (or power supply unit) 500 can generate multiple panel driving voltages based on external power voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. This will be discussed later. Figure 5 Describe the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0111] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0112] Alternatively, similar to the scan driver 610, transmit driver 620, and data driver 700, each of the timing control circuit 400 and power supply circuit 500 can be located in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include multiple timing transistors, and each power supply circuit 500 may include multiple power transistors. The multiple timing transistors and multiple power transistors can be formed on a semiconductor substrate SSUB (see [link to semiconductor panel]) using semiconductor processes. Figure 9 On the data driver 700. For example, multiple timing transistors and multiple power transistors can be formed by CMOS, but embodiments of this disclosure are not limited thereto. Each of the timing control circuit 400 and the power supply circuit 500 can be disposed on the data driver 700 and the first pad portion of PDA1 (see...). Figure 6 )between.

[0113] Figure 5 It is a diagram. Figure 4The equivalent circuit diagram of the example of the first sub-pixel shown in the figure.

[0114] refer to Figure 5 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line ECL1, the second emit control line ECL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to the first drive voltage line VSL, which is subject to a first drive voltage VSS corresponding to a low potential voltage; the second drive voltage line VDL, which is subject to a second drive voltage VDD corresponding to a high potential voltage; and the third drive voltage line VIL, which is subject to a third drive voltage VINT corresponding to an initialization voltage.

[0115] The first sub-pixel SP1 may include multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0116] The light-emitting element LE emits light in response to a drive current flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE can be proportional to the drive current. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the embodiments of this disclosure are not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode; in this case, the light-emitting element LE can be a miniature light-emitting diode.

[0117] The first transistor T1 may be a driving transistor that controls the source-drain current (hereinafter referred to as "drive current") flowing between the source and drain electrodes of the first transistor T1 according to the voltage applied to the gate electrode of the first transistor T1.

[0118] A second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect the one electrode of the first capacitor CP1 to the data line DL. Accordingly, the data voltage of the data line DL can be applied to the one electrode of the first capacitor CP1.

[0119] The third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by the control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. Therefore, when the gate electrode and drain electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode.

[0120] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emitter control signal of the first emitter control line ECL1 to connect the second node N2 to the third node N3. Correspondingly, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. A fifth transistor T5 can be disposed between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third drive voltage line VIL. Correspondingly, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE.

[0121] A sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emitter control signal of the second emitter control line ECL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Accordingly, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1.

[0122] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL.

[0123] Each of the first transistors T1 to the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 to the sixth transistor T6 can be a P-type MOSFET, but the embodiments of this disclosure are not limited thereto. Each of the first transistors T1 to the sixth transistor T6 can be an N-type MOSFET. Alternatively, some of the first transistors T1 to the sixth transistor T6 can be P-type MOSFETs, and each of the remaining transistors can be an N-type MOSFET.

[0124] Despite Figure 5 The diagram illustrates the first sub-pixel SP1, which includes six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to this. Figure 5 The equivalent circuit diagram is shown in the figure. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 5 The diagram shows the number of transistors and capacitors.

[0125] Furthermore, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 can be combined with... Figure 5The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the descriptions of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 will not be repeated in this disclosure.

[0126] Figure 6 It is a diagram. Figure 3 The diagram shows a schematic floor plan of an example display panel.

[0127] refer to Figure 6 The display area DAA of the display panel 100 according to the embodiment includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to the embodiment includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0128] The scan driver 610 can be disposed on a first side of the display area DAA, and the transmit driver 620 can be disposed on a second side of the display area DAA. For example, the scan driver 610 can be disposed on one side of the display area DAA in the first direction DR1, and the transmit driver 620 can be disposed on the other side of the display area DAA in the first direction DR1. However, embodiments of this disclosure are not limited thereto, and the scan driver 610 and the transmit driver 620 can be disposed on both the first and second sides of the display area DAA.

[0129] The first pad portion PDA1 may include a plurality of first pads PD1 connected to pads or bumps on the circuit board 300 via conductive adhesive members. The first pad portion PDA1 may be located on the third side of the display area DAA. For example, the first pad portion PDA1 may be located on one side of the display area DAA in the second direction DR2. The first pad portion PDA1 may be located on the outside of the data driver 700 in the second direction DR2.

[0130] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating normally. The multiple second pads PD2 may be connected to fixtures or probes during the inspection process, or they may be connected to a circuit board for inspection. The circuit board used for inspection may be a rigid printed circuit board formed of a rigid material or a flexible printed circuit board formed of a flexible material.

[0131] The second pad portion PDA2 can be located on the fourth side of the display area DAA. For example, the second pad portion PDA2 can be located on the other side of the display area DAA in the second direction DR2. The second pad portion PDA2 can also be located on the second direction DR2 outside the second distribution circuit 720.

[0132] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL, and as a result, the number of multiple first pads PD1 can be reduced. The first distribution circuit 710 can be disposed on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side of the display area DAA in the second direction DR2.

[0133] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be located on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be located on the other side of the display area DAA in the second direction DR2.

[0134] The cathode connection portion (CCA) can be the display element layer (EML) (see...). Figure 9 The second electrode CAT (see) Figure 9 The region connected to the first drive voltage line VSL of the non-display area NDA. The cathode connection portion CCA may be located outside at least one side of the display area DAA. For example, the cathode connection portion CCA may be located outside at least one of the left, right, top, and bottom sides of the display area DAA. Alternatively, as Figure 6 As illustrated in the diagram, the cathode connection portion CCA can be configured to surround the display area DAA in order to minimize the deviation of the first drive voltage VSS caused by the voltage drop (IR drop) or voltage rise (IR rise) of the second electrode CAT in the display area DAA.

[0135] Figure 7 It is a diagram. Figure 6 A schematic enlarged plan view of an example of the display area shown in the diagram. Figure 8 It is a diagram. Figure 6 A schematic enlarged plan view of another example of the display area shown in the diagram.

[0136] refer to Figure 7 and Figure 8 Each of the pixels PX includes a first emission region EA1 for the emission region of the first sub-pixel SP1, a second emission region EA2 for the emission region of the second sub-pixel SP2, and a third emission region EA3 for the emission region of the third sub-pixel SP3.

[0137] The first launch area EA1, the second launch area EA2, and the third launch area EA3 can be arranged as follows in the plan view: Figure 7 and Figure 8 The diagram shows a quadrilateral or hexagonal shape, but the embodiments of this disclosure are not limited thereto. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may have polygonal shapes, circular shapes, elliptical shapes, or atypical shapes other than quadrilaterals or hexagons in the plan view.

[0138] like Figure 7 As illustrated in the diagram, in each of the plurality of pixels PX, a first emission region EA1 and a second emission region EA2 may be adjacent to each other in a first direction DR1. Furthermore, the first emission region EA1 and a third emission region EA3 may be adjacent to each other in the first direction DR1. In some aspects, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in a second direction DR2. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different.

[0139] Alternatively, such as Figure 8 As illustrated in the diagram, the emission regions EA1, EA2, EA3, and EA4 can have a hexagonal shape in the plan view. In this case, the first emission region EA1 and the third emission region EA3 can be adjacent in the first direction DR1, and the second emission region EA2 and the fourth emission region EA4 can be adjacent in the second direction DR2. In some aspects, the first emission region EA1 and the second emission region EA2 can be adjacent in the first oblique direction DD1, and the second emission region EA2 and the third emission region EA3 can be adjacent in the second oblique direction DD2. In some aspects, the first emission region EA1 and the fourth emission region EA4 can be adjacent in the second oblique direction DD2, and the third emission region EA3 and the fourth emission region EA4 can be adjacent in the first oblique direction DD1. The first oblique direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2, and the second oblique direction DD2 can be a direction perpendicular to the first oblique direction DD1.

[0140] The first sub-pixel SP1 can emit a first light, the second sub-pixel SP2 can emit a second light, and the third sub-pixel SP3 can emit a third light. Here, the first light can be light in the blue band, the second light can be light in the green band, and the third light can be light in the red band. For example, the blue band can be a band of light whose main peak wavelength is in the range of approximately 370nm to 460nm, the green band can be a band of light whose main peak wavelength is in the range of approximately 480nm to 560nm, and the red band can be a band of light whose main peak wavelength is in the range of approximately 600nm to 750nm.

[0141] like Figure 7 As illustrated in the diagram, each of the multiple pixels PX may include three emission regions EA1, EA2, and EA3, or as shown in the diagram. Figure 8 The diagram shows that four emission regions EA1, EA2, EA3, and EA4 may be included. In this case, the fourth emission region EA4 may be the emission region of the fourth sub-pixel SP4, and may emit the same second light as the second emission region EA2, but the embodiments of this disclosure are not limited thereto.

[0142] The emission regions of multiple pixels PX can be arranged in a stripe structure along the first direction DR1, such as... Figure 8 The launch areas EA1, EA2, EA3, and EA4 shown in the diagram are arranged in a diamond shape. The structure, or the emission area therein, is arranged in a hexagonal shape.

[0143] Figure 9 The diagram is along Figure 7 The diagram shows a schematic cross-sectional view of an example display panel, taken by line I1-I1'.

[0144] refer to Figure 9 The display panel 100 includes a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), an adhesive layer (ADL), an optical layer (OPL), a cover layer (CVL), and a polarizing plate (POL).

[0145] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) can be a reference. Figure 5 The first transistor T1 to the sixth transistor T6 are described.

[0146] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be disposed on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the first type of impurity. In an example where the first type of impurity is a P-type impurity, the second type of impurity can be an N-type impurity. Alternatively, when the first type of impurity is an N-type impurity, the second type of impurity can be a P-type impurity.

[0147] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0148] The lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating film (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating film (SINS) can also be disposed on the lower insulating film (BINS).

[0149] Each of the source region SA and the drain region DA can be a region doped with a type 1 impurity. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA on a third-direction DR3 in the thickness direction of the semiconductor substrate SSUB. The channel region CH can overlap with the gate electrode GE on a third-direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE.

[0150] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. Due to the lower insulating film BINS, the first low-concentration impurity region LDD1 can be a region with a lower impurity concentration than the source region SA. Due to the lower insulating film BINS, the second low-concentration impurity region LDD2 can be a region with a lower impurity concentration than the drain region DA. Due to the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA can be increased, thereby increasing the length of the channel region CH of each of the pixel transistors PTR.

[0151] A first semiconductor insulating film SINS1 can be disposed on a semiconductor substrate SSUB. A second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1.

[0152] Multiple contact terminals (CTEs) can be disposed on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR) through a hole penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The multiple contact terminals (CTEs) can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them.

[0153] The third semiconductor insulating film (SINS3) can be disposed on the side surface of each of the plurality of contact terminals (CTEs). The top surface of each of the plurality of contact terminals (CTEs) can be exposed and not covered by the third semiconductor insulating film (SINS3).

[0154] Each of the first semiconductor insulating film SINS1, the second semiconductor insulating film SINS2, and the third semiconductor insulating film SINS3 can be made of silicon carbonitride (SiC). x N y ) or silicon dioxide (SiO) x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0155] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate, such as polyimide. In this case, the thin-film transistor can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, while the polymer resin substrate can be a flexible substrate that can be bent or flexed.

[0156] The backplane EBP of the light-emitting element includes multiple conductive layers ML1 to ML8, multiple through holes VA1 to VA9, and multiple interlayer insulating films INS1 to INS9.

[0157] The first interlayer insulating film INS1 to the ninth interlayer insulating film INS9 are used to insulate the first conductive layer ML1 to the eighth conductive layer ML8. The first conductive layer ML1 to the eighth conductive layer ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving... Figure 5 The circuit of the first sub-pixel SP1 is shown in the figure.

[0158] For example, transistors T1 to T6 are formed in a semiconductor backplane SBP, and the connection between transistors T1 to T6 and the first capacitor CP1 and the second capacitor CP2 is achieved through the first conductive layer ML1 to the eighth conductive layer ML8. In some aspects, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the drain region corresponding to the drain electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE is also achieved through the first conductive layer ML1 to the eighth conductive layer ML8.

[0159] The first conductive layers ML1 to ML8 and the first through-holes VA1 to VA8 can be formed of substantially the same material. The first conductive layers ML1 to ML8 and the first through-holes VA1 to VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The first interlayer insulating films INS1 to INS8 can be formed of substantially the same material. The first interlayer insulating films INS1 to INS8 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0160] The ninth interlayer insulating film INS9 can be disposed on the eighth interlayer insulating film INS8 and the eighth conductive layer ML8. The ninth interlayer insulating film INS9 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0161] Each of the ninth vias VA9 can penetrate the ninth interlayer insulating film INS9 and connect to the exposed eighth conductive layer ML8. The ninth vias VA9 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0162] The display element layer (EML) can be disposed on the backplane (EBP) of the light-emitting element. The display element layer (EML) may include a tenth interlayer insulating film (INS10) and an eleventh interlayer insulating film (INS11), a reflective electrode (RL), a tenth through-hole (VA10), a first electrode (AND), a light-emitting stack (IL), a second electrode (CAT), a pixel defining film (PDL), and multiple trenches (TRC).

[0163] The reflective electrodes RL can be disposed on the ninth interlayer insulating film INS9. Each of the reflective electrodes RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, as... Figure 9As illustrated in the figure, each of the reflective electrodes RL may include a first reflective electrode through a fourth reflective electrode RL1, RL2, RL3, and RL4.

[0164] The first reflective electrode RL1 can be disposed on the ninth interlayer insulating film INS9 and can be connected to the ninth through-hole VA9. Each of the second reflective electrodes RL2 can be disposed on its corresponding first reflective electrode RL1. Each of the third reflective electrodes RL3 can be disposed on its corresponding second reflective electrode RL2. Each of the fourth reflective electrodes RL4 can be disposed on its corresponding third reflective electrode RL3.

[0165] Since the second reflective electrode RL2 is an electrode that essentially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4.

[0166] The first reflective electrode RL1 can be formed from any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), a nitride of any one of them, or an alloy comprising any one of them. For example, the first reflective electrode RL1 can contain titanium nitride (TiN). x The second reflective electrode RL2 may contain aluminum (Al), and the third reflective electrode RL3 may contain titanium nitride (TiN). x Furthermore, the fourth reflective electrode RL4 may include titanium (Ti).

[0167] The tenth interlayer insulating film INS10 can be disposed on the ninth interlayer insulating film INS9. The tenth interlayer insulating film INS10 can be disposed between adjacent reflective electrodes RL. The tenth interlayer insulating film INS10 can be a film used to flatten the stepped portion caused by the reflective electrode RL. The eleventh interlayer insulating film INS11 can be disposed on the tenth interlayer insulating film INS10 and the reflective electrode RL.

[0168] The tenth interlayer insulating film INS10 and the eleventh interlayer insulating film INS11 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0169] The eleventh interlayer insulating film INS11 can be an optical auxiliary layer for adjusting the resonant distance of light emitted from the light-emitting stack IL in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The thickness of the eleventh interlayer insulating film INS11 can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode RL to the second electrode CAT according to the main peak wavelength of the light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the thickness of the eleventh interlayer insulating film INS11 can be set for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0170] For example, such as Figure 9 As illustrated, the thickness of the eleventh interlayer insulating film INS11 in the first sub-pixel SP1 can be greater than the thickness of the eleventh interlayer insulating film INS11 in the second sub-pixel SP2, and the thickness of the eleventh interlayer insulating film INS11 in the second sub-pixel SP2 can be greater than the thickness of the eleventh interlayer insulating film INS11 in the third sub-pixel SP3. In this case, the distance between the first electrode AND and the reflective electrode RL in the first sub-pixel SP1 is greater than the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2. In some aspects, the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2 is greater than the distance between the first electrode AND and the reflective electrode RL in the third sub-pixel SP3.

[0171] Each of the tenth vias VA10 can penetrate the eleventh interlayer insulating film INS11 and connect to the exposed fourth reflective electrode RL4. The tenth vias VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them. The thickness of the tenth via VA10 in the first sub-pixel SP1 can be greater than the thickness of the tenth via VA10 in the second sub-pixel SP2, and the thickness of the tenth via VA10 in the second sub-pixel SP2 can be greater than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0172] The first electrode AND of each of the light-emitting elements LE can be disposed on the eleventh interlayer insulating film INS11 and connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the reflective electrode RL, the first vias VA1 to the ninth vias VA9, the first conductive layers ML1 to the eighth conductive layers ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), a nitride of any one of them, or an alloy including any one of them. For example, the first electrode AND of each of the light-emitting elements LE can be titanium nitride (TiN). x ).

[0173] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL can separate a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3. Each of the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3 can be a region of the light-emitting element (LE) comprising the first electrode AND, the light-emitting stack IL, and the second electrode CAT.

[0174] The first emission region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0175] The pixel-defining film (PDL) may include first pixel-defining films to third pixel-defining films PDL1, PDL2, and PDL3. The first pixel-defining film PDL1 may be disposed on the edge of the first electrode AND of each of the light-emitting elements (LEs), the second pixel-defining film PDL2 may be disposed on the first pixel-defining film PDL1, and the third pixel-defining film PDL3 may be disposed on the second pixel-defining film PDL2. The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 may be made of silicon oxide (SiO2). xAn inorganic film of type ) is formed. Alternatively, the first pixel defining film PDL1 and the third pixel defining film PDL3 can be formed of silicon nitride (SiN). x Inorganic films of this type are formed, while the second pixel defining film PDL2 can be made of silicon oxide (SiO2). x Formation of inorganic films. The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 can each have approximately The thickness.

[0176] To reduce or prevent the possibility of the first encapsulated inorganic film TFE1 breaking due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may have a cross-sectional structure with stepped portions. Step coverage refers to the ratio of the degree to which the film is coated on the inclined portion to the degree to which the film is coated on the flat portion. The lower the step coverage, the more likely the film is to break at the inclined portion.

[0177] Each of the multiple trench TRCs can penetrate the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. The eleventh interlayer insulating film INS11 can be partially recessed at each of the multiple trench TRCs.

[0178] At least one trench TRC can be set between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 9 The illustration shows two trench TRCs positioned between adjacent sub-pixels SP1, SP2, and SP3, but the embodiments disclosed herein are not limited thereto.

[0179] The light-emitting stacked layer IL can include multiple stacked layers IL1, IL2 and IL3. Figure 9 The illustration shows a three-tiered structure of a light-emitting stack IL comprising a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3, but embodiments of this disclosure are not limited thereto. For example, as Figure 10 As shown in the diagram, the light-emitting stacked layer IL can have a dual tandem structure comprising two stacked layers.

[0180] In a three-tiered cascade structure, the light-emitting stack IL can have a cascaded structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different light. For example, the light-emitting stack IL may include a first stacked layer IL1 that emits a first light, a second stacked layer IL2 that emits a second light, and a third stacked layer IL3 that emits a third light. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 can be stacked sequentially.

[0181] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first light-emitting layer emitting first light, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second light-emitting layer emitting second light, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third light-emitting layer emitting third light, and a third electron transport layer are sequentially stacked.

[0182] A first charge generation layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stacked layer IL1 and a P-type charge generation layer for supplying holes to the second stacked layer IL2. The N-type charge generation layer may include a dopant of a metallic material.

[0183] A second charge generation layer for supplying holes to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0184] A first stacked layer IL1 can be disposed on the first electrode AND and the pixel defining film PDL, and the residual film RIL disposed on the bottom surface of each trench TRC can be made of the same material as the first stacked layer IL1. Due to the trench TRC, the first stacked layer IL1 can be disconnected between adjacent sub-pixels SP1, SP2, and SP3. A second stacked layer IL2 can be disposed on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 can be disconnected between adjacent sub-pixels SP1, SP2, and SP3. In the trench TRC, a cavity ESS or blank space can be disposed between the residual film IL and the second stacked layer IL2. A third stacked layer IL3 can be disposed on the second stacked layer IL2. The third stacked layer IL3 is not disconnected by the trench TRC and can be configured such that the third stacked layer IL3 covers the second stacked layer IL2 in each of the trench TRCs.

[0185] In a three-series structure, each of the plurality of trench TRCs can be a structure for disconnecting the first charge generation layer, the second charge generation layer, and the first hole transport layer to the third hole transport layer of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3. In some aspects, in a dual-series structure, each of the plurality of trench TRCs can be a structure for disconnecting the lower stack layer and the charge generation layer disposed between the lower stack layer and the upper stack layer.

[0186] To stably disconnect the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel defining film PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. To disconnect the charge generation layer and hole transport layer of the light-emitting stacked layer IL of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, different structures can exist instead of trench TRCs. For example, instead of trench TRCs, inverted conical partition walls can be provided on the pixel defining film PDL.

[0187] In some respects, Figure 9 The illustration shows a light-emitting stack IL disposed in a first emission region EA1, a second emission region EA2, and a third emission region EA3; however, embodiments of this disclosure are not limited thereto. For example, instead of the light-emitting stack IL, the first light-emitting layer may be disposed in the first emission region EA1 and may be omitted from the second emission region EA2 and the third emission region EA3. Furthermore, the second light-emitting layer may be disposed in the second emission region EA2 and may be omitted from the first emission region EA1 and the third emission region EA3. Additionally, the third light-emitting layer may be disposed in the third emission region EA3 and may be omitted from the first emission region EA1 and the second emission region EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL may be omitted.

[0188] The second electrode CAT can be disposed on the light-emitting stack IL. That is, the second electrode CAT can be disposed on the third stack IL3. The second electrode CAT can be formed of a transparent conductive material (TCO) that can transmit light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. In the example where the second electrode CAT is formed of a semi-transmissive conductive material, the luminous efficiency can be improved in each of the first to third sub-pixels SP1, SP2, and SP3 due to the microcavity effect.

[0189] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film TFE1 and TFE3 for preventing oxygen or moisture from penetrating into the display element layer EML. The first encapsulation inorganic film TFE1 can be disposed on the second electrode CAT, and the second encapsulation inorganic film TFE3 can be disposed above the first encapsulation inorganic film TFE1. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 can be made of silicon nitride (SiN). x ) layer, silicon oxynitride (SiO) x N y ) layer, silicon dioxide (SiO) x ) layer, titanium oxide (TiO) x ) layer and aluminum oxide (AlO) x Multiple inorganic films in the layer are formed by alternating stacking of multiple layers.

[0190] In some aspects, the encapsulation layer TFE may include at least one organic film TFE2 for protecting the display element layer EML from foreign matter such as dust. The encapsulation organic film TFE2 may be disposed between a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE3. The encapsulation organic film TFE2 may be a monomer. Alternatively, the encapsulation organic film TFE2 may be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0191] The adhesive layer ADL can be a layer used to bond the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL can be a double-sided adhesive component. In some aspects, the adhesive layer ADL can be a transparent adhesive component, such as a transparent adhesive or a transparent adhesive resin.

[0192] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 may be disposed on the adhesive layer ADL.

[0193] The first color filter CF1 can overlap with the first emission region EA1 of the first sub-pixel SP1. The first color filter CF1 can transmit light of a first color, namely, light in the blue band. The blue band can be approximately 370 nm to approximately 460 nm. Therefore, the first color filter CF1 can transmit light of the first color emitted from the first emission region EA1.

[0194] The second color filter CF2 can overlap with the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color, namely, light in the green band. The green band can be approximately 480 nm to approximately 560 nm. Therefore, the second color filter CF2 can transmit light of the second color emitted from the second emission region EA2.

[0195] The third color filter CF3 can overlap with the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of the third color, that is, light in the red band. The red band can be approximately 600nm to approximately 750nm. Therefore, the third color filter CF3 can transmit light of the third color emitted from the third emission region EA3.

[0196] Multiple lenses LNS can be respectively disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the multiple lenses LNS can be a structure for improving the proportion of light on the front side of the guiding display device 20. Each of the multiple lenses LNS can have a cross-sectional shape that convexes in the upward direction.

[0197] A filler layer (FIL) can be disposed on multiple lens lenses (LNS). The filler layer FIL can have a predetermined refractive index, such that light propagates along the third-direction DR3 at the interface between the filler layer FIL and the multiple lens lenses (LNS). Furthermore, the filler layer FIL can be a planarization layer. The filler layer FIL can be an organic film, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0198] A cover layer CVL can be disposed on a filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. In an example where the cover layer CVL is a glass substrate, the cover layer CVL can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to bond the cover layer CVL. In an example where the cover layer CVL is a glass substrate, the cover layer CVL can act as an encapsulation substrate. In an example where the cover layer CVL is a polymer resin, the cover layer CVL can be directly coated onto the filler layer FIL.

[0199] The polarizing plate (POL) can be disposed on one surface of the CVL (container layer). The polarizing plate (POL) can be a structure used to reduce or prevent visibility reduction caused by reflection of external light. The polarizing plate (POL) can include a linear polarizing plate and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but embodiments of this disclosure are not limited thereto. However, the polarizing plate (POL) can be omitted when the first to third color filters CF1, CF2, and CF3 sufficiently overcome the visibility reduction caused by reflection of external light.

[0200] Figure 10 The diagram is along Figure 7 The diagram shows a schematic cross-sectional view of another example of a display panel, taken by line I1-I1'.

[0201] Figure 10 Implementation examples and Figure 9 The difference in the embodiment is that the first electrode AND of each of the light-emitting elements LE is in contact with and electrically connected to the side surface of the connection electrode ANC connected to the eighth conductive layer ML8. Figure 10 Implementation examples and Figure 9 The embodiment also differs in that the trench TRC is omitted, and instead, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 have an eaves-shaped or mushroom-shaped cross-sectional structure. Figure 10 In the embodiments, the already omitted Figure 9 Redundant descriptions of parts described in the embodiments.

[0202] refer to Figure 10 Multiple connecting electrodes ANC can be respectively disposed on the first portion AA1 of the ninth interlayer insulating film INS9. Each of the multiple connecting electrodes ANC can be disposed on its corresponding first portion AA1 of the ninth interlayer insulating film INS9. The multiple connecting electrodes ANC can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), nitrides of any one of them, alloys including any one of them, or transparent conductive oxides. For example, the multiple connecting electrodes ANC may include titanium (Ti), titanium nitride (TiN), etc. x Indium tin oxide (ITO) or indium zinc oxide (IZO), but this disclosure is not limited thereto.

[0203] Multiple reflective electrodes RL can be disposed on multiple connecting electrodes ANC. Each of the multiple reflective electrodes RL can be disposed on its corresponding connecting electrode ANC. The multiple reflective electrodes RL can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them. For example, each of the multiple reflective electrodes RL may include aluminum (Al) with high reflectivity.

[0204] Multiple optical auxiliary films (OALs) can be separately disposed on multiple reflective electrodes (RLs). Each of the multiple optical auxiliary films (OALs) can be disposed on its corresponding reflective electrode (RL). The multiple optical auxiliary films (OALs) can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0205] In each of the first emission region EA1 and the third emission region EA3, a stepped layer STPL can be disposed on the reflective electrode RL, and an optical auxiliary film OAL can be disposed on the stepped layer STPL. In the second emission region EA2, for example, only the optical auxiliary film OAL can be disposed on the reflective electrode RL. The thickness of the optical auxiliary film OAL can be substantially the same in the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0206] Due to the stepped layer STPL, the distance between the reflective electrode RL and the first electrode AND in the first emission region EA1 and the third emission region EA3 can be greater than the distance between the reflective electrode RL and the first electrode AND in the second emission region EA2. The thickness of the stepped layer STPL and the thickness of the optical auxiliary layer OAL can be set taking into account the wavelength and resonant distance of the light emitted from the first stacked layer IL1 of the light-emitting stack IL and the wavelength and resonant distance of the light emitted from the second stacked layer IL2 of the light-emitting stack IL.

[0207] Each of the light-emitting elements LE may include a first electrode AND, a light-emitting stack IL, and a second electrode CAT.

[0208] The first electrode AND of each of the light-emitting elements LE can be disposed on its corresponding optical auxiliary film OAL. Since the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary layer OAL are stacked sequentially, the first electrode AND of each of the light-emitting elements LE can be disposed on the top and side surfaces of the optical auxiliary layer OAL, the side surface of the reflective electrode RL, and the side surface of the connecting electrode ANC. Accordingly, the first electrode AND of each of the light-emitting elements LE can contact and be electrically connected to the side surfaces of the reflective electrode RL and the connecting electrode ANC. Therefore, compared to when the first electrode AND of each of the light-emitting elements LE is connected to the reflective electrode RL exposed through a through-hole penetrating the optical auxiliary film OAL, the number of masking processes can be reduced, thereby reducing manufacturing costs and improving manufacturing efficiency.

[0209] The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the connecting electrode ANC, the first through hole VA1 to the ninth through hole VA9, the first conductive layer ML1 to the eighth conductive layer ML8 and the contact terminal CTE.

[0210] The ninth interlayer insulating film INS9 may include a first portion AA1 that overlaps with the connecting electrode ANC on the third-direction DR3 and a second portion AA2 that does not overlap with the connecting electrode ANC on the third-direction DR3. The thickness of the first portion AA1 and the thickness of the second portion AA2 of the ninth interlayer insulating film INS9 may be substantially the same.

[0211] Alternatively, the thickness of the first portion AA1 of the ninth interlayer insulating film INS9 can be greater than the thickness of the second portion AA2 of the ninth interlayer insulating film INS9. In this case, the side surface of the first portion AA1 of the ninth interlayer insulating film INS9 can be exposed, and the first electrode AND of each of the light-emitting elements LE can be disposed on the exposed side surface of the first portion AA1 of the ninth interlayer insulating film INS9.

[0212] The first electrode AND of each of the light-emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (ND), a nitride of any one of them, an alloy of any one of them, or a transparent conductive oxide. For example, the first electrode AND of each of the light-emitting elements LE may include titanium (Ti), titanium nitride (TiN), etc. x Indium tin oxide (ITO) or indium zinc oxide (IZO), but this disclosure is not limited thereto.

[0213] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL can separate a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3.

[0214] The pixel-limiting film (PDL) may include the first pixel-limiting film to the fourth pixel-limiting film, PDL1, PDL2, PDL3 and PDL4.

[0215] The first pixel defining film PDL1 can be disposed on the first electrode AND of each of the light-emitting elements LE. Specifically, the first pixel defining film PDL1 can cover a portion of the top surface of the first electrode AND disposed on the optical auxiliary film OAL. Furthermore, the first pixel defining film PDL1 can cover the first electrode AND disposed on the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The first pixel defining film PDL1 can be disposed on the top surface of the second portion AA2 of the ninth interlayer insulating film INS9.

[0216] The planarization film PNS is a film used to flatten the stepped sections caused by the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL.

[0217] The planarization film PNS can be disposed on the first pixel defining film PDL1, which covers the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The planarization film PNS can also be disposed on the first pixel defining film PDL1, which is disposed on the second portion AA2 of the ninth interlayer insulating film INS9.

[0218] The planarization film PNS can be disposed between adjacent connecting electrodes ANC along the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent reflecting electrodes RL along the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent optical auxiliary films OAL along the first direction DR1 or the second direction DR2.

[0219] There is no step layer STPL in the second emission region EA2, while there is a step layer STPL in each of the first emission region EA1 and the third emission region EA3. Accordingly, the height of the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL in the second emission region EA2 can be smaller than the height of the connecting electrode ANC, the reflective electrode RL, the step layer STPL, and the optical auxiliary film OAL in the first emission region EA1 and the third emission region EA3. Therefore, the planarization film PNS can cover the top surface of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND disposed in the second emission region EA2.

[0220] Conversely, the top surface of the planarization film PNS can be flatly connected to the top surface of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND, which is disposed in the first emission region EA1 and the third emission region EA3. That is, the planarization film PNS may not cover the top surface of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND, which is disposed in each of the first emission region EA1 and the third emission region EA3.

[0221] The second pixel limiting film PDL2 can be disposed on the first pixel limiting film PDL1 and the planarization film PNS, the third pixel limiting film PDL3 can be disposed on the second pixel limiting film PDL2, and the fourth pixel limiting film PDL4 can be disposed on the third pixel limiting film PDL3. The first pixel limiting film PDL1 and the third pixel limiting film PDL3 can be made of silicon nitride (SiN). xInorganic films of this type are formed, while the second pixel defining film PDL2, the fourth pixel defining film PDL4, and the planarization film PNS can be formed from silicon oxide (SiO2). x ( ) Formation of an inorganic film. The first pixel defining film PDL1 is formed of a material different from that of the planarization film PNS, and therefore can act as a barrier in the chemical mechanical polishing process of the planarization film PNS.

[0222] When the planarization film PNS and the second pixel-defining film PDL2 are both formed as silicon oxide (SiO) x When using inorganic films, the planarization film PNS and the second pixel-defining film PDL2 can be formed as a single film.

[0223] Because the length of the third pixel defining film PDL3 in one direction is less than the length of the fourth pixel defining film PDL4 in one direction, the bottom surface of the fourth pixel defining film PDL4 can be exposed without being covered by the third pixel defining film PDL3. In other words, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 can have an eaves-shaped or mushroom-shaped cross-sectional structure.

[0224] A light-emitting stack IL can be disposed on a first electrode AND and a pixel-defining film PDL. The light-emitting stack IL can include a first stacked layer IL1 and a second stacked layer IL2 that emit different types of light. In an example where the light-emitting stack IL has a dual-tandem structure, one of the first stacked layer IL1 and the second stacked layer IL2 can emit light within a wavelength range including any one of a first light, a second light, and a third light, and the other can emit light within wavelength ranges including the other two types of light. For example, the first stacked layer IL1 can emit light within the wavelength ranges of both the first and third light, and the second stacked layer IL2 can emit light within the wavelength range of the second light. Here, the first light can be in the blue band, the second light can be in the green band, and the third light can be in the red band.

[0225] A charge generation layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The charge generation layer may include an N-type charge generation layer that supplies electrons to the first stacked layer IL1 and a P-type charge generation layer that supplies holes to the second stacked layer IL2. The N-type charge generation layer may include a dopant of a metallic material.

[0226] The first stacked layer IL1 is not formed on the exposed bottom surface of the fourth pixel-defining film PDL4, which is not covered by the third pixel-defining film PDL3, and therefore can be separated by the eaves-shaped or mushroom-shaped cross-sectional structure of the third pixel-defining film PDL3 and the fourth pixel-defining film PDL4. In this case, the first hole transport layer of the first stacked layer IL1 and the charge generation layer disposed between the first stacked layer IL1 and the second stacked layer IL2 can also be separated. Furthermore, although Figure 10 The illustration shows the second stacked layer IL2 connected without being disconnected; however, the second hole transport layer of the second stacked layer IL2 can be disconnected, and the second electron transport layer of the second stacked layer IL2 can be connected without being disconnected. Therefore, embodiments of this disclosure can prevent leakage current from flowing between adjacent emitting regions EA1, EA2, and EA3 through the first hole transport layer of the first stacked layer IL1, the second hole transport layer of the second stacked layer IL2, and the charge generation layer. Accordingly, embodiments of this disclosure can prevent the light-emitting stacked layers IL in adjacent emitting regions EA1, EA2, and EA3 from emitting light other than the originally desired light due to the influence of the aforementioned current.

[0227] although Figure 10 The figure illustrates a dual-tandem structure in which the light-emitting stacked IL comprises two stacked layers IL1 and IL2, but the embodiments disclosed herein are not limited thereto. For example, as... Figure 9 As illustrated in the diagram, the light-emitting stack IL can have a triple-tandem structure comprising three stacked layers. In this case, the light-emitting stack IL can be designed such that the charge-generating layers between the first stacked layer IL1 and the second stacked layer IL2, and between the second stacked layer IL2 and the third stacked layer IL3, are disconnected by adjusting the height of the third pixel-defining film PDL3. Alternatively, as... Figure 9 As illustrated in the diagram, a trench TRC can be added that penetrates the first pixel defining film PDL1, the planarization film PNS, the second pixel defining film PDL2, and the third pixel defining film PDL3. In this case, the trench TRC can penetrate at least a portion of the ninth interlayer insulating film INS9, but the embodiments of this disclosure are not limited thereto.

[0228] Figure 11 This is a schematic perspective view illustrating an example of a head-mounted display. Figure 12 It is a diagram. Figure 11 The diagram shows a schematic exploded perspective view of a head-mounted display.

[0229] refer to Figure 11 and Figure 12According to an embodiment, the head-mounted display 1000 includes a first display device 20_1, a second display device 20_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head mounting strap 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0230] The first display device 20_1 provides an image to the user's left eye, and the second display device 20_2 provides an image to the user's right eye. Because each of the first display device 20_1 and the second display device 20_2 is combined with... Figures 3 to 10 The display devices 20 described are substantially the same, so the descriptions of the first display device 20_1 and the second display device 20_2 will be omitted.

[0231] The first optical component 1510 may be disposed between the first display device 20_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 20_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0232] The intermediate frame 1400 can be disposed between the first display device 20_1 and the control circuit board 1600, and between the second display device 20_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 20_1, the second display device 20_2, and the control circuit board 1600.

[0233] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 20_1 and the second display device 20_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data DATA, and transmit the digital video data DATA to the first display device 20_1 and the second display device 20_2 via connectors.

[0234] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 20_1, and digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 20_2. Alternatively, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 20_1 and the second display device 20_2.

[0235] The display device housing 1100 is used to house the first display device 20_1, the second display device 20_2, the intermediate frame 1400, the first optical component 1510, the second optical component 1520, and the control circuit board 1600. The housing cover 1200 is configured to cover the open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 positioned thereon for the user's left eye and a second eyepiece 1220 positioned thereon for the user's right eye. Figure 11 and Figure 12 The illustration shows the first eyepiece 1210 and the second eyepiece 1220 being configured separately, but the embodiments of this disclosure are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0236] The first eyepiece 1210 can be aligned with the first display device 20_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 20_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 20_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 20_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0237] A head-mounting strap 1300 is used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned over the user's left and right eyes, respectively. In an example where the display device housing 1100 is implemented as lightweight and compact, such as... Figure 13 As shown in the diagram, the head-mounted display 1000 can be provided with eyeglass frames instead of a head-mounted strap 1300.

[0238] Figure 13 This is a schematic perspective view illustrating another example of a head-mounted display.

[0239] refer to Figure 13 The head-mounted display 1000_1 according to the embodiment may be an eyeglass-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to the embodiment may include a display device 20_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, an optical path changing component 1070, and a display device housing 1200_1.

[0240] The display device housing 1200_1 may include a display device 20_3, an optical component 1060, and a light path changing component 1070. The image displayed on the display device 20_3 can be magnified by the optical component 1060, and after the light path of the image is changed by the light path changing component 1070, it can be provided to the user's right eye through the right eye lens 1020. As a result, the user can view an augmented reality image that combines the virtual image displayed on the display device 20_3 with the real image viewed through the right eye lens 1020.

[0241] Figure 13 The illustration shows the display device housing 1200_1 disposed at the right end of the support frame 1030, but the embodiments of this disclosure are not limited thereto. For example, the display device housing 1200_1 may be disposed at the left end of the support frame 1030, and in this case, the image displayed on the display device 20_3 may be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030, and in this case, the user may view the image displayed on the display device 20_3 through both the left and right eyes.

[0242] Figure 14 This is a schematic diagram of a deposition apparatus according to an embodiment of the present disclosure.

[0243] refer to Figure 14 The deposition apparatus 2000 according to embodiments of the present disclosure can be used to form a deposition material layer on a backplane substrate (hereinafter referred to as substrate) 3000. For example, the deposition apparatus 2000 according to embodiments of the present disclosure can be used to form a light-emitting material layer on a backplane substrate 3000 used for manufacturing a display panel. In this case, such as Figure 9 and Figure 10 As shown in the figure, the semiconductor backplane SBP and the light-emitting element backplane EBP can be arranged on the backplane substrate 3000, and an electrode pattern AND, such as an anode electrode, and a pixel defining film PDL with an opening exposing the electrode pattern AND can be disposed on the light-emitting element backplane EBP.

[0244] The deposition apparatus 2000 according to embodiments of the present disclosure can be used to form a plurality of light-emitting material layers on a plurality of electrode patterns AND. For example, the deposition apparatus 2000 according to embodiments of the present disclosure can be used to form a plurality of first light-emitting material layers for emitting a first light having a blue wavelength, respectively arranged on a plurality of electrode patterns AND in a plurality of first emission regions EA1; a plurality of second light-emitting material layers for emitting a second light having a green wavelength, respectively arranged on a plurality of electrode patterns AND in a plurality of second emission regions EA2; and a plurality of third light-emitting material layers for emitting a third light having a blue wavelength, respectively arranged on a plurality of electrode patterns AND in a plurality of third emission regions EA3.

[0245] Figure 15 This is a schematic bottom view of a backplane substrate according to an embodiment of the present disclosure.

[0246] refer to Figure 15 The backplane substrate 3000 may include a plurality of display unit areas 3010, edge areas (or edge portions), and scribe lines 3020 disposed between the display unit areas 3010. The plurality of display unit areas 3010 may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1, and the plurality of display unit areas 3010 may be individually individualized into a plurality of display panels 100 by a dicing process after the display manufacturing process is completed. For example, the first direction DR1 may be a first horizontal direction, and the second direction DR2 may be a second horizontal direction perpendicular to the first direction DR1. In this case, the first direction DR1 may be the X-axis direction, and the second direction DR2 may be the Y-axis direction.

[0247] Although not illustrated in detail, each of the display unit areas 3010 may include a semiconductor backplane SBP and a light-emitting element backplane EBP disposed on the semiconductor backplane SBP, and multiple electrode patterns AND may be disposed on the light-emitting element backplane EBP. Furthermore, a pixel defining film PDL may be disposed on the display unit area 3010 and the scribing area 3020, and the pixel defining film PDL may have multiple openings exposing the electrode patterns AND.

[0248] According to one embodiment of this disclosure, a plurality of sensors 3100 for measuring the gap between a backplane substrate 3000 and a deposition mask 4000 in a deposition process for forming a deposited material layer can be formed on the backplane substrate 3000. For example, each of the plurality of sensors 3100 may include a measurement electrode 3110, a contact pad 3120, and wiring 3130, and may be arranged on a pixel defining film (PDL). Specifically, the plurality of measurement electrodes 3110 may be respectively disposed on a scribe zone 3020 and at a preset measurement point, and the plurality of contact pads 3120 may be arranged on an edge portion of the backplane substrate 3000. A plurality of wirings 3130 may connect the measurement electrodes 3110 and the contact pads 3120, and may be disposed on the scribe zone 3020. As shown, five sensors 3100 are arranged on the backplane substrate 3000, but the position and number of sensors 3100 can be varied, and the scope of this disclosure is not limited thereto.

[0249] According to one embodiment of this disclosure, the measuring electrode 3110, the contact pad 3120, and the wiring 3130 may be formed of a conductive material (e.g., a metal such as copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), or neodymium (Nd), an oxide or nitride of said metal, or a transparent conductive oxide such as indium tin oxide (ITO), zinc oxide (ZnO), or indium zinc oxide (IZO).

[0250] For example, after a conductive material layer is formed on a pixel-defining film (PDL), the conductive material layer can be patterned to simultaneously form a measurement electrode 3110, contact pads 3120, and wiring 3130 on the PDL. Specifically, although not shown, after a photoresist pattern (not shown) is formed on the conductive material layer exposing portions other than where the measurement electrode 3110, contact pads 3120, and wiring 3130 will be formed, an anisotropic etching process using the photoresist pattern as an etching mask can be performed to form the measurement electrode 3110, contact pads 3120, and wiring 3130 on the PDL. In another example, the measurement electrode 3110, contact pads 3120, and wiring 3130 can be formed using a damascene process.

[0251] Figure 16 This is a schematic plan view illustrating a deposition mask according to an embodiment of the present disclosure. Figure 17 It is a diagram. Figure 16 The diagram shows a schematic enlarged plan view of the mask unit area, and... Figure 18 It is along Figure 17 The diagram shows a schematic enlarged cross-section taken by line I2-I2'.

[0252] refer to Figures 16 to 18 The deposition mask 4000 may include a plurality of mask unit regions 4210, an edge region, and a grid region 4220 disposed between the plurality of mask unit regions 4210, and the plurality of mask unit regions 4210 respectively correspond to a plurality of display unit regions 3010 of the backplane substrate 3000. Each of the mask unit regions 4210 may have a plurality of pixel openings 4230 that expose the electrode pattern AND of the backplane substrate 3000 in the deposition process.

[0253] For example, the deposition mask 4000 may include a mask frame 4100 and a diaphragm 4200 disposed on the mask frame 4100. In this case, the diaphragm 4200 may include a plurality of mask unit regions 4210 and a grid region 4220 disposed between the mask unit regions 4210, and each of the mask unit regions 4210 may have a plurality of pixel openings 4230. The mask frame 4100 may have unit openings 4110 and may include rib regions 4120 defining the unit openings 4110. In this case, the plurality of mask unit regions 4210 may be respectively arranged on the plurality of unit openings 4110, and the grid region 4220 may be disposed on the rib region 4120. Furthermore, the mask unit regions 4210 may be exposed through the unit openings 4110, and the pixel openings 4230 may be connected to the unit openings 4110 while penetrating the mask unit regions 4210.

[0254] like Figure 16 As shown in the figure, multiple mask unit regions 4210 can be arranged in a matrix along a first direction DR1 and a second direction DR2. For example, multiple mask unit regions 4210 can be arranged in a matrix along a first horizontal direction DR1 and a second horizontal direction DR2 perpendicular to the first horizontal direction DR1, and can be arranged to correspond to multiple display unit regions 3010 of the backplane substrate 3000, respectively.

[0255] A diaphragm 4200 can be disposed on the front surface of the mask frame 4100, and a rear inorganic membrane 4300 can be disposed on the rear surface of the mask frame 4100. The diaphragm 4200 and the rear inorganic membrane 4300 can be formed of the same material. For example, the diaphragm 4200 and the rear inorganic membrane 4300 can be made of materials such as silicon nitride (SiN). x Inorganic materials, such as those used in the example, are formed and can be formed to have a thickness of approximately 0.5 μm to approximately 3 μm by a thermochemical vapor deposition (TCVD) process. That is, the front inorganic film and the rear inorganic film 4300 can be simultaneously formed on the front and rear surfaces of the mask frame 4100 by a TCVD process, respectively, and the front inorganic film can be used as a diaphragm 4200.

[0256] A single-crystal silicon substrate can be used as a mask frame 4100, and a pixel opening 4230 can be formed by forming a diaphragm 4200 on the mask frame 4100 and then patterning the diaphragm 4200. For example, the pixel opening 4230 can be formed by forming a photoresist pattern (not shown) on the diaphragm 4200 that exposes the portion where the pixel opening 4230 will be formed, and then performing an anisotropic etching process using the photoresist pattern as an etching mask until the mask frame 4100 is exposed.

[0257] The back inorganic film 4300 may have a back opening 4310 communicating with the unit opening 4110, and may serve as an etching mask in the etching process used to form the unit opening 4110. For example, the back opening 4310 may be formed by forming a photoresist pattern (not shown) on the back inorganic film 4300 that exposes the portion where the back opening 4310 will be formed, and then performing an anisotropic etching process using the photoresist pattern as an etching mask until the back surface of the mask frame 4100 is exposed.

[0258] The cell opening 4110 can be formed as a mask cell region 4210 exposing the diaphragm 4200 by an anisotropic etching process using the inorganic film 4300 as an etching mask. For example, the cell opening 4110 can be formed by a wet etching process using tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH). In this case, the single-crystal silicon substrate used as the mask frame 4100... <100> The crystal orientation can be a third orientation DR3, such that the cell opening 4110 can be formed by a wet etching process to have a width that gradually decreases toward the diaphragm 4200 (i.e., on the third orientation DR3). For example, each of the inner surfaces of the cell opening 4110 can be formed to have a tilt of approximately 54.74°.

[0259] According to one embodiment of this disclosure, the deposition mask 4000 may include a plurality of spacers 4400 corresponding to a plurality of sensors 3100 on a backplane substrate 3000. Specifically, the plurality of spacers 4400 may be arranged on a grid region 4220 of the deposition mask 4000 to correspond to a plurality of measurement electrodes 3110 respectively. In an example in which the backplane substrate 3000 is positioned on the deposition mask 4000 to perform a deposition process, the measurement electrodes 3110 and the spacers 4400 face each other, and the gap between the measurement electrodes 3110 and the spacers 4400 can be measured based on the capacitance between the measurement electrodes 3110 and the spacers 4400. In this case, each of the spacers 4400 can be used as a sensor dog (or detection target) for measuring the gap between the backplane substrate 3000 and the deposition mask 4000, and the gap between the backplane substrate 3000 and the deposition mask 4000 can be calculated based on the gap between the measurement electrodes 3110 and the spacers 4400.

[0260] The spacer 4400 can be formed of a dielectric material or a conductive material. For example, the spacer 4400 can be formed of a material such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x ), hafnium oxide (HfO) x ) or zirconium oxide (ZrO) x In another example, the spacer 4400 may be formed of a dielectric material such as copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), or neodymium (Nd), an oxide or nitride of said metal, or a transparent conductive oxide such as indium tin oxide (ITO), zinc oxide (ZnO), or indium zinc oxide (IZO).

[0261] Spacers 4400 can be formed on separator 4200 after separator 4200 is formed. In this case, pixel openings 4230 can be formed after spacers 4400 is formed. Specifically, spacers 4400 can be formed on grid regions 4220 of separator 4200 to correspond to measurement electrodes 3110 on backplane substrate 3000. For example, after a dielectric material layer or a conductive material layer is formed on separator 4200, spacers 4400 can be formed on separator 4200 by patterning the dielectric material layer or the conductive material layer. Specifically, although not shown, after a photoresist pattern (not shown) is formed on the dielectric material layer or the conductive material layer exposing the portion where spacers 4400 will be formed, an anisotropic etching process using the photoresist pattern as an etching mask can be performed until separator 4200 is exposed to form spacers 4400 on separator 4200.

[0262] According to another embodiment of this disclosure, the spacer 4400 may be omitted in the deposition mask 4000. In this case, during the deposition process, the measuring electrode 3110 may face the diaphragm 4200 of the deposition mask 4000, and the gap between the measuring electrode 3110 and the diaphragm 4200 may be measured based on the capacitance between the measuring electrode 3110 and the diaphragm 4200.

[0263] Figure 19 It is a diagram. Figure 15 A schematic enlarged bottom view of another example of the sensor shown in the figure.

[0264] refer to Figure 19 Multiple sensors 3200 can be arranged on a backplane substrate 3000. Each of the sensors 3200 may include a first contact electrode 3210, a second contact electrode 3220, a first contact pad 3230, a second contact pad 3240, a first wiring 3250, and a second wiring 3260. The first contact electrode 3210 and the second contact electrode 3220 may be arranged on a scribe area 3020, and the first contact pad 3230 and the second contact pad 3240 may be arranged on an edge portion of the backplane substrate 3000. The first wiring 3250 and the second wiring 3260 can connect the first contact electrode 3210 and the second contact electrode 3220 to the first contact pad 3230 and the second contact pad 3240, respectively, and may be disposed on the scribe area 3020.

[0265] The first contact electrode 3210 and the second contact electrode 3220, the first contact pad 3230 and the second contact pad 3240, as well as the first wiring 3250 and the second wiring 3260, may be formed of a conductive material (e.g., a metal such as copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) or neodymium (Nd), an oxide or nitride of said metal, or a transparent conductive oxide such as indium tin oxide (ITO), zinc oxide (ZnO) or indium zinc oxide (IZO).

[0266] For example, after a conductive material layer is formed on a pixel-defining film (PDL), the conductive material layer can be patterned to form a first contact electrode 3210 and a second contact electrode 3220, a first contact pad 3230 and a second contact pad 3240, and a first wiring 3250 and a second wiring 3260 on the PDL. Specifically, although not shown, after a photoresist pattern (not shown) exposing portions of the first contact electrode 3210 and the second contact electrode 3220, the first contact pad 3230 and the second contact pad 3240, and the first wiring 3250 and the second wiring 3260 to be formed is formed on the conductive material layer, an anisotropic etching process using the photoresist pattern as an etching mask can be performed to form the first contact electrode 3210 and the second contact electrode 3220, the first contact pad 3230 and the second contact pad 3240, and the first wiring 3250 and the second wiring 3260 on the PDL. In another example, the first contact electrode 3210 and the second contact electrode 3220, the first contact pad 3230 and the second contact pad 3240, and the first wiring 3250 and the second wiring 3260 can be formed by a damascene process.

[0267] When each of the sensors 3200 includes a first contact electrode 3210 and a second contact electrode 3220 as described herein, the spacers 4400 of the deposition mask 4000 may be formed of a conductive material. Specifically, when the backplane substrate 3000 is positioned on the deposition mask 4000, the first contact electrode 3210 and the second contact electrode 3220 may contact the spacers 4400 corresponding to the first contact electrode 3210 and the second contact electrode 3220, and the first contact electrode 3210 and the second contact electrode 3220 may be electrically connected through the corresponding spacers 4400. Specifically, when the first contact electrode 3210 and the second contact electrode 3220 are electrically connected, it can be determined that the first contact electrode 3210 and the second contact electrode 3220 are in contact with the spacer 4400 at corresponding contact points between the first contact electrode 3210, the second contact electrode 3220, and the spacer 4400. Conversely, when the first contact electrode 3210 and the second contact electrode 3220 are not electrically connected, it can be determined that the first contact electrode 3210 and the second contact electrode 3220 are not in contact with the spacer 4400 at corresponding contact points. As a result, the gap between the backplane substrate 3000 and the deposition mask 4000 can be measured depending on whether the first contact electrode 3210 and the second contact electrode 3220 are electrically connected at multiple measurement points.

[0268] Return to reference Figure 14 According to embodiments of the present disclosure, the deposition apparatus 2000 may include a deposition source 2200, a substrate chuck 2300, and a mask chuck 2400. The deposition source 2200 is used to provide deposition material on a backplane substrate 3000. The substrate chuck 2300 is used to support the backplane substrate 3000 such that the backplane substrate 3000 faces the deposition source 2200. The mask chuck 2400 is disposed between the deposition source 2200 and the substrate chuck 2300 and supports the deposition mask 4000 such that the deposition mask 4000 faces the backplane substrate 3000.

[0269] Deposition source 2200, substrate chuck 2300, and mask chuck 2400 can be disposed in processing chamber 2100. Processing chamber 2100 may have an internal space, and the deposition process for forming a deposition material layer on backplane substrate 3000 can be performed within the internal space of processing chamber 2100. Processing chamber 2100 may be connected to a vacuum pump (not shown), and a vacuum atmosphere may be generated within the internal space of processing chamber 2100 by the vacuum pump. An opening (not shown) for loading / unloading backplane substrate 3000 and deposition mask 4000 may be provided on one wall of processing chamber 2100, and said opening may be opened and closed by a gate valve (not shown).

[0270] The deposition source 2200 can be disposed in the processing chamber 2100, and the deposition material can be stored in the deposition source 2200. The deposition source 2200 can evaporate deposition materials such as organic materials, inorganic materials, or conductive materials, and the evaporated deposition material can be deposited on the electrode pattern AND of the backplane substrate 3000 through the pixel opening 4230 of the deposition mask 4000. For example, the deposition source 2200 can evaporate organic materials used to form a light-emitting material layer on the backplane substrate 3000, and a heater (not shown) for evaporating the organic material can be provided. The evaporated deposition material can be deposited on the electrode pattern AND of the backplane substrate 3000 through the pixel opening 4230 of the deposition mask 4000. Figure 14 As shown in the diagram, the deposition source 2200 can be positioned on the central portion of the bottom surface of the processing chamber 2100, but the deposition source 2200 can be configured to move horizontally via a separate actuator (not shown).

[0271] The substrate chuck 2300 can be disposed above the deposition source 2200 and can support the backplane substrate 3000 such that the backplane substrate 3000 faces the deposition source 2200. For example, the substrate chuck 2300 can be an electrostatic chuck that uses electrostatic force to hold the rear surface of the backplane substrate 3000. Specifically, the electrode pattern AND, the pixel defining film PDL, and the sensor 3100 can be disposed on the front surface of the backplane substrate 3000, and the substrate chuck 2300 can hold the rear surface of the backplane substrate 3000 such that the front surface of the backplane substrate 3000 faces downward, i.e., facing the deposition source 2200.

[0272] Multiple lifting fingers 2500 for loading the backplane substrate 3000 onto the substrate chuck 2300 can be disposed in the processing chamber 2100. The multiple lifting fingers 2500 can be disposed around the substrate chuck 2300 and the mask chuck 2400, and can be vertically moved by multiple finger drivers 2510 respectively. For example, three or four lifting fingers 2500 can be disposed around the substrate chuck 2300 and the mask chuck 2400. The backplane substrate 3000 can be loaded into the processing chamber 2100 by a transfer robot (not shown) and can be transferred from the transfer robot to the lifting fingers 2500 below the substrate chuck 2300. In this case, the rear surface of the backplane substrate 3000 can face the bottom surface of the substrate chuck 2300, and the lifting fingers 2500 can support the front edge portion of the backplane substrate 3000. The finger driver 2510 can raise the lifting finger 2500 so that the back plate substrate 3000 becomes adjacent to the bottom surface of the substrate chuck 2300, and then the rear surface of the back plate substrate 3000 can be held on the bottom surface of the substrate chuck 2300 by electrostatic force.

[0273] Figure 20 It is a diagram. Figure 14The diagram shows a schematic plan view of the mask chuck. Figure 21 It is a diagram. Figure 14 The diagram shows a schematic cross-sectional view of the substrate chuck and mask chuck.

[0274] refer to Figure 20 and Figure 21 The mask chuck 2400 can be horizontally disposed in the processing chamber 2100 between the deposition source 2200 and the substrate chuck 2300, and can support the edge portion of the deposition mask 4000. For example, the mask chuck 2400 can have an annular shape, and can be an electrostatic chuck that uses electrostatic force to hold the bottom edge portion of the deposition mask 4000. However, unlike the above, the mask chuck 2400 can have a quadrilateral plate shape with a circular opening.

[0275] The deposition apparatus 2000 may include a grid support 2410 for supporting the mask cell region 4210 of the deposition mask 4000. For example, the grid support 2410 may include a grid plate 2412 for supporting the rib region 4120 of the mask frame 4100, a support ring 2414 extending downward from the edge portion of the grid plate 2412, and a flange 2416 surrounding the lower portion of the support ring 2414. The grid plate 2412 may have a disk shape and may have an opening 2418 corresponding to the cell opening 4110 of the mask frame 4100. Furthermore, the grid plate 2412 and the support ring 2414 may be disposed in a mask chuck 2400, and the mask chuck 2400 may be disposed on the flange 2416.

[0276] Return to reference Figure 14 The deposition mask 4000 can be loaded into the processing chamber 2100 by a transfer robot and can be transferred to a lifting finger 2500 above the mask chuck 2400. The edge portion of the deposition mask 4000 can be positioned on the end of the lifting finger 2500, and the finger actuator 2510 can lower the lifting finger 2500 to load the deposition mask 4000 onto the mask chuck 2400. In this case, although not shown, a recess (not shown) can be provided at the edge portion of the top surface of the mask chuck 2400 into which the lifting finger 2500 is inserted, and the finger actuator 2510 can rotate the lifting finger 2500 such that after the deposition mask 4000 is loaded onto the mask chuck 2400, the lifting finger 2500 does not overlap with the mask chuck 2400.

[0277] The deposition apparatus 2000 may include a substrate chuck driver 2600 for moving a substrate chuck 2300 and a mask chuck driver 2700 for moving a mask chuck 2400. For example, the substrate chuck driver 2600 can move the substrate chuck 2300 in a first direction DR1, a second direction DR2, and a third direction DR3 to adjust the position of the backplane substrate 3000. In this case, the first direction DR1 may be a first horizontal direction, the second direction DR2 may be a second horizontal direction perpendicular to the first direction DR1, and the third direction DR3 may be a vertical direction. That is, the first direction DR1, the second direction DR2, and the third direction DR3 may be the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively.

[0278] The substrate chuck driver 2600 can sequentially rotate the substrate chuck 2300 about the Z-axis to adjust the azimuth angle of the backplane substrate 3000. Furthermore, the substrate chuck driver 2600 can sequentially rotate the substrate chuck 2300 about the X-axis and about the Y-axis to adjust the tilt of the backplane substrate 3000. For example, the substrate chuck driver 2600 may include a hexapod actuator 2610 that provides six degrees of freedom (X, Y, Z, θx, θy, and θz) of motion.

[0279] The substrate chuck driver 2600 may include a substrate stage 2620 with a hexapod actuator 2610 mounted thereon and a second actuator 2630 connected to the substrate stage 2620. The substrate stage 2620 may be horizontally disposed in the processing chamber 2100, and the second actuator 2630 may be disposed above the processing chamber 2100. The second actuator 2630 may be connected to the substrate stage 2620 via a plurality of drive shafts 2632 extending through the top cover of the processing chamber 2100 in a third direction DR3 (i.e., the vertical direction (Z-axis direction)), and may move the substrate stage 2620 in the direction of the central axis of the hexapod actuator 2610 (i.e., the vertical direction). For example, the second actuator 2630 may be configured to use a brushless DC motor, a linear motor, or a direct drive (DD) motor, etc., and the height of the substrate chuck 2300 may be adjusted to load or unload the backplane substrate 3000.

[0280] Although not illustrated in detail, the hexapod actuator 2610 may include a first platform connected to the substrate chuck 2300, a second platform mounted to the substrate stage 2620, and six sub-actuators disposed between the first and second platforms. The six sub-actuators can move and rotate the first platform to adjust the horizontal position, vertical position, azimuth angle, and tilt of the backplane substrate 3000. For example, each of the six sub-actuators may be configured to use a brushless DC motor, a voice coil linear motor, a stepper motor, a direct drive (DD) motor, or a servo motor, etc.

[0281] The mask chuck driver 2700 can move and rotate the mask chuck 2400 to adjust the horizontal position and azimuth angle of the deposition mask 4000. The mask chuck driver 2700 can move the mask chuck 2400 in a direction parallel to the deposition mask 4000 and rotate the mask chuck 2400 about its central axis. For example, the mask chuck driver 2700 can move the mask chuck 2400 in a first direction DR1 (X-axis) and a second direction DR2 (Y-axis), and can rotate the mask chuck 2400 about a third direction DR3 (Z-axis).

[0282] The mask chuck driver 2700 may include, for example, a piezoelectric actuator 2710 that provides motion in three degrees of freedom (X, Y, and θz). The piezoelectric actuator 2710 may have an annular or quadrilateral ring shape, and the mask chuck 2400 may be disposed on the piezoelectric actuator 2710. The mask chuck driver 2700 may include a mask stage 2720 horizontally disposed in the processing chamber 2100 and supporting the piezoelectric actuator 2710. For example, the mask stage 2720 may have an opening for exposing the deposition mask 4000 toward the deposition source 2200 and may be supported by a plurality of pillars 2722 connected to a top cover of the processing chamber 2100. However, the scope of this disclosure is not limited thereto because the support structure of the mask stage 2720 can be varied.

[0283] Return to reference Figure 21 The deposition apparatus 2000 may include a plurality of gap sensors 2800 for measuring the gap between the substrate chuck 2300 and the mask chuck 2400. For example, the plurality of gap sensors 2800 may be arranged on the edge portion of the substrate chuck 2300, and the gap sensors 2800 may measure the gap of the mask chuck 2400 through through-holes 2310 penetrating the edge portion of the substrate chuck 2300.

[0284] After the backplane substrate 3000 and the deposition mask 4000 are loaded onto the substrate chuck 2300 and the mask chuck 2400, respectively, the second actuator 2630 can lower the backplane substrate 3000 to a preset height, and the hexapod actuator 2610 can adjust the height of the substrate chuck 2300 so that the gap between the backplane substrate 3000 and the deposition mask 4000 becomes a preset gap, for example, approximately 100 μm to approximately 200 μm. Next, the gap between the substrate chuck 2300 and the mask chuck 2400 can be measured by the gap sensor 2800, and the hexapod actuator 2610 can adjust the parallelism between the substrate chuck 2300 and the mask chuck 2400 based on the gap measurement results provided by the gap sensor 2800. For example, a capacitive proximity sensor can be used as a gap sensor 2800, and the hexapod actuator 2610 can adjust the parallelism between the substrate chuck 2300 and the mask chuck 2400 by adjusting the tilt of the substrate chuck 2300.

[0285] Although not shown, the deposition apparatus 2000 may further include a plurality of second gap sensors (not shown) for measuring the gap between the substrate chuck 2300 and the mask chuck 2400. For example, the plurality of second gap sensors may be arranged on the edge portion of the substrate chuck 2300, and the second gap sensors may measure the gap of the mask chuck 2400 through second through-holes (not shown) penetrating the edge portion of the substrate chuck 2300. In this case, the hexapod actuator 2610 may adjust the height of the substrate chuck 2300 such that the gap between the backplane substrate 3000 and the deposition mask 4000 becomes a preset gap, for example, approximately 10 μm to approximately 50 μm, and the gap between the substrate chuck 2300 and the mask chuck 2400 may be measured a second time by the second gap sensors. The hexapod actuator 2610 may then adjust the parallelism between the substrate chuck 2300 and the mask chuck 2400 a second time based on the gap measured by the second gap sensors. For example, a confocal sensor with a higher resolution than a capacitive proximity sensor can be used as a second gap sensor.

[0286] As described herein, after adjusting the parallelism between the substrate chuck 2300 and the mask chuck 2400, alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed. For example, although not shown, a plurality of substrate alignment keys (not shown) can be arranged on the edge portions of the backplane substrate 3000, and a plurality of mask alignment keys (not shown) corresponding to the plurality of substrate alignment keys can be arranged on the edge portions of the deposition mask 4000. Furthermore, the deposition apparatus 2000 may include a camera unit (not shown) for detecting the substrate alignment keys and the mask alignment keys, and an illumination unit (not shown) for illuminating the substrate alignment keys and the mask alignment keys, and the substrate chuck 2300 and / or the mask chuck 2400 may be provided with through-holes (not shown) for providing illumination light and detecting the substrate alignment keys and the mask alignment keys.

[0287] For example, the illumination unit can provide near-infrared (NIR) or short-wave infrared (SWIR) light with wavelengths of approximately 1010 nm to approximately 1020 nm, and the camera unit can detect the infrared light transmitted through the backplane substrate 3000 and the deposition mask 4000. The hexapod actuator 2610 can perform alignment between the backplane substrate 3000 and the deposition mask 4000 based on the position information of the substrate alignment key and the mask alignment key acquired by the camera unit. For example, the hexapod actuator 2610 can adjust the position and azimuth angle of the substrate chuck 2300 based on image information acquired by the camera unit.

[0288] In some embodiments, as described above, the alignment between the backplane substrate 3000 and the deposition mask 4000 is performed after the parallelism adjustment between the substrate chuck 2300 and the mask chuck 2400 is performed. However, in some embodiments, unlike the above, the parallelism adjustment between the substrate chuck 2300 and the mask chuck 2400 can be performed after the alignment between the backplane substrate 3000 and the deposition mask 4000 is performed. Furthermore, unlike the above, in some embodiments, the alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed by the piezoelectric actuator 2710.

[0289] As described herein, after performing parallelism adjustments between the substrate chuck 2300 and the mask chuck 2400, and alignment between the backplane substrate 3000 and the deposition mask 4000, the backplane substrate 3000 can be positioned on the deposition mask 4000. For example, the hexapod actuator 2610 can adjust the height of the substrate chuck 2300 such that the gap between the backplane substrate 3000 and the deposition mask 4000 becomes a preset gap, such as a gap of a few micrometers. In another example, the hexapod actuator 2610 can adjust the height of the substrate chuck 2300 such that the backplane substrate 3000 contacts the deposition mask 4000.

[0290] After the backplane substrate 3000 is positioned on the deposition mask 4000, the gap between the backplane substrate 3000 and the deposition mask 4000 can be measured by a sensor 3100 on the backplane substrate 3000. In this case, as... Figure 20 and Figure 21 As shown in the diagram, a signal detector 2900 for detecting measurement signals can be disposed in a mask chuck 2400.

[0291] Figure 22 It is a diagram. Figure 21 The diagram shows a schematic cross-sectional view of the signal detector.

[0292] refer to Figure 22 A slot 2420 may be provided at the edge portion of the mask chuck 2400 into which a signal detector 2900 is inserted, and the deposition mask 4000 may have a through opening 4010 exposing the signal detector 2900. In this case, the contact pads 3120 on the backplane substrate 3000 may be arranged facing the signal detector 2900 through the through opening 4010 of the deposition mask 4000. The signal detector 2900 may include a plurality of probes 2910 for detecting measurement signals, and the plurality of probes 2910 may respectively contact the contact pads 3120 on the backplane substrate 3000 through the through opening 4010 of the deposition mask 4000.

[0293] The signal detector 2900 can detect the capacitance between the measurement electrode 3110 on the backplane substrate 3000 and the diaphragm 4200 of the deposition mask 4000, or the capacitance between the measurement electrode 3110 on the backplane substrate 3000 and the spacer 4400 on the diaphragm 4200, thereby measuring the gap between the backplane substrate 3000 and the deposition mask 4000. The substrate chuck driver 2600 can adjust the parallelism between the backplane substrate 3000 and the deposition mask 4000 based on the gap between the backplane substrate 3000 and the deposition mask 4000 measured by the sensor 3100 (i.e., based on the measurement result of the gap between the backplane substrate 3000 and the deposition mask 4000 provided by the sensor). Specifically, the hexapod actuator 2610 can adjust the tilt of the substrate chuck 2300 so that all gaps between the backplate substrate 3000 and the deposition mask 4000 meet the preset tolerance range, thereby supporting the consistency of the gaps between the backplate substrate 3000 and the deposition mask 4000 and improving the parallelism between the backplate substrate 3000 and the deposition mask 4000.

[0294] In another example, when Figure 19When the sensor 3200 shown in the diagram is arranged on the backplane substrate 3000, the signal detector 2900 can have multiple probes corresponding to the first contact pad 3230 and the second contact pad 3240, respectively, and can determine whether the first contact electrode 3210 and the second contact electrode 3220 on the backplane substrate 3000 are in contact with the spacer 4400 on the deposition mask 4000. In this case, the hexapod actuator 2610 can adjust the tilt of the substrate chuck 2300 so that both the first contact electrode 3210 and the second contact electrode 3220 on the backplane substrate 3000 are in contact with the spacer 4400 on the deposition mask 4000, thereby supporting the uniformity of the gap between the backplane substrate 3000 and the deposition mask 4000 and improving the parallelism between the backplane substrate 3000 and the deposition mask 4000.

[0295] Figure 23 It is a diagram. Figure 22 The diagram shows a schematic enlarged cross-sectional view of the through-hole opening of the deposition mask.

[0296] refer to Figure 23 The deposition mask 4000 may have a through-hole 4010 formed through the mask frame 4100, the diaphragm 4200, and the post-inorganic film 4300. When the backplane substrate 3000 is positioned on the deposition mask 4000, the through-hole 4010 may expose the contact pads 3120 on the backplane substrate 3000. For example, the through-hole 4010 may include a first opening 4240 penetrating the diaphragm 4200, a second opening 4320 penetrating the post-inorganic film 4300, and a third opening 4130 penetrating the mask frame 4100.

[0297] The first opening 4240 can be formed simultaneously with the pixel opening 4230. For example, the pixel opening 4230 and the first opening 4240 can be formed by forming a photoresist pattern (not shown) on the diaphragm 4200 that exposes the portions where the pixel opening 4230 and the first opening 4240 will be formed, and then performing an anisotropic etching process using the photoresist pattern as an etching mask until the mask frame 4100 is exposed.

[0298] The second opening 4320 can be formed simultaneously with the rear opening 4310. For example, the rear opening 4310 and the second opening 4320 can be formed by forming a photoresist pattern (not shown) on the rear inorganic film 4300 that exposes the portion where the rear opening 4310 and the second opening 4320 will be formed, and then performing an anisotropic etching process using the photoresist pattern as an etching mask until the rear surface of the mask frame 4100 is exposed.

[0299] The third opening 4130 can be formed simultaneously with the unit opening 4110. For example, the unit opening 4110 and the third opening 4130 can be formed by a wet etching process using tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH). In this case, the diaphragm 4200 and the post-inorganic film 4300 can serve as etching masks for forming the third opening 4130.

[0300] In another example, although not illustrated, a through-hole 4010 can be pre-provided on the monocrystalline silicon substrate serving as the mask frame 4100. Specifically, the through-hole 4010 can be pre-formed via a laser cutting process when the monocrystalline silicon substrate is in a bare wafer state.

[0301] Figure 24 This is a schematic plan view illustrating a deposition mask according to another embodiment of the present disclosure.

[0302] refer to Figure 24 The deposition mask 4000 may have a recess 4020 for exposing the contact pads 3120 of the backplane substrate 3000 when the backplane substrate 3000 is positioned on the deposition mask 4000. For example, the recess 4020 may be formed on a side surface of the deposition mask 4000 and may be aligned with a reference surface. Figure 23 The through-hole 4010 is formed in the same manner as described. In another example, a recess 4020 can be pre-provided on the monocrystalline silicon substrate that serves as the mask frame 4100. Specifically, the recess 4020 can be pre-formed by a laser cutting process when the monocrystalline silicon substrate is in a bare wafer state.

[0303] Figure 25 This is a schematic plan view illustrating a deposition mask according to yet another embodiment of the present disclosure. Figure 26 It is along Figure 25 The diagram shows a schematic enlarged cross-section taken by line I3-I3'.

[0304] refer to Figure 25 and Figure 26Multiple sensors 4500 for measuring the gap between the backplane substrate 3000 and the deposition mask 4000 can be formed on the deposition mask 4000. For example, each of the multiple sensors 4500 may include a measurement electrode 4510, a contact pad 4520, and wiring 4530, and may be disposed on the diaphragm 4200. Specifically, the multiple measurement electrodes 4510 may be arranged on the grid area 4220 of the diaphragm 4200 at preset measurement points, and the multiple contact pads 4520 may be arranged on the edge portion of the diaphragm 4200. Multiple wirings 4530 can connect the measurement electrodes 4510 and the contact pads 4520, and may be arranged on the grid area 4220 of the diaphragm 4200. As shown, five sensors 4500 are arranged on the deposition mask 4000, but the position and number of sensors 4500 can be varied, and the scope of this disclosure is not limited thereto.

[0305] The measuring electrode 4510, contact pad 4520, and wiring 4530 can be formed of a conductive material (e.g., a metal such as copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), or neodymium (Nd), an oxide or nitride of said metal, or a transparent conductive oxide such as indium tin oxide (ITO), zinc oxide (ZnO), or indium zinc oxide (IZO).

[0306] For example, after a conductive material layer is formed on the separator 4200, the conductive material layer can be patterned to simultaneously form the measurement electrode 4510, contact pads 4520, and wiring 4530 on the separator 4200. Specifically, although not shown, after a photoresist pattern (not shown) is formed on the conductive material layer exposing portions other than where the measurement electrode 4510, contact pads 4520, and wiring 4530 will be formed, an anisotropic etching process using the photoresist pattern as an etching mask can be performed to form the measurement electrode 4510, contact pads 4520, and wiring 4530 on the separator 4200. In another example, the measurement electrode 4510, contact pads 4520, and wiring 4530 can be formed using a damascene process.

[0307] Specifically, pad openings 4250 penetrating the diaphragm 4200 can be formed before the conductive material layer is formed. For example, the pad openings 4250 can be formed simultaneously with the pixel openings 4230. For example, the pixel openings 4230 and pad openings 4250 can be formed by forming a photoresist pattern (not shown) on the diaphragm 4200 that exposes the portions where the pixel openings 4230 and pad openings 4250 will be formed, and then performing an anisotropic etching process using the photoresist pattern as an etching mask until the mask frame 4100 is exposed. In this case, the conductive material layer can be formed on the diaphragm 4200 such that the pad openings 4250 are buried, and can be patterned such that the contact pads 4520 are located in the pad openings 4250.

[0308] According to this embodiment, the deposition mask 4000 may have a sensor opening 4030 that exposes the contact pad 4520. The sensor opening 4030 may include a fourth opening 4330 that penetrates the inorganic membrane 4300 and a fifth opening 4140 that penetrates the mask frame 4100.

[0309] The fourth opening 4330 can be formed simultaneously with the rear opening 4310. For example, the rear opening 4310 and the fourth opening 4330 can be formed by forming a photoresist pattern (not shown) on the rear inorganic film 4300 that exposes the portions where the rear opening 4310 and the fourth opening 4330 will be formed, and then performing an anisotropic etching process using the photoresist pattern as an etching mask until the rear surface of the mask frame 4100 is exposed.

[0310] The fifth opening 4140 can be formed simultaneously with the unit opening 4110. For example, the unit opening 4110 and the fifth opening 4140 can be formed by a wet etching process using tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH). In this case, the post-inorganic film 4300 can serve as an etching mask for forming the unit opening 4110 and the fifth opening 4140.

[0311] According to this embodiment, when the deposition mask 4000 is loaded onto the mask chuck 2400, the probe 2910 of the signal detector 2900 can contact the contact pad 4520 through the sensor opening 4030. Furthermore, when the backplane substrate 3000 is positioned on the deposition mask 4000, the signal detector 2900 can use the probe 2910 to detect the capacitance between the pixel defining film (PDL) on the backplane substrate 3000 and the measurement electrode 4510 on the deposition mask 4000, thereby measuring the gap between the backplane substrate 3000 and the deposition mask 4000.

[0312] Figure 27 This is a flowchart illustrating a deposition method according to yet another embodiment of the present disclosure. Figure 28It is a diagram. Figure 27 The flowchart of step S200 is shown in the figure. Figure 29 It is a diagram. Figure 28 The flowchart of step S240 is shown in the figure.

[0313] In the description of the methods and processes herein, operations may be performed in a different order than those shown and / or described, or in a different order or at different times. Some operations may also be omitted from the flowchart, one or more operations may be repeated, or additional operations may be added. As with the example aspects described herein, descriptions of elements "may be set up" and "may be formed," etc., include methods, processes, and techniques for setting up, forming, positioning, and modifying said elements, etc.

[0314] refer to Figures 27 to 29 In step S100, the method may include forming a plurality of sensors on the backplane substrate 3000 or the deposition mask 4000 to measure the gap between the backplane substrate 3000 and the deposition mask 4000 using the plurality of sensors. For example, as Figure 15 As illustrated, the backplane substrate 3000 may include a plurality of display unit regions 3010, edge regions (or edge portions), and scribe lines 3020 disposed between the display unit regions 3010. The plurality of display unit regions 3010 may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1, and the plurality of display unit regions 3010 may be individually individualized into a plurality of display panels 100 by a dicing process after the display manufacturing process is completed. Although not illustrated in detail, each of the display unit regions 3010 may include a semiconductor backplane SBP and a light-emitting element backplane EBP disposed on the semiconductor backplane SBP, and a plurality of electrode patterns AND may be disposed on the light-emitting element backplane EBP. Furthermore, a pixel defining film PDL may be disposed on the display unit regions 3010 and the scribe lines 3020, and the pixel defining film PDL may have a plurality of openings exposing the electrode patterns AND.

[0315] Multiple sensors 3100 can be formed on the backplane substrate 3000 and can measure the gap between the backplane substrate 3000 and the deposition mask 4000. For example, Figure 15 As illustrated, each of the plurality of sensors 3100 may include a measurement electrode 3110, a contact pad 3120, and wiring 3130, and may be arranged on a pixel defining film (PDL). Specifically, the plurality of measurement electrodes 3110 may be respectively disposed on the scribe area 3020 and at preset measurement points, and the plurality of contact pads 3120 may be arranged on the edge portion of the backplane substrate 3000. A plurality of wirings 3130 can connect the measurement electrodes 3110 and the contact pads 3120, and may be disposed on the scribe area 3020. Figure 15 As shown, five sensors 3100 are arranged on the backplane substrate 3000, but the position and number of sensors 3100 can be changed in various ways, and the scope of this disclosure is not limited thereto.

[0316] The measuring electrode 3110, contact pad 3120, and wiring 3130 can be formed of a conductive material (e.g., a metal such as copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), or neodymium (Nd), an oxide or nitride of said metal, or a transparent conductive oxide such as indium tin oxide (ITO), zinc oxide (ZnO), or indium zinc oxide (IZO).

[0317] For example, after a conductive material layer is formed on a pixel-defining film (PDL), the conductive material layer can be patterned to simultaneously form a measurement electrode 3110, contact pads 3120, and wiring 3130 on the PDL. Specifically, although not shown, after a photoresist pattern (not shown) is formed on the conductive material layer exposing portions other than where the measurement electrode 3110, contact pads 3120, and wiring 3130 will be formed, an anisotropic etching process using the photoresist pattern as an etching mask can be performed to form the measurement electrode 3110, contact pads 3120, and wiring 3130 on the PDL. In another example, the measurement electrode 3110, contact pads 3120, and wiring 3130 can be formed using a damascene process.

[0318] like Figures 16 to 18 As illustrated in the figure, the deposition mask 4000 may include a plurality of mask unit regions 4210, an edge region, and a grid region 4220 disposed between the plurality of mask unit regions 4210, and the plurality of mask unit regions 4210 respectively correspond to a plurality of display unit regions 3010 of the backplane substrate 3000. Each of the mask unit regions 4210 may have a plurality of pixel openings 4230 that expose the electrode pattern AND of the backplane substrate 3000 in the deposition process.

[0319] For example, the deposition mask 4000 may include a mask frame 4100 and a diaphragm 4200 disposed on the mask frame 4100. In this case, the diaphragm 4200 may include a plurality of mask unit regions 4210 and a grid region 4220 disposed between the mask unit regions 4210, and each of the mask unit regions 4210 may have a plurality of pixel openings 4230. The mask frame 4100 may have unit openings 4110 and may include rib regions 4120 defining the unit openings 4110. In this case, the plurality of mask unit regions 4210 may be respectively arranged on the plurality of unit openings 4110, and the grid region 4220 may be disposed on the rib region 4120. Furthermore, the mask unit regions 4210 may be exposed through the unit openings 4110, and the pixel openings 4230 may be connected to the unit openings 4110 while penetrating the mask unit regions 4210.

[0320] like Figure 16 As shown in the figure, multiple mask unit regions 4210 can be arranged in a matrix along a first direction DR1 and a second direction DR2. For example, multiple mask unit regions 4210 can be arranged in a matrix along a first horizontal direction DR1 and a second horizontal direction DR2 perpendicular to the first horizontal direction DR1, and can be arranged to correspond to multiple display unit regions 3010 of the backplane substrate 3000, respectively.

[0321] A diaphragm 4200 can be disposed on the front surface of the mask frame 4100, and a rear inorganic membrane 4300 can be disposed on the rear surface of the mask frame 4100. The diaphragm 4200 and the rear inorganic membrane 4300 can be formed of the same material. For example, the diaphragm 4200 and the rear inorganic membrane 4300 can be made of materials such as silicon nitride (SiN). x Inorganic materials, such as those used in the example, are formed and can be formed to have a thickness of approximately 0.5 μm to approximately 3 μm by a thermochemical vapor deposition (TCVD) process. That is, the front inorganic film and the rear inorganic film 4300 can be simultaneously formed on the front and rear surfaces of the mask frame 4100 by a TCVD process, respectively, and the front inorganic film can be used as a diaphragm 4200.

[0322] A single-crystal silicon substrate can be used as a mask frame 4100, and a pixel opening 4230 can be formed by forming a diaphragm 4200 on the mask frame 4100 and then patterning the diaphragm 4200. For example, the pixel opening 4230 can be formed by forming a photoresist pattern (not shown) on the diaphragm 4200 that exposes the portion where the pixel opening 4230 will be formed, and then performing an anisotropic etching process using the photoresist pattern as an etching mask until the mask frame 4100 is exposed.

[0323] The back inorganic film 4300 may have a back opening 4310 communicating with the unit opening 4110, and may serve as an etching mask in the etching process used to form the unit opening 4110. For example, the back opening 4310 may be formed by forming a photoresist pattern (not shown) on the back inorganic film 4300 that exposes the portion where the back opening 4310 will be formed, and then performing an anisotropic etching process using the photoresist pattern as an etching mask until the back surface of the mask frame 4100 is exposed.

[0324] The cell opening 4110 can be formed as a mask cell region 4210 exposing the diaphragm 4200 by an anisotropic etching process using the inorganic film 4300 as an etching mask. For example, the cell opening 4110 can be formed by a wet etching process using tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH). In this case, the single-crystal silicon substrate used as the mask frame 4100... <100> The crystal orientation can be a third orientation DR3, such that the cell opening 4110 can be formed by a wet etching process to have a width that gradually decreases toward the diaphragm 4200 (i.e., on the third orientation DR3). For example, each of the inner surfaces of the cell opening 4110 can be formed to have a tilt of approximately 54.74°.

[0325] As described herein, when the sensor 3100 is arranged on the backplane substrate 3000, the gap between the backplane substrate 3000 and the deposition mask 4000 can be measured based on the capacitance between the measuring electrode 3110 and the diaphragm 4200.

[0326] In another example, a plurality of spacers 4400, each corresponding to a plurality of sensors 3100 on a backplane substrate 3000, can be formed on a deposition mask 4000. Specifically, the plurality of spacers 4400 can be formed on a grid region 4220 of the deposition mask 4000 to correspond to a plurality of measurement electrodes 3110, respectively. In an example where the backplane substrate 3000 is positioned on the deposition mask 4000, the measurement electrodes 3110 and the spacers 4400 face each other, and the gap between the measurement electrodes 3110 and the spacers 4400 can be measured based on the capacitance between the measurement electrodes 3110 and the spacers 4400. In this case, each of the spacers 4400 can be used as a sensor dog (or detection target) for measuring the gap between the backplane substrate 3000 and the deposition mask 4000, and the gap between the backplane substrate 3000 and the deposition mask 4000 can be calculated based on the gap between the measurement electrodes 3110 and the spacers 4400.

[0327] The spacer 4400 can be formed of a dielectric material or a conductive material. For example, the spacer 4400 can be formed of a material such as silicon oxide (SiO2). x ), silicon nitride (SiN)x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x ), hafnium oxide (HfO) x ) or zirconium oxide (ZrO) x In another example, the spacer 4400 may be formed of a dielectric material such as copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), or neodymium (Nd), an oxide or nitride of said metal, or a transparent conductive oxide such as indium tin oxide (ITO), zinc oxide (ZnO), or indium zinc oxide (IZO).

[0328] Spacers 4400 can be formed on separator 4200 after separator 4200 is formed. In this case, pixel openings 4230 can be formed after spacers 4400 is formed. Specifically, spacers 4400 can be formed on grid regions 4220 of separator 4200 to correspond to measurement electrodes 3110 on backplane substrate 3000. For example, after a dielectric material layer or a conductive material layer is formed on separator 4200, spacers 4400 can be formed on separator 4200 by patterning the dielectric material layer or the conductive material layer. Specifically, although not shown, after a photoresist pattern (not shown) is formed on the dielectric material layer or the conductive material layer exposing the portion where spacers 4400 will be formed, an anisotropic etching process using the photoresist pattern as an etching mask can be performed until separator 4200 is exposed to form spacers 4400 on separator 4200.

[0329] In another example, such as Figure 19 As illustrated, multiple sensors 3200, each including a first contact electrode 3210, a second contact electrode 3220, a first contact pad 3230, a second contact pad 3240, a first wiring 3250, and a second wiring 3260, can be formed on a backplane substrate 3000. The first contact electrode 3210 and the second contact electrode 3220 can be formed at multiple preset measurement points in the scribe area 3020, and the first contact pad 3230 and the second contact pad 3240 can be formed on the edge portion of the backplane substrate 3000. The first wiring 3250 and the second wiring 3260 can connect the first contact electrode 3210 and the second contact electrode 3220 to the first contact pad 3230 and the second contact pad 3240, respectively, and can be formed on the scribe area 3020.

[0330] The first contact electrode 3210 and the second contact electrode 3220, the first contact pad 3230 and the second contact pad 3240, as well as the first wiring 3250 and the second wiring 3260, may be formed of a conductive material (e.g., a metal such as copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) or neodymium (Nd), an oxide or nitride of said metal, or a transparent conductive oxide such as indium tin oxide (ITO), zinc oxide (ZnO) or indium zinc oxide (IZO).

[0331] For example, after a conductive material layer is formed on a pixel-defining film (PDL), the conductive material layer can be patterned to form a first contact electrode 3210 and a second contact electrode 3220, a first contact pad 3230 and a second contact pad 3240, and a first wiring 3250 and a second wiring 3260 on the PDL. Specifically, although not shown, after a photoresist pattern (not shown) exposing portions of the first contact electrode 3210 and the second contact electrode 3220, the first contact pad 3230 and the second contact pad 3240, and the first wiring 3250 and the second wiring 3260 to be formed is formed on the conductive material layer, an anisotropic etching process using the photoresist pattern as an etching mask can be performed to form the first contact electrode 3210 and the second contact electrode 3220, the first contact pad 3230 and the second contact pad 3240, and the first wiring 3250 and the second wiring 3260 on the PDL. In another example, the first contact electrode 3210 and the second contact electrode 3220, the first contact pad 3230 and the second contact pad 3240, and the first wiring 3250 and the second wiring 3260 can be formed by a damascene process.

[0332] When each of the sensors 3200 includes a first contact electrode 3210 and a second contact electrode 3220 as described herein, the spacers 4400 of the deposition mask 4000 may be formed of a conductive material. Specifically, when the backplane substrate 3000 is positioned on the deposition mask 4000, the first contact electrode 3210 and the second contact electrode 3220 may contact the spacers 4400 corresponding to the first contact electrode 3210 and the second contact electrode 3220, and the first contact electrode 3210 and the second contact electrode 3220 may be electrically connected through the corresponding spacers 4400. Specifically, when the first contact electrode 3210 and the second contact electrode 3220 are electrically connected, it can be determined that the first contact electrode 3210 and the second contact electrode 3220 are in contact with the spacer 4400 at corresponding contact points between the first contact electrode 3210, the second contact electrode 3220, and the spacer 4400. Conversely, when the first contact electrode 3210 and the second contact electrode 3220 are not electrically connected, it can be determined that the first contact electrode 3210 and the second contact electrode 3220 are not in contact with the spacer 4400 at corresponding contact points. As a result, the gap between the backplane substrate 3000 and the deposition mask 4000 can be measured depending on whether the first contact electrode 3210 and the second contact electrode 3220 are electrically connected at multiple measurement points.

[0333] refer to Figure 27 and Figure 28 In step S200, the method may include positioning the backplane substrate 3000 on the deposition mask 4000. Specifically, in step S220, the method may include loading the backplane substrate 3000 and the deposition mask 4000 onto the substrate chuck 2300 and the mask chuck 2400, respectively.

[0334] For example, the backplane substrate 3000 can be loaded into the processing chamber 2100 by a transfer robot (not shown) and can be transferred from the transfer robot to the lifting finger 2500 below the substrate chuck 2300. In this case, the rear surface of the backplane substrate 3000 can face the bottom surface of the substrate chuck 2300, and the lifting finger 2500 can support the front edge portion of the backplane substrate 3000. The finger actuator 2510 can raise the lifting finger 2500 so that the backplane substrate 3000 becomes adjacent to the bottom surface of the substrate chuck 2300, and then the rear surface of the backplane substrate 3000 can be held on the bottom surface of the substrate chuck 2300 by electrostatic force.

[0335] The deposition mask 4000 can be loaded into the processing chamber 2100 by a transfer robot and can be transferred to the lifting finger 2500 above the mask chuck 2400. The edge portion of the deposition mask 4000 can be placed on the end of the lifting finger 2500, and the finger actuator 2510 can lower the lifting finger 2500 to load the deposition mask 4000 onto the mask chuck 2400. In this case, the edge portion of the deposition mask 4000 can be placed on the mask chuck 2400, and the mask cell area 4210 of the deposition mask 4000 can be placed on the grid support 2410. Furthermore, the edge portion of the deposition mask 4000 can be held on the mask chuck 2400 by electrostatic force, and the rib area 4120 of the mask frame 4100 can be supported by the grid plate 2412.

[0336] refer to Figure 28 and Figure 29 In step S240, the method may include adjusting the parallelism between the substrate chuck 2300 and the mask chuck 2400. Specifically, the method may include measuring the gap between the substrate chuck 2300 and the mask chuck 2400 using a gap sensor and adjusting the parallelism between the substrate chuck 2300 and the mask chuck 2400 based on the gap measurement results provided by the gap sensor.

[0337] For example, in step S242, the method may include adjusting the gap between the backplane substrate 3000 and the deposition mask 4000 to a first gap. Specifically, the second actuator 2630 may lower the substrate chuck 2300 to a preset height, and the hexapod actuator 2610 may adjust the height of the substrate chuck 2300 such that the gap between the backplane substrate 3000 and the deposition mask 4000 becomes, for example, a first gap of approximately 100 μm to approximately 200 μm.

[0338] In step S244, the method may include initially measuring the gap between the substrate chuck 2300 and the mask chuck 2400 using a first gap sensor. Figure 21 As illustrated, a first gap sensor can be disposed on the edge portion of the substrate chuck 2300, and the distance to the mask chuck 2400 can be measured through a through-hole formed through the edge portion of the substrate chuck 2300. For example, a capacitive proximity sensor can be used as the first gap sensor.

[0339] In step S246, the method may include an initial adjustment of the parallelism between the substrate chuck 2300 and the mask chuck 2400 based on an initial gap measurement (i.e., based on the initially measured gap). For example, the hexapod actuator 2610 may adjust the tilt of the substrate chuck 2300 based on the initially measured gap, thereby initially adjusting the parallelism between the substrate chuck 2300 and the mask chuck 2400.

[0340] In step S248, the method may include adjusting the gap between the backplane substrate 3000 and the deposition mask 4000 to a second gap smaller than the first gap. Specifically, the hexapod actuator 2610 may adjust the height of the substrate chuck 2300 such that the gap between the backplane substrate 3000 and the deposition mask 4000 becomes, for example, a second gap of about 10 μm to about 50 μm.

[0341] In step S250, the method may include measuring the gap between the substrate chuck 2300 and the mask chuck 2400 a second time using a second gap sensor. Figure 21 As illustrated in the diagram, the second gap sensor can be disposed on the edge portion of the substrate chuck 2300, and the distance to the mask chuck 2400 can be measured through a through-hole formed through the edge portion of the substrate chuck 2300. For example, a confocal sensor with a higher resolution than the first gap sensor can be used as the second gap sensor and can be disposed on the edge portion of the substrate chuck 2300 adjacent to the first gap sensor.

[0342] In step S252, the method may include a second adjustment of the parallelism between the substrate chuck 2300 and the mask chuck 2400 based on a second measurement of the gap (i.e., based on the second measured gap). For example, the hexapod actuator 2610 may adjust the tilt of the substrate chuck 2300 based on the second measured gap, thereby adjusting the parallelism between the substrate chuck 2300 and the mask chuck 2400 for the second time.

[0343] refer to Figure 28 After adjusting the parallelism between the substrate chuck 2300 and the mask chuck 2400 as described herein, the method may include aligning the backplane substrate 3000 and the deposition mask 4000 with each other in step S260. For example, although not shown, a plurality of substrate alignment keys (not shown) may be arranged on the edge portions of the backplane substrate 3000, and a plurality of mask alignment keys (not shown) corresponding to the plurality of substrate alignment keys may be arranged on the edge portions of the deposition mask 4000. Furthermore, the deposition apparatus 2000 may include a camera unit (not shown) for detecting the substrate alignment keys and the mask alignment keys, and an illumination unit (not shown) for illuminating the substrate alignment keys and the mask alignment keys, and the substrate chuck 2300 and / or the mask chuck 2400 may be provided with through-holes (not shown) for providing illumination light and detecting the substrate alignment keys and the mask alignment keys.

[0344] For example, the illumination unit can provide near-infrared (NIR) or short-wave infrared (SWIR) light with wavelengths of approximately 1010 nm to approximately 1020 nm, and the camera unit can detect the infrared light transmitted through the backplane substrate 3000 and the deposition mask 4000. The hexapod actuator 2610 can perform alignment between the backplane substrate 3000 and the deposition mask 4000 based on the position information of the substrate alignment key and mask alignment key acquired by the camera unit. For example, the hexapod actuator 2610 can adjust the X-axis position, Y-axis position, and azimuth angle of the substrate chuck 2300 based on image information acquired by the camera unit.

[0345] In some embodiments, as described above, the backplane substrate 3000 and the deposition mask 4000 are aligned with each other after a second adjustment of the parallelism between the substrate chuck 2300 and the mask chuck 2400; however, the embodiments of this disclosure are not limited thereto. For example, unlike above, the backplane substrate 3000 and the deposition mask 4000 may be aligned with each other after an initial adjustment of the parallelism between the substrate chuck 2300 and the mask chuck 2400.

[0346] After aligning the backplane substrate 3000 and the deposition mask 4000 as described herein, in step S280, the method may include adjusting the gap between the substrate chuck 2300 and the mask chuck 2400 such that the backplane substrate 3000 is positioned on the deposition mask 4000. For example, the hexapod actuator 2610 may adjust the height of the substrate chuck 2300 such that the gap between the backplane substrate 3000 and the deposition mask 4000 becomes a predetermined gap, such as a gap of a few micrometers. In another example, the hexapod actuator 2610 may adjust the height of the substrate chuck 2300 such that the backplane substrate 3000 contacts the deposition mask 4000.

[0347] Return to reference Figure 27 After the backplane substrate 3000 is positioned on the deposition mask 4000, in step S300, the method may include measuring the gap between the backplane substrate 3000 and the deposition mask 4000 using a sensor. For example, if as Figure 15 The sensors 3100, each including a measurement electrode 3110, a contact pad 3120, and a wiring 3130, are formed on the backplane substrate 3000. The capacitance between the measurement electrode 3110 and the diaphragm 4200 of the deposition mask 4000 can be detected by the signal detector 2900, thereby measuring the gap between the backplane substrate 3000 and the deposition mask 4000.

[0348] In another example, such as Figures 16 to 18As shown in the figure, when the spacer 4400 is formed on the diaphragm 4200 of the deposition mask 4000, the capacitance between the measuring electrode 3110 and the spacer 4400 can be detected by the signal detector 2900, thereby measuring the gap between the backplane substrate 3000 and the deposition mask 4000.

[0349] In another example, such as Figure 19 As illustrated in the figure, when a sensor 3200, comprising a first contact electrode 3210, a second contact electrode 3220, a first contact pad 3230, a second contact pad 3240, a first wiring 3250, and a second wiring 3260, is formed on a backplane substrate 3000, the method may include detecting, by a signal detector 2900, whether the first contact electrode 3210 and the second contact electrode 3220 are in contact with each other and the spacer 4400, i.e., whether the first contact electrode 3210 and the second contact electrode 3220 are electrically connected, thereby measuring the gap between the backplane substrate 3000 and the deposition mask 4000.

[0350] In another example, such as Figure 25 As illustrated in the figure, when a sensor 4500, each including a measurement electrode 4510, a contact pad 4520, and wiring 4530, is formed on a deposition mask 4000, the method may include measuring the gap between the backplane substrate 3000 and the deposition mask 4000 by detecting the capacitance between the pixel defining film PDL on the backplane substrate 3000 and the measurement electrode 4510 by a signal detector 2900.

[0351] After measuring the gap between the backplane substrate 3000 and the deposition mask 4000 as described herein, in step S400, the method may include adjusting the parallelism between the backplane substrate 3000 and the deposition mask 4000 based on the gap between the backplane substrate 3000 and the deposition mask 4000 (i.e., the measurement result of the gap). For example, the hexapod actuator 2610 may adjust the tilt of the substrate chuck 2300 such that all gaps between the backplane substrate 3000 and the deposition mask 4000 meet a preset tolerance range. Specifically, the tilt of the substrate chuck 2300 may be adjusted such that the capacitance values ​​between the measuring electrode 3110 and the diaphragm 4200, between the measuring electrode 3110 and the spacer 4400, or between the measuring electrode 4510 and the pixel defining film (PDL) all meet the tolerance range. In another example, the tilt of the substrate chuck 2300 may be adjusted such that both the first contact electrode 3210 and the second contact electrode 3220 are electrically connected. As a result, by performing step S400, the gap between the backplane substrate 3000 and the deposition mask 4000 can become consistent, and the parallelism between the backplane substrate 3000 and the deposition mask 4000 can be improved.

[0352] After performing step S400, in step S500, the method may include providing a deposition material on the backplane substrate 3000 through a deposition mask 4000. The provision of the deposition material forms a deposition material layer on the backplane substrate 3000. For example, the deposition source 2200 may disperse organic material (e.g., in gaseous or vapor form) for forming a light-emitting material layer on the backplane substrate 3000, and the dispersed organic material may be deposited on the electrode pattern AND of the backplane substrate 3000 through pixel openings 4230 of the deposition mask 4000.

[0353] The deposition techniques and apparatus according to embodiments of the present disclosure described herein can improve the parallelism between the backplane substrate 3000 and the deposition mask 4000, thereby improving the pixel position accuracy of the light-emitting material layer formed on the backplane substrate 3000. Furthermore, the deposition techniques and apparatus described herein can help reduce color mixing between light-emitting material layers.

[0354] The aspects of this invention should not be construed as limited to the embodiments set forth herein. Rather, exemplary embodiments are provided so that this disclosure will be thorough and complete, and these embodiments will fully convey the inventive concept to those skilled in the art.

[0355] Although the invention has been specifically illustrated and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A deposition method, comprising: forming a plurality of sensors on a substrate or a deposition mask to measure a gap between the substrate and the deposition mask; positioning the substrate on the deposition mask; measuring the gap between the substrate and the deposition mask using the plurality of sensors; adjusting a parallelism between the substrate and the deposition mask based on the gap between the substrate and the deposition mask; and providing a deposition material through the deposition mask onto the substrate, wherein providing the deposition material forms a deposition material layer on the substrate.

2. The deposition method of claim 1, wherein: the substrate includes a plurality of display cell regions, an edge region, and a scribe region disposed between the plurality of display cell regions, and each of the plurality of sensors includes: a measurement electrode formed on the scribe region; a contact pad formed on the edge region; and wiring formed on the scribe region and connecting the measurement electrode and the contact pad. each of the gaps between the substrate and the deposition mask is measured based on a capacitance between the measurement electrode and the deposition mask.

3. The deposition method of claim 2, wherein, 4. The deposition method of claim 2, further comprising: forming a plurality of spacers on the deposition mask, wherein each of the gaps between the substrate and the deposition mask is measured based on a capacitance between the measurement electrode and a corresponding spacer included among the plurality of spacers.

5. The deposition method of claim 1, wherein: the deposition mask includes a plurality of mask cell regions, an edge region, and a mesh region disposed between the plurality of mask cell regions, and each of the plurality of sensors includes: a measurement electrode formed on the mesh region; a contact pad formed on the edge region; and wiring formed on the mesh region and connecting the measurement electrode and the contact pad. each of the gaps between the substrate and the deposition mask is measured based on a capacitance between the measurement electrode and the substrate.

6. The deposition method of claim 5, wherein, the positioning of the substrate on the deposition mask includes:

7. The deposition method of claim 1, wherein, loading the substrate and the deposition mask onto a substrate chuck and a mask chuck, respectively, such that the substrate and the deposition mask face each other; adjusting a parallelism between the substrate chuck and the mask chuck; aligning the substrate and the deposition mask to each other; and adjusting a gap between the substrate chuck and the mask chuck such that the substrate is positioned on the deposition mask. the adjustment of the parallelism between the substrate chuck and the mask chuck includes:

8. The deposition method according to claim 7, wherein, measuring a gap between the substrate chuck and the mask chuck using a gap sensor arranged on the substrate chuck; and adjusting an inclination of the substrate chuck based on the gap between the substrate chuck and the mask chuck.

9. A deposition apparatus, comprising: a deposition source to provide a deposition material onto a substrate; a mask chuck disposed above the deposition source and supporting a deposition mask; a substrate chuck disposed above the mask chuck and supporting the substrate such that the substrate faces the deposition mask; ​ and a substrate chuck driver adjusting a position and a tilt of the substrate chuck to position the substrate on the deposition mask and adjust parallelism between the substrate and the deposition mask, wherein a plurality of sensors for measuring a gap between the substrate and the deposition mask are disposed on the substrate or the deposition mask, and the substrate chuck driver adjusts the tilt of the substrate chuck based on a measurement of the gap between the substrate and the deposition mask provided by the plurality of sensors.

10. The deposition apparatus of claim 9, wherein: the substrate includes a plurality of display cell regions, a margin region, and a scribe region disposed between the plurality of display cell regions, and each of the plurality of sensors includes: a measurement electrode formed on the scribe region; a contact pad formed on the margin region; and a wiring disposed on the scribe region and connecting the measurement electrode and the contact pad.

11. The deposition apparatus of claim 10, further comprising: a signal detector including a plurality of probes in contact with the contact pads of the plurality of sensors.

12. The deposition apparatus of claim 11, wherein: the signal detector is disposed in the mask chuck, and the deposition mask has a through-hole or a groove through which the plurality of probes pass.

13. The deposition apparatus of claim 11, wherein, the signal detector respectively detects capacitances between the measurement electrodes of the plurality of sensors and the deposition mask, and measures the gap between the substrate and the deposition mask based on the detected capacitances.

14. The deposition apparatus of claim 11, wherein: a plurality of spacers are disposed on the deposition mask and face the measurement electrodes of the plurality of sensors, and the signal detector respectively detects capacitances between the measurement electrodes of the plurality of sensors and the plurality of spacers, and measures the gap between the substrate and the deposition mask based on the detected capacitances.

15. The deposition apparatus of claim 9, wherein: the deposition mask includes a mask cell region, a margin region, and a grid region disposed between the mask cell regions, and each of the plurality of sensors includes: a measurement electrode disposed on the grid region; a contact pad disposed on the margin region; and a wiring disposed on the grid region and connecting the measurement electrode and the contact pad.

16. The deposition apparatus of claim 15, further comprising: a signal detector including a plurality of probes in contact with the contact pads of the plurality of sensors.

17. The deposition apparatus of claim 16, wherein: the signal detector is disposed in the mask chuck, the deposition mask has a sensor opening exposing the contact pads, and the plurality of probes are in contact with the contact pads through the sensor opening.

18. The deposition apparatus of claim 16, wherein, the signal detector respectively detects capacitances between the measurement electrodes of the plurality of sensors and the substrate, and measures the gap between the substrate and the deposition mask based on the detected capacitances.

19. The deposition apparatus of claim 9, further comprising: a plurality of gap sensors for measuring a gap between the substrate chuck and the mask chuck, wherein the substrate chuck driver adjusts the tilt of the substrate chuck based on measurements of the gap between the substrate chuck and the mask chuck provided by the plurality of gap sensors to adjust a parallelism between the substrate chuck and the mask chuck.

20. An electronic device comprising a display panel comprising a substrate and a layer of light emitting material formed on the substrate using the deposition apparatus of any one of claims 9 to 19.

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