Clock skew error correction method based on analog-to-digital converter and medium
By acquiring the clock skew error information of the analog-to-digital converter and actively correcting it using gain logic circuits and digitally adjustable delay circuits, the problems of high power consumption and increased area in the prior art are solved, and a better clock skew error correction effect is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-28
- Publication Date
- 2026-03-10
AI Technical Summary
Existing technologies for handling clock skew errors in analog-to-digital converters often employ passive methods such as power isolation, substrate isolation, and shielding, which lead to increased power consumption and chip area, while also resulting in poor spurious suppression.
By acquiring the clock skew error information of the analog-to-digital converter, active correction is performed using gain logic circuits and digitally adjustable delay circuits, including storing the clock skew error information, gain conversion, and switching branch adjustment, inversely canceling the clock skew error.
It effectively reduces power consumption, reduces chip area, improves the correction effect of clock skew error, and ensures electrostatic protection capability.
Smart Images
Figure CN121643741A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the chip technical field, and particularly to a clock skew error correction method based on an analog-to-digital converter and a medium. BACKGROUND
[0002] In the chip technical field, when an analog-to-digital converter converts a signal, it is usually disturbed by various disturbances, and when the disturbances act on the clock signal of the analog-to-digital converter, clock skew is caused. If the clock skew occurs periodically, the corresponding spurs will appear on the spectrum of the sampled signal.
[0003] The inventor found that the prior art has the following defects in the process of implementing the present application: For such disturbances, the general processing method includes passive means such as power isolation, substrate isolation, or shielding. These means usually require additional design costs, including but not limited to increased power consumption, increased chip area, or weakened electrostatic protection capability. As a result, due to the compromise of the aforementioned various costs, the spur suppression caused by the disturbance cannot achieve good results. SUMMARY
[0004] The present application provides a clock skew error correction method based on an analog-to-digital converter and a medium to better correct clock skew errors.
[0005] According to one aspect of the present application, a clock skew error correction method based on an analog-to-digital converter is provided, which comprises:
[0006] Obtaining and acquiring the current clock collection frequency corresponding to the target analog-to-digital converter, and obtaining the current periodic clock skew error information by a pre-set clock skew error extraction method, and storing the current periodic clock skew error information in a clock skew error storage;
[0007] When the target analog-to-digital converter sends the current clock signal data to the target digital processing module, instructing the target gain logic circuit conversion module to obtain the current periodic clock skew error information in the clock skew error storage, and performing gain conversion on the current periodic clock skew error information to obtain a target to-be-corrected clock skew error;
[0008] According to the target to-be-corrected clock skew error, adjusting each switch branch in the pre-set digital adjustable delay circuit driver to realize reverse cancellation of the target to-be-corrected clock skew error according to the adjusted digital adjustable delay circuit driver, and sending the current clock signal data to the target digital processing module.
[0009] According to another aspect of the present application, there is provided an apparatus for correcting clock skew error based on an analog-to-digital converter, comprising:
[0010] a current periodic clock skew error information storage module configured to obtain current periodic clock skew error information according to a current clock acquisition frequency corresponding to the target analog-to-digital converter, and store the current periodic clock skew error information in a clock skew error storage;
[0011] a target clock skew error to be corrected determination module configured to instruct a target gain logic circuit conversion module to obtain the current periodic clock skew error information in the clock skew error storage and perform gain conversion on the current periodic clock skew error information to obtain a target clock skew error to be corrected when the target analog-to-digital converter sends current clock signal data to a target digital processing module;
[0012] a target clock skew error to be corrected correction module configured to adjust each switch branch in a pre-set digital adjustable delay circuit driver according to the target clock skew error to be corrected, so as to realize reverse compensation of the target clock skew error to be corrected according to the adjusted digital adjustable delay circuit driver, and send the current clock signal data to the target digital processing module.
[0013] According to another aspect of the present application, there is provided an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method for correcting clock skew error based on an analog-to-digital converter according to any one of the embodiments of the present application when executing the computer program.
[0014] According to another aspect of the present application, there is provided a computer readable storage medium storing computer instructions for causing a processor to implement the method for correcting clock skew error based on an analog-to-digital converter according to any one of the embodiments of the present application when executing the computer instructions.
[0015] The technical scheme of the embodiment of the present application acquires the current clock collection frequency corresponding to the target analog-to-digital converter, obtains the current periodic clock skew error information through the pre-set clock skew error extraction method, and stores the current periodic clock skew error information in the clock skew error storage; when the target analog-to-digital converter sends the current clock signal data to the target digital processing module, the target gain logic circuit conversion module acquires the current periodic clock skew error information in the clock skew error storage, and performs gain conversion on the current periodic clock skew error information to obtain the target to-be-corrected clock skew error; according to the target to-be-corrected clock skew error, each switch branch in the pre-set digital adjustable delay circuit driver is adjusted to realize the reverse offset of the target to-be-corrected clock skew error according to the adjusted digital adjustable delay circuit driver, and the current clock signal data is sent to the target digital processing module. The problem of poor effect and large power consumption caused by passive means such as power isolation, substrate isolation or shielding for clock skew correction is solved, the clock skew error correction is better realized, the power consumption required for error correction is reduced, the use of chip area is reduced, and the electrostatic protection capability of the chip is ensured.
[0016] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0018] Figure 1 is a flow chart of an analog-to-digital converter-based clock skew error correction method according to the first embodiment of the present application;
[0019] Figure 2 is a structural schematic diagram of an analog-to-digital converter-based clock skew error correction device according to the second embodiment of the present application;
[0020] Figure 3 is a structural schematic diagram of an electronic device according to the third embodiment of the present application. DETAILED DESCRIPTION
[0021] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort should belong to the protection scope of the present application.
[0022] It should be noted that the terms "target", "current" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.
[0023] It should be noted that in the technical solutions of the present application, the collected information is information and data authorized by the user or authorized by all parties, and the collection, storage, use, processing, transmission, provision, disclosure and application of related data comply with relevant laws, regulations and standards of relevant countries and regions, necessary security measures are taken, do not violate public order and good customs, and provide corresponding operation portal for user to choose authorization or refusal; if the user chooses to refuse, enter the expert decision-making process.
[0024] Embodiment one
[0025] Figure 1 A flowchart of a clock skew error correction method based on an analog-to-digital converter is provided for the first embodiment of the present application. The present embodiment is applicable to the case of actively correcting the generated clock skew error in the process of sending clock signal data to the analog-to-digital converter. The method can be executed by a clock skew error correction device based on an analog-to-digital converter, which can be realized in the form of hardware and / or software.
[0026] Correspondingly, as shown in Figure 1 , the method comprises:
[0027] S110, acquiring and obtaining current periodic clock skew error information according to a current clock collection frequency corresponding to the target analog-to-digital converter through a pre-set clock skew error extraction method, and storing the current periodic clock skew error information in a clock skew error storage.
[0028] In the embodiment, the clock skew error correction method can be performed in a chip testing link or after the chip is integrated into a system, and the method belongs to an active correction method.
[0029] In the embodiment, when the target analog-to-digital converter sends current clock signal data to the target digital processing module, since the current clock collection frequency corresponding to the target analog-to-digital converter can be set as Fs, the frequency of the target digital processing module of the interference source is , where n is a period, and thus the clock skew occurs every n periods, and the time length corresponding to the period is . Therefore, the correction processing of the clock skew error needs to be periodically performed.
[0030] Therefore, before the correction of the clock skew error, the current periodic clock skew error information needs to be acquired and stored in the clock skew error storage.
[0031] Specifically, the acquiring and obtaining current periodic clock skew error information according to a current clock collection frequency corresponding to the target analog-to-digital converter through a pre-set clock skew error extraction method includes: obtaining a pre-set integer multiple parameter value, and multiplying the integer multiple parameter value with the current clock collection frequency corresponding to the target analog-to-digital converter to calculate a current analog-to-digital converter input frequency; inputting test data to the target analog-to-digital converter according to the current analog-to-digital converter input frequency to obtain current analog-to-digital converter test output data; and obtaining current periodic clock skew error information through the clock skew error extraction method according to the current analog-to-digital converter test output data.
[0032] In detail, the obtaining current periodic clock skew error information through the clock skew error extraction method according to the current analog-to-digital converter test output data includes: performing fast Fourier transform spectrum analysis on the current analog-to-digital converter test output data through the clock skew error extraction method to obtain each spur center frequency point, and target skew spur amplitude and target skew spur frequency corresponding to each spur center frequency point, respectively; and filtering the current analog-to-digital converter test output data using a pre-set target band-pass filter according to each spur center frequency point, target skew spur amplitude and target skew spur frequency to obtain the current periodic clock skew error information.
[0033] The current periodic clock skew error information can be clock skew error information of a complete period collected. The clock skew error memory can be a memory for storing current periodic clock skew error information of different periods.
[0034] In the embodiment, when the current ADC input frequency is an integer multiple of the current clock collection frequency, the ideal current ADC outputs a direct current signal. For the disturbed current ADC, the clock skew will change regularly. Specifically, according to the input frequency, the current ADC output will contain clock skew information in addition to the direct current signal, which is related to the frequency of the interference source.
[0035] Therefore, first, the integer multiple parameter value is obtained. Assuming that the integer multiple parameter value is M and the current clock collection frequency is Fs, the current ADC input frequency can be calculated as . Further, the current ADC input frequency can be used to input test data to the target ADC to obtain current ADC test output data, that is, the current ADC test output data contains clock skew information. Accordingly, the current periodic clock skew error information is obtained by the clock skew error extraction method.
[0036] Specifically, the current ADC test output data is subjected to fast Fourier transform spectrum analysis. The clock skew caused by the periodic interference will produce spurs at specific frequencies. It can be assumed that the spurs are generated at , , , …, frequencies, where k is an integer. Therefore, the corresponding spur generation center frequency can be obtained, which is , and the target skew spur amplitude and the target skew spur frequency corresponding to each spur generation center frequency.
[0037] Further, the target bandpass filter, specifically a comb filter, can be used to filter the target skew spur amplitude and the target skew spur frequency corresponding to the current ADC test output data according to the spur generation center frequency , to obtain the current periodic clock skew error information. Through the above processing operation, the output data can be changed into a set of periodically changing data, and the set of periodic data is cut off for a complete period and stored in the designated clock skew error memory. Accordingly, the current periodic clock skew error information extracted can be used to correct the clock skew error of the ADC.
[0038] S120, when the target analog-to-digital converter sends current clock signal data to the target digital processing module, instructing the target gain logic circuit conversion module to obtain current periodic clock skew error information in the clock skew error memory, and to perform gain conversion on the current periodic clock skew error information to obtain a target to-be-corrected clock skew error.
[0039] The target gain logic circuit conversion module can be a module for performing gain conversion processing on the clock skew error information.
[0040] Optionally, when the target analog-to-digital converter sends current clock signal data to the target digital processing module, instructing the target gain logic circuit conversion module to obtain current periodic clock skew error information in the clock skew error memory, and to perform gain conversion on the current periodic clock skew error information to obtain a target to-be-corrected clock skew error, includes: when the target analog-to-digital converter sends current clock signal data to the target digital processing module, a current gain parameter value is calculated by a pre-set gain calculation method; instructing the target gain logic circuit conversion module to obtain the current periodic clock skew error information in the clock skew error memory; instructing the target gain logic circuit conversion module to use the current gain parameter value to perform gain correction conversion on the current periodic clock skew error information to obtain the target to-be-corrected clock skew error.
[0041] The gain calculation method can be a method for calculating a gain parameter value, which can be a least square method.
[0042] In this embodiment, if the target analog-to-digital converter sends current clock signal data to the target digital processing module, a current gain parameter value G is first calculated. Then, the target gain logic circuit conversion module can be used to perform gain correction conversion on the current periodic clock skew error information according to the current gain parameter value G to obtain a specific target to-be-corrected clock skew error. The target to-be-corrected clock skew error can correspond to a corresponding periodic delay control word.
[0043] S130, according to the target to-be-corrected clock skew error, adjusting each switch branch in the pre-set digital adjustable delay circuit driver to realize reverse cancellation of the target to-be-corrected clock skew error according to the adjusted digital adjustable delay circuit driver, and sending the current clock signal data to the target digital processing module.
[0044] The digital adjustable delay circuit driver can be a driver used to reverse cancel the target to-be-corrected clock skew error.
[0045] Specifically, the target digital adjustable delay circuit corresponding to the digital adjustable delay circuit driver includes a plurality of switch branches, and each switch branch is arranged with a capacitor of different size; the digital adjustable delay circuit driver is located between the target analog-to-digital converter and the target digital processing module, and is used for performing clock skew error correction processing on the transmitted current clock signal data.
[0046] In the embodiment, the target digital adjustable delay circuit includes a plurality of switch branches, and each switch branch can access a corresponding capacitor by controlling the opening or closing of a switch. Different sizes of capacitors are arranged on each switch branch.
[0047] Optionally, the adjusting each switch branch in the preset digital adjustable delay circuit driver according to the target clock skew error to be corrected comprises: performing capacitor parameter conversion on the target clock skew error to be corrected by using a preset capacitor parameter logic circuit calculation method to obtain a current correction capacitor parameter; and adjusting each switch branch in the target digital adjustable delay circuit corresponding to the digital adjustable delay circuit driver according to the current correction capacitor parameter to obtain an adjusted target adjustment digital adjustable delay circuit; wherein the target adjustment digital adjustable delay circuit is used for counteracting the target clock skew error to be corrected.
[0048] The capacitor parameter logic circuit calculation method can be a method of determining a required current correction capacitor parameter according to a periodic delay control word in the target clock skew error to be corrected.
[0049] Specifically, the adjusting each switch branch in the target digital adjustable delay circuit corresponding to the digital adjustable delay circuit driver according to the current correction capacitor parameter to obtain an adjusted target adjustment digital adjustable delay circuit comprises: obtaining capacitor parameters corresponding to each switch branch in the target digital adjustable delay circuit; determining whether the capacitor parameter corresponding to one switch branch or the capacitor parameters corresponding to a plurality of switch branches and values meet the requirements of the current correction capacitor parameter, if yes, setting the switch corresponding to the one or more switch branches to a closed state, and setting the switches corresponding to the remaining switch branches to an open state to obtain the target adjustment digital adjustable delay circuit; and if not, feeding back error information instructions to the user.
[0050] In the embodiment, after determining that the current correction capacitor parameter is calculated, each switch branch needs to be adjusted according to the capacitor parameter corresponding to each switch branch. It is assumed that the current correction capacitor parameter is A; it is assumed that the target digital adjustable delay circuit includes three switch branches, wherein the capacitor parameter corresponding to the switch branch 1 is B; the capacitor parameter corresponding to the switch branch 2 is C; the capacitor parameter corresponding to the switch branch 3 is D; it is assumed that .
[0051] Further, since the combination of the capacitor parameter C corresponding to the switch branch 2 and the capacitor parameter D corresponding to the switch branch 3 meets the requirement of the current corrected capacitor parameter, the switch corresponding to the switch branch 2 and the switch branch 3 needs to be set to the closed state, and the switch corresponding to the switch branch 1 needs to be set to the open state; and then the target adjustment digital adjustable delay circuit can be generated. Conversely, if the requirement of the current corrected capacitor parameter cannot be met, an error information instruction is fed back to the user.
[0052] In the embodiment, the target to-be-corrected clock skew error generated in the process of sending the current clock signal data by the target analog-to-digital converter to the target digital processing module can be counteracted by the target adjustment digital adjustable delay circuit corresponding to the digital adjustable delay circuit driver, so that the target digital processing module can only receive the current clock signal data. In this way, the spur caused by the clock skew can be completely corrected, and the precision of spur suppression also depends on the calculation precision of the correction algorithm, the storage capacity of the clock skew error storage, and the minimum step of the numerical adjustable delay, and the like.
[0053] The technical scheme of the embodiment of the application acquires the current periodic clock skew error information through a pre-set clock skew error extraction method according to the current clock acquisition frequency corresponding to the target analog-to-digital converter, and stores the current periodic clock skew error information in a clock skew error storage; when the target analog-to-digital converter sends the current clock signal data to the target digital processing module, the target gain logic circuit conversion module is instructed to acquire the current periodic clock skew error information in the clock skew error storage, and to perform gain conversion on the current periodic clock skew error information to obtain a target to-be-corrected clock skew error; according to the target to-be-corrected clock skew error, each switch branch in the pre-set digital adjustable delay circuit driver is adjusted to counteract the target to-be-corrected clock skew error in the reverse direction according to the adjusted digital adjustable delay circuit driver, and the current clock signal data is sent to the target digital processing module. The problem of poor effect and high power consumption caused by passive means such as power isolation, substrate isolation or shielding for clock skew correction is solved, the correction of the clock skew error is better implemented, the power consumption required for error correction is reduced, the use of chip area is reduced, and the electrostatic protection capability of the chip is ensured.
[0054] Embodiment two
[0055] Figure 2A structural schematic diagram of a clock skew error correction device based on an analog-to-digital converter is provided for Embodiment Two of the present application. The clock skew error correction device based on an analog-to-digital converter provided in this embodiment can be implemented through software and / or hardware, and can be configured in a terminal device or a server to implement the clock skew error correction method based on an analog-to-digital converter in the embodiments of the present application. As shown in FIG. Figure 2 The device includes a current periodic clock skew error information storage module 210, a target clock skew error to be corrected determination module 220, and a target clock skew error to be corrected correction module 230.
[0056] The current periodic clock skew error information storage module 210 is configured to acquire current clock collection frequency corresponding to the target analog-to-digital converter, obtain current periodic clock skew error information through a pre-set clock skew error extraction method, and store the current periodic clock skew error information in a clock skew error storage.
[0057] The target clock skew error to be corrected determination module 220 is configured to instruct a target gain logic circuit conversion module to acquire the current periodic clock skew error information in the clock skew error storage and perform gain conversion on the current periodic clock skew error information to obtain target clock skew error to be corrected when the target analog-to-digital converter sends current clock signal data to a target digital processing module.
[0058] The target clock skew error to be corrected correction module 230 is configured to adjust each switch branch in a pre-set digital adjustable delay circuit driver according to the target clock skew error to be corrected, to realize reverse offset of the target clock skew error to be corrected according to the adjusted digital adjustable delay circuit driver, and send the current clock signal data to the target digital processing module.
[0059] The technical solution of this invention involves acquiring and obtaining current periodic clock skew error information based on the current clock acquisition frequency corresponding to the target analog-to-digital converter (ADC) using a pre-set clock skew error extraction method, and storing the current periodic clock skew error information in a clock skew error memory. When the target ADC sends current clock signal data to the target digital processing module, the target gain logic circuit conversion module is instructed to acquire the current periodic clock skew error information in the clock skew error memory and perform gain conversion on the current periodic clock skew error information to obtain the target clock skew error to be corrected. Based on the target clock skew error to be corrected, each switch branch in the pre-set digital adjustable delay circuit driver is adjusted to reversely cancel the target clock skew error to be corrected using the adjusted digital adjustable delay circuit driver, and the current clock signal data is sent to the target digital processing module. It solves the problems of poor performance and high power consumption caused by passive clock skew correction through power isolation, substrate isolation or shielding, and better realizes clock skew error correction, reduces the power consumption required for error correction, reduces the chip area used, and ensures the chip's electrostatic protection capability.
[0060] Based on the above embodiments, the current periodic clock skew error information storage module 210 may specifically include: a current analog-to-digital converter (ADC) input frequency calculation unit, which may be specifically used to: obtain a preset integer multiple parameter value and multiply it with the current clock acquisition frequency corresponding to the target ADC to calculate the current ADC input frequency; a current ADC test output data determination unit, which may be specifically used to: input test data to the target ADC according to the current ADC input frequency to obtain the current ADC test output data; and a current periodic clock skew error information determination unit, which is used to obtain the current periodic clock skew error information based on the current ADC test output data and through the clock skew error extraction method.
[0061] Based on the above embodiments, the current periodic clock skew error information determination unit can be specifically used to: perform fast Fourier transform spectrum analysis on the current analog-to-digital converter test output data using the clock skew error extraction method to obtain each spurious generation center frequency, and the target skew spurious amplitude and target skew spurious frequency corresponding to each spurious generation center frequency; and filter the current analog-to-digital converter test output data using a pre-set target bandpass filter according to each spurious generation center frequency, target skew spurious amplitude, and target skew spurious frequency to obtain the current periodic clock skew error information.
[0062] On the basis of the above embodiments, the target clock skew error to be corrected determination module 220 can be specifically used for: when the target analog-to-digital converter sends current clock signal data to the target digital processing module, calculating a current gain parameter value by using a preset gain calculation method; instructing the target gain logic circuit conversion module to obtain current periodic clock skew error information in the clock skew error storage; and instructing the target gain logic circuit conversion module to use the current gain parameter value to perform gain correction conversion on the current periodic clock skew error information to obtain the target clock skew error to be corrected.
[0063] On the basis of the above embodiments, the target digital adjustable delay circuit corresponding to the digital adjustable delay circuit driver includes a plurality of switch branches, and each switch branch is arranged with a capacitor of different size; the digital adjustable delay circuit driver is located between the target analog-to-digital converter and the target digital processing module, and is used for performing clock skew error correction processing on the transmitted current clock signal data.
[0064] On the basis of the above embodiments, the target clock skew error to be corrected correction module 230 can specifically include: a current correction capacitor parameter determination unit, which can be specifically used for: using a preset capacitor parameter logic circuit calculation method to perform capacitor parameter conversion on the target clock skew error to be corrected to obtain a current correction capacitor parameter; and a target adjusted digital adjustable delay circuit determination unit, which can be specifically used for: adjusting each switch branch in the target digital adjustable delay circuit corresponding to the digital adjustable delay circuit driver according to the current correction capacitor parameter to obtain an adjusted target digital adjustable delay circuit; wherein the target adjusted digital adjustable delay circuit is used for counteracting the target clock skew error to be corrected.
[0065] On the basis of the above embodiments, the target adjusted digital adjustable delay circuit determination unit can be specifically used for: obtaining capacitor parameters corresponding to each switch branch in the target digital adjustable delay circuit; judging whether the capacitor parameter corresponding to one switch branch or the capacitor parameters corresponding to a plurality of switch branches meets the requirement of the current correction capacitor parameter, if yes, setting the switch corresponding to the one or more switch branches to a closed state, and setting the switches corresponding to the remaining switch branches to an open state to obtain the target adjusted digital adjustable delay circuit; and if not, feeding back error information instructions to the user.
[0066] The clock skew error correction device based on an analog-to-digital converter provided in the embodiments of the present application can execute the clock skew error correction method based on an analog-to-digital converter provided in any of the embodiments of the present application, and has the corresponding function modules and beneficial effects of the execution method.
[0067] Embodiment three
[0068] Figure 3 A structural diagram of an electronic device 10 of Embodiment Three that can be used to implement the present application is shown. The electronic device is intended to represent a variety of forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular telephones, smart phones, wearable devices (e.g., headsets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present application described and / or claimed in this document.
[0069] As shown in Figure 3 The electronic device 10 includes at least one processor 11, and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., communicatively connected to the at least one processor 11, where the memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer programs stored in the read-only memory (ROM) 12 or loaded into the random access memory (RAM) 13 from the storage unit 18. Various programs and data required for the operation of the electronic device 10 can also be stored in the RAM 13. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.
[0070] Various components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc., an output unit 17, such as various types of displays, a speaker, etc., a storage unit 18, such as a magnetic disk, an optical disk, etc., and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.
[0071] The processor 11 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs various methods and processes described above, such as the clock skew error correction method based on an analog-to-digital converter.
[0072] In some embodiments, the clock skew error correction method based on an analog-to-digital converter can be implemented as a computer program tangibly embodied in a computer readable storage medium, such as storage unit 18. In some embodiments, parts or all of the computer program can be loaded and / or installed onto electronic device 10 via, for example, ROM 12 and / or communication unit 19. When the computer program is loaded onto RAM 13 and executed by processor 11, one or more steps of the clock skew error correction method based on an analog-to-digital converter described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to perform the clock skew error correction method based on an analog-to-digital converter by way of other any suitable means, such as, for example, by way of firmware.
[0073] The method comprises: obtaining and according to the current clock acquisition frequency corresponding to the target analog-to-digital converter, obtaining the current periodic clock skew error information by the pre-set clock skew error extraction method, and storing the current periodic clock skew error information in the clock skew error storage; when the target analog-to-digital converter sends the current clock signal data to the target digital processing module, instructing the target gain logic circuit conversion module to obtain the current periodic clock skew error information in the clock skew error storage, and performing gain conversion on the current periodic clock skew error information to obtain the target to-be-corrected clock skew error; according to the target to-be-corrected clock skew error, adjusting each switch branch in the pre-set digital adjustable delay circuit driver to realize the reverse offset of the target to-be-corrected clock skew error according to the adjusted digital adjustable delay circuit driver, and sending the current clock signal data to the target digital processing module.
[0074] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, specially designed application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.
[0075] Computer programs for implementing the methods of the present application can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer program, when executed, enables the functions / acts specified in the flowcharts and / or block diagrams to be implemented. The computer program can be executed entirely on a machine, partially on a machine, partially on a machine as a standalone software package and partially on a remote machine or entirely on a remote machine or server.
[0076] In the context of the present application, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer-readable storage medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of a machine-readable storage medium will include one or more lines of a program of instructions in a transitory signal, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
[0077] To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.
[0078] The systems and techniques described here can be implemented in a computing system that includes a back end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front end component, e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here, or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.
[0079] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. A server can be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system, to solve the defects of large management difficulty and weak business scalability in traditional physical host and VPS service.
[0080] It should be understood that the various forms of flow shown above can be re-ordered, added to, or deleted from without departing from the scope of the present disclosure. For example, the steps recited in the present disclosure can be executed in parallel, executed in sequence, or executed in different orders, as long as the desired results of the technical solutions of the present disclosure are achieved, and the present disclosure is not limited herein.
[0081] The above detailed description does not constitute a limitation on the protection scope of the present application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.
[0082] Example Four
[0083] The fourth embodiment of the present application also provides a computer readable storage medium, computer readable instructions of which, when executed by a computer processor, are used to perform an analog-to-digital converter-based clock skew error correction method, which comprises: obtaining and according to a current clock acquisition frequency corresponding to a target analog-to-digital converter, obtaining current periodic clock skew error information by a pre-set clock skew error extraction method, and storing the current periodic clock skew error information in a clock skew error storage; when the target analog-to-digital converter sends current clock signal data to a target digital processing module, instructing a target gain conversion module to obtain the current periodic clock skew error information in the clock skew error storage, and performing gain conversion on the current periodic clock skew error information to obtain a target to-be-corrected clock skew error; and according to the target to-be-corrected clock skew error, adjusting each switch branch in a pre-set digital adjustable delay circuit driver to realize reverse offset of the target to-be-corrected clock skew error according to the adjusted digital adjustable delay circuit driver, and sending the current clock signal data to the target digital processing module.
[0084] Of course, the computer executable instructions of the computer readable storage medium provided by the embodiment of the present application are not limited to the method operations described above, but can also perform related operations in the analog-to-digital converter-based clock skew error correction provided by any embodiment of the present application.
[0085] From the above description of the embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software and necessary general hardware, and of course can also be implemented by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a floppy disk, a read-only memory (ROM), a random access memory (RAM), a FLASH, a hard disk or an optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in various embodiments of the present application.
[0086] It is worth noting that in the above-described embodiments of the analog-to-digital converter-based clock skew error correction, each unit and module included is only divided according to functional logic, but is not limited to the above-mentioned division, as long as the corresponding functions can be realized; in addition, the specific names of each functional unit are only for easy mutual differentiation, and do not limit the protection scope of the present application.
[0087] The above detailed description does not limit the scope of the application. Various modifications, combinations, sub-combinations and alternatives can be made to the detailed description. Any modification, equivalent replacement and improvement etc. made within the spirit and principle of the application shall be included in the scope of the application.
Claims
1. A method for correcting clock skew errors in an analog-to-digital converter, comprising: The method comprises the following steps: acquiring current periodic clock skew error information according to a current clock acquisition frequency corresponding to a target analog-to-digital converter, and storing the current periodic clock skew error information in a clock skew error storage; when the target analog-to-digital converter sends current clock signal data to a target digital processing module, instructing a target gain logic circuit conversion module to acquire the current periodic clock skew error information in the clock skew error storage, and performing gain conversion on the current periodic clock skew error information to obtain a target to-be-corrected clock skew error; adjusting each branch of a preset digital adjustable delay circuit driver according to the target to-be-corrected clock skew error, so as to realize reverse offsetting of the target to-be-corrected clock skew error according to the adjusted digital adjustable delay circuit driver, and sending the current clock signal data to the target digital processing module.
2. The method of claim 1, wherein, The method comprises the following steps: acquiring a preset integer multiple parameter value, multiplying the integer multiple parameter value by a current clock acquisition frequency corresponding to a target analog-to-digital converter, and calculating a current analog-to-digital converter input frequency; inputting test data to the target analog-to-digital converter according to the current analog-to-digital converter input frequency, and obtaining current analog-to-digital converter test output data; acquiring current periodic clock skew error information according to the current analog-to-digital converter test output data and by using a clock skew error extraction method.
3. The method of claim 2, wherein, The method comprises the following steps: performing fast Fourier transform spectrum analysis on the current analog-to-digital converter test output data by using the clock skew error extraction method, so as to obtain each spur center frequency point, and target skew spur amplitude and target skew spur frequency corresponding to each spur center frequency point, respectively; filtering the current analog-to-digital converter test output data by using a preset target band-pass filter according to each spur center frequency point, target skew spur amplitude and target skew spur frequency, so as to obtain the current periodic clock skew error information.
4. The method of claim 3, wherein, The method comprises the following steps: when the target analog-to-digital converter sends current clock signal data to a target digital processing module, calculating a current gain parameter value by using a preset gain calculation method; instructing a target gain logic circuit conversion module to acquire current periodic clock skew error information in the clock skew error storage; The target gain logic circuit conversion module is used for converting and correcting the current periodic clock skew error information by using the current gain parameter value to obtain the target clock skew error to be corrected.
5. The method of claim 4, wherein, The target digital adjustable delay circuit corresponding to the digital adjustable delay circuit driver comprises a plurality of switch branches, and different sizes of capacitors are arranged on each switch branch. The digital adjustable delay circuit driver is located between the target analog-to-digital converter and the target digital processing module, and is used for correcting the clock skew error of the transmitted current clock signal data.
6. The method of claim 5, wherein, The method for adjusting each switch branch in the preset digital adjustable delay circuit driver according to the target clock skew error to be corrected comprises: The target clock skew error to be corrected is converted into a current correction capacitor parameter by using a preset capacitor parameter logic circuit calculation method. Each switch branch in the target digital adjustable delay circuit corresponding to the digital adjustable delay circuit driver is adjusted according to the current correction capacitor parameter to obtain an adjusted target digital adjustable delay circuit. The target adjusted digital adjustable delay circuit is used for counteracting the target clock skew error to be corrected.
7. The method of claim 6, wherein, The method for adjusting each switch branch in the target digital adjustable delay circuit corresponding to the digital adjustable delay circuit driver according to the current correction capacitor parameter to obtain an adjusted target digital adjustable delay circuit comprises: The capacitor parameters corresponding to each switch branch in the target digital adjustable delay circuit are obtained. It is judged whether the capacitor parameters corresponding to one switch branch or the capacitor parameters corresponding to a plurality of switch branches and values meet the requirement of the current correction capacitor parameter, if yes, the switches corresponding to the one or more switch branches are set to a closed state, and the switches corresponding to the remaining switch branches are set to an open state to obtain the target adjusted digital adjustable delay circuit. If not, an error information instruction is fed back to the user.
8. An apparatus for correcting clock skew errors in an analog-to-digital converter, comprising: The current periodic clock skew error information storage module is used for obtaining and obtaining the current periodic clock skew error information by using a preset clock skew error extraction method according to a current clock collection frequency corresponding to the target analog-to-digital converter, and storing the current periodic clock skew error information in a clock skew error storage. The target clock skew error to be corrected determination module is used for instructing the target gain logic circuit conversion module to obtain the current periodic clock skew error information in the clock skew error storage and converting the current periodic clock skew error information by gain to obtain the target clock skew error to be corrected when the target analog-to-digital converter transmits current clock signal data to the target digital processing module. The target clock skew error correction module is configured to adjust each switch branch in the preset digital adjustable delay circuit driver according to the target clock skew error to be corrected, so as to realize reverse offset of the target clock skew error to be corrected according to the adjusted digital adjustable delay circuit driver, and send the current clock signal data to the target digital processing module.
9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the clock skew error correction method based on an analog-to-digital converter in any one of claims 1-7.
10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for causing the processor to implement the clock skew error correction method based on an analog-to-digital converter in any one of claims 1-7.