Receiver circuit

Abstract

A receiver circuit includes a plurality of decision feedback equalizer sub-circuits, each decision feedback equalizer sub-circuit being associated with one of a plurality of divided clock signals. Each decision feedback equalizer sub-circuit is configured to receive PAM signaling representing a current network symbol. Each of the plurality of decision feedback equalizer sub-circuits is configured for sequential generation of output symbols and comprises: a first delay block configured to apply a delay to PAM signaling to provide delayed PAM signaling, where the first delay block is clocked by a divided clock signal associated with the decision feedback equalizer sub-circuit; a coefficient application block; an amplitude limiter; and a second delay block configured to apply a delay to a DFE sub-circuit output symbol from the limiter to provide an output symbol, where the second delay block is clocked by a divided clock signal associated with the decision feedback equalizer sub-circuit.

Description

Technical Field

[0001] This disclosure relates to receiver circuitry for processing pulse amplitude modulation (PAM) signaling. Background Technology

[0002] Pulse Amplitude Modulation (PAM) is a method of encoding data within a signal, where the amplitude of a pulse varies over a known time range to represent data symbols. Summary of the Invention

[0003] According to a first aspect of this disclosure, a receiver circuit is provided for processing pulse amplitude modulation (PAM) signaling representing a network symbol stream, wherein the receiver circuit is configured to receive:

[0004] A network clock signal, the network clock signal corresponding to a network frequency; and

[0005] Multiple frequency-divided clock signals, among which:

[0006] Each divided clock signal is defined by the same frequency division as each other divided clock signal, wherein the frequency division is an integer multiple of the network frequency, and

[0007] Each of the plurality of frequency-divided clock signals has a phase offset relative to each of the other frequency-divided clock signals, such that the rising edge of each of the plurality of frequency-divided clock signals is evenly spaced from the rising edge of each of the other frequency-divided clock signals.

[0008] The receiver circuit includes:

[0009] Receiver output; and

[0010] Multiple decision feedback equalizer sub-circuits, each decision feedback equalizer sub-circuit being associated with one of the frequency division clock signals, wherein:

[0011] Each decision feedback equalizer subcircuit is configured to receive the PAM signaling representing the current network symbol;

[0012] Each of the plurality of decision feedback equalizer subcircuits is configured for sequential generation of output symbols;

[0013] Each of the decision feedback equalizer sub-circuits includes:

[0014] A first delay block, configured to apply a delay to the PAM signaling in order to provide delayed PAM signaling, wherein the first delay block is timed by the frequency division clock signal associated with the decision feedback equalizer subcircuit;

[0015] A coefficient application block, configured to apply a plurality of coefficients to the delayed PAM signaling to provide processed PAM signaling, wherein each coefficient is based on one or more of a plurality of previously output symbol values ​​provided by a sequence of decision feedback equalizer subcircuits;

[0016] A limiter, configured to apply one or more thresholds to the processed PAM signaling to provide DFE subcircuit output symbols; and

[0017] A second delay block, configured to apply a delay to the output symbol of the DFE subcircuit to provide an output symbol, wherein the second delay block is timed by the frequency division clock signal associated with the decision feedback equalizer subcircuit; and

[0018] A switching circuit is configured to sequentially provide the output symbols already generated by each of the decision feedback equalizer subcircuits as an output symbol stream at the receiver output.

[0019] This receiver circuitry can improve / increase the frequency of PAM signal processing (higher baud rate of the link).

[0020] In one or more embodiments, each of the plurality of decision feedback equalizer subcircuits is timed by a different one of the plurality of frequency division clock signals and by only one of the frequency division clock signals.

[0021] In one or more embodiments, the limiter is timed by a frequency-divided clock signal associated with the decision feedback equalizer subcircuit.

[0022] In one or more embodiments, the limiter operates at an integer fraction of the network frequency. The integer may correspond to the number of divided clock signals.

[0023] In one or more embodiments, each decision feedback equalizer subcircuit includes multiple speculative circuits.

[0024] In one or more embodiments, each decision feedback equalizer subcircuit is configured to:

[0025] A set of temporary output symbols is generated based on the PAM signaling representing the current network symbol; wherein each of the set of temporary output symbols corresponds to a forward-looking value of the output symbol for different values ​​of the preceding output symbol;

[0026] The output symbol is generated using the immediately preceding output symbol generated by the preceding adaptive filter circuit in the sequence.

[0027] In one or more embodiments:

[0028] Each decision feedback equalizer subcircuit includes multiple processing branches, with each of the possible values ​​of the output symbol corresponding to a processing branch;

[0029] Each processing branch applies a coefficient value associated with a different value of the preceding output symbol to the delayed PAM signaling received from the first delay block in order to provide forward-looking processed PAM signaling;

[0030] Each processing branch includes a limiter configured to apply one or more thresholds to the forward-looking processed PAM signaling in order to provide the temporary output symbol for the branch.

[0031] In one or more embodiments, the receiver circuitry is configured to extract a network clock signal from received PAM signaling.

[0032] In one or more embodiments, the receiver circuitry is configured to generate a frequency-divided clock signal from a network clock signal.

[0033] In one or more embodiments, the limiter of each decision feedback equalizer subcircuit is configured to selectively apply one, two, or three thresholds to process PAM-2, PAM-3, or PAM-4 signaling, respectively.

[0034] In one or more embodiments, the switching circuit is a multiplexer.

[0035] A wired transceiver that includes any receiver circuitry disclosed herein is also disclosed.

[0036] An Ethernet transceiver that includes any receiver circuitry disclosed herein is also disclosed.

[0037] While the invention is open to various modifications and alternatives, its details have been illustrated by way of example in the accompanying drawings and will be described in detail. However, it should be understood that other embodiments besides the specific embodiments described may also exist. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are also covered.

[0038] The foregoing discussion is not intended to present every example embodiment or every implementation within the scope of the present or future claims. The accompanying drawings and detailed description further illustrate various example embodiments. A more complete understanding of these various example embodiments can be achieved by considering the following detailed description in conjunction with the accompanying drawings. Attached Figure Description

[0039] One or more embodiments will now be described with reference to the accompanying drawings, by way of example only, in which:

[0040] Figure 1Examples of different PAM modulation levels are shown;

[0041] Figure 2 The receiver circuitry used to process PAM signaling is shown.

[0042] Figure 3 An example structure of a digital equalizer for an M-ary PAM transceiver is shown.

[0043] Figure 4 Show Figure 3 Alternative implementation schemes for DFE;

[0044] Figure 5 An example of a receiver circuit according to this disclosure is shown;

[0045] Figure 6 An example of a frequency-divided clock signal according to this disclosure is shown;

[0046] Figure 7 Another example of a receiver circuit according to this disclosure is shown; and

[0047] Figure 8 Another example of a receiver circuit according to this disclosure is shown. Detailed Implementation

[0048] To provide a simple example, a pulse with low amplitude can represent zero, and a pulse with high amplitude can represent one. The time range allocated to each data symbol is constant, allowing the receiver to understand which pulse represents which symbol in the message.

[0049] PAM symbols can represent a wider range of data than just zeros and ones. By implementing different numbers of thresholds, the device can distinguish different numbers of data symbols that can be represented by pulses.

[0050] Figure 1 Examples of different PAM modulation levels are shown. Figure 1 a) shows two-level PAM modulation (PAM-2), Figure 1 b) shows three-level PAM modulation (PAM-3), and Figure 1 c) shows four-level PAM modulation (PAM-4).

[0051] According to the data symbols of PAM-2, two different values ​​can be represented, so a threshold 101a is needed to distinguish the two different values ​​(the first value is when the level is higher than the threshold 101a, and the second value is when the level is lower than the threshold 101a).

[0052] According to the PAM-3 data symbols, three different values ​​can be represented, requiring two different thresholds 101b and 102b to distinguish these three different values. These thresholds are a high threshold and a low threshold. The symbols can have: a first value when the level is higher than the high threshold 101b, a second value when the level is between the high threshold 101b and the low threshold 102b, and a third value when the level is lower than the low threshold 102b.

[0053] The PAM-4 data symbols can represent four different values, requiring three different thresholds 101c, 102c, and 103c to distinguish these values. These thresholds are a high threshold, a middle threshold, and a low threshold. The symbols can have: a first value when the level is above the high threshold 101c; a second value when the level is between the high threshold 101c and the middle threshold 102c; a third value when the level is between the middle threshold 102c and the low threshold 103c; and a fourth value when the level is below the low threshold 102c. It should be understood that this mode can continue for all PAM modulation levels above four.

[0054] A limiter can be used to apply one or more PAM thresholds to received PAM signaling in order to determine the value of the output symbol.

[0055] Figure 2 A receiver circuit 204 for processing PAM signaling, which can be used in, for example, an Ethernet network, is shown. The receiver circuit 204 includes a receiver input 205 and a receiver output 206. The receiver input 205 receives PAM network signaling. The receiver output 206 provides output symbols.

[0056] The received PAM network signaling is processed sequentially by the following components: a programmable gain amplifier (PGA) 207, an analog-to-digital converter (ADC) 208, and a feedforward equalizer (FFE) 209. As is known in the art, the FFE 209 reduces inter-symbol interference.

[0057] The output of FFE 209 is connected to the first input of summing component 210. The output of decision feedback equalizer (DFE) 211 is connected to the second input of summing component 210. Summing component 210 subtracts the output signal of DFE 211 from the output signal of FFE 209 to provide a signal to limiter 212. Limiter applies one or more PAM thresholds to the signal it receives from summing component 210 (as discussed above), such that limiter provides an output symbol stream to receiver output 206. Figure 2 As shown, the output symbol stream is also provided as an input signal to the DFE211.

[0058] Figure 3 An example structure of a digital equalizer for an M-ary PAM transceiver is shown. Figure 3 Still Figure 2 The features shown have been given the corresponding reference numerals in the 300 series.

[0059] Figure 3 The DFE 311 has multiple taps, each of which provides a DFE feedback signal. Figure 3 The DFE feedback signal is provided to summing component 310 for subtraction from the signal labeled FFE sum. Each tap applies coefficients (DFE 1, DFE 2, DFE 3, etc.) to a delayed form of the output symbol provided by receiver output 306. In this way, DFE 311 can be viewed as applying multiple coefficients based on one or more of a plurality of previous output symbol values; that is, applying the result of multiplying the coefficient value (e.g., DFE 1) by an earlier previous output symbol (e.g., D[1], which is the immediately preceding output symbol provided as a result of applying a single delay to the output symbol provided to receiver output 306).

[0060] like Figure 3 As can be seen, the output signal of the first DFE tap (the result of multiplying DFE 1 and D[1]) is fed back to the input of the limiter 312, the output of which is the input to the first DFE tap. This path is in Figure 3 The symbol is indicated by a dashed line and is marked with reference numeral 313. This is the timing critical path of the DFE 311, which is closed in one clock cycle at the GHz baud frequency.

[0061] Figure 4 Show Figure 3 An alternative implementation of DFE. This implementation can be viewed as providing a single-level preview.

[0062] Single-stage preview (also known as predictive DFE or including speculative circuitry) pre-calculates all possible combinations of DFE tap 1 in order to reduce the above reference Figure 3 The described critical path timing issue.

[0063] Figure 4 DFE 411 in the code is used to process PAM-3 signaling. In this way, output symbols can have values ​​of +1, 0, or -1. When each of these potential output symbol values ​​is multiplied by DFE 1, the result will be '+DFE 1', '0', or '-DFE 1'. Figure 4 In this process, a separate processing branch is provided for applying each of these coefficient values, and the result is provided to a limiter to determine a temporary output symbol. These temporary output symbols are each provided to the input of multiplexer 416. The selector of multiplexer 416 receives the immediately preceding output symbol (D[1]) to select the temporary output symbol associated with the actual value of the immediately preceding output symbol. In this way, the time spent applying the coefficients in the first DFE tap is reduced, such as... Figure 4 The dashed line 414 in the middle represents this, which is more than Figure 3 The corresponding path 313 is faster. In other words, the computational circuitry (or digital circuitry) is reduced, which is beneficial for higher clock speed operation (higher baud rates for PAM communication).

[0064] However, the calculations for the second DFE tap and the preliminary calculations for DFE tap 1 will subsequently be applied to the critical path timing. This is due to... Figure 4 The figure is indicated by the dashed line marked 415 in the attached figure.

[0065] Figure 5 An example of receiver circuit 511 according to this disclosure is shown. More specifically, Figure 5 The DFE circuitry for processing Pulse Amplitude Modulation (PAM) signaling 517 representing a network symbol stream (i.e., the actual value of the symbols transmitted to receiver circuitry 511) is shown. As will be understood from the earlier description, PAM signaling 517 is processed by... Figure 5 The receiver circuit 511 shown has been processed before receiving the signal. The FFE and DFE are used for adaptive equalization of the channel used for PAM signal reception.

[0066] Receiver circuit 511 receives a network clock signal (not shown) corresponding to the network frequency. In some examples, this signal may be extracted from PAM signaling by the receiver circuit itself, and this signal may be referred to as a baud clock. Receiver circuit 511 also receives a plurality of frequency-divided clock signals 518, 519, and 520. Each frequency-divided clock signal 518, 519, and 520 defines the same frequency division as each of the other frequency-divided clock signals, and the frequency division is an integer multiple of the network frequency. Receiver circuit 511 may generate the frequency-divided clock signal itself from the network clock signal.

[0067] In this example, there are three frequency-divided clock signals 518, 519, and 520, and therefore the frequency of each frequency-divided clock signal 518, 519, and 520 is one-third of the network frequency. Furthermore, each of the plurality of frequency-divided clock signals 518, 519, and 520 has a phase shift relative to each of the other frequency-divided clock signals 518, 519, and 520, such that the rising edge of each of the plurality of frequency-divided clock signals 518, 519, and 520 is evenly spaced from the rising edge of each of the other frequency-divided clock signals 518, 519, and 520.

[0068] Figure 6 An example is shown of the divider clock signals 618 and 619 and the associated network clock signal (clock baud) for a receiver circuit that processes only two divider clock signals.

[0069] Return to Figure 5 The receiver circuit 511 has an input 521 for receiving pulse amplitude modulation (PAM) signaling 517. The receiver circuit 511 also has a receiver output 522 for providing an output symbol stream.

[0070] The receiver circuit 511 includes multiple decision feedback equalizer sub-circuits 523, each of the frequency division clock signals 518, 519, and 520 corresponding to one decision feedback equalizer sub-circuit. In this example, three decision feedback equalizer sub-circuits 523 are shown. See below for reference. Figure 7 and 8 In the described example, there are two decision feedback equalizer sub-circuits. It will be understood that the receiver circuit disclosed herein may typically include two or more decision feedback equalizer sub-circuits.

[0071] Each decision feedback equalizer subcircuit 523 is configured to receive PAM signaling representing the current network symbol (sometimes, we refer to the current network symbol as 'n', and earlier output symbols as 'n-1', 'n-2', etc.). Each of the plurality of decision feedback equalizer subcircuits 523 is configured for the sequential generation of output symbols. That is, each of the plurality of decision feedback equalizer subcircuits 523 generates output symbols sequentially, such that the generated output symbols can be provided one after another sequentially to the receiver output 522 to provide an output symbol stream at the receiver output 522. This will be discussed in more detail below.

[0072] Each of the decision feedback equalizer sub-circuits 523 includes a first delay block 524, a coefficient application block 525, a limiter 526, and a second delay block 527.

[0073] The first delay block 524 applies a delay to the received PAM signaling 517 to provide delayed PAM signaling. The first delay block 524 is timed by a frequency-divided clock signal associated with the decision feedback equalizer subcircuit 523. Figure 5 In the middle: the upper decision feedback equalizer subcircuit 523 is timed by clock phase 1 518; the middle decision feedback equalizer subcircuit is timed by clock phase 2 519, and so on. As will be discussed below, the PAM output symbols generated by the first and second decision feedback equalizer subcircuit 523 (the decision feedback equalizer subcircuits timed by clock phases 1 518 and 2 519) are used to estimate the PAM output symbol of the third decision feedback equalizer subcircuit (the decision feedback equalizer subcircuit timed by clock phase n 520), and vice versa, in a cyclic or round-robin manner. Figure 5 The line indicating the exchange of previous output symbols between decision feedback equalizer subcircuits 523 is not included to avoid occlusion. Figure 5 Other features. In a circuit with only two decision feedback equalizer subcircuits. Figure 7 and 8 In the example, we include lines to illustrate the exchange of previous output symbols between decision feedback equalizer subcircuits.

[0074] The coefficient application block 525 is configured to apply multiple coefficients to delayed PAM signaling to provide processed PAM signaling. As will be discussed in more detail below, each coefficient is based on one of multiple previous output symbol values ​​provided by a sequence of decision feedback equalizer subcircuits 523. That is, because the multiple decision feedback equalizer subcircuits 523 provide output symbols sequentially, the output symbols of the other decision feedback equalizer subcircuits 523 are used to implement the functionality of the DFE tap using earlier output symbol values. For example, in the case of two decision feedback equalizer subcircuits, the odd-numbered ones (n-1, n-3, etc.) of the multiple previous output symbols are provided by the other subcircuit, and the even-numbered ones are provided by the subcircuit in question.

[0075] Limiter 526 applies one or more thresholds to the processed PAM signaling to provide the DFE subcircuit output symbol. (See above reference.) Figure 1 As discussed, the number of thresholds applied depends on the number of different PAM modulation levels being used. In some examples, the limiter 526 of each decision feedback equalizer subcircuit can selectively apply one, two, or three thresholds to handle PAM-2, PAM-3, or PAM-4 signaling respectively. In this way, the same circuit can be used to handle different types of PAM signaling.

[0076] The second delay block 527 applies a delay to the output symbol of the DFE subcircuit to provide the output symbol. The second delay block 527 is timed by a frequency-divided clock signal associated with the decision feedback equalizer subcircuit. That is, the first delay block 524 and the second delay block 527 in each decision feedback equalizer subcircuit 523 are timed by the same frequency-divided clock signal. This is important because it means that each decision feedback equalizer subcircuit 523 operates at a fraction of the network / baud frequency. Advantageously, this greatly reduces the timing critical path of the receiver circuit 511 and thus improves the performance of the receiver circuit 511. More specifically, this improves / increases the frequency of PAM signal processing (higher baud rate of the link).

[0077] Finally, refer to Figure 5 The receiver circuit 511 includes a switching circuit 522 that sequentially provides the output symbols generated by each of the decision feedback equalizer subcircuits 523 as an output symbol stream at the receiver output 522. In the following examples, the functionality of the switching circuit 522 is implemented as a multiplexer. However, it will be understood that any implementation that sequentially passes the output symbols generated by the individual decision feedback equalizer subcircuits 523 to the receiver output 522 can be used.

[0078] from Figure 5As will be understood from the description, each of the plurality of decision feedback equalizer subcircuits 523 is timed by a different one of the plurality of frequency division clock signals 518, 519, 520, and is timed by only one of the frequency division clock signals 518, 519, 520.

[0079] Figure 7 Another example of receiver circuit 711 according to this disclosure is shown. Figure 7 Still Figure 5 The features shown have been given the corresponding reference numerals in the 700 series. Figure 7 The example can be viewed as using a multi-Baud cycle and a first-level lookup. This first-level lookup, also known as using speculative circuitry, is similar to the reference above. Figure 4 The described process.

[0080] Figure 7 Each decision feedback equalizer subcircuit 723 in the sequence includes a speculative circuit. The speculative circuit has multiple processing branches, each of the possible values ​​of the output symbol corresponding to a processing branch. Each processing branch applies a coefficient value associated with a different value of the immediately preceding output symbol (i.e., '+DFE 1', '0', or '-DFE 1') to the delayed PAM signaling received from the first delay block 724 to provide forward-looking processed PAM signaling. The forward-looking PAM signaling in each branch is then provided to limiters 726a, 726b, 726c to determine the temporary output symbol of the branch. These temporary output symbols are each provided to the input of multiplexer 716. The selector of multiplexer 716 receives the immediately preceding output symbol (D[1]) from the immediately preceding decision feedback equalizer subcircuit 723 in the sequence.

[0081] In this manner, the speculation circuit in each decision feedback equalizer subcircuit 723 is configured to generate a set of temporary output symbols (outputs of the three limiters 726a, 726b, 726c) based on PAM signaling representing the current network symbol; wherein, for different values ​​of the preceding output symbol n-1 (i.e., after applying coefficients associated with each of the possible values ​​of the preceding output symbol n-1), each of the set of temporary output symbols corresponds to a forward-looking value of the current output symbol n. The speculation circuit is also configured to generate the current output symbol n using the preceding output symbol n-1 generated by the preceding adaptive filter circuit in the sequence.

[0082] exist Figure 7 In the example, there are two decision feedback equalizer sub-circuits 723. Therefore, there are also two frequency-divided clock signals. Figure 7These are labeled Clk ph1 and Clk ph2. These frequency-divided clock signals are a type of baud clock division and have a 180-degree phase difference with each other. In fact, by Figure 7 The frequency-divided clock signal used in the receiver circuit 711 is Figure 6 The frequency division clock signal is shown in the figure.

[0083] Beneficial, Figure 7 The arrangement resolves the timing critical path into two Baud cycles. This means that, with one timing critical path being a single Baud cycle... Figure 3 Significant improvements compared to the circuit.

[0084] In the diagram, the dashed timing arc is at the baud rate, while the dotted-dash timing arc 730 is at half the baud rate. From... Figure 7 It is evident that, advantageously, the timing arc 730 included in each decision feedback equalizer subcircuit 723 is at half the baud rate. This implies that the speculative circuitry including limiters 726a, 726b, and 726c, as described above... Figure 5 The same method described works at half the frequency of the baud rate.

[0085] Figure 8 Another example of a receiver circuit 811 according to this disclosure is shown. Figure 8 Examples can be considered as using a multi-port loop without Figure 7 The first-level preview.

[0086] As from Figure 8 As can be seen, the first and second delay blocks in each decision feedback equalizer subcircuit 823 are timed by the same frequency-divided clock signal. Again, advantageously, this allows each decision feedback equalizer subcircuit 823 to operate at a fraction of the network / baud frequency. This also resolves the timing critical path for use in implementing high-frequency PAM signal processing.

[0087] Will understand, even Figure 7 and 8 The examples use a divide-by-two baud clock, but can be extended to N (3, 4, ...) dividers. Furthermore, the examples disclosed herein can be used with any wired transceiver using any PAM-N scheme. Additionally, the examples disclosed herein can be used with digital echo cancellers for different versions of Ethernet transceivers.

[0088] One or more of the examples disclosed herein can be used to implement a high-speed adaptive digital equalizer for an Ethernet transceiver (or any high-speed Ethernet transceiver).

[0089] Some of the examples disclosed in this paper involve using multi-baud loops and look-ahead (speculation) DFE loop unrolling to resolve timing critical paths at limiters for high-speed PAM-N transceivers. This resolves timing critical paths for PAM-N applications with high baud rates. It also enables the function of secondary look-ahead without the high hardware requirements that would otherwise be necessary for secondary look-ahead.

[0090] Unless a specific order is explicitly stated, the instructions and / or flowchart steps in the above diagrams may be performed in any order. Furthermore, those skilled in the art will recognize that while one example set of instructions / methods has been discussed, the material in this specification can be combined in various ways to produce other examples, and should be understood within the context of the detailed description provided herein.

[0091] In some example embodiments, the instruction set / method steps described above are implemented as functional and software instructions embodied in an executable instruction set, which is implemented on a computer or a machine programmed and controlled by the executable instructions. Such instructions are loaded to execute on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, microcontroller, processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing device. A processor may refer to a single component or multiple components.

[0092] In other examples, the instruction sets / methods illustrated herein, along with their associated data and instructions, are stored in appropriate storage devices, which are implemented as one or more non-transitory machine- or computer-readable or computer-usable storage media. Such computer-readable or computer-usable storage media are considered part of an article (or article of manufacture). An article or article of manufacture can refer to any single or multiple manufactured components. Non-transitory machine- or computer-usable media as defined herein do not include signals, but such media may be capable of receiving and processing information from signals and / or other transient media.

[0093] Example embodiments of the materials discussed in this specification may be implemented, in whole or in part, via networks, computers, or data-based devices and / or services. These may include cloud, Internet, intranet, mobile devices, desktop computers, processors, lookup tables, microcontrollers, consumer devices, infrastructure, or other enabling devices and services. As may be used herein and in the claims, the following non-exclusive definitions are provided.

[0094] In one example, one or more instructions or steps discussed in this article are automated. The terms automated or automatic (and similar variations) mean using computers and / or mechanical / electrical devices to control the operation of equipment, systems, and / or processes without human intervention, observation, effort, and / or decision-making.

[0095] It should be understood that any components referred to as coupled can be directly or indirectly coupled or connected. In the case of indirect coupling, another component can be placed between two components that are said to be coupled.

[0096] In this specification, exemplary embodiments have been presented according to a selected set of details. However, those skilled in the art will understand that many other exemplary embodiments, including different selected sets of details, can be practiced. It is intended that the appended claims cover all possible exemplary embodiments.

Claims

1. A receiver circuit for processing pulse amplitude modulation, PAM, signaling representing a stream of network symbols, characterized by, The receiver circuit is configured to receive: a network clock signal, the network clock signal corresponding to a network frequency; and a plurality of divided clock signals, wherein: each divided clock signal defines a same division as each other divided clock signal, where the division is an integer multiple of the network frequency, and each of the plurality of divided clock signals exists in a phase offset relative to each of the other divided clock frequencies, such that rising edges of each of the plurality of divided clock signals are evenly spaced apart from rising edges of each other divided clock signal; wherein the receiver circuit comprises: a receiver output; and a plurality of decision feedback equalizer sub-circuits, each decision feedback equalizer sub-circuit associated with one of the divided clock signals, wherein: each decision feedback equalizer sub-circuit is configured to receive the PAM signaling representing a current network symbol; each of the plurality of decision feedback equalizer sub-circuits is configured for output of a sequential generation of symbols; each of the decision feedback equalizer sub-circuits comprises: a first delay block configured to apply a delay to the PAM signaling so as to provide delayed PAM signaling, where the first delay block is clocked by the divided clock signal associated with the decision feedback equalizer sub-circuit; a coefficient application block configured to apply a plurality of coefficients to the delayed PAM signaling so as to provide processed PAM signaling, where each coefficient is based on one or more of a plurality of previous output symbol values provided by a sequence of decision feedback equalizer sub-circuits; a slicer configured to apply one or more thresholds to the processed PAM signaling so as to provide a DFE sub-circuit output symbol; and a second delay block configured to apply a delay to the DFE sub-circuit output symbol so as to provide an output symbol, where the second delay block is clocked by the divided clock signal associated with the decision feedback equalizer sub-circuit; and a switching circuit configured to provide, in sequence, the output symbols that have been generated by each of the decision feedback equalizer sub-circuits as an output symbol stream at the receiver output.

2. The receiver circuit of claim 1, wherein, Each of the plurality of decision feedback equalizer sub-circuits is clocked by a different one of the plurality of divided clock signals and by only one of the divided clock signals.

3. A receiver circuit as claimed in claim 1 or claim 2, characterised in that, The slicer is clocked by the divided clock signal associated with the decision feedback equalizer sub-circuit.

4. The receiver circuit of claim 3, wherein, The slicer operates at an integer fraction of the network frequency, where the integer corresponds to the number of divided clock signals.

5. A receiver circuit as claimed in any one of the preceding claims, characterised in that, Each decision feedback equalizer sub-circuit comprises a plurality of speculation circuits.

6. A receiver circuit as claimed in any one of the preceding claims, characterised in that, Each decision feedback equalizer sub-circuit is configured to: generate a set of tentative output symbols based on the PAM signaling representing the current network symbol; where each of the set of tentative output symbols corresponds to a look-ahead value of the output symbol for a different value of an immediately preceding output symbol; generate the output symbol using the immediately preceding output symbol generated by a preceding adaptive filtering circuit in the sequence.

7. The receiver circuit of claim 6, wherein: each decision feedback equalizer sub-circuit comprises a plurality of processing branches, each processing branch corresponding to one of the possible values of the output symbol; each processing branch applies a coefficient value associated with a different value of the immediately preceding output symbol to the delayed PAM signaling received from the first delay block to provide prospective processed PAM signaling; each processing branch comprises a slicer configured to apply one or more thresholds to the prospective processed PAM signaling to provide the interim output symbol for the branch.

8. A receiver circuit as claimed in any one of the preceding claims, characterised in that, the receiver circuit is configured to extract the network clock signal from the received PAM signaling.

9. A receiver circuit as claimed in any one of the preceding claims, characterised in that, the receiver circuit is configured to generate the divided clock signal from the network clock signal.

10. A wired transceiver, characterized by the wired transceiver comprises the receiver circuit of any preceding claim.

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