An isolation device

Abstract

The application discloses an isolation device, comprising: a circuit board; a ring-shaped magnetic core completely embedded in an insulating medium; a first signal coil and a second signal coil arranged around the ring-shaped magnetic core; the first signal coil comprises a first pattern part formed in a first conductive pattern layer, a second pattern part formed in a second conductive pattern layer and a first conductive via connecting the two; the second signal coil comprises a third pattern part formed in the first conductive pattern layer, a fourth pattern part formed in the second conductive pattern layer and a second conductive via connecting the two; the first pattern part and the third pattern part are located in different areas, and the second pattern part and the fourth pattern part are located in different areas; the terminals of the first signal coil and the second signal coil are respectively led out from the corresponding pattern parts and electrically connected to the bottom layer of the circuit board; all the space paths between the first signal coil and the second signal coil are interrupted by the insulating medium layer, so that complete isolation of the input side and the output side circuits is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to an isolation device. BACKGROUND

[0002] New energy vehicles and industrial data centers have an increasing demand for isolation packaging devices, and there are increasingly high requirements for the isolation ability and speed optimization of the isolation packaging devices. Power transistors need to use an isolator for driving, and the function of the isolator is to turn on and turn off the power device to reduce the loss. The existing isolation packaging devices mostly rely on photosensitive or capacitors to achieve isolation, and the photoelectric isolation sensitivity is not enough and the speed is low, and the capacitor isolation brings parasitic capacitance and is easy to break down.

[0003] At present, advanced signal isolation devices mostly use substrate integrated packaging technology, and the integrated circuit dies of the input side and the output side are integrated on a ceramic or organic substrate through wire bonding or flip-chip bonding, and are entirely covered in plastic packaging material. Such a structure has the advantages of small size, high integration, good thermal mechanical reliability, etc., and can be widely applied in the fields of industrial communication, power management, etc. However, due to factors such as substrate wiring density, chip edge electric field concentration, and plastic encapsulation internal micropores, the electrical isolation ability between the input and the output is usually only up to 2kV to 3kV of direct current. Although improvements are made by increasing isolation grooves or introducing high dielectric materials, it still faces great challenges to stably achieve an insulation level of 5kV or above of direct current, especially in high temperature and high humidity or high common mode transient interference environments, the isolation reliability significantly decreases. SUMMARY

[0004] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application proposes an isolation device, which realizes the complete isolation of the input side and the output side circuits in the physical space by constructing a full-embedded magnetic coupling structure inside a multi-layer circuit board, and can stably realize an isolation withstand voltage of 8kV of direct current.

[0005] According to an embodiment of the present application, an isolation device comprises: a circuit board, which is formed by alternately laminating a plurality of conductive pattern layers and a plurality of insulating medium layers, and at least comprises a first conductive pattern layer and a second conductive pattern layer, and a single layer or multiple layers of insulating medium are arranged between adjacent conductive pattern layers; a ring-shaped magnetic core, which is completely embedded in the single layer or multiple layers of insulating medium; a first signal coil and a second signal coil, which are both arranged around the center hole of the ring-shaped magnetic core and are not electrically connected to each other; the first signal coil comprises a first pattern part formed on the first conductive pattern layer, a second pattern part formed on the second conductive pattern layer, and a first conductive via hole connecting the first pattern part and the second pattern part; the second signal coil comprises a third pattern part formed on the first conductive pattern layer, a fourth pattern part formed on the second conductive pattern layer, and a second conductive via hole connecting the third pattern part and the fourth pattern part; wherein the first pattern part and the third pattern part are located in different regions of the first conductive pattern layer, and the second pattern part and the fourth pattern part are located in different regions of the second conductive pattern layer; the terminals of the first signal coil and the second signal coil are respectively led out from the corresponding pattern parts and electrically connected to the connection area of the bottom layer of the circuit board, and all the space paths between the first signal coil and the second signal coil are interrupted by the insulating medium layers to achieve electrical isolation.

[0006] Compared with the prior art isolating device adopting substrate integration and surface packaging process, the input side and the output side circuit are completely isolated in physical space by constructing the full-buried magnetic coupling structure inside the multilayer circuit board.

[0007] According to some embodiments of the present application, the first pattern part and the third pattern part both extend around the center hole of the ring-shaped magnetic core and are separated from each other in the circumferential direction in the plane of the first conductive pattern layer, and respectively occupy different sector regions of the outer periphery of the ring-shaped magnetic core; and the second pattern part and the fourth pattern part both extend around the center hole of the ring-shaped magnetic core and are separated from each other in the circumferential direction in the plane of the second conductive pattern layer, and respectively occupy different sector regions of the outer periphery of the ring-shaped magnetic core.

[0008] According to some embodiments of the present application, the connection region includes a first connection region and a second connection region isolated from each other, and the first connection region and the second connection region are respectively arranged on opposite sides of the circuit board bottom layer in the horizontal direction; the terminal of the first signal coil is electrically connected to at least one pad of the first connection region, and the terminal of the second signal coil is electrically connected to at least one pad of the second connection region; with the center of the annular magnetic core as a reference, the main winding of the first signal coil is located in the left side region of the annular magnetic core, and the first connection region is arranged on the left side of the circuit board bottom layer; the main winding of the second signal coil is located in the right side region of the annular magnetic core, and the second connection region is arranged on the right side of the circuit board bottom layer; wherein the first connection region and the second connection region each include a plurality of pads for respectively accessing input side signals and output side signals.

[0009] According to some embodiments of the present application, the connection region includes a first connection region and a second connection region isolated from each other, and the first connection region and the second connection region are respectively arranged on opposite sides of the circuit board bottom layer in the horizontal direction; the circuit board further includes a third conductive pattern layer located above the first conductive pattern layer and the second conductive pattern layer and isolated therefrom by the insulating medium layer; the third conductive pattern layer includes a fifth pattern part and a sixth pattern part isolated from each other; the first signal coil has a first end and a second end, the first end is electrically connected to a first pad of the first connection region, and the second end is electrically connected to a second pad of the first connection region; the fifth pattern part is simultaneously electrically connected to the first end and the first pad through a third conductive via and is simultaneously electrically connected to the second end and the second pad through a fourth conductive via; the second signal coil has a third end and a fourth end, the third end is electrically connected to a third pad of the second connection region, and the fourth end is electrically connected to a fourth pad of the second connection region; the sixth pattern part is simultaneously electrically connected to the third end and the third pad through a fifth conductive via and is simultaneously electrically connected to the fourth end and the fourth pad through a sixth conductive via.

[0010] According to some embodiments of the present application, further including an input side chip and an output side chip, the input side chip is electrically connected to the fifth pattern part for driving the first signal coil, and the output side chip is electrically connected to the sixth pattern part for receiving the output signal of the second signal coil; wherein a first dispensing layer is formed around the pins of the input side chip, and the first dispensing layer covers the pins of the input side chip and the adjacent fifth pattern part region; a second dispensing layer is formed around the pins of the output side chip, and the second dispensing layer covers the pins of the output side chip and the adjacent sixth pattern part region.

[0011] According to some embodiments of the present application, the plastic package is formed by an insulating plastic material, and completely covers the top layer of the circuit board to seal the exposed conductive structures of the input-side chip, the output-side chip, the fifth patterned portion and the sixth patterned portion of the top layer of the circuit board in the plastic package.

[0012] According to some embodiments of the present application, the connecting region includes a plurality of pads, at least some of which extend to the edge of the circuit board; a depth-controlled half-hole is provided on the pad extending to the edge of the circuit board, the depth-controlled half-hole is located at the area of the pad close to the edge of the circuit board and is exposed to the side edge of the circuit board; the depth of the depth-controlled half-hole is less than the total thickness of the circuit board, and the hole wall and the hole bottom of the depth-controlled half-hole are both metallized surfaces, so that the exposed side wall formed by the depth-controlled half-hole at the side edge of the circuit board is a continuous conductive surface.

[0013] According to some embodiments of the present application, a conductive via is further provided on the pad extending to the edge of the circuit board, the conductive via is located on the side of the depth-controlled half-hole facing the center of the circuit board and extends from the surface of the pad to the inside of the circuit board to electrically connect with the conductive structure of the inner layer; wherein the conductive via has a metallized hole wall and an insulating resin body filled therein, and the top of the conductive via is flush with the surface of the pad.

[0014] According to some embodiments of the present application, the depth-controlled half-hole does not have a metal cover at the outermost edge of the circuit board, and the metallized surfaces of the hole wall and the hole bottom of the depth-controlled half-hole terminate at the inside of the outermost edge of the circuit board, exposing the insulating medium layer; the conductive part of the depth-controlled half-hole is separated from the outermost surface of the circuit board by the insulating medium layer, forming a non-conductive edge isolation area.

[0015] According to some embodiments of the present application, the circuit board is provided with a stepped profile adjacent to the side edge of the bottom layer, the stepped profile is composed of a vertical side wall surface and a horizontal bottom surface connected to the outer edge of the bottom; the depth-controlled half-hole penetrates the pad and extends to the vertical side wall surface, and does not extend to the horizontal bottom surface.

[0016] Additional aspects and advantages of the present application will be made apparent from the following description, which, taken in conjunction with the accompanying drawings, which are shown by way of illustration. BRIEF DESCRIPTION OF DRAWINGS

[0017] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description, taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is a structural schematic diagram of a first perspective view of an isolation device according to an embodiment of the present application;

[0019] Figure 2 is a structural schematic diagram of a second perspective of the isolation device according to an embodiment of the present application;

[0020] Figure 3 is a structural schematic diagram of an internal structure of the isolation device without insulation medium according to an embodiment of the present application Figure 1 ;

[0021] Figure 4 is a structural schematic diagram of an internal structure of the isolation device without insulation medium according to an embodiment of the present application Figure 2 ;

[0022] Figure 5 is a structural schematic diagram of an internal structure of the isolation device without insulation medium according to an embodiment of the present application Figure 3 ;

[0023] Figure 6 is a block diagram of an input circuit and an output circuit of the isolation device according to an embodiment of the present application;

[0024] Figure 7 is a structural schematic diagram of an internal structure of the isolation device with insulation medium according to an embodiment of the present application Figure 1 ;

[0025] Figure 8 is a structural schematic diagram of an internal structure of the isolation device with insulation medium according to an embodiment of the present application Figure 2 ;

[0026] Figure 9 is a structural schematic diagram of the isolation device with a plastic package according to an embodiment of the present application;

[0027] Figure 10 is a structural schematic diagram of the isolation device without a plastic package according to an embodiment of the present application;

[0028] Figure 11 is a structural schematic diagram of a third perspective of the isolation device according to an embodiment of the present application;

[0029] Figure 12 is Figure 11 an enlarged schematic diagram of A in FIG. 8.

[0030] Reference signs:

[0031] 1, circuit board; 11, insulating dielectric layer; 12, first conductive pattern layer; 13, second conductive pattern layer; 14, third conductive pattern layer; 15, fifth pattern part; 16, sixth pattern part; 17, third conductive via; 18, fourth conductive via; 19, fifth conductive via; 20, sixth conductive via; 2, toroidal core; 3, first signal coil; 31, first pattern part; 32, second pattern part; 33, first conductive via; 34, first end; 35, second end; 4, second signal coil; 41, third pattern part; 42, fourth pattern part; 43, second conductive via; 44, third end; 45, fourth end; 5, first connection area; 51, first solder pad; 52, second solder pad; 53, depth control half-hole; 54, conductive via hole; 55, edge isolation area; 56, stepped profile; 5601, vertical side wall surface; 5602, horizontal bottom surface; 6, second connection area; 61, third solder pad; 62, fourth solder pad; 7, input-side chip; 71, first dispensing layer; 8, output-side chip; 9, plastic package; 10, solder resist layer. DETAILED DESCRIPTION

[0032] Embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0033] Reference is made below to Figures 1-12 A magnetic isolation device is described according to embodiments of the present application. As shown in Figures 1-6 The present application proposes a full-buried magnetic isolation device structure based on a multi-layer printed circuit board. The magnetic isolation device according to embodiments of the present application includes a circuit board 1, a toroidal core 2, a first signal coil 3, and a second signal coil 4. The circuit board 1 is formed by alternately laminating a plurality of conductive pattern layers and a plurality of insulating dielectric layers 11, and a single layer or multiple layers of insulating dielectric are arranged between adjacent conductive pattern layers, wherein at least a first conductive pattern layer 12 and a second conductive pattern layer 13 are included. The toroidal core 2 is completely embedded in the single layer or multiple layers of insulating dielectric. The first signal coil 3 and the second signal coil 4 are both arranged around the center hole of the toroidal core 2, and are not electrically connected to each other.

[0034] Specifically, the circuit board 1 is a double-layer circuit board, a three-layer circuit board or other multi-layer circuit board, which is formed by alternately stacking and hot-pressing and curing a plurality of conductive pattern layers and a plurality of insulating medium layers 11. The adjacent conductive pattern layers are electrically isolated by one or more insulating medium layers 11. The circuit board 1 internally contains at least a first conductive pattern layer 12 and a second conductive pattern layer 13. The annular magnetic core 2 is entirely embedded in the insulating medium layer 11 inside the circuit board 1 and is completely covered by the insulating medium material and is not exposed to the external surface of the circuit board 1. The annular magnetic core 2 is in a closed loop shape and has a central hole as a core component of the magnetic flux coupling path. The first signal coil 3 is wound around the central hole of the annular magnetic core 2 to form a multi-turn conductive coil structure for receiving or transmitting input side signals. The second signal coil 4 is also arranged around the central hole of the annular magnetic core 2, and its winding direction and position are independent of the first signal coil 3. The two are close to each other in space to realize magnetic coupling, but are completely electrically isolated and do not have any direct or indirect conductive connection. The first signal coil 3 and the second signal coil 4 are respectively led out to the designated connection area of the circuit board 1 through the conductive vias or traces inside the circuit board 1 for establishing electrical connection with the external input circuit and output circuit. The entire structure is integrally formed by a multi-layer board pressing process, and the annular magnetic core 2 is fixed in the insulating medium layer 11 during the lamination process to avoid displacement during subsequent reflow soldering or plastic packaging. Since the first signal coil 3 and the second signal coil 4 only transfer signals through magnetic field coupling, high electrical isolation between the input side and the output side is achieved.

[0035] In a further specific embodiment of the present application, the first signal coil 3 includes a first pattern part 31 formed in the first conductive pattern layer 12, a second pattern part 32 formed in the second conductive pattern layer 13, and a first conductive via 33 connecting the first pattern part 31 and the second pattern part 32. The second signal coil 4 includes a third pattern part 41 formed in the first conductive pattern layer 12, a fourth pattern part 42 formed in the second conductive pattern layer 13, and a second conductive via 43 connecting the third pattern part 41 and the fourth pattern part 42. Among them, the first pattern part 31 and the third pattern part 41 are located in different isolated areas of the first conductive pattern layer 12, and the second pattern part 32 and the fourth pattern part 42 are located in different isolated areas of the second conductive pattern layer 13.

[0036] It can be understood that the first signal coil 3 is composed of multiple conductive parts on different conductive pattern layers by vertical interconnection structure. Specifically, the first signal coil 3 includes a first pattern part 31 formed on the first conductive pattern layer 12, a second pattern part 32 formed on the second conductive pattern layer 13, and a first conductive via 33 connecting the first pattern part 31 and the second pattern part 32. The first pattern part 31 and the second pattern part 32 are both arc-shaped or spiral-shaped conductive tracks extending around the central hole of the annular magnetic core 2, and the first conductive via 33 penetrates the insulating medium layer 11 between the two to electrically connect the first pattern part 31 and the second pattern part 32, thereby forming part of a multi-turn winding.

[0037] The second signal coil 4 is also implemented in a cross-layer structure, including a third pattern part 41 formed on the first conductive pattern layer 12, a fourth pattern part 42 formed on the second conductive pattern layer 13, and a second conductive via 43 connecting the third pattern part 41 and the fourth pattern part 42. The third pattern part 41 and the fourth pattern part 42 are also arranged around the central hole of the annular magnetic core 2.

[0038] On the first conductive pattern layer 12, the first pattern part 31 and the third pattern part 41 are separated from each other, leaving enough insulating gap between them to ensure that the input side and the output side have no electrical connection in this layer. On the second conductive pattern layer 13, the second pattern part 32 and the fourth pattern part 42 are also arranged in different areas isolated from each other, and there is no conductive bridge or shared copper foil between them. The two groups of coils are respectively led out through their respective conductive paths, and there is no electrical connection between them. All pattern parts are integrally formed with the insulating medium layer 11 through the circuit board 1 lamination process, and the conductive via can be electrically connected by hole wall metallization.

[0039] Through the above layout, the first signal coil 3 as a whole constitutes an input side winding, and the second signal coil 4 as a whole constitutes an output side winding. The two groups of coils are physically coupled around the same annular magnetic core 2, but always remain electrically isolated in all conductive layers and via paths, thereby realizing high integration and high isolation strength of signal transmission function in the circuit board 1.

[0040] Further, the terminals of the first signal coil 3 and the terminals of the second signal coil 4 are respectively led out from the corresponding pattern parts and electrically connected to the connection areas on the bottom layer of the circuit board 1, and all the space paths between the first signal coil 3 and the second signal coil 4 are blocked by the insulating medium layer 11 to achieve electrical isolation.

[0041] Specifically, the terminals of the first signal coil 3 are drawn from their corresponding patterned sections, and extend to the input-side connection area on the bottom layer of the circuit board 1 via conductive vias or traces. The terminals of the second signal coil 4 are likewise drawn from their corresponding patterned sections, and are connected to the output-side connection area on the bottom layer of the circuit board 1 via conductive vias or traces. The input-side and output-side connection areas described above form input-side and output-side external interfaces on the bottom layer of the circuit board 1, which are electrically isolated from each other, for connecting external circuits. On each conductive patterned layer, the input-side and output-side patterned sections are arranged in different areas isolated from each other, which are filled with dense insulating medium to ensure that the specified minimum creepage distance and electrical clearance requirements are met. Therefore, in the entire signal transmission path, all conductive parts from the first signal coil 3 and its drawing structure, and from the second signal coil 4 and its drawing structure, are always electrically isolated in three-dimensional space, without any shared conductive layer, via or pad between them, and are completely separated by one or more insulating medium layers 11 in any cross-sectional or interlayer path. This three-dimensional isolation layout ensures that there is no direct or indirect conductive path between the input-side and the output-side, thereby achieving high-reliability electrical isolation in physical structure.

[0042] In some embodiments, the entire magnetic coupling structure is completely embedded inside the multilayer circuit board 1, with the toroidal magnetic core 2, the first signal coil 3 and the second signal coil 4 all being wrapped in insulating medium and not exposed to the external surface of the circuit board 1. The insulating medium is an epoxy-based material with a dielectric strength greater than 45 kV / mm. All conductive paths of the input-side and the output-side, including the coil patterned sections, conductive vias and drawing terminals, are completely filled and physically separated by the epoxy medium in three-dimensional space, without air gaps, solder joint interfaces or plastic encapsulation layering, etc. Benefiting from the synergistic effect of the above-mentioned fully-embedded magnetic core winding layout and high-dielectric-strength epoxy medium, a high-reliability insulating barrier is formed between the input-side and the output-side, significantly suppressing electric field concentration and partial discharge, so that the overall isolation device has excellent electrical isolation performance.

[0043] Thus, compared with the prior art isolating device using substrate integration and surface packaging process, the present application realizes complete isolation of the input side and output side circuits in physical space by constructing a full-embedded magnetic coupling structure inside the multilayer circuit board 1. That is, the annular magnetic core 2 is completely embedded in the high dielectric strength insulating dielectric layer 11, and the first signal coil 3 and the second signal coil 4 are respectively connected by the pattern part on the first conductive pattern layer 12 and the second conductive pattern layer 13 through the respective independent first conductive via 33 and the second conductive via 43 to form a double-layer winding structure distributed across layers. The "double-layer pattern-vertical via interconnection" architecture not only ensures effective magnetic coupling of the signal, but more importantly, in the entire three-dimensional space, from the coil body, interlayer connection to the lead-out to the circuit board bottom layer connection area, there is no any common conductive layer, shared via or adjacent wire between the input side and the output side, and all potential electrical paths are completely blocked by one or more continuous and dense insulating dielectric layers 11, thereby constructing a truly three-dimensional isolated path. Thanks to this physical level complete isolation design, the present application fundamentally eliminates the risk of electric field concentration and partial discharge caused by the wire bonding area, exposed solder joints or plastic encapsulation interface gap in traditional packaging. According to actual measurement, the isolating device can stably realize isolation voltage of 5kV or more, which is significantly better than the prior art which generally only reaches 2-3kV level, while maintaining high integration and miniaturization, meeting the safety requirements of enhanced insulation, and providing a magnetic isolation solution with high performance and high safety for new energy vehicles, medical equipment and industrial control systems and other high reliability application scenarios.

[0044] In some embodiments of the present application, the first pattern part 31 and the third pattern part 41 both extend around the center hole of the annular magnetic core 2 and are separated from each other in the circumferential direction in the plane of the first conductive pattern layer 12, respectively occupying different sector regions of the outer periphery of the annular magnetic core 2. And the second pattern part 32 and the fourth pattern part 42 both extend around the center hole of the annular magnetic core 2 and are separated from each other in the circumferential direction in the plane of the second conductive pattern layer 13, respectively occupying different sector regions of the outer periphery of the annular magnetic core 2.

[0045] As Figure 3As shown, the first signal coil 3 and the second signal coil 4 are arranged in a circumferentially separated sector layout within the multilayer circuit board 1 to further improve the electrical isolation performance between the input side and the output side. Specifically, on the first conductive pattern layer 12, the first pattern portion 31 constituting the first signal coil 3 and the third pattern portion 41 constituting the second signal coil 4 both extend around the central hole of the toroidal magnetic core 2, forming arc-shaped or spiral conductive traces. These two pattern portions are separated from each other in the circumferential direction of the toroidal magnetic core 2 without overlapping or being adjacent to each other, but instead occupying different sector regions of the outer periphery of the toroidal magnetic core 2. For example, the first pattern portion 31 can be arranged within a semicircle range of 0° to 160°, while the third pattern portion 41 is arranged within another semicircle range of 160° to 360°, leaving a sufficient width of insulating gap between them to ensure that there is no close-range parallel segment on this conductive layer that can form a capacitive coupling or a leakage channel. Similarly, on the second conductive pattern layer 13, the second pattern portion 32 constituting the first signal coil 3 and the fourth pattern portion 42 constituting the second signal coil 4 also extend around the central hole of the toroidal magnetic core 2 and are separated from each other in the circumferential direction in the layer plane. The second pattern portion 32 and the fourth pattern portion 42 are located in two non-overlapping sector regions of the outer periphery of the toroidal magnetic core 2, separated from each other by a complete insulating medium region, avoiding the formation of a high electric field concentration area in the vertical projection or interlayer alignment.

[0046] In particular, the projection areas of the first pattern portion 31 and the second pattern portion 32 in the vertical direction are substantially the same or completely overlap, i.e., their coverage ranges on different conductive layers are generally consistent, ensuring uniform magnetic field distribution of the first signal coil 3 in the vertical direction. Similarly, the projection areas of the third pattern portion 41 and the fourth pattern portion 42 in the vertical direction are also substantially the same or completely overlap, so that the magnetic field distribution of the second signal coil 4 is also uniform and efficient. This design not only ensures the independence of the two sets of coils in their respective conductive layers, but also maintains the consistency of the cross-layer windings, optimizing the overall magnetic coupling efficiency.

[0047] Thus, by implementing such a circumferentially separated sector layout in both the upper and lower conductive pattern layers, the input side winding and the output side winding are physically separated to the greatest extent in the entire three-dimensional space. This design not only significantly increases the shortest creepage distance and electrical gap between the input and the output, but also effectively reduces the interlayer parasitic capacitance, thereby suppressing the coupling of high-frequency common-mode noise and improving the common-mode transient immunity. At the same time, since the two sets of coils still jointly surround the same toroidal magnetic core 2, the magnetic flux path remains closed, and the signal is efficiently coupled through the magnetic field, balancing the isolation strength and transmission performance. The sector partition strategy combined with the fully embedded structure inside the circuit board 1 makes the entire magnetic isolation unit completely covered by the insulating medium with high dielectric strength, further strengthening the overall insulation reliability and providing a structural basis for achieving high voltage isolation of DC 5kV or above.

[0048] In some embodiments of the application, the connection region comprises a first connection region 5 and a second connection region 6, which are electrically isolated from each other and arranged on opposite sides of the bottom layer of the circuit board 1 along the horizontal direction. The terminals of the first signal coil 3 are electrically connected to at least one pad of the first connection region 5, and the terminals of the second signal coil 4 are electrically connected to at least one pad of the second connection region 6. With the center of the toroidal core 2 as the reference, the main winding of the first signal coil 3 is located in the left side region of the toroidal core 2, and the first connection region 5 is arranged on the left side of the bottom layer of the circuit board 1. The main winding of the second signal coil 4 is located in the right side region of the toroidal core 2, and the second connection region 6 is arranged on the right side of the bottom layer of the circuit board 1. Wherein, the first connection region 5 and the second connection region 6 each contain a plurality of pads, respectively used for connecting the input side signal and the output side signal.

[0049] As shown in Figures 2-5 The bottom layer of the circuit board 1 is provided with a first connection region 5 and a second connection region 6, which are electrically isolated from each other and arranged on opposite ends of the bottom layer of the circuit board 1 along the horizontal direction, and the distance between them is maximized. Here, the orientation description such as "left side" and "right side" is only used to represent the relative distance of the two connection regions in space, and is not a limitation on the actual installation direction or absolute coordinates of the circuit board 1; any layout that separates the input side and output side connection structures on opposite edges of the bottom layer of the circuit board 1 belongs to the equivalent embodiments of the present scheme.

[0050] The terminals of the first signal coil 3 are led out through internal conductive paths (such as conductive vias) and electrically connected to at least one pad in the first connection area 5; the terminals of the second signal coil 4 are led out through independent conductive paths (such as conductive vias) and electrically connected to at least one pad in the second connection area 6. With the center of the toroidal core 2 as a reference, the main winding of the first signal coil 3 is located in the left area of the toroidal core 2, and its lead-out wires naturally extend to the left area of the bottom layer of the circuit board 1; the main winding of the second signal coil 4 is located in the right area of the toroidal core 2, and its lead-out wires extend to the right area of the bottom layer. Since the two connection areas are arranged at opposite ends of the bottom layer of the circuit board 1, the shortest path along the surface between the input side and the output side external electrical interface is significantly lengthened, that is, the creepage distance is greatly increased. It can be understood that the longer the creepage distance, the lower the probability of electric leakage, electrochemical migration or flashover breakdown along the surface of the insulating material. Especially in harsh working conditions of high temperature and high humidity or the presence of ionic contaminants, a longer creepage path can effectively block the formation of surface conductive channels, thereby significantly improving the long-term reliability and voltage resistance of the isolation barrier. Combined with the epoxy medium (dielectric strength > 45 kV / mm) used inside the circuit board 1, the all-buried core structure and the three-dimensional spatial isolation of the multi-layer conductive pattern, the above layout further strengthens the overall insulation system. The actual measurement shows that this structure can stably withstand an isolation voltage of 5 kV or more, which is much better than the conventional 2 kV-3 kV scheme, and truly realizes the unity of high integration and high isolation reliability.

[0051] In some embodiments of the present application, the connection area includes a first connection area 5 and a second connection area 6 isolated from each other, and the first connection area 5 and the second connection area 6 are arranged on opposite sides of the horizontal direction of the bottom layer of the circuit board 1. The circuit board 1 further includes a third conductive pattern layer 14 located above the first conductive pattern layer 12 and the second conductive pattern layer 13 and isolated therefrom by the insulating medium layer 11. The third conductive pattern layer 14 includes a fifth pattern part 15 and a sixth pattern part 16 isolated from each other. The first signal coil 3 has a first end 34 electrically connected to a first pad 51 of the first connection area 5 and a second end 35 electrically connected to a second pad 52 of the first connection area 5. The fifth pattern part 15 is electrically connected to the first end 34 and the first pad 51 through a third conductive via 17, and electrically connected to the second end 35 and the second pad 52 through a fourth conductive via 18. The second signal coil 4 has a third end 44 electrically connected to a third pad 61 of the second connection area 6 and a fourth end 45 electrically connected to a fourth pad 62 of the second connection area 6. The sixth pattern part 16 is electrically connected to the third end 44 and the third pad 61 through a fifth conductive via 19, and electrically connected to the fourth end 45 and the fourth pad 62 through a sixth conductive via 20.

[0052] As Figure 4、 Figure 5 、 Figure 7 and Figure 8 The third conductive pattern layer 14 is located above the first conductive pattern layer 12 and the second conductive pattern layer 13, and is electrically isolated from the underlying conductive pattern layers by one or more insulating dielectric layers 11. The third conductive pattern layer 14 is provided with a fifth pattern portion 15 and a sixth pattern portion 16, which are isolated from each other and serve as mounting areas for the input-side chip 7 and the output-side chip 8, respectively. The input-side chip 7 is fixed on the fifth pattern portion 15 by means of flip-chip bonding or wire bonding, and its signal terminals are electrically connected to the fifth pattern portion 15; the output-side chip 8 is also mounted on the sixth pattern portion 16 and is electrically connected to the sixth pattern portion 16.

[0053] The first signal coil 3 is of a two-terminal structure, and does not contain a center tap or other intermediate terminal, but only has a first terminal 34 and a second terminal 35. The first terminal 34, a first pad 51 in the first connection area 5 on the bottom layer of the circuit board 1, and a part of the fifth pattern portion 15 are electrically connected to the same input signal node and are connected vertically through at least one conductive via that penetrates all three layers; the second terminal 35, a second pad 52 in the first connection area 5 on the bottom layer, and another part of the fifth pattern portion 15 constitute another input signal node and are connected through an independent conductive via that penetrates all three layers. In this way, the input-side chip 7 can interact with the two terminals of the first signal coil 3 through the fifth pattern portion 15, and the signal can be led out to the outside of the device through the bottom layer pad.

[0054] Correspondingly, the second signal coil 4 is also of a two-terminal structure, and does not contain any center tap, but only has a third terminal 44 and a fourth terminal 45. The third terminal 44, a third pad 61 in the second connection area 6 on the bottom layer, and a part of the sixth pattern portion 16 constitute the same output signal node and are connected vertically through a common conductive via; the fourth terminal 45, a fourth pad 62, and another part of the sixth pattern portion 16 constitute another output signal node and are connected through another set of conductive vias that penetrate all three layers. In this way, the output-side chip 8 establishes complete access to the second signal coil 4 and the external interface.

[0055] The double-terminal coil structure is a key design to improve the reliability of high-voltage isolation. Omitting the center tap avoids introducing additional conductive nodes and interlayer vias in the middle of the coil, thereby reducing the electric field concentration area and potential leakage path in the insulating medium. Since each group of coils only needs two external connection points, the first and second connection areas 5 and 6 on the bottom layer can be arranged at opposite ends of the bottom layer of the circuit board 1, significantly increasing the surface creepage distance and air gap. In high temperature and humidity or contaminated environments, longer creepage paths effectively suppress surface leakage and flashover risks. At the same time, the double-terminal structure ensures that there is only a single magnetic coupling path between the input and output sides, with no branch conductors crossing the isolation barrier, which is more in line with the safety requirements of strengthening insulation for continuous and uninterrupted insulation systems.

[0056] Since the fifth and sixth patterned portions 15 and 16 are isolated from each other on the top layer, and all conductive paths, including the coil body, chip mounting area, vertical interconnection via, and bottom layer pad, are completely covered by a high dielectric strength epoxy medium (dielectric strength greater than 45 kV / mm), the entire signal transmission link is physically completely isolated in three-dimensional space. As a result, this structure can stably withstand isolation voltages of 5 kV or higher, far superior to conventional 2-3 kV schemes, while supporting high-density chip mounting, it truly realizes high-reliability, high-voltage magnetic isolation performance. In addition, the top layer of the circuit board is protected by the resist solder layer 10 (such as ink), and the third conductive pattern layer 14 is exposed.

[0057] In some embodiments of the present application, the isolation device further comprises: an input-side chip 7 electrically connected to the fifth patterned portion 15 for driving the first signal coil 3, and an output-side chip 8 electrically connected to the sixth patterned portion 16 for receiving the output signal of the second signal coil 4. A first dispensing layer 71 is formed around the pins of the input-side chip 7, covering the pins of the input-side chip 7 and the adjacent area of the fifth patterned portion 15. A second dispensing layer is formed around the pins of the output-side chip 8, covering the pins of the output-side chip 8 and the adjacent area of the sixth patterned portion 16.

[0058] As shown in Figures 7-10 The input-side chip 7 is electrically connected to the fifth patterned portion 15 by flip-chip solder bumps or wire bonding, with multiple pins distributed around the chip's peripheral area. A first dispensing layer 71 is formed around the pins of the input-side chip 7, covering the pins of the input-side chip 7 and the adjacent surface area of the fifth patterned portion 15, forming a continuous encapsulation structure. Similarly, the output-side chip 8 is connected to the sixth patterned portion 16 by flip-chip soldering or wire bonding, with a second dispensing layer formed around its pins, covering the pins of the output-side chip 8 and the adjacent area of the sixth patterned portion 16.

[0059] The first and second dispensing layers 71 and 72 are made of low-stress, high-insulation adhesive material, such as modified epoxy resin or silicone-based glue, with good dielectric properties, moisture and heat resistance, and bonding strength. The functions of the dispensing layers include: fixing the chip pins or bonding wires to prevent connection failure caused by thermal cycling or mechanical vibration; filling the micro-gap between the pins and the pattern part to eliminate air cavities and avoid partial discharge; covering the exposed copper surface and solder joints to block the path of moisture and contaminants along the surface, significantly improving the local creepage distance; smoothing the geometric discontinuity at the pin root to reduce the electric field concentration coefficient and suppress corona or flashover under high voltage. Thus, since the dispensing layers only cover the local area around the respective chips, and the fifth pattern part 15 and the sixth pattern part 16 are already sufficiently electrically isolated on the top layer, the first and second dispensing layers are independent of each other and do not form a conductive or ionic channel across the isolation barrier. This local dispensing design further enhances the insulation reliability from the chip pins to the external interface, providing further protection for stable implementation of isolation withstand voltage of DC 5kV or above.

[0060] In some embodiments of the present application, the isolation device further comprises: a plastic package 9 formed by an insulating plastic packaging material, completely covering the top layer of the circuit board 1 to seal all the exposed conductive structures of the input-side chip 7, the output-side chip 8, the fifth pattern part 15, and the sixth pattern part 16 on the top layer of the circuit board 1 inside the plastic package 9.

[0061] Specifically, the plastic package 9 covers the surface of the top layer of the circuit board 1, embedding all the exposed conductive structures in the input-side chip 7, the output-side chip 8, the fifth pattern part 15, and the sixth pattern part 16 on the top layer inside it. The plastic package 9 forms a dense, pore-free protective layer after curing, effectively isolating external moisture, dust, and contaminants from eroding the surfaces of the chip pins, bonding wires, and pattern parts. At the same time, since the conductive structures of the input side and the output side are already separated by the spatial isolation of the fifth pattern part 15 and the sixth pattern part 16 on the top layer, the plastic package 9 forms a continuous high-insulation filling between them, further extending the creepage path along the surface of the top layer and eliminating the risk of partial discharge that may be caused by air gaps. The plastic package 9 strengthens the integrity of the overall isolation barrier from the packaging level, providing further protection for achieving high-voltage isolation of DC 5kV or above.

[0062] Furthermore, among the existing packaged devices based on circuit board 1, the following types mainly exist: The first type is a PCB with no metal sidewalls. In this type, the PCB sidewalls lack metallization, and the solder paste is only connected through bottom pads. At high temperatures, the pads are prone to detachment, resulting in poor soldering reliability and overall low reliability. The second type is a PCB with metal sidewalls and surface-mount devices (surface-mount without plastic encapsulation). In this type, because the sidewall metal is formed through vias, effective plastic encapsulation is impossible, significantly reducing the overall isolation capability of the device. The third type is a PCB with metal sidewalls and surface-mount devices (surface-mount with plastic encapsulation). Although the surface of this type can be plastic encapsulated, the sidewall metal needs to be cut later to form the plastic encapsulation. During the cutting process, metal residue and bare metal on the cut surface are prone to oxidation, affecting the solder paste application and posing reliability issues.

[0063] To overcome the shortcomings of the prior art, the present invention further proposes a packaging structure. Specifically, the connection area includes multiple pads, at least a portion of which extend to the edge of the circuit board 1. A depth-controlled semi-via 53 is provided on the pads extending to the edge of the circuit board 1. The depth-controlled semi-via 53 is located in the area of ​​the pads near the edge of the circuit board 1 and is exposed on the side of the circuit board 1. The depth of the depth-controlled semi-via 53 is less than the total thickness of the circuit board 1. The walls and bottom of the depth-controlled semi-via 53 are metallized surfaces, making the exposed sidewall formed by the depth-controlled semi-via 53 on the side of the circuit board 1 a continuous conductive surface.

[0064] like Figures 11-12 As shown, the controlled-depth half-hole 53 is located in the area near the edge of the circuit board 1, forming an opening on the side of the circuit board 1, thus exposing the hole wall structure of the controlled-depth half-hole 53 to the outer surface of the circuit board 1. The depth of the controlled-depth half-hole 53 is much less than the total thickness of the circuit board 1, and its hole wall and bottom are metallized to form a continuous conductive surface. Since the controlled-depth half-hole 53 does not penetrate the entire circuit board 1, its bottom terminates in an internal insulating layer, thus not forming an electrical connection with other conductive layer structures. At the same time, the exposed sidewall formed by the controlled-depth half-hole 53 on the side of the circuit board 1 is a complete and continuous metal surface, which can serve as a reliable external electrical contact interface, suitable for direct access of test probes, connector inserts, or solder pins.

[0065] Compared with the prior art, the application has the following obvious advantages: first, the sidewall metallization provides a welding contact surface, enhances the welding strength and reliability, and avoids the problem of high-temperature falling off when only relying on the bottom pad. Second, the design of the depth control half-hole 53 allows the surface molding material to cover the top layer and the sidewall without worrying about the interference of the sidewall metallization, thereby improving the isolation performance of the overall device. Third, after the hole wall and hole bottom of the depth control half-hole 53 are metallized, the oxidation of the sidewall metal can be effectively prevented, the tin effect of the solder paste is improved, and the long-term electrical connection reliability is ensured. Fourth, by setting the depth control half-hole 53 on the pad of the bottom layer of the circuit board 1, the function of the bottom pad for conventional surface mounting is retained, and additional lateral electrical access paths are provided. In addition, the metallized sidewall forms an efficient heat conduction channel, which quickly conducts the heat generated by the input side chip 7 or the output side chip 8 during operation from the inside of the circuit board 1 to the side surface of the device through the copper hole wall of the depth control half-hole 53, and then dissipates further through contact with the system PCB or heat dissipation structure, significantly reducing the chip junction temperature and improving the long-term reliability of the device in high load or high temperature environment. In addition, since the depth control half-hole 53 is only exposed to a local area on the side edge of the circuit board 1, and its depth is controlled and does not penetrate the isolation barrier, the main isolation path between the input side and the output side is always complete, significantly improving the testability and system integration flexibility of the device.

[0066] It is worth noting that the depth control semi-hole 53 in the present scheme not only has its hole wall metallized, but also has its hole bottom surface completely covered with metal. This design is different from the prior art which only has the hole wall of the semi-hole metallized. Specifically, in the conventional semi-hole structure, if the hole bottom is not metallized, a blind cavity composed of insulating medium will be formed inside the circuit board 1. When the device is overall molded, the high-temperature flowing plastic sealing material will easily penetrate into the blind hole bottom along the gap between the hole walls under the action of pressure, and after solidification, it will form closed bubbles, micro-cracks or interface delamination. These defects not only weaken the mechanical strength of the package, but also may become the starting point of local discharge under high-voltage working conditions, reducing the isolation reliability. In the present scheme, by synchronously metallizing the hole bottom of the depth control semi-hole 53, the entire semi-hole inner cavity including the sidewall and the bottom will form a continuous and dense conductive surface, thereby completely eliminating the internal blind hole cavity. When the plastic sealing material contacts the fully metallized surface, it is effectively blocked because there is no penetration channel, ensuring that a complete and defect-free interface is formed between the plastic sealing body 9 and the pad area. This not only improves the sealing performance of the package, but also avoids the concentration of thermal stress and the distortion of the electric field caused by internal cavities. In addition, the hole bottom metallization further enhances the heat conduction and electrical conductivity of the depth control semi-hole 53, enabling it to not only serve as a lateral soldering pin, but also more efficiently conduct the heat of the chip through the metal cavity to the sidewall and then dissipate it to the external environment. In combination with the side wetting surface formed by the hole wall metallization, the fully metallized semi-hole structure is superior to the scheme with only hole wall metallization in terms of electrical connection, thermal management and packaging reliability.

[0067] In some embodiments of the present application, the pad extending to the edge of the circuit board 1 is also provided with a conductive via 54, which is located on the side of the depth control semi-hole 53 facing the center of the circuit board 1 and extends from the pad surface to the inside of the circuit board 1 to electrically connect with the conductive structure of the inner layer. The conductive via 54 has a metallized hole wall and an insulating resin body filled therein, and the top thereof is flush with the pad surface.

[0068] It can be understood that the pad extending to the edge of the circuit board 1 is provided with both the conductive via 54 and the depth control semi-hole 53. The conductive via 54 is located on the side of the depth control semi-hole 53 facing the center of the circuit board 1, extends from the pad surface to the inside of the circuit board 1, and establishes electrical connection with the conductive structure of the inner layer, for leading external signals into or out of the multi-layer wiring network. The conductive via 54 has a metallized hole wall to ensure good electrical conductivity and thermal conductivity; meanwhile, an insulating resin body is filled inside the metallized hole wall, which completely fills the hole cavity and, after solidification, is coplanarized with the pad surface, so that the top of the conductive via 54 is flush with the pad surface. This structure not only retains the vertical interconnection function of the via, but also eliminates the depression or protrusion formed on the surface by the conventional via, providing a flat base for the subsequent plastic sealing process.

[0069] The structure realizes the electrical interconnection between the pad pin and the internal and external network through two independent connection paths: the conductive via hole 54 and the depth-controlled half-hole 53 of the sidewall metallization. On the one hand, the conductive via hole 54 provides a reliable vertical interconnection channel to ensure signal integrity; on the other hand, the metallized surface formed on the sidewall of the circuit board 1 provides an additional wetting interface for soldering. This double connection mechanism significantly improves the connection reliability and mechanical strength of the device pin pad, and is not prone to pull-out or pad-off phenomenon under high-temperature reflow soldering or thermal cycle stress. At the same time, the metallized sidewall and the copper structure of the conductive via hole 54 together form an efficient heat conduction path to quickly conduct the heat generated during chip operation, enhancing the heat dissipation capacity of the device. In addition, the conductive via hole 54 adopts an inner shift layout and is designed to be filled and flattened by electroplating, which has multiple advantages: first, the conductive via hole 54 does not penetrate the circuit board 1 and is located away from the side opening, effectively avoiding the formation of a through channel between the surface layer and the bottom layer due to the connection of the via hole; second, during subsequent plastic encapsulation, the flat surface filled with insulating resin can prevent the plastic encapsulation material from flowing into the hole or overflowing from the hole, ensuring uniform thickness of the plastic encapsulation material without air gaps, and ensuring the processability and sealing reliability of the overall surface plastic encapsulation; third, during the final welding of the device to the system PCB, the filled via hole structure can prevent solder from seeping into the interior along the hole wall, avoiding solder siphoning that leads to virtual welding, voids or internal contamination, thereby improving the welding yield and long-term reliability. In addition, the metallization design of the pad sidewall allows the solder to climb up the sidewall during welding, forming a solder joint that wraps around the side of the pad. This side wetting effect not only makes the welding more secure, but also allows the solder joint to be partially exposed in the side view direction, making it easier to directly inspect the welding quality through optical or X-ray methods and promptly detect defects such as virtual welding, insufficient solder or cracks, significantly reducing the risk of welding and improving the controllability and product consistency of the production process.

[0070] In summary, the composite pin structure simultaneously realizes high-reliability electrical connection, efficient heat dissipation, plastic encapsulation process compatibility, and inspectability without breaking the high-isolation barrier between the input side and the output side, providing key packaging support for high-density integration and high-reliability application of DC 5kV or higher high-voltage isolation devices.

[0071] In some embodiments of the present application, the depth-controlled half-hole 53 does not have a metal cover at the outermost edge of the circuit board 1, and the metallized surface of the hole wall and the hole bottom terminates inside the outermost edge of the circuit board 1, exposing the insulating medium layer 11. The conductive part of the depth-controlled half-hole 53 is separated from the outermost surface of the circuit board 1 by the insulating medium layer 11, forming a non-conductive edge isolation zone 55.

[0072] Specifically, in the manufacturing process, by etching the hole copper of the depth-controlled half-hole 53 exposed on the side wall of the circuit board 1 inward, the side wall metal can be moved inward, thereby exposing the insulating medium and forming a non-conductive edge isolation zone 55. This edge isolation zone 55 effectively avoids the metallization in the entire side wall direction, thereby preventing the plastic sealing material from flowing into the device interior or overflowing along the board edge through the through channel formed by the side wall metallization when the top layer is subsequently overall plastic sealed. This not only ensures the sealing integrity of the plastic sealing body 9, but also ensures the processability and consistency of the surface plastic sealing process, avoiding the hollowing, delamination or pollution caused by the leakage of the plastic sealing material. Secondly, compared with the traditional process of side wall metallization on the entire thickness of the circuit board 1 (such as full-depth milling + deep hole electroplating), the depth of the depth-controlled half-hole 53 used in the present solution is relatively shallow, usually only penetrating one to two layers and then terminating in the internal insulating medium. This shallow depth structure significantly reduces the mechanical stress of drilling or milling, the control difficulty of the flow resistance of the electroplating liquid, greatly improves the processing yield and reduces the manufacturing cost. Therefore, the design of the depth-controlled half-hole 53 combined with the edge insulating isolation zone meets the requirements of high-reliability electrical connection and lateral heat dissipation, while also considering high-voltage isolation, plastic sealing process compatibility and manufacturability.

[0073] In some embodiments of the present application, the circuit board 1 is provided with a stepped profile 56 adjacent to the side edge of the bottom layer, and the stepped profile 56 is composed of a vertical side wall surface 5601 and a horizontal bottom surface 5602 connected to the bottom outer edge thereof. The depth-controlled half-hole 53 penetrates the pad and extends to the vertical side wall surface 5601, and does not extend to the horizontal bottom surface 5602.

[0074] Specifically, the circuit board 1 is provided with a stepped profile 56 adjacent to the side edge of its bottom layer. The stepped profile 56 is composed of a vertical side wall surface 5601 and a horizontal bottom surface 5602 connected to the outer edge of the bottom, forming an inwardly recessed step structure. The depth and position of the depth-controlled half-hole 53 are precisely controlled so that it does not extend to the horizontal bottom surface 5602. It can be understood that the stepped profile 56 is located in the non-metallic coverage area of the device edge, and the sidewall metallization part on the pad (i.e. the metallized surface of the depth-controlled half-hole 53) is offset to the inside of the device, so that the metallized area is not in the same plane as the physical edge of the outermost side of the circuit board 1. After the completion of the whole board manufacturing of the device, the individual isolated devices are separated from the mother board by mechanical cutting or laser cutting along the horizontal bottom surface 5602. Since the cutting path is located in the horizontal bottom surface 5602 area without metal, the cutting process will not touch any conductive structure, thereby completely avoiding the metal residue, burr or exposed fresh metal surface caused by traditional full-metal sidewall cutting. This design effectively solves the key pain points in the prior art: in conventional sidewall metallization devices, cutting will expose the active metal surface, which will rapidly oxidize in the air, forming a high-impedance oxide layer, which will seriously affect the wetting and climbing ability of the solder during the subsequent reflow soldering process, resulting in virtual soldering, less solder or insufficient solder strength. In the present solution, the side edge of the cut device only exposes the horizontal bottom surface 5602 composed of insulating medium, and all the metallized structures are retained on the inside of the vertical side wall surface 5601, away from the cutting surface. Therefore, the sidewall metal remains intact and is not mechanically damaged, ensuring that the solder can wet the metallized sidewall of the depth-controlled half-hole 53 well during soldering, forming a firm and reliable solder joint.

[0075] In addition, due to the physical misalignment between the metallized area and the outermost edge of the device, even in a high-humidity or contaminated environment, external contaminants are difficult to directly contact the conductive surface, further improving the electrical stability during long-term use. Combined with the full-metalization of the hole wall and hole bottom of the depth-controlled half-hole 53, the non-conductive edge isolation area 55 and the overall encapsulation of the top plastic encapsulation 9, the stepped profile 56 design ensures the unity of the cuttability, soldering reliability and high-voltage isolation performance of the device from the manufacturing source, providing key process support for large-scale production of high-density and high-reliability magnetic isolation devices.

[0076] Therefore, the application provides a small-sized magnetic isolation packaging device with high isolation, high reliability and processability, which is constructed based on multilayer printed circuit board integration, a toroidal magnetic core 2 is completely embedded in a high dielectric strength epoxy medium, and an internal magnetic coupling structure is formed by two layers of pattern parts and vias, and meanwhile, the inside of the circuit board 1 is filled with insulating medium to realize complete physical isolation; the input side chip 7 and the output side chip 8 are respectively installed in the top layer of the pattern area isolated from each other, and magnetic isolation signal transmission is realized through a double-terminal non-tapped signal coil; the whole top layer structure is completely covered by an insulating plastic package body 9, and the bottom layer is provided with an input / output connection area at two ends, so as to ensure that the input and output circuits are completely physically isolated in three-dimensional space. The device pin pads are connected with the inner layer network through the inwardly moved conductive vias 54, the vias are filled with insulating resin after being metallized and are ground to be flush with the surface of the pads, which not only ensures the reliability of vertical interconnection, but also avoids the penetration of plastic sealing material or solder siphoning; meanwhile, the pads extend to the edge of the board and are integrated with depth control half-holes 53, the half-holes are metallized, and the conductive part thereof terminates at the inside of the outermost edge of the circuit board 1, forming a non-conductive edge isolation area 55, the metallized area of the side wall and the cutting surface are arranged in a staggered manner through a preset step structure, so as to ensure that the side wall of a single device is not exposed to metal and has no risk of oxidation after cutting. When welding, solder can wet and climb along the metallized side wall to form a firm and visible solder joint, which significantly improves the connection strength and process reliability. Thanks to the synergistic effect of the completely embedded magnetic core and the conductive distribution inside the circuit board 1, the epoxy medium, the end-to-end pad layout, the fully metallized depth control half-hole 53 and the edge insulation design, the device realizes an ultra-high isolation voltage of 8kV, which is much higher than the conventional 2kV-3kV level in the industry, and the overall size is small, which provides a magnetic isolation solution with high performance, high integration and mass production feasibility for high safety application scenarios such as new energy vehicles, industrial control and medical electronics.

[0077] In the description of the application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the application.

[0078] In the description of the specification, reference to "one embodiment", "some embodiments", "an exemplary embodiment", "an example", "a specific example", or "some examples" means that a particular feature, structure, material, or characteristic being described is included in at least one embodiment or example of the application. The appearances of the phrases "in one embodiment", "in some embodiments", "in an exemplary embodiment", "an example", "a specific example", or "some examples" in various places in the specification are not necessarily referring to the same embodiment or example.

[0079] While embodiments of the application have been shown and described, it is to be understood that the application is not limited to these embodiments. Rather, it is the intention that modifications, changes, substitutions, and variations be made to the embodiments in keeping with the principles and spirit of the application. The scope of the application is to be limited only by the claims and their equivalents.

Claims

1. An isolation device, characterized by, The application relates to a circuit board (1) comprising: a plurality of conductive pattern layers and a plurality of insulating medium layers (11) are alternately laminated, at least comprising a first conductive pattern layer (12) and a second conductive pattern layer (13) between adjacent conductive pattern layers, and a single layer or multiple layers of insulating medium are arranged therebetween; a ring-shaped magnetic core (2) is completely embedded in the single layer or multiple layers of insulating medium; a first signal coil (3) and a second signal coil (4) are arranged around the center hole of the ring-shaped magnetic core (2) and are not electrically connected to each other; the first signal coil (3) comprises a first pattern part (31) formed on the first conductive pattern layer (12), a second pattern part (32) formed on the second conductive pattern layer (13), and a first conductive via (33) connecting the first pattern part (31) and the second pattern part (32); the second signal coil (4) comprises a third pattern part (41) formed on the first conductive pattern layer (12), a fourth pattern part (42) formed on the second conductive pattern layer (13), and a second conductive via (43) connecting the third pattern part (41) and the fourth pattern part (42); wherein the first pattern part (31) and the third pattern part (41) are located in different regions of the first conductive pattern layer (12) and are isolated from each other, the second pattern part (32) and the fourth pattern part (42) are located in different regions of the second conductive pattern layer (13) and are isolated from each other; the terminals of the first signal coil (3) and the terminals of the second signal coil (4) are respectively led out from the corresponding pattern parts and electrically connected to the connection areas on the bottom layer of the circuit board (1), and all the space paths between the first signal coil (3) and the second signal coil (4) are separated by the insulating medium layers (11) to realize electrical isolation.

2. The isolation device of claim 1, wherein, the first pattern part (31) and the third pattern part (41) extend around the center hole of the ring-shaped magnetic core (2) and are separated from each other in the circumferential direction in the plane of the first conductive pattern layer (12) and respectively occupy different sector regions of the outer periphery of the ring-shaped magnetic core (2); and the second pattern part (32) and the fourth pattern part (42) extend around the center hole of the ring-shaped magnetic core (2) and are separated from each other in the circumferential direction in the plane of the second conductive pattern layer (13) and respectively occupy different sector regions of the outer periphery of the ring-shaped magnetic core (2).

3. The isolation device of claim 1, wherein, the connection areas comprise a first connection area (5) and a second connection area (6) which are isolated from each other, and the first connection area (5) and the second connection area (6) are respectively arranged on the opposite sides of the bottom layer of the circuit board (1) in the horizontal direction; the terminals of the first signal coil (3) are electrically connected to at least one pad of the first connection area (5), and the terminals of the second signal coil (4) are electrically connected to at least one pad of the second connection area (6). The main winding of the first signal coil (3) is located at the left side region of the ring-shaped magnetic core (2) with the center of the ring-shaped magnetic core (2) as a reference, and the first connecting region (5) is arranged at the left side of the bottom layer of the circuit board (1); the main winding of the second signal coil (4) is located at the right side region of the ring-shaped magnetic core (2), and the second connecting region (6) is arranged at the right side of the bottom layer of the circuit board (1); The first connecting region (5) and the second connecting region (6) each include a plurality of pads for respectively connecting input side signals and output side signals.

4. The isolation device of claim 1, wherein, The connecting region includes the first connecting region (5) and the second connecting region (6) which are isolated from each other and are arranged at opposite sides in the horizontal direction of the bottom layer of the circuit board (1); The circuit board (1) further includes a third conductive pattern layer (14) which is located above the first conductive pattern layer (12) and the second conductive pattern layer (13) and is isolated therefrom by the insulating medium layer (11); the third conductive pattern layer (14) includes a fifth pattern portion (15) and a sixth pattern portion (16) which are isolated from each other; The first signal coil (3) has a first end (34) and a second end (35), the first end (34) is electrically connected to a first pad (51) of the first connecting region (5), and the second end (35) is electrically connected to a second pad (52) of the first connecting region (5); the fifth pattern portion (15) is electrically connected to the first end (34) and the first pad (51) through a third conductive via (17) and is electrically connected to the second end (35) and the second pad (52) through a fourth conductive via (18); The second signal coil (4) has a third end (44) and a fourth end (45), the third end (44) is electrically connected to a third pad (61) of the second connecting region (6), and the fourth end (45) is electrically connected to a fourth pad (62) of the second connecting region (6); the sixth pattern portion (16) is electrically connected to the third end (44) and the third pad (61) through a fifth conductive via (19) and is electrically connected to the fourth end (45) and the fourth pad (62) through a sixth conductive via (20).

5. The isolation device of claim 4, wherein, The input side chip (7) is electrically connected to the fifth pattern portion (15) for driving the first signal coil (3), and the output side chip (8) is electrically connected to the sixth pattern portion (16) for receiving the output signal of the second signal coil (4); The first dispensing layer (71) is formed around the pins of the input-side chip (7) and covers the pins of the input-side chip (7) and the region of the adjacent fifth pattern part (15); the second dispensing layer is formed around the pins of the output-side chip (8) and covers the pins of the output-side chip (8) and the region of the adjacent sixth pattern part (16).

6. The isolation device of claim 5, wherein, Further comprising: The plastic package (9) is formed by an insulating plastic package material and completely covers the top layer of the circuit board (1) to seal the exposed conductive structures of the input-side chip (7), the output-side chip (8), the fifth pattern part (15) and the sixth pattern part (16) of the top layer of the circuit board (1) in the plastic package (9).

7. The isolation device of claim 1, wherein The connecting region comprises a plurality of pads, at least some of which extend to the edge of the circuit board (1); The pad extending to the edge of the circuit board (1) is provided with a depth control half-hole (53) located in the region close to the edge of the circuit board (1) and exposed to the side edge of the circuit board (1); the depth of the depth control half-hole (53) is less than the total thickness of the circuit board (1), the hole wall and the hole bottom of the depth control half-hole (53) are both metallized surfaces, and the exposed side wall formed on the side edge of the circuit board (1) is a continuous conductive surface.

8. The isolation device of claim 7, wherein, The pad extending to the edge of the circuit board (1) is also provided with a conductive via (54) located on the side of the depth control half-hole (53) facing the center of the circuit board (1) and extending from the surface of the pad to the inside of the circuit board (1) to electrically connect with the conductive structure of the inner layer; The conductive via (54) has a metallized hole wall and an insulating resin body filled therein, and the top thereof is flush with the surface of the pad.

9. The isolation device of claim 7, wherein, The depth control half-hole (53) does not have metal coverage at the outermost edge of the circuit board (1), and the metallized surfaces of the hole wall and the hole bottom terminate on the inner side of the outermost edge of the circuit board (1), exposing the insulating medium layer (11); The conductive part of the depth control half-hole (53) is separated from the outermost surface of the circuit board (1) by the insulating medium layer (11) to form a non-conductive edge isolation region (55).

10. The isolation device according to claim 7 or 9, characterized in that The circuit board (1) is provided with a stepped profile (56) adjacent to the side edge of the bottom layer, which is composed of a vertical side wall surface (5601) and a horizontal bottom surface (5602) connected to the outer edge of the bottom; the depth control half-hole (53) penetrates the pad and extends to the vertical side wall surface (5601) and does not extend to the horizontal bottom surface (5602).

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