MOS device and preparation method thereof
By setting gate structures with different dielectric constants above the JFET region of the MOS device, the capacitance problem between the gate and drain is solved, the device's response speed and high electric field resistance are improved, and the device's reliability is enhanced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-03
- Publication Date
- 2026-03-10
AI Technical Summary
The parasitic capacitance between the gate and drain in existing MOS devices leads to slower dynamic response, increased power consumption, and reduced device reliability.
A gate structure is provided above the JFET region of a MOS device, including an outer peripheral portion and a middle portion with different dielectric constants. The dielectric constant of the middle portion is smaller than that of the outer peripheral portion. By providing a gate structure including a gate oxide layer, a first dielectric layer and a gate layer above the JFET region, the dielectric constant of the middle portion is smaller than that of the outer peripheral portion.
The capacitance between the gate and drain structures is reduced, which improves the response speed of the MOS device, reduces power consumption, and enhances the device's ability to withstand high electric fields and its long-term stability.
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Figure CN121645955A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and in particular, relates to a MOS device and a preparation method of the MOS device. BACKGROUND
[0002] A MOS device (Metal-Oxide-Semiconductor Field-Effect Transistor) is a kind of semiconductor device, which is used to amplify or switch electronic signals, and the current between the source and the drain is controlled by the gate voltage. Although the MOS device exhibits obvious performance advantages, there are still some challenges in practical application, especially the problem of parasitic capacitance between the gate and the drain. The gate-drain capacitance not only affects the dynamic response speed of the device, causing the switching time to be prolonged, but also generates additional power consumption in the switching process, accelerates the aging of the device, and reduces the overall reliability.
[0003] Therefore, there is an urgent need for a MOS device to solve the above problems.
[0004] The above information disclosed in the background section is only used to enhance the understanding of the background of the technology described herein, and therefore, the background section can contain certain information that is not known to those skilled in the art as prior art in the country. SUMMARY
[0005] The main purpose of the present application is to provide a MOS device and a preparation method of the MOS device, so as to solve the problem of how to improve the reliability of the MOS device in the prior art.
[0006] In order to achieve the above purpose, according to one aspect of the present application, a MOS device is provided, comprising: a substrate; an epitaxial layer located on one side of the substrate; a JFET region located in the epitaxial layer; a gate structure located on the side of the JFET region away from the substrate, the orthographic projection of the gate structure on the substrate and the orthographic projection of the JFET region on the substrate at least partially overlap, the gate structure comprises a gate oxide layer, a first dielectric layer and a gate layer, the first dielectric layer is located on the side of the gate oxide layer away from the epitaxial layer, the gate layer is located on the side of the first dielectric layer away from the epitaxial layer, the first dielectric layer comprises an intermediate part and an outer peripheral part located on the outer periphery of the intermediate part, wherein the dielectric constant of at least part of the intermediate part is less than the dielectric constant of the outer peripheral part; a source structure located on the side of the epitaxial layer away from the substrate; a drain structure located on the side of the substrate away from the epitaxial layer.
[0007] Optionally, in the thickness direction perpendicular to the substrate, the dielectric constant of each position of the intermediate part is the same.
[0008] Optionally, along a direction perpendicular to a thickness direction of the substrate, the intermediate portion comprises first dielectric regions and second dielectric regions arranged alternately, and the second dielectric regions are in contact with the peripheral portion, wherein a dielectric constant of the first dielectric regions is greater than a dielectric constant of the second dielectric regions, and the dielectric constant of the second dielectric regions is less than a dielectric constant of the peripheral portion.
[0009] Optionally, along the direction perpendicular to the thickness direction of the substrate, a width of the first dielectric regions is a first width, and a width of the second dielectric regions is a second width, the first width and the second width are respectively 25-100 nm, and a ratio of the second width to the first width is 0.8:1-5:1.
[0010] Optionally, along the thickness direction of the substrate, an average thickness of the intermediate portion is greater than or equal to an average thickness of the peripheral portion.
[0011] Optionally, the MOS device further comprises a first doped region, a second doped region and a third doped region, the first doped region, the second doped region and the third doped region are located in the epitaxial layer, a projection of the gate structure on the substrate and a projection of the first doped region on the substrate at least partially overlap, the first doped region is located on a side of the second doped region and the third doped region close to the substrate, and in a direction perpendicular to the substrate, the first doped region is located on a side of the third doped region away from the second doped region, and the third doped region has a spacing from the JFET region, wherein a doping type of the first doped region is the same as a doping type of the second doped region, and the doping type of the first doped region is different from a doping type of the third doped region.
[0012] Optionally, a material of the first dielectric layer satisfies at least one of the following: a material of the peripheral portion comprises at least one of hafnium oxide, silicon nitride, titanium dioxide, aluminum oxide and zirconium oxide; and a material of the intermediate portion comprises at least one of fluorosilicate glass, porous organosilicate glass, fluorine-containing polyimide and benzocyclobutene.
[0013] Optionally, the MOS device satisfies at least one of the following: along the thickness direction of the substrate, an average thickness of the peripheral portion is 300-600 angstroms; and along the thickness direction of the substrate, an average thickness of the intermediate portion is 400-6000 angstroms.
[0014] Optionally, the MOS device further comprises a second dielectric layer located between adjacent gate structures and source structures and on a side of the gate structure away from the substrate; and an ohmic contact layer located between the source structure and the epitaxial layer.
[0015] To achieve the above object, according to another aspect of the present application, a method for manufacturing a MOS device is provided, the method is used for manufacturing any one of the MOS devices, and the method comprises the following steps: providing a substrate, and forming a preliminary epitaxial layer on one side of the substrate; processing part of the preliminary epitaxial layer to obtain a JFET region, and the remaining preliminary epitaxial layer forms the epitaxial layer; sequentially forming a gate oxide layer and a preliminary dielectric layer on the side of the JFET region away from the substrate; removing part of the preliminary dielectric layer to obtain at least one groove, and the remaining preliminary dielectric layer forms an outer peripheral part and an intermediate part in the groove, wherein the remaining preliminary dielectric layer is located on both sides of the removed preliminary dielectric layer, the dielectric constant of at least part of the intermediate part is smaller than the dielectric constant of the outer peripheral part, and the outer peripheral part and the intermediate part form a first dielectric layer; forming a gate layer on the side of the first dielectric layer away from the gate oxide layer, the gate oxide layer, the first dielectric layer and the gate layer form a gate structure, and the orthographic projection of the gate structure on the substrate and the orthographic projection of the JFET region on the substrate at least partially overlap; forming a source structure on the side of the epitaxial layer away from the substrate; and forming a drain structure on the side of the substrate away from the epitaxial layer.
[0016] The technical scheme of the present application provides a MOS device, which comprises a substrate, an epitaxial layer, a JFET region, a gate structure, a source structure and a drain structure, the epitaxial layer is located on one side of the substrate; the JFET region is located in the epitaxial layer; the gate structure is located on the side of the JFET region away from the substrate, the orthographic projection of the gate structure on the substrate and the orthographic projection of the JFET region on the substrate at least partially overlap, the gate structure comprises a gate oxide layer, a first dielectric layer and a gate layer, the first dielectric layer comprises an intermediate part and an outer peripheral part located on the outer periphery of the intermediate part, and the dielectric constant of at least part of the intermediate part is smaller than the dielectric constant of the outer peripheral part; the source structure is located on the side of the epitaxial layer away from the substrate; and the drain structure is located on the side of the substrate away from the epitaxial layer. By arranging the gate structure comprising the gate oxide layer, the first dielectric layer and the gate layer above the JFET region, wherein the first dielectric layer comprises the outer peripheral part and the intermediate part with different dielectric constants, and the dielectric constant of the intermediate part is smaller than the dielectric constant of the outer peripheral part. Since the material with low dielectric constant can be thicker than the material with high dielectric constant, the intermediate part has a better effect of reducing the capacitance between the gate structure and the drain structure. Since the MOS device reacts faster and consumes less power in the case of smaller capacitance, the MOS device is less damaged and has better long-term stability. In addition, the MOS device can also improve the high-voltage resistance of the MOS device since the material with high dielectric constant has good high-voltage resistance. Therefore, the reliability of the MOS device can be improved in terms of reducing power consumption and improving high-voltage resistance. BRIEF DESCRIPTION OF DRAWINGS
[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the application, and are incorporated in and constitute a part of this specification, the illustrative embodiments of the application, and explanations of the same, do not limit the application. In the drawings:
[0018] Figure 1 A structural schematic diagram of a MOS device according to a first embodiment of the present application is shown;
[0019] Figure 2 A structural schematic diagram of a MOS device according to a second embodiment of the present application is shown;
[0020] Figure 3 A flow chart of a method for manufacturing a MOS device according to the present application is shown;
[0021] Fig. 4(a)~(l) show structural schematic diagrams corresponding to specific flow charts of a method for manufacturing a MOS device according to a first embodiment of the present application.
[0022] In the above drawings, the following reference numerals are used:
[0023] 10, substrate; 20, epitaxial layer; 201, JFET region; 202, first doped region; 203, second doped region; 204, third doped region; 205, channel; 206, preliminary epitaxial layer; 30, gate structure; 301, gate oxide layer; 302, first dielectric layer; 3021, middle portion; 3022, peripheral portion; 3023, first dielectric region; 3024, second dielectric region; 303, gate layer; 304, preliminary dielectric layer; 305, recess; 40, source structure; 50, drain structure; 60, second dielectric layer; 70, ohmic contact layer. DETAILED DESCRIPTION
[0024] It should be noted that the following detailed description is merely exemplary and is intended to provide further description of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
[0025] It is to be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. It is to be understood that the terms "comprising," "including," and "having" can be used interchangeably.
[0026] It should be noted that the terms "first", "second", and the like in the description and in the claims of the present application and the above-described accompanying drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.
[0027] It should be understood that when an element (such as a layer, film, region, or substrate) is described as "on" another element, it can be directly on the other element, or an intermediate element can also be present. Moreover, in the specification and claims, when an element is described as "connected" to another element, it can be "directly connected" to the other element, or "connected" to the other element through a third element.
[0028] The gate-drain capacitance of the silicon carbide MOS device in the prior art is relatively large, which increases the delay of the device, additionally generates large power consumption, accelerates the degradation of the device, and the device has poor reliability.
[0029] As introduced in the background, the reliability of the MOS device in the prior art is not ideal. To solve the above problems, embodiments of the present application provide a MOS device and a preparation method of the MOS device.
[0030] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the accompanying drawings in the embodiments of the present application.
[0031] Figure 1 And Figure 2 is a structural schematic diagram of the MOS device according to the embodiments of the present application. As shown in Figure 1 And Figure 2 shown, comprising:
[0032] a substrate 10;
[0033] The material of the above-mentioned substrate 10 can be silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, sapphire, etc., and the resistivity of the substrate 10 can be 0.02±20% Ωcm.
[0034] an epitaxial layer 20 located on one side of the above-mentioned substrate 10;
[0035] In practical applications, the epitaxial layer 20 can be a single-layer structure or a multi-layer structure. The epitaxial layer 20 can be used as a drift layer and bear the main breakdown effect. The doping concentration of the epitaxial layer 20 can be 1E+15~1E+16 cm -3 The thickness of the epitaxial layer 20 can be set according to the breakdown voltage of the MOS device. The greater the voltage of the MOS device, the greater the thickness of the epitaxial layer 20. For example, when the voltage of the MOS device is 1200V, the thickness of the epitaxial layer 20 is 9~11μm; when the voltage of the MOS device is 650V, the thickness of the epitaxial layer 20 is 5~7μm.
[0036] The JFET region 201 is located in the epitaxial layer 20.
[0037] The doping type of the JFET region 201 (Junction Field-Effect Transistor region) is the same as that of the substrate 10, and the doping concentration thereof can be 1E+18±50% cm -3 The thickness thereof can be 0.8~0.9μm. The JFET region 201 is used to generate a lateral voltage drop and reverse bias the PN junction when the drain current increases, thereby increasing the on-resistance of the MOS device.
[0038] The gate structure 30 is located on the side of the JFET region 201 away from the substrate 10. The orthogonal projection of the gate structure 30 on the substrate 10 and the orthogonal projection of the JFET region 201 on the substrate 10 at least partially overlap. The gate structure 30 includes a gate oxide layer 301, a first dielectric layer 302, and a gate layer 303. The first dielectric layer 302 is located on the side of the gate oxide layer 301 away from the epitaxial layer 20. The gate layer 303 is located on the side of the first dielectric layer 302 away from the epitaxial layer 20. The first dielectric layer 302 includes an intermediate portion 3021 and a peripheral portion 3022 located on the periphery of the intermediate portion 3021. At least part of the intermediate portion 3021 has a dielectric constant smaller than that of the peripheral portion 3022.
[0039] The thickness of the gate oxide layer 301 is small, and can be 10-100 angstroms. The material of the gate oxide layer 301 can be silicon oxide, which can be used to improve the interface state and thus improve the carrier mobility. The gate electrode layer 303 includes a polysilicon material layer and a gate electrode layer, and the gate electrode layer is located on the side of the polysilicon material layer away from the first dielectric layer 302. In practical applications, the outer peripheral portion 3022 can be located on the outer periphery of the middle portion 3021 in any direction perpendicular to the thickness direction of the substrate 10, or can be located on the outer periphery of the middle portion 3021 in the entire direction perpendicular to the thickness direction of the substrate 10. The dielectric constant, also known as the relative dielectric constant, is a physical quantity used to describe the charge storage capacity and dielectric properties of a material. It is one of the inherent properties of the material, indicating the proportion of the charge storage capacity of a certain material relative to the charge storage capacity in a vacuum state under the action of the same electric field.
[0040] The source structure 40 is located on the side of the epitaxial layer 20 away from the substrate 10.
[0041] In practical applications, the source structure 40 can serve as the input end of the current, and the material of the source structure 40 can be an alloy of one or more of nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), platinum (Pt), etc.
[0042] The drain structure 50 is located on the side of the substrate 10 away from the epitaxial layer 20.
[0043] In practical applications, the drain structure 50 can serve as the output end of the current, and the material of the drain structure 50 can be an alloy of one or more of nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), platinum (Pt), etc.
[0044] The MOS device provided by the embodiment comprises a substrate, an epitaxial layer, a JFET region, a gate structure, a source structure and a drain structure. The epitaxial layer is located on one side of the substrate. The JFET region is located in the epitaxial layer. The gate structure is located on the side of the JFET region away from the substrate. The orthographic projection of the gate structure on the substrate and the orthographic projection of the JFET region on the substrate at least partially overlap. The gate structure comprises a gate oxide layer, a first dielectric layer and a gate layer. The first dielectric layer comprises a middle part and a peripheral part located on the periphery of the middle part. The dielectric constant of at least part of the middle part is smaller than the dielectric constant of the peripheral part. The source structure is located on the side of the epitaxial layer away from the substrate. The drain structure is located on the side of the substrate away from the epitaxial layer. By arranging the gate structure comprising the gate oxide layer, the first dielectric layer and the gate layer above the JFET region, wherein the first dielectric layer comprises the peripheral part and the middle part with different dielectric constants, and the dielectric constant of the middle part is smaller than the dielectric constant of the peripheral part. Since the material with low dielectric constant can be thicker than the material with high dielectric constant, the middle part has a better effect of reducing the capacitance between the gate structure and the drain structure. Since the MOS device reacts faster and consumes less power in the case of smaller capacitance, the damage to the MOS device is also smaller, and the long-term use stability is better. In addition, since the material with high dielectric constant has good high electric field resistance, the above MOS device can also improve the high electric field resistance of the MOS device. Therefore, by comprehensively using the above methods, the reliability of the MOS device can be improved from the aspects of reducing power consumption and improving high voltage resistance.
[0045] To further reduce the capacitance between the gate structure 30 and the drain structure 50, in the specific implementation process, as shown in Figure 1 the dielectric constant of each position of the middle part 3021 is the same in the thickness direction perpendicular to the substrate 10. Such uniform dielectric properties help to stabilize the dynamic performance of the MOS device, avoid uneven capacitance caused by local changes in the material, and further reduce energy loss and thermal stress during switching, thereby further improving the high-frequency response and overall reliability of the device.
[0046] In the above embodiment, the dielectric constant of each position of the middle part 3021 is the same, which means that the dielectric constant of each position in the middle part 3021 is smaller than the dielectric constant of the peripheral part 3022.
[0047] As shown in Figure 2As shown, along the thickness direction perpendicular to the substrate 10, the intermediate portion 3021 includes first dielectric regions 3023 and second dielectric regions 3024 arranged alternately, and the second dielectric regions 3024 are in contact with the peripheral portion 3022, wherein the dielectric constant of the first dielectric regions 3023 is greater than the dielectric constant of the second dielectric regions 3024, and the dielectric constant of the second dielectric regions 3024 is less than the dielectric constant of the peripheral portion 3022. The intermediate portion 3021 includes the first dielectric regions 3023 and the second dielectric regions 3024 arranged alternately, and the dielectric constant of the first dielectric regions 3023 is greater than the dielectric constant of the second dielectric regions 3024, so that the use of the material with high dielectric constant can be increased, thereby further improving the high electric field resistance of the MOS device.
[0048] In the implementation process, the dielectric constant of the peripheral portion 3022 can be the same as or different from the dielectric constant of the first dielectric regions 3023.
[0049] In order to further improve the high electric field resistance of the MOS device, as shown in Figure 2 As shown, along the thickness direction perpendicular to the substrate 10, the width of the first dielectric regions 3023 is a first width, and the width of the second dielectric regions 3024 is a second width, the first width and the second width are respectively 25-100 nm, and the ratio of the second width to the first width is 0.8:1-5:1. The first width and the second width are within the above range, and the ratio of the second width to the first width is within the above range, so that the improvement of the high electric field resistance of the MOS device and the reduction of the capacitance between the gate structure 30 and the drain structure 50 can be balanced.
[0050] In the implementation process, the first width can be greater than or less than the second width. The first width can be the same as or different from the second width.
[0051] As shown in Figure 1 and Figure 2 As shown, along the thickness direction of the substrate 10, the average thickness of the intermediate portion 3021 is greater than or equal to the average thickness of the peripheral portion 3022. The average thickness of the intermediate portion 3021 being greater than or equal to the average thickness of the peripheral portion 3022 can further reduce the capacitance between the gate structure 30 and the drain structure 50.
[0052] Since the thickness of the peripheral portion 3022 and the intermediate portion 3021 can be uneven, the thickness of the peripheral portion 3022 and the intermediate portion 3021 can be measured at different positions, and the average value is within the above range.
[0053] In some embodiments, as shown in Figure 1 andFigure 2 As shown in the above MOS device further comprises: a first doped region 202, a second doped region 203 and a third doped region 204, the first doped region 202, the second doped region 203 and the third doped region 204 are located in the epitaxial layer 20, the orthogonal projection of the gate structure 30 on the substrate 10 and the orthogonal projection of the first doped region 202 on the substrate 10 at least partially overlap, the first doped region 202 is located on the side of the second doped region 203 and the third doped region 204 close to the substrate 10, and in the direction perpendicular to the substrate 10, the first doped region 202 is located on the side of the third doped region 204 away from the second doped region 203, and the third doped region 204 has a spacing with the JFET region 201, wherein the doping type of the first doped region 202 is the same as the doping type of the second doped region 203, and the doping type of the first doped region 202 is different from the doping type of the third doped region 204. The second doped region 203 can reduce the lateral resistance of the first doped region 202. The third doped region 204 can form an ohmic contact with the source structure 40, thereby reducing the contact resistance.
[0054] In the above implementation, the doping type of the third doped region 204 is the same as the doping type of the JFET region 201, and the doping concentration of the second doped region 203 is greater than the doping concentration of the first doped region 202. In the thickness direction perpendicular to the substrate 10, the average thickness of the first doped region 202 can be 0.7-0.8 μm. The doping concentration of the first doped region 202 can be 1E+17±50% cm -3 In the thickness direction perpendicular to the substrate 10, the average thickness of the second doped region 203 can be 0.2-0.3 μm, and the doping concentration of the second doped region 203 can be 1E+19±50% cm -3 The doping elements of the first doped region 202 and the second doped region 203 can be B, Al and Ga, etc. In the thickness direction perpendicular to the substrate 10, the average thickness of the third doped region 204 can be 0.2-0.3 μm, and the doping concentration of the third doped region 204 can be 1E+19-1E+20 cm -3 A channel 205 is formed in the third doped region 204, and in the direction perpendicular to the thickness of the substrate 10, the width of the channel 205 is 0.3-0.6 μm.
[0055] In other embodiments, as Figure 1 and Figure 2As shown, the material of the first dielectric layer 302 satisfies at least one of the following: the material of the outer peripheral portion 3022 includes at least one of hafnium oxide, silicon nitride, titanium dioxide, aluminum oxide, and zirconium oxide; and the material of the intermediate portion 3021 includes at least one of fluorinated silicate glass, porous organic silicate glass, fluorine-containing polyimide, and benzocyclobutene.
[0056] In the above embodiments, the dielectric constant of hafnium oxide is between 20 and 25. The dielectric constant of silicon nitride is between 7 and 8. In addition to a high dielectric constant, silicon nitride also has good chemical stability and can effectively block the penetration of moisture and other contaminants. The dielectric constant of titanium dioxide is about 60, and the dielectric constant of aluminum oxide is about 9 to 10, which has good high-temperature resistance, oxidation resistance, and chemical stability. The dielectric constant of zirconium oxide is between 25 and 30, which has good insulation and thermal stability. Fluorinated silicate glass (FSG) is a silicate glass containing fluorine elements, and its dielectric constant is in the range of 3.6 to 3.8. Porous organic silicate glass (P-OSG) introduces pores into the organic silicate glass to further reduce the dielectric constant, and its dielectric constant is in the range of about 2.5 to 3.0. Fluorine-containing polyimide is a modified material of the polyimide family, which reduces the polarization between molecules by introducing fluorine elements, thereby reducing the dielectric constant. Its dielectric constant is between 3.0 and 3.5. Benzocyclobutene (BCB) is a high-performance polymer material with good electrical properties and thermal stability, and its dielectric constant is 2.5 to 2.6. It should be noted that in actual applications, the dielectric constant of these materials may vary due to various factors, including preparation process, material purity, temperature, frequency, and the presence of voids. For example, the dielectric constant of hafnium oxide varies in different phases (tetragonal and monoclinic), and the dielectric constant of hafnium oxide in the tetragonal phase is higher, which can reach more than 25, while the dielectric constant in the monoclinic phase is lower.
[0057] As Figure 1 and Figure 2As shown in the drawings, the MOS device satisfies at least one of the following conditions: the average thickness of the outer peripheral portion 3022 is 300-600 angstroms in the thickness direction of the substrate 10; and the average thickness of the intermediate portion 3021 is 400-6000 angstroms in the thickness direction of the substrate 10. The thickness of the outer peripheral portion 3022 and the thickness of the intermediate portion 3021 are respectively within the above ranges, which can prevent the MOS device from having a slow switching speed and a low driving capability due to a too thick first dielectric layer 302, and can also prevent the MOS device from having a low breakdown voltage and an unstable threshold voltage due to a too thin first dielectric layer 302.
[0058] In the implementation process, the thickness of the outer peripheral portion 3022 and the thickness of the intermediate portion 3021 can be uneven, so the thickness of the outer peripheral portion 3022 and the thickness of the intermediate portion 3021 can be measured at different positions and the average value is within the above ranges.
[0059] As shown in the drawings, Figure 1 and Figure 2 The MOS device further includes a second dielectric layer 60 located between the adjacent gate structure 30 and source structure 40 and on the side of the gate structure 30 away from the substrate 10; and an ohmic contact layer 70 located between the source structure 40 and the epitaxial layer 20.
[0060] In the embodiment, the second dielectric layer 60 can be used as an interlayer dielectric layer to isolate the gate structure 30 and the source structure 40. The material of the second dielectric layer 60 can be silicon oxide, and the thickness of the second dielectric layer 60 can be 600-1000 nm. The ohmic contact layer 70 can be formed of a metal material such as Ni or Ti.
[0061] The embodiment of the present application further provides a MOS device preparation method, and the method is used for preparing any one of the MOS devices, Figure 3 is a flowchart of the MOS device preparation method according to the embodiment of the present application. As shown in the drawings, Figure 3 The method includes the following steps.
[0062] In step S801, a substrate is provided, and a preliminary epitaxial layer is formed on one side of the substrate.
[0063] The material of the substrate can be silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, sapphire, or the like, and the resistivity of the substrate can be 0.02±20% Ωcm. The preliminary epitaxial layer can be a single-layer structure or a multi-layer structure. The preliminary epitaxial layer can be used as a drift layer to bear the main breakdown effect. The doping concentration of the preliminary epitaxial layer can be 1E+15-1E+16 cm -3The thickness of the preliminary epitaxial layer can be set according to the breakdown voltage of the MOS device, and the greater the voltage of the MOS device, the greater the thickness of the preliminary epitaxial layer.
[0064] In step S802, the JFET region is obtained by processing part of the preliminary epitaxial layer, and the remaining preliminary epitaxial layer forms the epitaxial layer.
[0065] The JFET region has the same doping type as the substrate, and the doping concentration can be 1E+18±50% cm -3 The thickness can be 0.8-0.9 μm. The JFET region is used to generate a lateral voltage drop when the drain current increases, to reverse bias the PN junction and increase the on-resistance of the MOS device.
[0066] In step S803, a gate oxide layer and a preliminary dielectric layer are formed in sequence on the side of the JFET region away from the substrate.
[0067] The thickness of the gate oxide layer is small, and can be 10-100 angstroms. The material of the gate oxide layer can be silicon oxide, which can be used to improve the interface state and thus improve the carrier mobility.
[0068] In step S804, part of the preliminary dielectric layer is removed to obtain at least one recess, and the remaining preliminary dielectric layer forms a peripheral portion and an intermediate portion in the recess, wherein the remaining preliminary dielectric layer is located on both sides of the removed preliminary dielectric layer, the dielectric constant of at least part of the intermediate portion is less than that of the peripheral portion, and the peripheral portion and the intermediate portion form a first dielectric layer.
[0069] In actual application, the peripheral portion can be located on the outer periphery in any direction perpendicular to the thickness of the substrate, or can be located on the outer periphery of the intermediate portion in the entire direction perpendicular to the thickness of the substrate.
[0070] In step S805, a gate layer is formed on the side of the first dielectric layer away from the gate oxide layer, the gate oxide layer, the first dielectric layer, and the gate layer form a gate structure, and the orthographic projection of the gate structure on the substrate and the orthographic projection of the JFET region on the substrate at least partially overlap.
[0071] The gate layer includes a polysilicon material layer and a gate electrode layer, and the gate electrode layer is located on the side of the polysilicon material layer away from the first dielectric layer.
[0072] In step S806, a source structure is formed on the side of the epitaxial layer away from the substrate.
[0073] The source structure can be an input end of current, and the material of the source structure can be an alloy of one or more of nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), and platinum (Pt).
[0074] Step S807, forming a drain structure on the side of the substrate away from the epitaxial layer.
[0075] Specifically, the drain structure can be an output end of current, and the material of the drain structure can be an alloy of one or more of nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), and platinum (Pt).
[0076] In order to enable those skilled in the art to more clearly understand the technical solutions of the present application, the implementation process of the preparation method of the MOS device of the present application will be described in detail below in combination with specific embodiments.
[0077] The present embodiment relates to a specific preparation method of a MOS device, wherein the structure obtained in each step is shown in FIG. 4, and the preparation method comprises the following steps:
[0078] Step S1: providing a substrate 10, and forming a preliminary epitaxial layer 206 on one side of the substrate 10 to obtain the structure shown in FIG. 4 (a);
[0079] Step S2: forming a second doped region 203 in the preliminary epitaxial layer 206 to obtain the structure shown in FIG. 4 (b); forming a first doped region 202 in the preliminary epitaxial layer 206 to obtain the structure shown in FIG. 4 (c); forming a third doped region 204 in the preliminary epitaxial layer 206 to obtain the structure shown in FIG. 4 (d); forming a JFET region 201 in the preliminary epitaxial layer 206, and the remaining preliminary epitaxial layer 206 forms an epitaxial layer 20 to obtain the structure shown in FIG. 4 (e);
[0080] Step S3: sequentially forming a gate oxide layer 301 and a preliminary dielectric layer 304 on the side of the JFET region 201 away from the substrate 10 to obtain the structure shown in FIG. 4 (f);
[0081] Step S4: removing part of the above-mentioned preliminary medium layer 304 to obtain at least one groove 305, and the remaining above-mentioned preliminary medium layer 304 forms an outer peripheral portion 3022 to obtain a structure as shown in Fig. 4(g), and an intermediate portion 3021 is formed in the above-mentioned groove 305, wherein the remaining above-mentioned preliminary medium layer 304 is located on both sides of the removed above-mentioned preliminary medium layer 304, the dielectric constant of at least part of the above-mentioned intermediate portion 3021 is less than the dielectric constant of the above-mentioned outer peripheral portion 3022, the above-mentioned outer peripheral portion 3022 and the above-mentioned intermediate portion 3021 form a first medium layer 302 to obtain a structure as shown in Fig. 4(h);
[0082] Step S5: forming a gate layer 303 on the side of the above-mentioned first medium layer 302 away from the above-mentioned gate oxide layer 301, the above-mentioned gate oxide layer 301, the above-mentioned first medium layer 302 and the above-mentioned gate layer 303 form a gate structure 30, the orthographic projection of the above-mentioned gate structure 30 on the above-mentioned substrate 10 and the orthographic projection of the above-mentioned JFET region 201 on the above-mentioned substrate 10 at least partially overlap to obtain a structure as shown in Fig. 4(i);
[0083] Step S6: forming a second medium layer 60 on the side of the above-mentioned gate structure 30 away from the substrate 10 to obtain a structure as shown in Fig. 4(j); forming an ohmic contact layer 70 on the side of the above-mentioned epitaxial layer 20 away from the above-mentioned substrate 10 to obtain a structure as shown in Fig. 4(k); forming a source structure 40 on the side of the above-mentioned epitaxial layer 20 away from the above-mentioned substrate 10 to obtain a structure as shown in Fig. 4(l); forming a drain structure 50 on the side of the above-mentioned substrate 10 away from the above-mentioned epitaxial layer 20 to obtain a structure as shown in Fig. 4(m). Figure 1
[0084] The technical features of the above-mentioned embodiments can be combined in any manner. In order to make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described, however, as long as the combinations of the technical features do not contradict, they should be considered within the scope of the present disclosure.
[0085] The above-mentioned only preferred embodiments of the present application, and not for limiting the present application, for those skilled in the art, the present application can have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application, should be included in the protection scope of the present application.
Claims
1. A MOS device, characterized by, The MOS device comprises: a substrate; an epitaxial layer on one side of the substrate; a JFET region in the epitaxial layer; a gate structure on the side of the JFET region away from the substrate, a projection of the gate structure on the substrate and a projection of the JFET region on the substrate at least partially overlap, the gate structure comprises a gate oxide layer, a first dielectric layer on the side of the gate oxide layer away from the epitaxial layer, and a gate layer on the side of the first dielectric layer away from the epitaxial layer, the first dielectric layer comprises a middle part and a peripheral part on the periphery of the middle part, and the dielectric constant of at least part of the middle part is less than that of the peripheral part; a source structure on the side of the epitaxial layer away from the substrate; a drain structure on the side of the substrate away from the epitaxial layer.
2. The MOS device of claim 1, wherein, The dielectric constant of each position of the middle part in the thickness direction perpendicular to the substrate is the same.
3. The MOS device of claim 1, wherein, The middle part comprises first dielectric regions and second dielectric regions arranged alternately in the thickness direction perpendicular to the substrate, and the second dielectric regions are in contact with the peripheral part, wherein the dielectric constant of the first dielectric regions is greater than that of the second dielectric regions, and the dielectric constant of the second dielectric regions is less than that of the peripheral part.
4. The MOS device of claim 3, wherein, In the thickness direction perpendicular to the substrate, the width of the first dielectric regions is a first width, and the width of the second dielectric regions is a second width, the first width and the second width are respectively 25-100 nm, and the ratio of the second width to the first width is 0.8:1-5:
1.
5. The MOS device of claim 1, wherein, In the thickness direction of the substrate, the average thickness of the middle part is greater than or equal to the average thickness of the peripheral part.
6. The MOS device of claim 1, wherein, The MOS device further comprises a first doped region, a second doped region and a third doped region in the epitaxial layer, a projection of the gate structure on the substrate and a projection of the first doped region on the substrate at least partially overlap, the first doped region is on the side of the second doped region and the third doped region close to the substrate, and in the direction perpendicular to the substrate, the first doped region is on the side of the third doped region away from the second doped region, and the third doped region has a spacing with the JFET region, wherein the doping type of the first doped region is the same as that of the second doped region, and the doping type of the first doped region is different from that of the third doped region.
7. The MOS device of claim 1, wherein, The material of the first dielectric layer satisfies at least one of the following conditions: The material of the peripheral part comprises at least one of hafnium oxide, silicon nitride, titanium dioxide, aluminum oxide and zirconium oxide; The material of the middle part comprises at least one of fluorosilicic acid glass, porous organosilicic acid glass, fluorine-containing polyimide and benzocyclobutene.
8. The MOS device of claim 1, wherein, The MOS device satisfies at least one of the following conditions: In the thickness direction of the substrate, the average thickness of the peripheral part is 300-600 angstroms; An average thickness of the intermediate portion is 400-6000 angstroms in a thickness direction of the substrate.
9. The MOS device of any of claims 1 to 8, wherein, The MOS device further comprises: a second dielectric layer between the adjacent gate structure and source structure and on a side of the gate structure away from the substrate; an ohmic contact layer between the source structure and the epitaxial layer.
10. A method of fabricating a MOS device, characterized by, The method is used for preparing the MOS device of any one of claims 1-9, and the method comprises: providing a substrate and forming a preliminary epitaxial layer on a side of the substrate; processing part of the preliminary epitaxial layer to obtain a JFET region, and the remaining preliminary epitaxial layer forms the epitaxial layer; forming a gate oxide layer and a preliminary dielectric layer on a side of the JFET region away from the substrate in sequence; removing part of the preliminary dielectric layer to obtain at least one recess, and the remaining preliminary dielectric layer forms an outer peripheral portion and an intermediate portion in the recess, wherein the remaining preliminary dielectric layer is located on both sides of the removed preliminary dielectric layer, a dielectric constant of at least part of the intermediate portion is less than a dielectric constant of the outer peripheral portion, and the outer peripheral portion and the intermediate portion form a first dielectric layer; forming a gate layer on a side of the first dielectric layer away from the gate oxide layer, the gate oxide layer, the first dielectric layer and the gate layer form a gate structure, and a normal projection of the gate structure on the substrate and a normal projection of the JFET region on the substrate at least partially overlap; forming a source structure on a side of the epitaxial layer away from the substrate; forming a drain structure on a side of the substrate away from the epitaxial layer.