A negative voltage surge resistant reverse connection preventing direct current filter assembly

Abstract

This application provides a DC filter component with negative voltage surge protection and reverse connection protection, relating to the field of electronic technology. It includes: a reverse connection protection circuit, a discharge circuit, a data acquisition and control circuit, and an input common-mode filter circuit. The reverse connection protection circuit includes a first NMOS transistor, whose drain is connected to the negative bus, its source is electrically connected to the first system ground, and its gate is electrically connected to the positive bus through a target resistor. The data acquisition and control circuit acquires the bus voltage and controls the first NMOS transistor to be turned off for a first preset time period when the bus voltage is less than or equal to a first preset voltage threshold. When the input power is lost, a group of capacitors is discharged through a first discharge resistor during the period when the bus voltage drops to a second preset voltage threshold, and a group of capacitors is discharged through a second discharge resistor during the period when the bus voltage drops from the second preset voltage threshold to a preset safe voltage value. Implementing the technical solution of this application improves the reliability of the DC filter component.

Description

Technical Field

[0001] This application relates to the field of electronic technology, specifically to a DC filter component that is resistant to negative voltage surges and reverse polarity. Background Technology

[0002] High-voltage DC power supply systems are increasingly widely used in harsh environments such as military and automotive applications, such as DC 270V, DC 540V, or other high-voltage DC systems. Their front-end DC filter components (or filter devices) must meet requirements for high reliability, low loss, and rapid safe discharge. However, the DC filter components in related technologies have significant shortcomings: First, regarding input reverse connection protection, conventional diode solutions introduce huge conduction losses and temperature rise. While reverse connection protection circuits based on MOSFETs have lower losses, their gate charge discharge is slow, failing to shut down in time during microsecond-level transient negative voltage surges, leading to reverse connection failure and endangering the safety of downstream equipment. Second, to meet military standards and other safety specifications, DC filter components must discharge the bus capacitor voltage to a safe voltage within a very short time after power failure. Related technologies typically use a fixed-value discharge resistor connected in parallel to the bus, which causes this resistor to continuously consume a large amount of power during normal operation, generating severe heat and reducing system efficiency and reliability. Therefore, the DC filter components in related technologies suffer from low reliability. Summary of the Invention

[0003] The purpose of this application is to overcome the above-mentioned technical problems. This application provides a DC filter component that is resistant to negative voltage surges and protected against reverse connection.

[0004] This application provides a DC filter component with negative voltage surge protection and reverse connection protection, including: a reverse connection protection circuit, a discharge circuit, a data acquisition and control circuit, and an input common-mode filter circuit. The reverse connection protection circuit includes a first NMOS transistor, wherein the drain of the first NMOS transistor is electrically connected to the negative bus, the source of the first NMOS transistor is electrically connected to the first system ground, and the gate of the first NMOS transistor is electrically connected to the positive bus through a target resistor. The first input terminal of the data acquisition and control circuit is electrically connected to the positive bus, the second input terminal of the data acquisition and control circuit is electrically connected to the first system ground, and the first output terminal of the data acquisition and control circuit is electrically connected to the gate of the first NMOS transistor. The data acquisition and control circuit is used to acquire the bus voltage and, when the bus voltage is low... When the voltage is equal to or equal to a first preset voltage threshold, the first NMOS transistor is controlled to be turned off for a first preset time period, wherein the first preset time period is less than 1µs, and the bus voltage represents the voltage between the positive bus and the first system ground. The first input terminal of the bleeder circuit is electrically connected to the positive bus, and the second input terminal of the bleeder circuit is electrically connected to the second system ground. The bleeder circuit includes a first bleeder resistor, a second bleeder resistor, and a second NMOS transistor. The first bleeder resistor is connected between the first output terminal and the second output terminal of the bleeder circuit. The first output terminal of the bleeder circuit is electrically connected to the positive bus, and the second output terminal of the bleeder circuit is electrically connected to the second system ground. The first end of the second bleeder resistor is connected to the first output terminal of the bleeder circuit. Electrically connected, the second terminal of the second bleeder resistor is electrically connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is electrically connected to the second system ground terminal; the third input terminal of the bleeder circuit is electrically connected to the second output terminal of the acquisition control circuit, which is also used to control the second NMOS transistor in the following manner: when the bus voltage is greater than or equal to the second preset voltage threshold, the gate of the second NMOS transistor is controlled to be at a low level; when the bus voltage is less than the second preset voltage threshold, the gate of the second NMOS transistor is controlled to be at a high level; wherein, when the input of the DC filter component is de-energized, during the period when the bus voltage drops to the second preset voltage threshold, a group of capacitors is discharged through the first bleeder resistor, and when the bus voltage drops from the second preset voltage threshold... During the period when the preset voltage threshold drops to the preset safe voltage value, a set of capacitors is discharged through the second bleeder resistor and the first bleeder resistor. The resistance of the first bleeder resistor is greater than that of the second bleeder resistor. The set of capacitors includes the energy storage capacitor and the filter capacitor in the back end of the DC filter component. The first input terminal and the second input terminal of the input common mode filter circuit are electrically connected to the positive terminal and the negative terminal of the input power supply, respectively. The first output terminal of the input common mode filter circuit is electrically connected to the positive bus, and the second output terminal of the input common mode filter circuit is electrically connected to the negative bus. The input common mode filter circuit is used to filter out common mode interference introduced by the external power grid and prevent back-end interference from being reverse coupled to the external power grid.

[0005] By adopting the above technical solutions, the reverse connection protection circuit uses a first NMOS transistor to reduce conduction losses and temperature rise. The acquisition and control circuit can control the first NMOS transistor to turn off within a first preset time of less than 1µs when the bus voltage is less than or equal to the first preset voltage threshold, ensuring the safety of downstream equipment. When the DC filter component input power is lost, the discharge circuit discharges the downstream energy storage capacitor and filter capacitor through a first discharge resistor with a larger resistance and a second discharge resistor with a smaller resistance, depending on the different stages of the bus voltage. This can meet the requirements of rapid discharge and reduce power consumption during normal operation. The input common-mode filter circuit can filter out common-mode interference introduced by the external power grid and prevent downstream interference from being reverse-coupled to the external power grid, thereby improving the reliability of the DC filter component.

[0006] Optionally, the DC filter component also includes a current surge suppression circuit. The first input terminal of the current surge suppression circuit is electrically connected to the positive bus, the second input terminal is electrically connected to the first system ground, the third input terminal is electrically connected to the second output terminal of the acquisition control circuit, and the output terminal is electrically connected to the second system ground. The current surge suppression circuit includes a third NMOS transistor and a pre-charge capacitor. The source of the third NMOS transistor serves as the second input terminal of the current surge suppression circuit, and the drain of the third NMOS transistor serves as the output terminal of the current surge suppression circuit. The acquisition control circuit is also used to control the third NMOS transistor in the following ways: during the power-on process of the DC filter component, when the bus voltage is greater than or equal to the second preset voltage threshold, the gate level of the third NMOS transistor is controlled by the pre-charge capacitor to achieve a soft start of the third NMOS transistor; during the power-off process of the DC filter component, when the bus voltage is less than the second preset voltage threshold, the second output terminal of the acquisition control circuit outputs a low level, and the pre-charge capacitor discharges through the second output terminal of the acquisition control circuit, so that the third NMOS transistor is turned off within a second preset time period, wherein the second preset time period is less than 1µs.

[0007] By adopting the above technical solution, a current surge suppression circuit is set in the DC filter component, including a third NMOS transistor and a pre-charge capacitor. During the power-on process of the DC filter component, when the bus voltage is greater than or equal to the second preset voltage threshold, the acquisition and control circuit controls the gate level of the third NMOS transistor through the pre-charge capacitor to achieve a soft start, which can avoid the impact of current surge on the bus voltage. During the power-off process of the DC filter component, when the bus voltage is less than the second preset voltage threshold, the second output terminal of the acquisition and control circuit outputs a low level, and the pre-charge capacitor discharges, causing the third NMOS transistor to be turned off within a second preset time of less than 1µs, ready to respond to the next power-on. Based on this circuit, even if there are short-term frequent power-on and power-off situations due to switching bounce or other reasons, this circuit can still achieve good current surge suppression function. At the same time, combined with the reverse connection protection circuit, the discharge circuit, the acquisition and control circuit, and the input common-mode filter circuit, the functions of input reverse connection protection, bus capacitor voltage discharge, bus voltage acquisition and control, and common-mode interference filtering can be realized, improving the reliability and stability of the DC filter component.

[0008] Optionally, the reverse connection protection circuit further includes: a first resistor, a first Zener diode, a first capacitor, and a first diode. The first resistor is connected between the gate and source of the first NMOS transistor. The anode and cathode of the first Zener diode are electrically connected to the source and gate of the first NMOS transistor, respectively. The first capacitor is connected in parallel with the first resistor. The target resistor includes a second resistor and a third resistor. The gate of the first NMOS transistor is electrically connected to the positive bus through the target resistor and the first diode. The second and third resistors are connected in series between the gate of the first NMOS transistor and the cathode of the first diode. The anode of the first diode is electrically connected to the positive bus. The first input terminal of the current surge suppression circuit is electrically connected to the positive bus through the first diode.

[0009] Optionally, the acquisition control circuit includes a linear auxiliary power supply circuit, a reference circuit, an acquisition circuit, and a comparator. The first and second input terminals of the linear auxiliary power supply circuit are electrically connected to the cathode of the first diode and the first system ground, respectively. The output terminal of the linear auxiliary power supply circuit is electrically connected to the power supply terminal of the comparator, providing operating power to the comparator. The first input terminal of the reference circuit is electrically connected to the output terminal of the linear auxiliary power supply circuit, and the second input terminal of the reference circuit is electrically connected to the first system ground. The first and second input terminals of the acquisition circuit are electrically connected to the cathode of the first diode and the first system ground, respectively. The output terminal of the acquisition circuit is electrically connected to the first non-inverting input terminal of the comparator, and the output terminal of the reference circuit is electrically connected to the first inverting input terminal of the comparator. The first output terminal of the comparator is electrically connected to the gate of the first NMOS transistor, serving as the first output terminal of the acquisition control circuit. The acquisition circuit acquires the bus voltage. When the bus voltage is less than or equal to a first preset voltage threshold, the first output terminal of the comparator outputs a low level, causing the first NMOS transistor to be turned off for a first preset duration.

[0010] Optionally, the linear auxiliary power supply circuit includes a fourth resistor, a second Zener diode, a second capacitor, a third capacitor, a first transistor, and a second diode. The collector of the first transistor is electrically connected to the cathode of the first diode, and the emitter of the first transistor is electrically connected to the anode of the second diode. The cathode of the second diode is electrically connected to the ground of the first system through the second capacitor. The third capacitor is connected between the base of the first transistor and the ground of the first system. The cathode of the second Zener diode is electrically connected to the base of the first transistor, and the anode of the second Zener diode is electrically connected to the ground of the first system. The fourth resistor is connected between the base and collector of the first transistor. The cathode of the second diode serves as the output terminal of the linear auxiliary power supply circuit. The reference circuit includes a fifth resistor and a first reference voltage source, wherein the fifth resistor is connected to the cathode of the second diode. The first reference voltage source is electrically connected to the negative terminal of the first reference voltage source, and the positive terminal of the first reference voltage source is electrically connected to the ground terminal of the first system. The negative terminal of the first reference voltage source is electrically connected to the reference terminal of the first reference voltage source, and the negative terminal of the first reference voltage source serves as the output terminal of the reference circuit. The acquisition circuit includes a sixth resistor, a seventh resistor, and an eighth resistor, wherein the sixth resistor, the seventh resistor, and the eighth resistor are connected in series between the negative terminal of the first diode and the ground terminal of the first system. The connection between the seventh resistor and the eighth resistor serves as the output terminal of the acquisition circuit. The acquisition control circuit also includes a ninth resistor, a fourth capacitor, and a third diode, wherein the positive terminal of the third diode is electrically connected to the first non-inverting input terminal of the comparator, the negative terminal of the third diode is electrically connected to the first output terminal of the comparator through the ninth resistor, and the fourth capacitor is connected between the power supply terminal of the comparator and the ground terminal of the first system.

[0011] Optionally, the acquisition control circuit further includes a tenth resistor, an eleventh resistor, a twelfth resistor, and a fourth diode. The second non-inverting input of the comparator is electrically connected to the output of the acquisition circuit; the second inverting input of the comparator is electrically connected to the output of the reference circuit through the tenth resistor; the eleventh resistor is connected between the second inverting input of the comparator and the first system ground; the anode of the fourth diode is electrically connected to the second non-inverting input of the comparator; and the cathode of the fourth diode is electrically connected to the second output of the comparator through the twelfth resistor. The second output of the comparator serves as the second output of the acquisition control circuit. The current surge suppression circuit further includes a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, and a seventeenth resistor. The circuit includes a resistor, a third Zener diode, and a fourth Zener diode. A pre-charge capacitor is connected between the second output terminal of the comparator and the first system ground. The thirteenth and fourteenth resistors are connected in series between the cathode of the first diode and the second output terminal of the comparator. The cathode of the third Zener diode is electrically connected to the second output terminal of the comparator. The anode of the third Zener diode is electrically connected to the gate of the third NMOS transistor through the fifteenth resistor. The cathode of the fourth Zener diode is electrically connected to the anode of the third Zener diode. The anode of the fourth Zener diode is electrically connected to the first system ground. The sixteenth resistor is connected in parallel with the fourth Zener diode. The seventeenth resistor is connected between the drain and source of the third NMOS transistor.

[0012] Optionally, the bleeder circuit further includes an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a fifth Zener diode, a sixth Zener diode, a seventh Zener diode, and a first optocoupler. The eighteenth and nineteenth resistors are connected in series between the positive bus and the gate of the second NMOS transistor. The twentieth resistor is connected between the gate of the second NMOS transistor and the second system ground. The anode of the fifth Zener diode is electrically connected to the second system ground, and the cathode of the fifth Zener diode is electrically connected to the gate of the second NMOS transistor. The twenty-first resistor is connected between the second output terminal of the acquisition control circuit and the cathode of the sixth Zener diode. The input terminal of the first optocoupler is connected between the anode of the sixth Zener diode and the first system ground, and the output terminal of the first optocoupler is connected between the gate of the second NMOS transistor and the second system ground. The twenty-second and twenty-third resistors are connected in series between the positive bus and the second output terminal of the acquisition control circuit. The cathode of the seventh Zener diode is electrically connected to the second output terminal of the acquisition control circuit, and the anode of the seventh Zener diode is electrically connected to the first system ground.

[0013] Optionally, the input common-mode filter circuit includes a ferrite common-mode inductor. The first input terminal of the ferrite common-mode inductor is electrically connected to the positive terminal of the input power supply, the first output terminal of the ferrite common-mode inductor is electrically connected to the positive bus, the second input terminal of the ferrite common-mode inductor is electrically connected to the negative terminal of the input power supply, and the second output terminal of the ferrite common-mode inductor is electrically connected to the negative bus.

[0014] Optionally, the DC filter component further includes: an output filter circuit, which includes a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, and a microcrystalline inductor. The fifth capacitor is connected between the positive bus and the ground terminal; the sixth capacitor is connected between the second system ground terminal and the ground terminal; the first input terminal of the microcrystalline inductor is electrically connected to the positive bus; the second input terminal of the microcrystalline inductor is electrically connected to the second system ground terminal; the seventh capacitor is connected between the first output terminal of the microcrystalline inductor and the ground terminal; the eighth capacitor is connected between the second output terminal of the microcrystalline inductor and the ground terminal; the ninth and tenth capacitors are both connected in parallel between the first and second output terminals of the microcrystalline inductor; and the eleventh capacitor is connected between the positive bus and the second system ground terminal. The first output terminal of the microcrystalline inductor serves as the positive output terminal of the DC filter component, and the second output terminal of the microcrystalline inductor serves as the negative output terminal of the DC filter component. The set of capacitors includes the fifth, sixth, seventh, eighth, ninth, tenth, and eleventh capacitors.

[0015] Optionally, the reverse connection protection circuit also includes a fourth NMOS transistor, wherein the gate, drain, and source of the fourth NMOS transistor are electrically connected to the gate, drain, and source of the first NMOS transistor, respectively.

[0016] Optionally, the current surge suppression circuit also includes a fifth NMOS transistor and a twenty-fourth resistor, wherein the gate of the fifth NMOS transistor is electrically connected to the positive terminal of the third Zener diode through the twenty-fourth resistor, and the drain and source of the fifth NMOS transistor are electrically connected to the drain and source of the third NMOS transistor, respectively.

[0017] In summary, one or more technical solutions provided in this application have at least the following technical effects or advantages:

[0018] 1. The reverse connection protection circuit uses a first NMOS transistor to reduce conduction losses and temperature rise. The acquisition and control circuit can control the first NMOS transistor to turn off within a first preset time of less than 1µs when the bus voltage is less than or equal to the first preset voltage threshold, ensuring the safety of downstream equipment. When the DC filter component input power is lost, the discharge circuit discharges the downstream energy storage capacitor and filter capacitor through a first discharge resistor with a larger resistance and a second discharge resistor with a smaller resistance, depending on the different stages of the bus voltage. This can meet the requirements of rapid discharge and reduce power consumption during normal operation. The input common-mode filter circuit can filter out common-mode interference introduced by the external power grid and prevent downstream interference from being reverse-coupled to the external power grid, thereby improving the reliability of the DC filter component.

[0019] 2. During the power-on process of the DC filter component, when the bus voltage is greater than or equal to the second preset voltage threshold, the acquisition control circuit controls the gate level of the third NMOS transistor through the pre-charge capacitor to achieve a soft start, which can avoid the impact of current surge on the bus voltage. During the power-off process of the DC filter component, when the bus voltage is less than the second preset voltage threshold, the second output terminal of the acquisition control circuit outputs a low level, and the pre-charge capacitor discharges to turn off the third NMOS transistor within a second preset time of less than 1µs, ready to respond to the next power-on. Based on this circuit, even if there are short-term frequent power-on and power-off situations due to switching bounce or other reasons, this circuit can still achieve good current surge suppression function. Attached Figure Description

[0020] Figure 1 This is a frame diagram of a DC filter component that is resistant to negative voltage surges and protected against reverse polarity, as provided in this application.

[0021] Figure 2 This is a framework diagram of another DC filter component with negative voltage surge protection and reverse polarity protection provided in this application;

[0022] Figure 3 This is a schematic diagram of the circuit principle of a DC filter component that is resistant to negative voltage surges and protected against reverse polarity, provided in this application.

[0023] Figure 4 This is a schematic diagram of the acquisition control circuit and the reverse connection protection fast shutdown circuit provided in this application;

[0024] Figure 5 This is a schematic diagram of the low-loss fast discharge circuit provided in this application;

[0025] Figure 6 This is a schematic diagram of the current surge suppression circuit provided in this application.

[0026] Explanation of reference numerals in the attached diagram: R1 - First resistor, R2 - Second resistor, R3 - Third resistor, R4 - Fourth resistor, R5 - Fifth resistor, R6 - Sixth resistor, R7 - Seventh resistor, R8 - Eighth resistor, R9 - Ninth resistor, R10 - Tenth resistor, R11 - Eleventh resistor, R12 - Twelfth resistor, R13 - Thirteenth resistor, R14 - Fourteenth resistor, R15 - Fifteenth resistor, R16 - Sixteenth resistor, R17 - Seventeenth resistor, R18 - Eighteenth resistor, R19 - Nineteenth resistor, R20 - Twentieth resistor, R21 - Twenty-first resistor, R22 - Twenty-second resistor, R23 - Twenty-third resistor, R24 - Twenty-fourth resistor, U1 - Comparator, Q1 - First NMOS transistor, Q2 - Second NMOS transistor, Q3 - Third NMOS transistor, Q4 - Fourth NMOS transistor, Q5 - Fifth NMOS transistor The following capacitors are listed: C1-first capacitor, C2-second capacitor, C3-third capacitor, C4-fourth capacitor, C5-fifth capacitor, C6-sixth capacitor, C7-seventh capacitor, C8-eighth capacitor, C9-ninth capacitor, C10-tenth capacitor, C11-eleventh capacitor, D1-first diode, D2-second diode, D3-third diode, D4-fourth diode, T1-first transistor, RS1-first reference voltage source, RD1-first bleeder resistor, RD2-second bleeder resistor, CP-precharge capacitor, L1-ferrite common mode inductor, L2-microcrystalline inductor, ZD1-first Zener diode, ZD2-second Zener diode, ZD3-third Zener diode, ZD4-fourth Zener diode, ZD5-fifth Zener diode, ZD6-sixth Zener diode, ZD7-seventh Zener diode, PD1-first optocoupler. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0028] In the description of the embodiments of this application, the words "for example" or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design that is described as "for example" or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Rather, the use of the words "for example" or "for instance" is intended to present the relevant concepts in a specific manner.

[0029] In the description of the embodiments of this application, the term "multiple" means two or more. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0030] In military and automotive products, the application of high-voltage DC power supplies is increasingly common, and these products typically need to meet several power supply and load characteristic standards. Common standards and specifications include GJB181B-2012 "Aircraft Power Supply Characteristics" (section 5.4.6, Polarity or Reverse Phase Sequence), HB20326.7-2016 "Power Supply Characteristic Standards" (HDC101, Load Characteristics, i.e., Start-up Inrush Current), HDC106 Power Line Spike Conductivity Test; and GJB151B-2013 "Electromagnetic Emissions and Sensitivity Requirements and Measurements for Military Equipment and Subsystems" (section 5.13, CS106 Power Line Spike Conductivity Test, etc.). Figure 1 Standards and specifications such as these require DC power supply equipment to have input reverse connection protection and to handle input negative voltage surges during operation (e.g., lightning standard DO-160 and power line spike signal conduction sensitivity CS106 both have requirements for negative voltage surge adaptability); GJB367A-2001 "General Specifications for Military Communication Equipment" requires in section 3.13.4.2 that high-voltage circuits, especially those with large-capacity capacitors, should have automatic discharge circuits, and when the high voltage is cut off, it should discharge to below 24V effective value within 2 seconds); high-voltage DC filter power supply products for military products need to meet the following requirements: 1) low-loss and high-reliability input reverse connection protection; 2) rapid discharge function of the back-end filter X capacitor and energy storage capacitor when the input power is lost; 3) load characteristics (i.e., start-up current surge suppression, which can meet the specified start-up current surge suppression standard under repeated power-on and power-off and frequent grid voltage fluctuations). However, the DC filtering components in related technologies have many shortcomings. For example, for DC input reverse connection protection, diodes are usually used, which are only suitable for low-voltage, low-current products. In high-voltage, high-current products, the voltage drop across the diodes is large, resulting in significant power loss and temperature rise. Alternatively, conventional MOSFETs can be used for reverse connection protection, but transient negative voltages during operation cannot be switched off in time. In addition, in existing technologies, the conventional design for DC high-voltage input power failure is to connect a resistor in parallel on the bus. When the input power fails, this parallel resistor is used for back-end filtering and discharge of the energy storage capacitor. However, due to the limitation of discharge time, the value of the discharge resistor cannot be too large (especially when the capacity of the back-end energy storage capacitor is large, the value of the discharge resistor needs to be even smaller). This means that the discharge resistor needs to work continuously during normal operation of the equipment, which introduces significant power loss and heat generation.

[0031] The following is in conjunction with the appendix Figure 1 - Appendix Figure 6 The embodiments of this application will be described in detail.

[0032] This application provides a DC filter component that is resistant to negative voltage surges and protected against reverse polarity, referring to... Figure 1 , Figure 1This is a framework diagram of a DC filter assembly for reverse polarity protection and withstands negative voltage surges, as provided in this application. The DC filter assembly includes: a reverse polarity protection circuit, a discharge circuit, a data acquisition and control circuit, and an input common-mode filter circuit. The reverse polarity protection circuit includes a first NMOS transistor Q1, wherein the drain of the first NMOS transistor Q1 is electrically connected to the negative bus, the source of the first NMOS transistor Q1 is electrically connected to the first system ground, and the gate of the first NMOS transistor Q1 is electrically connected to the positive bus through a target resistor. The first input terminal of the data acquisition and control circuit is electrically connected to the positive bus, the second input terminal of the data acquisition and control circuit is electrically connected to the first system ground, and the first output terminal of the data acquisition and control circuit is electrically connected to the gate of the first NMOS transistor Q1. The data acquisition and control circuit is used to acquire the bus voltage and, when… When the bus voltage is less than or equal to a first preset voltage threshold, the first NMOS transistor Q1 is turned off for a first preset duration, where the first preset duration is less than 1µs. The bus voltage represents the voltage between the positive bus and the first system ground. The first input terminal of the bleeder circuit is electrically connected to the positive bus, and the second input terminal of the bleeder circuit is electrically connected to the second system ground. The bleeder circuit includes a first bleeder resistor RD1, a second bleeder resistor RD2, and a second NMOS transistor Q2. The first bleeder resistor RD1 is connected between the first output terminal and the second output terminal of the bleeder circuit. The first output terminal of the bleeder circuit is electrically connected to the positive bus, and the second output terminal of the bleeder circuit is electrically connected to the second system ground. The first terminal of the second bleeder resistor RD2 is connected to the positive bus. The first output terminal is electrically connected, the second terminal of the second bleeder resistor RD2 is electrically connected to the drain of the second NMOS transistor Q2, and the source of the second NMOS transistor Q2 is electrically connected to the second system ground terminal; the third input terminal of the bleeder circuit is electrically connected to the second output terminal of the acquisition control circuit, which is also used to control the second NMOS transistor Q2 in the following manner: when the bus voltage is greater than or equal to the second preset voltage threshold, the gate of the second NMOS transistor Q2 is controlled to be at a low level; when the bus voltage is less than the second preset voltage threshold, the gate of the second NMOS transistor Q2 is controlled to be at a high level; wherein, when the input of the DC filter component is de-energized, during the period when the bus voltage drops to the second preset voltage threshold, a group of capacitors are discharged through the first bleeder resistor RD1. During the period when the line voltage drops from the second preset voltage threshold to the preset safe voltage value, a set of capacitors is discharged through the second bleeder resistor RD2 and the first bleeder resistor RD1, wherein the resistance of the first bleeder resistor RD1 is greater than the resistance of the second bleeder resistor RD2. The set of capacitors includes the energy storage capacitor and the filter capacitor in the back end of the DC filter component. The first input terminal and the second input terminal of the input common mode filter circuit are electrically connected to the positive terminal and the negative terminal of the input power supply, respectively. The first output terminal of the input common mode filter circuit is electrically connected to the positive bus, and the second output terminal of the input common mode filter circuit is electrically connected to the negative bus. The input common mode filter circuit is used to filter out common mode interference introduced by the external power grid and prevent back-end interference from being reverse coupled to the external power grid.

[0033] In the above embodiments, the reverse connection protection circuit uses a first NMOS transistor Q1 to reduce conduction losses and temperature rise. The acquisition and control circuit can control the first NMOS transistor Q1 to turn off within a first preset time of less than 1µs when the bus voltage is less than or equal to a first preset voltage threshold, ensuring the safety of downstream equipment. When the DC filter component input power is lost, the discharge circuit discharges the downstream energy storage capacitor and filter capacitor through a first discharge resistor RD1 with a larger resistance and a second discharge resistor RD2 with a smaller resistance, according to different stages of the bus voltage. This can meet the requirements of rapid discharge and reduce power consumption during normal operation. The input common-mode filter circuit can filter out common-mode interference introduced by the external power grid and prevent downstream interference from being reverse-coupled to the external power grid, thereby improving the reliability of the DC filter component.

[0034] This embodiment uses a low-on-resistance first NMOS transistor Q1 (silicon carbide NMOS transistor) as a reverse connection protection switch, connected in series in the negative (ground) circuit of the power supply. During normal power supply, the acquisition and control circuit applies a high voltage from the positive bus to the gate of the NMOS transistor through a target resistor, ensuring reliable conduction and forming a circuit. Unlike existing technologies that rely on the transistor's own characteristics for turn-off, this embodiment introduces an acquisition and control circuit to monitor the bus voltage in real time. When an input negative voltage surge occurs during operation, manifested as a sharp drop in bus voltage or a negative value, this embodiment detects the bus voltage. When it is less than or equal to a first preset voltage threshold, the acquisition and control circuit actively pulls down the gate voltage of the first NMOS transistor Q1, forcing it to turn off within a very short time (less than 1 microsecond), solving the problem in existing technologies where slow gate charge discharge makes it unable to handle transient negative voltages. For example, the normal operating bus voltage is 400-540V (or other voltage values), and the aforementioned first preset voltage threshold is 400V (or 350V, or other values). When the system loses power (such as when the power supply to the DC filter component fails), the energy storage capacitor on the bus needs to quickly discharge the high voltage to ensure safety. In this embodiment, the discharge route consists of two parallel paths: one is a large-value first discharge resistor RD1 that is always connected in parallel to the bus, and the other is a small-value second discharge resistor RD2 connected in series with an NMOS switch (second NMOS transistor Q2) and then connected in parallel to the bus. The acquisition and control circuit also monitors the bus voltage and controls the discharge process accordingly: During normal operation (bus voltage ≥ second preset voltage threshold), the acquisition and control circuit turns off the second NMOS transistor Q2. At this time, only the large-value first discharge resistor RD1 consumes a small amount of power, which greatly reduces the energy loss and heat generation during normal operation and solves the problem of high power consumption of fixed discharge resistors in the prior art. When power is lost during discharge (bus voltage < second preset voltage threshold), the acquisition and control circuit detects the drop in bus voltage and immediately turns on the second NMOS transistor Q2, connecting the small-value second discharge resistor RD2 to the circuit.For example, during normal operation, the bus voltage is 540V (or other voltage value), and the second preset voltage threshold is 400V (or other voltage value, which should generally not exceed the first preset voltage threshold, such as 380V). In the first stage of power failure, when the bus voltage is greater than the second preset voltage threshold, the voltage is first discharged based on the first bleeder resistor RD1 (which can be called the slow bleeder resistor), discharging the voltage from 540V to 400V, with a discharge time of approximately 1.8s-1.9s. In the second stage of power failure, when the bus voltage is less than 400V, the second NMOS transistor Q2 is turned on, and the second bleeder resistor RD2 (which can be called the fast bleeder resistor) is connected in parallel to the circuit, discharging rapidly together with the first bleeder resistor RD1. In fact, the discharge is carried out through the first bleeder resistor RD1 and the second bleeder resistor RD2 together, but mainly relies on the second bleeder resistor RD2. The discharge from 400V to the preset safe voltage value (such as 24V, or other values) can be completed in approximately tens of milliseconds. In this embodiment, the acquisition and control circuit is the "brain" of the entire system. By acquiring the same bus voltage signal, it realizes intelligent and coordinated control of the reverse connection protection circuit and the discharge circuit. The input common-mode filter circuit, as a standard front-end protection part, is responsible for filtering out power grid noise and ensuring electromagnetic compatibility. It is an integral part of the complete function of the device.

[0035] In an optional embodiment, such as Figure 2 As shown, the DC filter component also includes a current surge suppression circuit. The first input terminal of the current surge suppression circuit is electrically connected to the positive bus, the second input terminal is electrically connected to the first system ground, the third input terminal is electrically connected to the second output terminal of the acquisition control circuit, and the output terminal is electrically connected to the second system ground. The current surge suppression circuit includes a third NMOS transistor Q3 and a pre-charge capacitor CP. The source of the third NMOS transistor Q3 serves as the second input terminal of the current surge suppression circuit, and the drain of the third NMOS transistor Q3 serves as the output terminal of the current surge suppression circuit. The acquisition control circuit is also used to control the third NMOS transistor Q3 in the following ways: during the power-on process of the DC filter component, when the bus voltage is greater than or equal to the second preset voltage threshold, the gate level of the third NMOS transistor Q3 is controlled by the pre-charge capacitor CP to achieve a soft start of the third NMOS transistor Q3; during the power-off process of the DC filter component, when the bus voltage is less than the second preset voltage threshold, the second output terminal of the acquisition control circuit outputs a low level, and the pre-charge capacitor CP discharges through the second output terminal of the acquisition control circuit, so that the third NMOS transistor Q3 is turned off within a second preset time period, wherein the second preset time period is less than 1µs.

[0036] In the above embodiments, a current surge suppression circuit is set in the DC filter component, including a third NMOS transistor Q3 and a pre-charge capacitor CP. During the power-on process of the DC filter component, when the bus voltage is greater than or equal to a second preset voltage threshold, the acquisition control circuit controls the gate level of the third NMOS transistor Q3 through the pre-charge capacitor CP to achieve a soft start, which can avoid the impact of current surge on the bus voltage. During the power-off process of the DC filter component, when the bus voltage is less than the second preset voltage threshold, the second output terminal of the acquisition control circuit outputs a low level, and the pre-charge capacitor CP discharges, causing the third NMOS transistor Q3 to be turned off within a second preset time of less than 1µs, ready to respond to the next power-on. Based on this circuit, even if there are short-term frequent power-on and power-off situations due to switching jitter or other reasons, this circuit can still achieve good current surge suppression function. At the same time, combined with the reverse connection protection circuit, the discharge circuit, the acquisition control circuit and the input common-mode filter circuit, the functions of input reverse connection protection, bus capacitor voltage discharge, bus voltage acquisition control and common-mode interference filtering can be realized, improving the reliability and stability of the DC filter component.

[0037] The current surge suppression circuit includes a third NMOS transistor Q3 and a pre-charge capacitor CP. Its input terminal is connected to the positive bus and the first system ground terminal (corresponding to...). Figure 3 Connect GND2 and the acquisition control circuit, and connect the output terminal to the second system ground terminal (corresponding to GND2). Figure 3During power-on, when the bus voltage is greater than or equal to the second preset voltage threshold, the acquisition control circuit controls the gate level of the third NMOS transistor Q3 through the pre-charge capacitor to achieve the soft start of the third NMOS transistor Q3, thereby suppressing the current surge at the moment of power-on. In this way, the conduction degree of the third NMOS transistor Q3 can be gradually increased when the DC filter component is powered on, avoiding excessive current surge due to instantaneous conduction. During power-off (or power-down) process, when the bus voltage is lower than the second preset voltage threshold, the acquisition control circuit outputs a low level, and the pre-charge capacitor CP discharges quickly through this output terminal, so that the third NMOS transistor Q3 is turned off in less than 1 microsecond, so as to suppress the surge of the next power-on at any time. In existing technologies, DC filter components may experience significant current surges upon power-on due to the presence of energy storage or filter capacitors. This can impact the power supply system and the DC filter component itself, affecting system stability and reliability. While some existing products incorporate surge suppression, these surges are vulnerable to multiple power-on / off cycles due to human error or mechanical switch contact bounce. In such cases, the MOSFET may not be able to turn off quickly enough, leading to a loss of surge suppression capability during subsequent power-on cycles. This embodiment addresses this by using a pre-charge capacitor CP to control the gate level of the third NMOS transistor Q3 during power-on, achieving a soft start and effectively suppressing the current surge upon power-on. Furthermore, during power-off, the second output of the acquisition and control circuit is set to a low level, discharging the pre-charge capacitor CP and quickly turning off the third NMOS transistor Q3 to prepare for the next power-on. By incorporating a surge suppression circuit, this embodiment ensures the filter circuit maintains its surge suppression function even with frequent power-on / off cycles, reducing the impact of current surges on the system and improving overall system performance.

[0038] To make it easier to understand, firstly... Figure 3 The critical potential in the middle is explained. Figure 3 GND1 corresponds to the negative terminal of the aforementioned input power supply, and GND2 and GND3 correspond to the ground terminals of the first and second systems, respectively. The ground terminal of the first system can also be referred to as the negative bus 2 (e.g., Figure 3 (VC in the middle), the second system ground terminal can be called negative bus 3, the aforementioned negative bus (such as Figure 3 In this context, VB) is equivalent to negative busbar 1. Figure 3 VA is the positive busbar. Figure 3 GND4 corresponds to the negative output terminal of the aforementioned DC filter component. Figure 3 The EARTH in the text (corresponding to the aforementioned grounding terminal) is the grounding point of the device's outer casing.

[0039] In an optional embodiment, such as Figure 3As shown, the reverse connection protection circuit further includes: a first resistor R1, a first Zener diode ZD1, a first capacitor C1, and a first diode D1. The first resistor R1 is connected between the gate and source of the first NMOS transistor Q1. The anode and cathode of the first Zener diode ZD1 are electrically connected to the source and gate of the first NMOS transistor Q1, respectively. The first capacitor C1 is connected in parallel with the first resistor R1. The target resistor includes a second resistor R2 and a third resistor R3. The gate of the first NMOS transistor Q1 is electrically connected to the positive bus via the target resistor and the first diode D1. The second resistor R2 and the third resistor R3 are connected in series between the gate of the first NMOS transistor Q1 and the cathode of the first diode D1. The anode of the first diode D1 is electrically connected to the positive bus. The first input terminal of the current surge suppression circuit is electrically connected to the positive bus via the first diode D1.

[0040] In the above embodiment, the first resistor R1 and the first capacitor C1 can filter and buffer the gate voltage of the first NMOS transistor Q1 to stabilize the gate voltage; the first Zener diode ZD1 can prevent the gate voltage of the first NMOS transistor Q1 from being too high and damaged; the first diode D1 can further ensure that the power supply of the acquisition and control system is not affected by reverse voltage under negative surge voltage conditions, ensuring circuit safety; the second resistor R2 and the third resistor R3 can divide the voltage to provide a suitable bias voltage for the gate of the first NMOS transistor Q1; the current surge suppression circuit is connected to the positive bus through the first diode D1, which can further ensure the normal operation of the reverse connection protection circuit and the current surge suppression circuit, and improve the reliability and stability of the DC filter component.

[0041] The first resistor R1 is connected between the gate and source of the first NMOS transistor Q1, stabilizing the gate-source voltage and providing a path for gate charge discharge. The first Zener diode ZD1 has its anode connected to the source of the first NMOS transistor Q1 and its cathode connected to the gate, limiting the maximum gate-source voltage and preventing overvoltage damage to the first NMOS transistor Q1. The first capacitor C1 is connected in parallel with the first resistor R1, slowing down the rate of gate voltage change and enhancing circuit stability. The target resistor is composed of the second resistor R2 and the third resistor R3 connected in series, working with the first diode D1 to connect the positive bus to the gate of the first NMOS transistor Q1. This serves both current limiting protection, preventing excessive current from damaging the gate, and voltage division to keep the gate voltage within a suitable range. The unidirectional conductivity of the diode also prevents reverse voltage from affecting gate control. When the bus voltage is normal, the acquisition and control circuit controls the first NMOS transistor Q1 to conduct, allowing current to flow normally through the loop containing the first NMOS transistor Q1. When the bus voltage is less than or equal to the first preset voltage threshold, the acquisition and control circuit will control the first NMOS transistor Q1 to turn off within 1μs to block the reverse current. When an input reverse connection abnormality occurs, other components will ensure the stable operation of the first NMOS transistor Q1 and the reliable implementation of the reverse connection protection function from different aspects. This embodiment stabilizes the gate voltage of the first NMOS transistor Q1, limits the gate current, and prevents the influence of reverse current, so that the first NMOS transistor Q1 can work more stably and reliably. In terms of input reverse connection protection, the first NMOS transistor Q1 in this embodiment is on the negative line terminal, and the reverse connection protection at the moment of power-on is automatically realized based on the built-in diode of the first NMOS transistor Q1. In terms of negative voltage surge protection, it can respond more accurately to changes in bus voltage. When the input voltage (or bus voltage) drops to a predetermined value, the first NMOS transistor Q1 is turned off in advance. That is, before the negative voltage surge occurs, the first NMOS transistor Q1 is turned off in a timely and reliable manner to block the reverse current, effectively protect the safety of downstream equipment, and improve the reliability of the reverse connection protection function of the entire DC filter component.

[0042] In an optional embodiment, the acquisition control circuit includes a linear auxiliary power supply circuit, a reference circuit, an acquisition circuit, and a comparator. The first input terminal and the second input terminal of the linear auxiliary power supply circuit are electrically connected to the cathode of the first diode D1 and the first system ground terminal, respectively. The output terminal of the linear auxiliary power supply circuit is electrically connected to the power supply terminal of the comparator U1. The linear auxiliary power supply circuit is used to provide operating power to the comparator U1 (e.g., ...). Figure 3The reference circuit's first input terminal is electrically connected to the output terminal of the linear auxiliary source circuit, and the reference circuit's second input terminal is electrically connected to the first system ground terminal. The first and second input terminals of the acquisition circuit are electrically connected to the cathode of the first diode D1 and the first system ground terminal, respectively. The acquisition circuit's output terminal is electrically connected to the first non-inverting input terminal of comparator U1, and the reference circuit's output terminal is electrically connected to the first inverting input terminal of comparator U1. The first output terminal of comparator U1 is electrically connected to the gate of the first NMOS transistor Q1, and the first output terminal of comparator U1 serves as the first output terminal of the acquisition control circuit. The acquisition circuit is used to acquire the bus voltage. When the bus voltage is less than or equal to the first preset voltage threshold, the first output terminal of comparator U1 outputs a low level, so that the first NMOS transistor Q1 is turned off within the first preset time period.

[0043] In the above embodiment, the linear auxiliary power supply circuit provides operating power to comparator U1, ensuring that comparator U1 operates normally; the acquisition circuit acquires the bus voltage and compares it with the reference voltage output by the reference circuit in comparator U1. When the bus voltage is less than or equal to the first preset voltage threshold, comparator U1 outputs a low level, which can turn off the first NMOS transistor Q1 within the first preset time period, achieving fast response and avoiding the failure of the reverse connection protection function when a microsecond-level transient negative voltage surge occurs, thereby improving the reliability of the DC filter component.

[0044] The linear auxiliary power supply circuit draws power from the cathode of the first diode D1 and converts it into a stable, lower-voltage DC power supply specifically for powering comparator U1 and the reference circuit. The acquisition circuit (typically a resistor divider network) samples the bus voltage in real time and scales it down to a low-voltage sampled signal proportional to the bus voltage, suitable for processing by comparator U1 (e.g., ...). Figure 3The voltage (VTEST) is sent to the non-inverting input (e.g., the first non-inverting input) of comparator U1; the reference circuit (usually a precision reference source, such as a TL431 or Bandgap reference) generates a highly stable and accurate voltage value (VREF), which corresponds to the first preset voltage threshold that triggers shutdown. This reference voltage is then sent to the inverting input of comparator U1. Under normal conditions (positive connection, normal voltage): When the bus voltage is normal, VTEST > VREF. At this time, comparator U1 outputs a high level, keeping the first NMOS transistor Q1 on. Under abnormal conditions (undervoltage (including negative voltage surge, undervoltage will occur before the negative voltage surge)): When a momentary negative voltage surge occurs, the bus voltage drops sharply. Once VTEST ≤ VREF from the acquisition circuit output, the output state of comparator U1 will instantly flip, outputting a low level. This low level acts directly on the gate of the first NMOS transistor Q1 through the first output terminal of the acquisition control circuit, thereby forcibly turning off the first NMOS transistor Q1 for a first preset time (less than 1µs), thus blocking reverse current and realizing the negative voltage surge anti-reverse connection function during operation. At the same time, the linear auxiliary power supply circuit provides a stable operating power supply for comparator U1, ensuring the stable operation of the entire acquisition control circuit. This embodiment, through precise voltage comparison and timely control signal output, can quickly and accurately control the first NMOS transistor Q1 to turn off when the bus voltage is abnormal (such as a negative voltage surge), blocking reverse current within 1μs. This effectively protects downstream equipment from damage caused by reverse current, improving the reliability and response speed of the reverse connection protection function. It is suitable for harsh environments such as military and automotive applications where reliability requirements are extremely high. The precise voltage control and protection mechanism can flexibly set the first preset voltage threshold according to different application needs, achieving accurate response to different voltage anomalies. This provides more precise protection for the DC filter components and downstream equipment, improving the overall performance of the DC filter components.

[0045] In an optional embodiment, such as Figure 3As shown, the linear auxiliary power supply circuit includes a fourth resistor R4, a second Zener diode ZD2, a second capacitor C2, a third capacitor C3, a first transistor T1, and a second diode D2. The collector of the first transistor T1 is electrically connected to the cathode of the first diode D1, and the emitter of the first transistor T1 is electrically connected to the anode of the second diode D2. The cathode of the second diode D2 is electrically connected to the first system ground through the second capacitor C2. The third capacitor C3 is connected between the base of the first transistor T1 and the first system ground. The cathode of the second Zener diode ZD2 is electrically connected to the base of the first transistor T1, and the anode of the second Zener diode ZD2 is electrically connected to the first system ground. The fourth resistor R4 is connected between the base and collector of the first transistor T1. The cathode of the second diode D2 serves as the output terminal of the linear auxiliary power supply circuit. The reference circuit includes a fifth resistor R5 and a second... A reference voltage source RS1 is provided, wherein the fifth resistor R5 is connected between the negative terminal of the second diode D2 and the negative terminal of the first reference voltage source RS1, the positive terminal of the first reference voltage source RS1 is electrically connected to the first system ground, and the negative terminal of the first reference voltage source RS1 is electrically connected to the reference terminal of the first reference voltage source RS1. The negative terminal of the first reference voltage source RS1 serves as the output terminal of the reference circuit. The acquisition circuit includes a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8, wherein the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 are connected in series between the negative terminal of the first diode D2 and the first system ground, and the connection between the seventh resistor R7 and the eighth resistor R8 serves as the output terminal of the acquisition circuit. The acquisition control circuit also includes a ninth resistor R9, a fourth capacitor C4, and a third diode D3, wherein the positive terminal of the third diode D3 is connected to the first non-inverting input terminal of the comparator U1 (e.g., ...). Figure 3 The non-inverting input terminal of U1A is electrically connected, the cathode of the third diode D3 is electrically connected to the first output terminal of comparator U1 through the ninth resistor R9, and the fourth capacitor C4 is connected between the power supply terminal and the first system ground terminal of comparator U1.

[0046] In the above embodiment, the linear auxiliary power supply circuit provides a stable operating power supply for the comparator U1, the reference circuit provides a stable reference voltage, and the acquisition circuit acquires the bus voltage. In conjunction with the ninth resistor R9, the fourth capacitor C4, and the third diode D3, the acquisition control circuit can accurately acquire the bus voltage. When the bus voltage is less than or equal to the first preset voltage threshold, the first NMOS transistor Q1 is turned off within the first preset time period to avoid the failure of the reverse connection protection function and improve the reliability of the DC filter component.

[0047] The linear auxiliary power supply circuit is a series-connected voltage regulator circuit consisting of a first transistor T1, a second Zener diode ZD2, and a fourth resistor R4. The second Zener diode ZD2 stabilizes the base voltage of the first transistor T1, and combined with the biasing effect of the fourth resistor R4, it ensures a stable emitter output voltage. The second diode D2 provides reverse isolation, and the second capacitor C2 and the third capacitor C3 (e.g., C3) filter and store energy for the output voltage and base voltage, respectively, ensuring a low-noise, stable power supply for comparator U1. The first reference voltage source RS1 (e.g., TL431) draws power from the linear auxiliary power supply circuit through the fifth resistor R5. Its reference terminal is shorted to the negative terminal, outputting a stable reference voltage (corresponding to the first preset voltage threshold), providing a precise comparison reference for comparator U1. The sixth, seventh, and eighth resistors form a series voltage divider network to sample the bus voltage between the negative terminal of the first diode D1 and the first system ground. A sampled signal proportional to the bus voltage is output through the connection point of the seventh and eighth resistors to comparator U1. This sampled signal directly reflects the magnitude of the bus voltage, and its amplitude is adjusted to a suitable range for the input of comparator U1 (to avoid high voltage damage to the comparator), serving as the actual input voltage of comparator U1 (such as the first non-inverting input). Comparator U1 compares the sampled signal from the acquisition circuit with the reference voltage of the reference circuit and outputs a control level. The third diode D3 and the ninth resistor R9 form a hysteresis comparator circuit to prevent the comparator from frequently flipping its output level near the threshold point. The fourth capacitor C4 filters the power supply of comparator U1 to reduce power supply noise interference. The overall workflow of the acquisition and control circuit is as follows: After the bus voltage is input through the first diode D1, the linear auxiliary power supply circuit converts it into a stable comparator power supply. The acquisition circuit obtains a low-voltage sampling signal (or voltage divider signal) proportional to the bus voltage through the voltage divider of the sixth to eighth resistors. The reference circuit provides a fixed reference voltage (i.e., the reference voltage). The comparator U1 compares the sampling signal with the reference voltage. If the bus voltage is abnormal, it outputs a low level to turn off the first NMOS transistor Q1, realizing reverse connection protection; if it is normal, it keeps the first NMOS transistor Q1 on. This embodiment achieves a microsecond-level fast response before the arrival of transient negative voltage surges through stable power supply, accurate reference, accurate bus voltage acquisition, and fast turn-off control of the first NMOS transistor Q1. It reliably blocks reverse current and effectively protects downstream equipment (such as military electronics and vehicle controllers) from reverse connection damage. Its reliability is significantly higher than that of traditional diode or simple MOS transistor solutions.

[0048] In an optional embodiment, such as Figure 3 As shown, the acquisition control circuit also includes a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a fourth diode D4. The second non-inverting input terminal of comparator U1 (as shown) Figure 3The non-inverting input terminal of comparator U1B is electrically connected to the output terminal of the acquisition circuit. The second inverting input terminal of comparator U1 is electrically connected to the output terminal of the reference circuit through the tenth resistor R10. The eleventh resistor R11 is connected between the second inverting input terminal of comparator U1 and the first system ground terminal. The anode of the fourth diode D4 is electrically connected to the second non-inverting input terminal of comparator U1, and the cathode of the fourth diode D4 is electrically connected to the second output terminal of comparator U1 through the twelfth resistor R12. The second output terminal of comparator U1 serves as the second output terminal of the acquisition control circuit. The current surge suppression circuit also includes the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15, the sixteenth resistor R16, the seventeenth resistor R17, the third Zener diode ZD3, and the fourth Zener diode ZD4. The precharge capacitor CP is connected between the second output terminal of comparator U1 and the first system ground terminal. The thirteenth resistor R13 and the fourteenth resistor R14 are connected in series between the cathode of the first diode D1 and the second output terminal of comparator U1. The cathode of the third Zener diode ZD3 is electrically connected to the second output terminal of comparator U1. The anode of the third Zener diode ZD3 is electrically connected to the gate of the third NMOS transistor Q3 through the fifteenth resistor R15. The cathode of the fourth Zener diode ZD4 is electrically connected to the anode of the third Zener diode ZD3. The anode of the fourth Zener diode ZD4 is electrically connected to the first system ground terminal. The sixteenth resistor R16 is connected in parallel with the fourth Zener diode ZD4. The seventeenth resistor R17 is connected between the drain and source of the third NMOS transistor Q3.

[0049] In the above embodiment, the tenth resistor R10, eleventh resistor R11, twelfth resistor R12 and fourth diode D4 in the acquisition control circuit work together to accurately acquire the bus voltage and compare it with the reference voltage, providing a signal for the control current surge suppression circuit. The thirteenth resistor R13, fourteenth resistor R14, fifteenth resistor R15, sixteenth resistor R16, seventeenth resistor R17, third Zener diode ZD3, and fourth Zener diode ZD4 in the current surge suppression circuit work together with the pre-charge capacitor CP to achieve the soft start of the third NMOS transistor Q3 when the DC filter component is powered on, avoiding current surge impact. When powered off, the third NMOS transistor Q3 is turned off within a second preset time of less than 1µs, suppressing the next surge current caused by frequent power-on in a short period of time due to switch bounce or human operation, thereby improving the reliability and stability of the DC filter component.

[0050] The comparator U1 in this embodiment also includes a second non-inverting input terminal, a second inverting input terminal, and a second output terminal, forming a dual-channel control channel, i.e., the comparator U1 is a dual-channel voltage comparator; the fourth diode D4 and the twelfth resistor R12 constitute a hysteresis comparator circuit to avoid the comparator frequently switching the output level near the threshold point; the pre-charge capacitor CP is connected between the second output terminal of the comparator U1 and the first system ground terminal. When the second output terminal of the comparator U1 is at a high level, it draws power from the negative terminal of the first diode D1 through the thirteenth resistor R13 and the fourteenth resistor R14 to charge, slowly raising the gate voltage of the third NMOS transistor Q3 to achieve a soft start; when power is off, it discharges quickly through the second output terminal of the comparator U1 to accelerate the gate voltage drop; specifically, when the bus voltage is ≥ the second preset voltage threshold, the second output terminal of the comparator U1 outputs a high level, and the pre-charge capacitor CP achieves a soft start for the third NMOS transistor Q3; when the bus voltage is < the second preset voltage threshold, it outputs a low level to achieve the purpose of quickly turning off the third NMOS transistor Q3 in the current surge suppression circuit. The third Zener diode ZD3 raises the gate threshold voltage of the third NMOS transistor Q3, extending its soft-start time. The fourth Zener diode ZD4 (connected in parallel with the sixteenth resistor R16) further stabilizes the gate potential, preventing damage to the third NMOS transistor Q3 due to excessive gate voltage. The seventeenth resistor R17 is connected in parallel between the drain and source of the third NMOS transistor Q3 to precharge the downstream capacitor before Q3 is fully turned on. The optimized charging and discharging logic of the pre-charge capacitor CP allows Q3 to maintain its surge suppression capability even under frequent power-on and power-off conditions in a short period. The third Zener diode ZD3 raises the turn-on voltage of the Zener diode, delaying the turn-on of Q3. The acquisition and control circuit synchronously controls the bleeder circuit and the surge suppression circuit through the dual outputs of the same comparator, avoiding signal delays or conflicts between multiple control units. This ensures coordinated action between "bleeder start" and "surge suppression shutdown" during power failure, further optimizing system safety performance.

[0051] In an optional embodiment, such as Figure 3As shown, the bleeder circuit also includes an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a fifth Zener diode ZD5, a sixth Zener diode ZD6, a seventh Zener diode ZD7, and a first optocoupler PD1. The eighteenth resistor R18 and the nineteenth resistor R19 are connected in series between the positive bus and the gate of the second NMOS transistor Q2. The twentieth resistor R20 is connected between the gate of the second NMOS transistor Q2 and the second system ground. The anode of the fifth Zener diode ZD5 is electrically connected to the second system ground, and the cathode of the fifth Zener diode ZD5 is electrically connected to the second system ground. The gate of NMOS transistor Q2 is electrically connected. The twenty-first resistor R21 is connected between the second output terminal of the acquisition control circuit and the cathode of the sixth Zener diode ZD6. The input terminal of the first optocoupler PD1 is connected between the anode of the sixth Zener diode ZD6 and the first system ground. The output terminal of the first optocoupler PD1 is connected between the gate of the second NMOS transistor Q2 and the second system ground. The twenty-second resistor R22 and the twenty-third resistor R23 are connected in series between the positive bus and the second output terminal of the acquisition control circuit. The cathode of the seventh Zener diode ZD7 is electrically connected to the second output terminal of the acquisition control circuit, and the anode of the seventh Zener diode ZD7 is electrically connected to the first system ground.

[0052] In the above embodiment, the arrangement of the eighteenth resistor R18, nineteenth resistor R19, twentieth resistor R20, twenty-first resistor R21, twenty-second resistor R22, twenty-third resistor R23, fifth Zener diode ZD5, sixth Zener diode ZD6, seventh Zener diode ZD7, and first optocoupler PD1 in the bleeder circuit enables more precise control over the conduction and cutoff of the second NMOS transistor Q2. Combined with the acquisition and control circuit's acquisition and judgment of the bus voltage, this allows for more efficient control of the discharge process of the capacitor by the bleeder resistor based on the bus voltage conditions. The Zener diodes stabilize and clamp the voltage in the circuit, protecting the second NMOS transistor Q2 and other components from damage caused by excessive voltage. Multiple resistors, in conjunction with the acquisition and control circuit and optocouplers, perform voltage division and current limiting on the bus voltage, enabling the bleeder circuit to better adapt to different operating voltage and current environments, thus improving the overall performance and reliability of the DC filter components.

[0053] Resistors R18 (18th), R19 (19th), R20 (20th), and ZD5 (5th) form the basic drive and gate protection circuit for the second NMOS transistor Q2. Optocoupler PD1 (1st), ZD6 (6th), and R21 (21st) form an isolated control signal transmission channel from the acquisition control circuit to Q2. Resistors R22 (22nd), R23 (23rd), and ZD7 (7th) provide pull-up and clamp protection for the output of the acquisition control circuit. When the acquisition control circuit outputs a high level, optocoupler PD1 conducts, further pulling down the gate level of Q2 to ensure reliable cutoff. When the acquisition control circuit outputs a low level, optocoupler PD1 deactivates, and the gate voltage of Q2 rises normally, ensuring Q2 conducts and can discharge through the second bleeder resistor RD2 (e.g., a fast-discharge resistor).

[0054] In an optional embodiment, such as Figure 3 As shown, the input common-mode filter circuit includes a ferrite common-mode inductor L1. The first input terminal of the ferrite common-mode inductor L1 is electrically connected to the positive terminal of the input power supply, the first output terminal of the ferrite common-mode inductor L1 is electrically connected to the positive bus, the second input terminal of the ferrite common-mode inductor L1 is electrically connected to the negative terminal of the input power supply, and the second output terminal of the ferrite common-mode inductor L1 is electrically connected to the negative bus.

[0055] In the above embodiment, the ferrite common-mode inductor L1 of the input common-mode filter circuit can filter out common-mode interference introduced by the external power grid and also prevent back-end interference from being reverse-coupled to the external power grid.

[0056] The ferrite common-mode inductor L1 has two coils with the same number of turns but opposite winding directions, connected in series between the positive and negative input power supply buses and the negative input power supply buses, respectively, sharing the same ferrite core. When common-mode interference (i.e., interference signals in the same direction existing simultaneously between the positive and negative terminals and ground) is introduced from the external power grid, the interference current will generate magnetic fields in the same direction in the two coils. The magnetic fields are superimposed within the ferrite core, thus forming a high impedance to the common-mode interference current, significantly attenuating the interference signal and preventing it from entering the back end of the DC filter component. At the same time, the ferrite common-mode inductor L1 can also prevent interference signals generated inside the DC filter component from being reverse-coupled to the external power grid, avoiding pollution of the power grid and ensuring the cleanliness and stability of the power grid.

[0057] In an optional embodiment, such as Figure 3As shown, the DC filter component also includes: an output filter circuit, which includes a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, and a microcrystalline inductor L2. The fifth capacitor C5 is connected between the positive bus and the ground terminal; the sixth capacitor C6 is connected between the second system ground terminal and the ground terminal; the first input terminal of the microcrystalline inductor L2 is electrically connected to the positive bus; the second input terminal of the microcrystalline inductor L2 is electrically connected to the second system ground terminal; the seventh capacitor C7 is connected between the first output terminal of the microcrystalline inductor and the ground terminal; the eighth capacitor... C8 is connected between the second output terminal and the ground terminal of the microcrystalline inductor L2. The ninth capacitor C9 and the tenth capacitor C10 are both connected in parallel between the first output terminal and the second output terminal of the microcrystalline inductor L2. The eleventh capacitor C11 is connected between the positive bus and the second system ground terminal. The first output terminal of the microcrystalline inductor L2 serves as the positive output terminal of the DC filter component, and the second output terminal of the microcrystalline inductor L2 serves as the negative output terminal of the DC filter component. A set of capacitors includes the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, the tenth capacitor C10, and the eleventh capacitor C11.

[0058] In the above embodiments, an output filter circuit is set in the DC filter component. The capacitors and microcrystalline inductors therein can filter the output power to make the output power more stable. At the same time, these capacitors also participate in the discharge process of the discharge circuit as energy storage and filter capacitors, which helps to discharge the bus capacitor voltage to a safe voltage after power failure.

[0059] The microcrystalline inductor is connected in series between the positive bus, the second system ground, and the output of the DC filter component. Its high permeability and low loss characteristics can specifically attenuate differential-mode interference and common-mode interference at the output. The fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, and the eighth capacitor C8 form a common-mode filter network. Through the capacitive reactance characteristics of the capacitors, common-mode interference (interference between signal and ground) is directed to the ground terminal, thereby achieving common-mode noise suppression. The ninth capacitor C9 and the tenth capacitor C10 are directly connected in parallel between the first and second output terminals of the microcrystalline inductor L2 to form a differential-mode filter path, which can efficiently attenuate differential-mode interference (such as ripple and pulse interference) between the positive and negative outputs. The eleventh capacitor C11 is connected in parallel between the positive bus and the second system ground terminal to further suppress differential-mode noise at the output front end and reduce the transmission of interference to the output terminal. Residual common-mode interference from the external power grid is introduced to the ground terminal through capacitors C5 (fifth) and C6 (sixth). Common-mode interference generated by the back-end circuit is suppressed by capacitors C7 (seventh) and C8 (eighth) to prevent interference from affecting the front end or radiating outwards. Differential-mode ripple and pulse interference at the output terminal are initially attenuated at the front end by capacitor C11 (eleventh), further suppressed by the inductive impedance of microcrystalline inductor L2, and finally completely filtered out by capacitors C9 (ninth) and C10 (tenth) to ensure stable output voltage / current. After the input power is lost, the charge stored in capacitors five to eleven is discharged in stages through the discharge circuit. It is first slowly discharged by the high-resistance first discharge resistor RD1, and then quickly reduced to a safe voltage by the low-resistance second discharge resistor RD2 to meet safety specifications.

[0060] In an optional embodiment, such as Figure 3 As shown, the reverse connection protection circuit also includes a fourth NMOS transistor Q4, wherein the gate, drain, and source of the fourth NMOS transistor Q4 are electrically connected to the gate, drain, and source of the first NMOS transistor Q1, respectively.

[0061] In the above embodiment, the fourth NMOS transistor Q4 and the first NMOS transistor Q1 form a "parallel redundancy" structure: their gates are connected together (simultaneously receiving the first output signal of the acquisition control circuit and the voltage signal of the target resistor), their drains are connected together (both connected to the negative bus), and their sources are connected together (both connected to the first system ground), forming a completely synchronous turn-on / turn-off control link. By using "dual parallel transistors" instead of "single transistor carrying," the essence is to reduce the circuit's on-resistance and temperature rise, and improve the current carrying capacity without changing the reverse connection protection control logic.

[0062] The gate, drain, and source of the fourth NMOS transistor Q4 are electrically connected to the gate, drain, and source of the first NMOS transistor Q1, respectively. This connection effectively forms a parallel NMOS transistor structure. The fourth NMOS transistor Q4 and the first NMOS transistor Q1 work in parallel to jointly provide reverse connection protection. When the input voltage is normal, both the first NMOS transistor Q1 and the fourth NMOS transistor Q4 are turned on, and current can flow normally through these two NMOS transistors. When the input voltage is undervoltage (before reverse connection), the acquisition and control circuit will quickly detect the abnormality of the bus voltage and control the first NMOS transistor Q1 and the fourth NMOS transistor Q4 to be turned off simultaneously within a first preset time (less than 1µs) to prevent reverse current from flowing in and protect downstream equipment. By connecting two NMOS transistors in parallel, the circuit's conduction capability can be increased, the on-resistance reduced, the conduction loss decreased, and the circuit's reliability improved.

[0063] In an optional embodiment, such as Figure 3 As shown, the current surge suppression circuit also includes a fifth NMOS transistor Q5 and a twenty-fourth resistor R24. The gate of the fifth NMOS transistor Q5 is electrically connected to the positive terminal of the third Zener diode ZD3 through the twenty-fourth resistor R24. The drain and source of the fifth NMOS transistor Q5 are electrically connected to the drain and source of the third NMOS transistor Q3, respectively.

[0064] In the above embodiments, during the power-on process of the DC filter component, when the bus voltage is greater than or equal to the second preset voltage threshold, the fifth NMOS transistor Q5 can achieve soft start together with the third NMOS transistor Q3 to reduce the transient inrush current borne by a single transistor; during the power-off process of the DC filter component, when the bus voltage is less than the second preset voltage threshold, the fifth NMOS transistor Q5 can be turned off together with the third NMOS transistor Q3 within a second preset time period. At the same time, the DC filter component also has the functions of input reverse connection protection, fast discharge of bus capacitor voltage, and common-mode interference filtering, which improves the reliability and efficiency of the system.

[0065] The gate of the fifth NMOS transistor Q5 is connected to the positive terminal of the third Zener diode ZD3 through the twenty-fourth resistor R24, and its drain and source are connected to the drain and source of the third NMOS transistor Q3, respectively. This connection method actually forms a parallel NMOS transistor structure, with the fifth NMOS transistor Q5 and the third NMOS transistor Q3 working in parallel to jointly undertake the current surge suppression function. When the bus voltage is in an undervoltage state (below the second preset voltage threshold), the second output terminal of the comparator U1 outputs a low level, pulling down the gate levels of the third NMOS transistor Q3 and the fifth NMOS transistor Q5, turning off both transistors. In this state, the seventeenth resistor R17 plays a pre-charging role, storing some energy for the relevant capacitors in advance, thereby reducing the electrical stress during the subsequent MOS transistor turn-on stage. When the bus voltage recovers to a non-undervoltage state (above the second preset voltage threshold), the second output of comparator U1 switches to a high-impedance state, and the pre-charge capacitor CP begins to charge. Its voltage gradually rises, causing the gate voltages of the third NMOS transistor Q3 and the fifth NMOS transistor Q5 to slowly rise, so that the two transistors gradually transition from a slightly conducting state to a fully conducting state. After the two transistors are fully conducting, their low-impedance characteristics between their drain and source will short-circuit the seventeenth resistor R17, preventing the resistor from continuously consuming energy.

[0066] The present application will be described in detail below with reference to specific embodiments. This application provides a DC filter component with high-performance reverse connection protection and low-loss fast discharge function for high-voltage, high-current applications. The DC filter component includes an input common-mode filter circuit, an input reverse connection protection circuit, a current surge suppression circuit, an acquisition and control circuit, and a low-power discharge circuit.

[0067] (1) Input reverse connection protection circuit and acquisition control circuit:

[0068] Under the premise of conventional NMOS reverse connection protection, an input voltage acquisition and fast shutdown control circuit is added, such as... Figure 4 As shown, Figure 4 It includes an input reverse connection protection circuit and an acquisition control circuit. Specifically, the circuit includes:

[0069] The linear auxiliary power supply circuit consists of a fourth resistor R4, a first transistor T1 (high voltage transistor), a second diode D2, a second Zener diode ZD2, a second capacitor C2, and a third capacitor C3. It has low power consumption, does not generate EMC interference, and supplies power to the first comparison unit U1A (one of the comparison units in comparator U1).

[0070] The reference circuit consists of a first reference voltage source RS1 and a fifth resistor R5;

[0071] The input voltage sampling circuit consists of resistors R6 (sixth resistor), R7 (seventh resistor), and R8 (eighth resistor). When the bus input voltage drops to a predetermined value (corresponding to the aforementioned first preset voltage threshold), the first comparison unit U1A of the acquisition control circuit outputs a low level, quickly pulling down VGS1 to turn off the first NMOS transistor Q1 and the fourth NMOS transistor Q4. The necessity of this fast turn-off circuit design is as follows: Under normal power supply conditions, the bus voltage is positive, VB (corresponding to the aforementioned negative bus) is the reference potential 0V, VA (corresponding to the aforementioned positive bus) is the input voltage with the highest level, and VGS1 is a driving voltage of approximately DC15~DC18V. When a negative lightning strike voltage or other rapidly fluctuating negative voltage occurs, the voltage of VB will quickly exceed the voltage of VA within a few microseconds. At this time, the voltage reference point in the circuit becomes VA, but the highest voltage is not VB, but VGS1, because the first NMOS transistor Q1... MOSFET Q1, the fourth NMOS transistor Q4, and the first Zener diode ZD1 all have junction capacitance, along with an external capacitor C1. The voltage stored in these capacitors, approximately 15-18V (VGS1 relative to VC), needs to be discharged quickly. The normal discharge of VGS1 requires passing through the circuit of the first resistor R1, or the circuit of the second resistor R2, the third resistor R3, the internal resistance of the power supply (in the absence of the first diode), and the circuit of the first NMOS transistor Q1. Because it is a high-voltage DC power supply, the resistance values ​​of these resistors are usually tens of K or even larger. The junction capacitance of a single high-voltage MOSFET is several nF. Taking a 1nF capacitor and a 10K discharge resistor as an example, the time t for discharging the VGS1 voltage from 18V to 2V is approximately 22us. Therefore, when a reverse voltage of μS occurs during operation, without adding a fast turn-off circuit, the first NMOS transistor Q1 will be in the conducting state and will not provide the reverse connection protection effect.

[0072] t = - R*C*ln[U(t) / U0], where R represents the discharge resistance, such as 10K, C represents the total capacitance, such as 1nF, U(t) represents the voltage of VGS1 at time t, such as 2V, and U0 represents the voltage of VGS1 at time 0, i.e. the initial voltage, such as 18V.

[0073] The acquisition control circuit used in this embodiment can perform acquisition and judgment during the positive voltage drop. The comparator's response speed is typically within the nanosecond level. Its output is an open-source gate. When the output level is low and turns off the first NMOS transistor Q1, VGS1 is discharged through pin 1 of U1A, which can ensure that the bus voltage turns off the first NMOS transistor Q1 before it drops to the negative voltage. Usually, it takes a switching time of microseconds for the bus voltage to be pulled down from positive to negative. During this time, the comparator U1 can complete the voltage acquisition and turn off the first NMOS transistor Q1 and the fourth NMOS transistor Q4. Figure 4The purpose of the first diode D1 (redundant design) used for reverse connection protection and the third capacitor C3 used for filtering and energy storage is to further improve the reliability of the circuit. Even if the switching speed of the positive and negative voltage of the bus is faster, and the negative voltage arrives before the first NMOS transistor Q1 and the fourth NMOS transistor Q4 have time to turn off, it can be ensured that the acquisition and control circuit is not affected by the negative voltage and can continue to complete the turn-off of the first NMOS transistor Q1 and the fourth NMOS transistor Q4 within a hundred ns.

[0074] Compared to the diode solution, this embodiment uses a low-RDS silicon carbide NMOS reverse connection protection circuit. Compared to conventional NMOS reverse connection protection circuits, it adds a fast turn-off circuit. When the input voltage drops to a predetermined value, the NMOS is turned off in advance to prevent energy from flowing to the downstream load when the input voltage reverses to a negative voltage. In terms of conduction loss, the RDS of a 1200V low-RDS silicon carbide NMOS can be as small as 10~20 milliohms or even smaller. Taking 20 milliohms as an example, when a single NMOS carries a current of 5A, its power loss is only about 0.5W (while...). Using a high-voltage diode solution, the voltage drop of the high-voltage diode is 1.2V, and a 5A current will generate 6W of power loss and temperature rise. The specific current value flowing through a single NMOS can be flexibly selected based on the heat dissipation situation. When the current is large, multiple NMOS can be connected in parallel to further reduce the on-resistance and loss (with two NMOS connected in parallel, each MOS only needs to bear 1 / 2 of the original current and 1 / 4 of the power loss, and the total loss of two NMOS is halved). Even if multiple diodes are connected in parallel, the voltage drop of each individual diode changes relatively little, and the overall power loss does not change much.

[0075] Existing reverse connection protection patents (such as CN211530724U) require the generation of reverse current before detection and shutdown, resulting in low reliability. Other patents place the NMOS on the positive power line and require a charge pump principle to turn the NMOS on and off (such as CN202411198356.0). The voltage detection circuit in this patent is only used for over / under voltage protection. Its reverse connection protection function requires a negative voltage detection circuit (using a current sensing amplifier and corresponding peripheral circuitry) to detect the polarity of the input voltage before driving the gate control circuit. This results in high overall circuit design complexity and slow response speed. For example, the charge pump's response speed, especially when restarting, is slow. The biggest problem is that if reverse connection protection relies on a current sensing amplifier and other supporting circuits to detect reverse current, the current sensing amplifier chip needs a separate external power supply to complete the process during reverse connection. This means that the entire reverse connection and reverse current protection function cannot be completed using the bus voltage alone.

[0076] In this embodiment, the NMOS is located on the negative terminal. Reverse connection protection at power-on is automatically implemented based on the NMOS's built-in diode. The bus voltage is collected and used in conjunction with comparator U1 to achieve transient negative voltage (equivalent to reverse connection protection during operation). In this embodiment, as long as the negative voltage is eliminated, the NMOS's body diode can transiently return to the conducting state (depending only on the reverse recovery speed of the body diode, usually in the hundreds of nanoseconds range), reducing the power-down time of the downstream load. Moreover, the charge pump solution is similar to an oring (using an NMOS as an ideal diode), which is more difficult to design in high-voltage systems. Currently, there are no high-voltage oring chips on the market; the response time and recovery time of low-voltage oring chips are in the microsecond range. At the same time, the charge pump solution needs to continuously generate square wave drive pulses, which will generate EMC interference.

[0077] (2) Low-power discharge circuit

[0078] When the input power fails, the bus voltage (mainly the eleventh capacitor C11 and other inter-line X filter capacitors and possible energy storage capacitors at the back end) is first discharged to the threshold voltage (e.g., a DC540V system drops to DC400V) based on the first discharge resistor RD1 (also called the slow discharge resistor). At this time, pin 7 of the second comparator unit U1B (another comparator unit in comparator U1) outputs a low level, the sixth Zener diode ZD6 and the first optocoupler PD1 are not conducting, VGS2 becomes high, turning on the second NMOS transistor Q2, and the second discharge resistor RD2 (also called the fast discharge resistor) (with a resistance value smaller than RD1 (slow discharge resistor)) conducts, accelerating the discharge. Since the first discharge resistor RD1 only needs to discharge the voltage from DC540V to DC400V ( The time can be around 1.8S~1.9S), and tens to 100ms of time need to be reserved for the second bleeder resistor RD2 (fast bleeder resistor) to quickly bleed and complete the bleed from DC400V to DC24V. This solution can significantly reduce the temperature rise and normal power loss of the system by increasing the resistance value of RD1 (slow bleeder resistor). Especially considering that DC400V~DC540V is the operating voltage range of the downstream DC / DC power module, and given the known no-load loss of the power module and the normal power consumption of the downstream load, the bus voltage bleed in the DC540V~DC400V range during input power failure can also rely on the downstream DC / DC power module and the normal load for bleeding. In this way, the resistance value of RD1 (slow bleeder resistor) can be larger (lower normal power consumption), or even eliminated.

[0079] This embodiment directly controls the input based on the input voltage at the input terminal. Neither the acquisition nor the control needs to be isolated, and the product has a common-mode inductor filter at the front end, which can avoid interference and misjudgment caused by high-frequency noise. The design is simpler and the response is more timely. Moreover, the product does not require relay control, and the performance is more reliable (there is no limit to the number of contact actions).

[0080] (3) Current surge suppression circuit adapted to transient repeated power-on and power-off cycles

[0081] Using MOSFETs or relays for current surge suppression (soft start) is a common design approach. This solves the problem of severely reduced current surge suppression effectiveness in thermistor-based soft start solutions during continuous startup due to thermistor overheating, and significantly enhances component reliability. However, conventional MOSFET or relay-based current surge suppression solutions can only meet the current surge suppression requirements of frequent power-on / off cycles with intervals of tens or hundreds of milliseconds. If there are severe voltage fluctuations on the bus due to large equipment startup / shutdown or lightning strikes, resulting in microsecond-level voltage fluctuations, the pre-charge capacitor CP cannot discharge in time, further reducing the equipment's current surge suppression effectiveness. The result will also fail, and will further aggravate the voltage fluctuation of the bus grid along with other equipment; moreover, R_NC in the figure will increase the normal power loss of the thirteenth resistor R13 and the fourteenth resistor R14; in this embodiment, by detecting the input voltage, when the input voltage drops to a certain level, VCTR1 becomes low level, providing a fast discharge channel for the pre-charge capacitor CP, and quickly turning off the third NMOS transistor Q3 and the fifth NMOS transistor Q5, waiting for the slow start-up when entering the next power-on, so as to meet the suppression of surge current during frequent switching (Note: R_NC in this embodiment can be cancelled to reduce the normal power loss of the thirteenth resistor R13 and the fourteenth resistor R14).

[0082] (4) There is a first-stage ferrite common-mode inductor L1 at the circuit input port to prevent the back-end interference signal from being spatially coupled to the front-end control circuit and then flowing out through the input port; due to the design of the current surge suppression circuit, the back-end can select X capacitors in a relatively wide range according to EMC debugging requirements; the back-end of the circuit is equipped with microcrystalline inductor L2 to suppress low-frequency interference, and Y capacitors to suppress common-mode interference.

[0083] In the above embodiments, the NMOS reverse connection protection circuit, combined with the fast turn-off circuit controlled by the input voltage, can cope with transient negative voltage surges during operation. The discharge circuit has two loops: slow discharge and fast discharge. The fast discharge is controlled by the bus voltage. When power is lost, the slow discharge circuit first discharges the bus voltage to the threshold point, and then the fast discharge circuit is activated. The NMOS current surge suppression has a fast turn-off circuit. The fast turn-off circuit is controlled by the bus input voltage, which can meet the current surge suppression requirements when power is restarted due to voltage fluctuations at the microsecond level. Single or multiple comparators can control the reverse connection protection circuit, the transient repetitive power-on / off current surge suppression circuit, and the low-power fast discharge resistor circuit. In this embodiment, two comparators are used only to facilitate the adjustment of the threshold voltage of each comparator and improve the control flexibility. Q1 and Q4, and Q3 and Q5 are all parallel redundant designs to further reduce conduction losses and temperature rise. In product design, they can be reasonably increased or decreased based on the system current and the internal resistance and thermal conductivity of the MOS transistor.

[0084] The above description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Other embodiments of this disclosure will be readily apparent to those skilled in the art upon consideration of the disclosure herein.

[0085] This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art that are not described in this disclosure.

Claims

1. A DC filter assembly with resistance to negative voltage surges and reverse polarity protection, characterized in that, include: The circuit includes a reverse connection protection circuit, a discharge circuit, a data acquisition and control circuit, and an input common-mode filter circuit. The reverse connection protection circuit includes a first NMOS transistor, wherein the drain of the first NMOS transistor is electrically connected to the negative bus, the source of the first NMOS transistor is electrically connected to the first system ground, and the gate of the first NMOS transistor is electrically connected to the positive bus through a target resistor. The first input terminal of the acquisition control circuit is electrically connected to the positive bus, the second input terminal of the acquisition control circuit is electrically connected to the first system ground terminal, and the first output terminal of the acquisition control circuit is electrically connected to the gate of the first NMOS transistor. The acquisition control circuit is used to acquire the bus voltage and control the first NMOS transistor to be turned off within a first preset time when the bus voltage is less than or equal to a first preset voltage threshold, wherein the first preset time is less than 1µs, and the bus voltage represents the voltage between the positive bus and the first system ground terminal. The first input terminal of the bleeder circuit is electrically connected to the positive bus, and the second input terminal of the bleeder circuit is electrically connected to the second system ground. The bleeder circuit includes a first bleeder resistor, a second bleeder resistor, and a second NMOS transistor. The first bleeder resistor is connected between the first output terminal and the second output terminal of the bleeder circuit. The first output terminal of the bleeder circuit is electrically connected to the positive bus, and the second output terminal of the bleeder circuit is electrically connected to the second system ground. The first end of the second bleeder resistor is electrically connected to the first output terminal of the bleeder circuit, and the second end of the second bleeder resistor is electrically connected to the drain of the second NMOS transistor. The source of the second NMOS transistor is electrically connected to the second system ground. The third input terminal of the bleeder circuit is electrically connected to the second output terminal of the acquisition control circuit. The acquisition control circuit is further configured to control the second NMOS transistor in the following manner: when the bus voltage is greater than or equal to a second preset voltage threshold, the gate of the second NMOS transistor is controlled to be at a low level; when the bus voltage is less than the second preset voltage threshold, the gate of the second NMOS transistor is controlled to be at a high level. When the input of the DC filter component is de-energized, during the period when the bus voltage drops to the second preset voltage threshold, a group of capacitors is discharged through the first bleeder resistor. During the period when the bus voltage drops from the second preset voltage threshold to a preset safe voltage value, the group of capacitors is discharged through the second bleeder resistor and the first bleeder resistor. The resistance value of the first bleeder resistor is greater than the resistance value of the second bleeder resistor. The group of capacitors includes the energy storage capacitor and the filter capacitor in the rear end of the DC filter component. The first input terminal and the second input terminal of the input common-mode filter circuit are electrically connected to the positive terminal and the negative terminal of the input power supply, respectively. The first output terminal of the input common-mode filter circuit is electrically connected to the positive bus, and the second output terminal of the input common-mode filter circuit is electrically connected to the negative bus. The input common-mode filter circuit is used to filter out common-mode interference introduced by the external power grid and to prevent back-end interference from being reverse-coupled to the external power grid. The DC filter component further includes a current surge suppression circuit, wherein the first input terminal of the current surge suppression circuit is electrically connected to the positive bus, the second input terminal of the current surge suppression circuit is electrically connected to the first system ground, the third input terminal of the current surge suppression circuit is electrically connected to the second output terminal of the acquisition control circuit, and the output terminal of the current surge suppression circuit is electrically connected to the second system ground; the current surge suppression circuit includes a third NMOS transistor and a pre-charge capacitor, the source of the third NMOS transistor serves as the second input terminal of the current surge suppression circuit, and the drain of the third NMOS transistor serves as the output terminal of the current surge suppression circuit; The acquisition control circuit is also used to control the third NMOS transistor in the following ways: During the power-on process of the DC filter component, when the bus voltage is greater than or equal to the second preset voltage threshold, the gate level of the third NMOS transistor is controlled by the pre-charge capacitor to achieve a soft start of the third NMOS transistor; during the power-off process of the DC filter component, when the bus voltage is less than the second preset voltage threshold, the second output terminal of the acquisition control circuit outputs a low level, and the pre-charge capacitor discharges through the second output terminal of the acquisition control circuit, so that the third NMOS transistor is turned off within a second preset time period, wherein the second preset time period is less than 1µs.

2. The DC filter component according to claim 1, characterized in that, The reverse connection protection circuit further includes: a first resistor, a first Zener diode, a first capacitor, and a first diode, wherein... The first resistor is connected between the gate and source of the first NMOS transistor. The anode and cathode of the first Zener diode are electrically connected to the source and gate of the first NMOS transistor, respectively. The first capacitor is connected in parallel with the first resistor. The target resistor includes a second resistor and a third resistor. The gate of the first NMOS transistor is electrically connected to the positive bus through the target resistor and the first diode. The second resistor and the third resistor are connected in series between the gate of the first NMOS transistor and the cathode of the first diode. The anode of the first diode is electrically connected to the positive bus. The first input terminal of the current surge suppression circuit is electrically connected to the positive bus through the first diode.

3. The DC filter component according to claim 2, characterized in that, The acquisition and control circuit includes a linear auxiliary source circuit, a reference circuit, an acquisition circuit, and a comparator, wherein, The first input terminal and the second input terminal of the linear auxiliary power supply circuit are electrically connected to the cathode of the first diode and the ground terminal of the first system, respectively. The output terminal of the linear auxiliary power supply circuit is electrically connected to the power supply terminal of the comparator. The linear auxiliary power supply circuit is used to provide operating power to the comparator. The first input terminal of the reference circuit is electrically connected to the output terminal of the linear auxiliary source circuit, and the second input terminal of the reference circuit is electrically connected to the first system ground terminal. The first input terminal and the second input terminal of the acquisition circuit are electrically connected to the cathode of the first diode and the first system ground terminal, respectively. The output terminal of the acquisition circuit is electrically connected to the first non-inverting input terminal of the comparator. The output terminal of the reference circuit is electrically connected to the first inverting input terminal of the comparator. The first output terminal of the comparator is electrically connected to the gate of the first NMOS transistor. The first output terminal of the comparator serves as the first output terminal of the acquisition control circuit. The acquisition circuit is used to acquire the bus voltage. When the bus voltage is less than or equal to the first preset voltage threshold, the first output terminal of the comparator outputs a low level so that the first NMOS transistor is turned off within a first preset time period.

4. The DC filter component according to claim 3, characterized in that, The linear auxiliary power supply circuit includes a fourth resistor, a second Zener diode, a second capacitor, a third capacitor, a first transistor, and a second diode. The collector of the first transistor is electrically connected to the cathode of the first diode, the emitter of the first transistor is electrically connected to the anode of the second diode, the cathode of the second diode is electrically connected to the ground of the first system through the third capacitor, the second capacitor is connected between the base of the first transistor and the ground of the first system, the cathode of the second Zener diode is electrically connected to the base of the first transistor, the anode of the second Zener diode is electrically connected to the ground of the first system, the fourth resistor is connected between the base and collector of the first transistor, and the cathode of the second diode serves as the output terminal of the linear auxiliary power supply circuit. The reference circuit includes a fifth resistor and a first reference voltage source. The fifth resistor is connected between the negative terminal of the second diode and the negative terminal of the first reference voltage source. The positive terminal of the first reference voltage source is electrically connected to the first system ground terminal. The negative terminal of the first reference voltage source is electrically connected to the reference terminal of the first reference voltage source. The negative terminal of the first reference voltage source serves as the output terminal of the reference circuit. The acquisition circuit includes a sixth resistor, a seventh resistor, and an eighth resistor, wherein the sixth resistor, the seventh resistor, and the eighth resistor are connected in series between the cathode of the first diode and the ground terminal of the first system, and the connection between the seventh resistor and the eighth resistor serves as the output terminal of the acquisition circuit. The acquisition control circuit further includes a ninth resistor, a fourth capacitor, and a third diode. The anode of the third diode is electrically connected to the first non-inverting input terminal of the comparator, and the cathode of the third diode is electrically connected to the first output terminal of the comparator through the ninth resistor. The fourth capacitor is connected between the power supply terminal of the comparator and the first system ground terminal.

5. The DC filter component according to claim 3, characterized in that, The acquisition and control circuit also includes a tenth resistor, an eleventh resistor, a twelfth resistor, and a fourth diode, wherein, The second non-inverting input terminal of the comparator is electrically connected to the output terminal of the acquisition circuit. The second inverting input terminal of the comparator is electrically connected to the output terminal of the reference circuit through the tenth resistor. The eleventh resistor is connected between the second inverting input terminal of the comparator and the first system ground terminal. The anode of the fourth diode is electrically connected to the second non-inverting input terminal of the comparator. The cathode of the fourth diode is electrically connected to the second output terminal of the comparator through the twelfth resistor. The second output terminal of the comparator serves as the second output terminal of the acquisition control circuit. The current surge suppression circuit further includes a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, a third Zener diode, and a fourth Zener diode, wherein... The pre-charge capacitor is connected between the second output terminal of the comparator and the first system ground terminal. The thirteenth resistor and the fourteenth resistor are connected in series between the cathode of the first diode and the second output terminal of the comparator. The cathode of the third Zener diode is electrically connected to the second output terminal of the comparator. The anode of the third Zener diode is electrically connected to the gate of the third NMOS transistor through the fifteenth resistor. The cathode of the fourth Zener diode is electrically connected to the anode of the third Zener diode. The anode of the fourth Zener diode is electrically connected to the first system ground terminal. The sixteenth resistor is connected in parallel with the fourth Zener diode. The seventeenth resistor is connected between the drain and source of the third NMOS transistor.

6. The DC filter component according to claim 1, characterized in that, The discharge circuit further includes an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a fifth Zener diode, a sixth Zener diode, a seventh Zener diode, and a first optocoupler, wherein... The eighteenth and nineteenth resistors are connected in series between the positive bus and the gate of the second NMOS transistor. The twentieth resistor is connected between the gate of the second NMOS transistor and the second system ground. The anode of the fifth Zener diode is electrically connected to the second system ground, and the cathode of the fifth Zener diode is electrically connected to the gate of the second NMOS transistor. The twentieth resistor is connected between the second output terminal of the acquisition control circuit and the cathode of the sixth Zener diode. The input terminal of the first optocoupler is connected between the anode of the sixth Zener diode and the first system ground, and the output terminal of the first optocoupler is connected between the gate of the second NMOS transistor and the second system ground. The twenty-second and twenty-third resistors are connected in series between the positive bus and the second output terminal of the acquisition control circuit. The cathode of the seventh Zener diode is electrically connected to the second output terminal of the acquisition control circuit, and the anode of the seventh Zener diode is electrically connected to the first system ground.

7. The DC filter component according to claim 1, characterized in that, The input common-mode filter circuit includes a ferrite common-mode inductor. The first input terminal of the ferrite common-mode inductor is electrically connected to the positive terminal of the input power supply. The first output terminal of the ferrite common-mode inductor is electrically connected to the positive bus. The second input terminal of the ferrite common-mode inductor is electrically connected to the negative terminal of the input power supply. The second output terminal of the ferrite common-mode inductor is electrically connected to the negative bus.

8. The DC filter component according to claim 1, characterized in that, The DC filter component further includes: an output filter circuit, which comprises a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, and a microcrystalline inductor, wherein... The fifth capacitor is connected between the positive bus and the ground terminal; the sixth capacitor is connected between the second system ground terminal and the ground terminal; the first input terminal of the microcrystalline inductor is electrically connected to the positive bus; the second input terminal of the microcrystalline inductor is electrically connected to the second system ground terminal; the seventh capacitor is connected between the first output terminal of the microcrystalline inductor and the ground terminal; the eighth capacitor is connected between the second output terminal of the microcrystalline inductor and the ground terminal; the ninth and tenth capacitors are both connected in parallel between the first and second output terminals of the microcrystalline inductor; the eleventh capacitor is connected between the positive bus and the second system ground terminal; the first output terminal of the microcrystalline inductor serves as the positive output terminal of the DC filter component; the second output terminal of the microcrystalline inductor serves as the negative output terminal of the DC filter component; the set of capacitors includes the fifth, sixth, seventh, eighth, ninth, tenth, and eleventh capacitors.

9. The DC filter component according to claim 1, characterized in that, The reverse connection protection circuit further includes a fourth NMOS transistor, wherein the gate, drain, and source of the fourth NMOS transistor are electrically connected to the gate, drain, and source of the first NMOS transistor, respectively.

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