A low power state logic synthesis method, system, medium and program product

Abstract

The application discloses a low-energy state logic synthesis method, system, medium and program product, the method comprises the following steps: screening simple logic functions which meet the requirements of the tolerable margin of threshold voltage; dividing all the screened simple logic functions into multiple logic function sets by changing the number of the screened simple logic functions; performing energy consumption driven function decomposition, simple logic function merging and state logic gate mapping on original complex calculation functions in the input state logic design file in units of logic function sets, and selecting the optimal mapping result as the final output mapping result according to the principle of minimum energy consumption. The application aims to improve reliability by selecting a synthesis unit library for synthesis through reliability evaluation of state logic gates, and reduce the overall energy consumption of the state logic gate execution sequence through various energy consumption optimizations of function decomposition, simple logic function merging, mapping and result selection.

Description

A low-power state logic synthesis method, system, medium, and program product Technical Field

[0001] This invention belongs to the field of digital circuit technology, specifically relating to a low-power state logic synthesis method, system, medium, and program product. Background Technology

[0002] With the rapid development of the Internet of Things (IoT) and edge computing, terminal devices typically rely on limited power reserves, making energy consumption control extremely stringent. However, the physical separation of computing and storage units in the traditional von Neumann architecture leads to frequent data transfers. Significant latency and energy consumption are inevitable along these transmission paths, resulting in the "memory wall" and "power wall" problems that limit performance improvements. With the rapid development of IoT and edge computing, data-intensive applications are increasingly dominating, making this problem particularly critical. The concept of in-memory computing (IMC) offers an exciting solution to the "memory wall" and "power wall" problems by embedding computing power into storage units to reduce data transfers.

[0003] Due to the non-volatility and threshold switching characteristics of memristors, in-memory state logic computation based on memristor memory arrays (MCBAs) eliminates the bottleneck of data transfer by performing logic operations within the memristor cells (memristors), demonstrating great potential as a next-generation edge computing carrier. As shown in Figure 1, the state logic computation unit (mMPU) mainly includes a state logic computation controller (mMPU controller) and a memristor memory array (MCBA). The in-memory state logic computation system can be implemented by cascading state logic gates within the memristor memory array. As shown in Figure 2, based on the circuit structure of parallel memristors + series resistors, various state logic gates have been implemented, covering IMP (Implication), NOR (Normal), OR (Or), and other functions. Logic inputs and outputs are represented by the resistance states of the memristors, with high resistance (HRS) representing logic '0' and low resistance (LRS) representing logic '1'. For example, (i) and (ii) in Figure 2 can be used as two different state logic gates, and their corresponding logic functions are achieved by applying appropriate control voltages (V in Figure 2). R and V W This is achieved through a trigger condition switching process.

[0004] Based on the differences in specific input-output mapping methods, state logic gates can be divided into two categories: simple state logic gates and composite state logic gates. For simple state logic gates, the logic input and output are mapped to different memristor cells, and can be further divided into set (SET) type (implementing logic functions based on conditional set process) and reset (RESET) type (implementing logic functions based on conditional reset process). For example, the circuit structure shown in Figure 2(ii) can implement a set gate with NOR function (OUT = ~(IN1 + IN2)), where "~" represents the inversion operation. The truth table of this circuit structure is shown in Table 1.

[0005] Table 1: Truth Table of Set-Type NOR Gates

[0006]

[0007] Referring to Table 1, the two logic inputs are the resistance states of memristors IN1 and IN2, while the logic output is the final resistance state of memristor OUT, whose initial resistance state is set to 0 (HRS). Under a suitable applied voltage V... R and V W Under these conditions, the resistance state of the memristor OUT will only switch to logic 1 (LRS) when both IN1 and IN2 are logic '0' (HRS). A compound gate is an extension of a simple gate.

[0008] For example, if the initial resistance state of the memristor OUT is not fixed to logic '0', but is regarded as the third logic input, then the set-type NOR gate shown in Figure 2(ii) can be extended into a composite state logic gate with ONOR function (OUT' = ~(IN1 + IN2) +OUT), and its complete truth table is shown in Table 2.

[0009] Table 2: Truth Table of Compound State Logic Gates for ONOR Function

[0010]

[0011] Complex computational functions can be implemented by cascading multiple state logic gates in a memristor memory array, as shown in Figure 3. Gate1 and Gate2 represent two cascaded state logic gates. The applied voltage V in steps ① and ②... R and V WUnder these conditions, complex computational functions can be performed. For the same computational task, different synthesis mapping methods will produce state logic execution sequences with vastly different performance. To date, various state logic synthesis processes have been developed to seek optimized cascade sequences. A representative work is SIMPLER MAGIC, which utilizes CMOS logic synthesis tools to decompose complex computational functions and develops a mapping algorithm to obtain cascade sequences through device multiplexing in single-row mapping mode. Recent works on LOSSS and ILOSS have expanded the variety of state logic gates and introduced composite gates through separate post-processing stages to further improve computational efficiency, while also considering the input coverage problem. However, most current state logic synthesis research (such as SIMPLERMAGIC and LOSSS) mainly focuses on optimizing computational latency or reducing the number of operation steps, while paying insufficient attention to energy consumption, which is crucial for edge applications. Although the LESP mode in the ILOSS toolset has initially introduced some basic energy optimization ideas, it lacks further improvement strategies and systematic evaluation.

[0012] Furthermore, all current state logic synthesis work fails to consider the impact of threshold voltage changes on the execution of state logic gates. For practical memristors, resistor state switching depends on the threshold voltage (V0). SET / V RESET These voltages fluctuate, as shown in Figure 4. Since the execution of state logic gates is guaranteed through a condition switching process, this means that the voltage allocated to the output device must be higher or lower than the device's threshold voltage. Changes in the threshold voltage may cause logic operations to fail.

[0013] Therefore, in order to improve the reliability of computing systems, considering the threshold voltage fluctuation of memristors and selecting more stable state logic gates is an effective approach; to meet the urgent needs of low-power edge computing scenarios, it is imperative to study new comprehensive mapping methods oriented towards energy consumption optimization. Summary of the Invention

[0014] The technical problem to be solved by this invention is to provide a low-energy-consumption state logic synthesis method, system, medium, and program product, addressing the aforementioned problems of the prior art. This invention aims to improve system reliability by evaluating the reliability of state logic gate implementations and using selected state logic gates with higher reliability as a synthesis unit library for synthesis. By introducing the energy consumption information of state logic gates into the synthesis mapping process and employing various optimization methods to continuously reduce the overall energy consumption of the state logic gate execution sequence, the invention obtains the mapping result with the lowest energy consumption through comparison and selection of the results.

[0015] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0016] A low-energy-consumption state logic synthesis method includes the following steps:

[0017] S101, For a given simple logic function, construct state logic gates based on a given device model and obtain the tolerance margin of the state logic gates to the threshold voltage, and select state logic gates and corresponding simple logic functions whose tolerance margin to the threshold voltage meets the requirements.

[0018] S102, by changing the number of simple logic functions selected, all the selected simple logic functions are divided into multiple logic function sets; for each logic function set, the logic gates corresponding to the simple logic functions in the logic function set are used as the standard cell library of the synthesis tool, and the synthesis tool is used to perform synthesis to realize the energy consumption driven function decomposition, and the original complex calculation function in the input state logic design file is transformed into a function netlist composed of simple logic functions.

[0019] S103. For each functional netlist under the logical function set, find the simple logical function combination that can be merged in the functional netlist and merge it into the corresponding simple logical function or composite logical function through the energy-saving merging process. Reconstruct the netlist to make its logical function correct and obtain a new functional netlist containing composite logical functions.

[0020] S104. For each new functional netlist under the logic function set, the new functional netlist is mapped using a mapping tool. During the mapping process, the array size of the memristor memory array is continuously reduced until the mapping tool can no longer complete the mapping of the new functional netlist, thereby obtaining a mapping result consisting of the execution sequence of state logic gates under the minimum memristor memory array size.

[0021] S105: Statistical performance indicators are calculated for the mapping results of complex computing functions under each logical function set. By comparing the performance indicators of the mapping results of the same complex computing function under different logical function sets, the mapping result with the best performance is selected as the final output mapping result based on the principle of lowest energy consumption.

[0022] Optionally, step S101 includes:

[0023] S201, For a given simple logic function, construct state logic gates based on a given device model;

[0024] S202, for each state logic gate, generate a combination of hypothetical parameters for various device relationship indicators based on the threshold voltage of the device. These device relationship indicators include the reset voltage ratio. Set voltage ratio Ratio of the full reset voltage Its calculation function expression is:

[0025] , , ;

[0026] in, and These are the maximum and minimum values ​​of the reset threshold voltage, respectively. and These are the maximum and minimum values ​​of the set threshold voltage, respectively. The minimum threshold voltage required for a complete reset;

[0027] S203, for each state logic gate, calculate its set voltage range under various parameter assumptions based on the node voltage conditions that must be met for its successful execution. Or reset voltage range Its calculation function expression is:

[0028] ;

[0029] ;

[0030] S204 will set the voltage range and reset voltage range As an evaluation metric for the tolerance margin of threshold voltage for state logic gates, the set voltage range under all parameter assumption combinations is selected. Or reset voltage range State logic gates with voltages greater than a preset threshold are considered to have a tolerance margin that meets the requirements for threshold voltage, and the simple logic functions corresponding to these state logic gates can be obtained.

[0031] Optionally, step S102 includes:

[0032] S301, under the constraints of the synthesis tool, by changing the number of simple logic functions selected, all the selected simple logic functions are divided into multiple logic function sets;

[0033] S302, for each logic function set, the logic gates corresponding to all simple logic functions in the logic function set are used as the standard cell library of the synthesis tool, and the area attribute value of the logic gate corresponding to each simple logic function is set to the energy consumption value of the corresponding state logic gate, and the maximum load capacitance is set to the preset maximum value.

[0034] S303 sets the maximum delay in the synthesis constraints to a preset maximum value and the maximum area to 0 for each different standard cell library. It also sets the synthesis process of the synthesis tool to optimize the area to achieve energy-driven functional decomposition and starts the iterative synthesis process of the synthesis tool, thereby transforming the original complex calculation functions in the input state logic design file into a functional netlist composed of simple logic functions.

[0035] Optionally, after step S101 and before step S102, the correctness of the selected state logic gates is verified based on the given device model: circuit-level simulation is performed on the selected state logic gates based on the given device model. During the circuit-level simulation, the gap length between the tip of the conductive filament inside the device and the electrode is directly used as the state variable to define logic "0" and logic "1". Logic "0" indicates that the gap length is greater than or equal to a preset value and the memristor cell is in a high resistance state, and logic "1" indicates that the gap length is less than the preset value and the memristor cell is in a low resistance state. The circuit-level simulation verification is also performed on the composite logic gates extended from the simple logic gates to ensure the correctness of their composite logic functions.

[0036] Optionally, the processing of the functional netlist under each logical function set in step S103 includes:

[0037] S401: For the current functional netlist, based on each preset merging type, sequentially search the current functional netlist for possible simple logic function combinations to be merged. If a merging simple logic function combination exists and the energy consumption is reduced after merging, then the merging operation is performed first, and the netlist structure is adjusted to ensure the correctness of the netlist function; otherwise, the merging operation is not performed. If a circular dependency problem occurs during the merging process, the energy consumption before and after merging is used to determine whether merging is possible. If it is determined that merging is possible, the location of the circular dependency problem is recorded and the merging operation is completed; otherwise, the merging operation is not performed, and the search continues. The circular dependency problem refers to the situation where, among all logic functions driven by the covered input, the composite logic function must be executed last. If other logic functions need to use both the covered input and the output of the composite logic function simultaneously, the correctness of the result will be affected regardless of the execution order, resulting in an irreconcilable contradiction. The merging operation keeps the calculated input and output signals unchanged. If the original input and output signals are about to be covered during the merging process, then this merging operation is not performed.

[0038] S402, after completing all preset merge type searches in the current functional netlist, according to the location of the circular dependency problem recorded, a copy gate COPY is added between the overwritten state logic gate and the composite state logic gate generated by the merge to back up the data of the originally overwritten state logic gate to avoid conflicts, and then the reconstructed new functional netlist is output.

[0039] S403. After completing the merging operation, the equivalence checking tool is used to perform formal equivalence verification on the new functional netlist that introduces composite state logic gates to ensure the logical correctness of the reconstructed netlist.

[0040] Optionally, the processing of the new functional netlist for each logical function set in step S104 includes:

[0041] S501, determine the minimum number of units (CU) required for each node to complete the calculation based on the node connection relationship of the new functional netlist;

[0042] S502, set the array width of the memristor storage array, and use a single row of the memristor storage array for mapping. Divide a row of memristor cells into two parts. One part of the memristor cells directly stores the original input and does not need to be initialized. The other memristor cells serve as intermediate nodes and outputs. Considering the ratio of the number of set gates to reset gates in the new functional netlist and the ratio of the minimum number of cells (CU) of set gates to the maximum number of cells (CUs) of reset gates, the memristor cells are initialized to 0 and 1 respectively according to the initialization ratio shown in the following formula:

[0043] ;

[0044] in, To initialize the ratio, This indicates the number of memristor cells initialized to 1. This indicates the number of memristor cells initialized to 0. This indicates the total number of reset gates in the new functional netlist. This represents the total number of simple state logic gates in the new functional netlist. This represents the maximum value of the minimum unit number CU in the reset gate. This represents the maximum value of the minimum number of cells CU in the set gate; based on this initialization ratio multiplied by the total number of memristor cells that need to be initialized, the number of memristor cells initialized to 1 is calculated and rounded up, and the number of memristor cells initialized to 0 is the total number of memristor cells that need to be initialized minus the number of memristor cells initialized to 1.

[0045] S503, for the new functional netlist, a recursive approach is used to complete the mapping process of state logic gates from their logical functions in the new functional netlist to specific memristor cells. This includes: representing the new functional netlist as a directed acyclic graph (DAG), and then allocating resources to the current node from top to bottom, starting from the root node of the DAG used to represent the output node; the parent node can only allocate resources after all child nodes have been allocated resources, thus recursively allocating resources to all its input child nodes; simultaneously, when mapping composite state logic gates, the memristor cells occupied by the covered child nodes are directly allocated to them, and the allocation of the composite state logic gate can only be performed after all other nodes driven by its covered input have been allocated; all child nodes of a node are allocated in descending order of their minimum number of cells (CU); memristor cells that are no longer needed are reinitialized, and memristor cells that were originally initialized to 0 are still initialized to 0, and memristor cells that were initialized to 1 are still initialized to 1.

[0046] S504 continuously reduces the array width of the memristor storage array until mapping cannot be completed to obtain the minimum mappable array width and the execution sequence of the state logic gates at this time. Under the current array width, if all nodes can be allocated, the execution sequence of the state logic gates in a single row of the memristor storage array is output, and the array width is reduced to continue the mapping process until mapping cannot be completed. If allocation cannot be completed, a mapping error message is printed, the process ends and exits, and the minimum array width that can be mapped and the execution sequence of the state logic gates under this array width are obtained.

[0047] Optionally, in step S105, when calculating the performance indicators of the mapping results of complex computing functions under each logical function set, the performance indicators include the minimum array width when each logical function set is used as a standard cell library, as well as the energy consumption and latency under the minimum array width. The step of selecting the best-performing mapping result as the final output mapping result based on the principle of minimum energy consumption includes: obtaining the mapping result with the lowest energy consumption by comparing the energy consumption information of the mapping results obtained by the same complex computing function using different logical function sets. If the energy consumption of multiple logical function sets is the same, then the latency or the minimum mappable array width is compared to select the best-performing result. If all performance indicators are the same, then the mapping result of one logical function set is selected as the final output mapping result.

[0048] The present invention also provides a low-power state logic synthesis system, including a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to execute the low-power state logic synthesis method.

[0049] The present invention also provides a computer-readable storage medium storing a computer program or instructions that are programmed or configured to execute the low-power state logic synthesis method by a processor.

[0050] The present invention also provides a computer program product, including a computer program or instructions that are programmed or configured to execute the low-power state logic synthesis method via a processor.

[0051] Compared with existing technologies, the present invention can mainly achieve the following beneficial effects: The present invention improves the reliability of computing systems by constructing a state logic gate reliability evaluation framework to screen the state logic gates with high reliability in memristor memory arrays for synthesis mapping. By introducing the energy consumption information of state logic gates into the state logic synthesis mapping process, the present invention achieves the combined processing of energy-driven functional decomposition and energy consumption reduction. Multiple logic function sets are constructed, and different types of simple logic function sets can be used for synthesis mapping to obtain mapping results with different performance. By comparing the overall energy consumption of the results, the mapping result with the lowest energy consumption can be selected as the final output mapping result. Attached Figure Description

[0052] Figure 1 is a schematic diagram of the system structure of the state logic calculation unit in the prior art.

[0053] Figure 2 shows the configuration of the state logic circuit structure of parallel memristor + series resistor in the existing MCBA.

[0054] Figure 3 demonstrates the implementation of state logic gate cascading in MCBA using existing technology.

[0055] Figure 4 is a schematic diagram of threshold voltage fluctuation in a practical memristor in the prior art.

[0056] Figure 5 is a schematic diagram of the basic process of the method according to an embodiment of the present invention.

[0057] Figure 6 is a schematic diagram of the node voltage of the memristor in an embodiment of the present invention.

[0058] Figure 7 shows the results of evaluating the reliability of state logic gates using an actual RRAM model in an embodiment of the present invention. Wherein (a) is the reliability of the SET gate as p... RES The reliability assessment results of the changes; (b) is ρ SET When ρ = 1.3, the RESET gate follows ρ CLR The reliability assessment results of the change; (c) is ρ SET When ρ = 1.4, the RESET gate follows ρ CLR The reliability assessment results of the changes; (d) is ρ CLR When ρ = 1.2, the RESET gate follows ρ SETThe reliability assessment results of the change; (e) is ρ CLR When ρ = 1.3, the RESET gate follows ρ SET The results of the reliability assessment were changed.

[0059] Figure 8 is a simulation diagram of the state logic gates in the embodiment of the present invention, wherein (a) is the SPICE simulation result of the state logic gates used; (b) is the circuit structure of COPY, NOT, IMP and ANOT gates; and (c) is the circuit structure of NAND, NOR, AND, OR, ANAND, ANOR, ONOR, OAND and AOR gates.

[0060] Figure 9 is a schematic diagram of the processing of all merging cases in the embodiments of the present invention, wherein (a) is the merging case of ONOR / IMP / OAND, (b) is the merging case of ANOR / ANOT / ANAND / AOR, (c) is the merging case of ONOR / IMP / OAND+NOT, (d) is the merging case of ANOR / ANOT / ANAND / AOR+NOT, (e) is the merging case of OR / NOR / AND / NAND, (f) is the merging case of NOT, (g) is the merging case of ONOR / IMP / OAND+NOT, and (h) is the merging case of ANOR / ANOT / ANAND / AOR+NOT.

[0061] Figure 10 is a schematic diagram of the directed acyclic graph (DAG) representation of the new functional netlist in an embodiment of the present invention, the calculation of the minimum unit number (CU) of each node, and the node allocation order. Detailed Implementation

[0062] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0063] As shown in Figure 5, the low-power state logic synthesis method of this embodiment includes the following steps:

[0064] S101, For a given simple logic function, construct state logic gates based on a given device model and obtain the tolerance margin of the state logic gates to the threshold voltage. Select state logic gates and corresponding simple logic functions whose tolerance margin to the threshold voltage meets the requirements. Since the tolerance margin to the threshold voltage is high, its reliability is high. Therefore, it can be regarded as a set of state logic gates with high reliability for subsequent synthesis mapping process.

[0065] S102, by changing the number of selected simple logic functions used, all selected simple logic functions are divided into multiple logic function sets; for each logic function set, the logic gates corresponding to the simple logic functions in the logic function set are used as the standard cell library (.lib) of the synthesis tool, and the synthesis tool is used to perform synthesis to realize the energy-driven function decomposition, and the original complex calculation functions in the input state logic design file (specifically the HDL design file in this embodiment, with the suffix .v) are transformed into a functional netlist composed of simple logic functions;

[0066] S103. For each set of logical functions, find the simple logical function combinations that can be merged in the functional netlist and merge them into the corresponding simple logical function or composite logical function through energy-saving merging process. Reconstruct the netlist to make its logical function correct and obtain a new functional netlist containing composite logical functions (suffix still .v).

[0067] S104. For each new functional netlist under the logic function set, the new functional netlist is mapped using a mapping tool. During the mapping process, the array size of the memristor storage array is continuously reduced until the mapping tool can no longer complete the mapping of the new functional netlist. This yields a mapping result (with the suffix .json) consisting of the execution sequence of state logic gates under the minimum memristor storage array size.

[0068] S105: Statistical performance metrics are calculated for the mapping results of complex computing functions under each logical function set. By comparing the performance metrics of the mapping results of the same complex computing function under different logical function sets, the mapping result with the best performance is selected as the final output mapping result (with the suffix .json) based on the principle of lowest energy consumption.

[0069] In this embodiment, step S101 includes:

[0070] S201, For a given simple logic function, construct state logic gates based on a given device model;

[0071] For example, the device model used in this embodiment is the Stanford RRAM Model v1.0.0, an open-source RRAM model described in Verilog-A. Its threshold voltage, high and low resistance values, and series resistance values ​​in the circuit are shown in Table 3. Since the device reset process is gradual, an additional parameter V exists. CLEAR This represents the minimum voltage required for a complete reset under its uniform pulse width.

[0072] Table 3: Parameters of Device Model and State Logic Gate Circuit

[0073]

[0074] Based on the specific settings of the device model and the key parameters of the memristor, including the threshold voltage, the resistance values ​​of the high and low resistance states, state logic gate circuits can be constructed using the device model.

[0075] S202, for each state logic gate, generate a combination of hypothetical parameters for various device relationship indicators based on the threshold voltage of the device. These device relationship indicators include the reset voltage ratio. Set voltage ratio Ratio of the full reset voltage Its calculation function expression is:

[0076] , , ;

[0077] in, and These are the maximum and minimum values ​​of the reset threshold voltage, respectively. and These are the maximum and minimum values ​​of the set threshold voltage, respectively. The minimum threshold voltage required for a complete reset;

[0078] In this embodiment, the fluctuation of the device threshold voltage is considered, and a reliability assessment framework is constructed based on the key parameters of the device (memristor). In practical memristors, the fluctuation of the threshold voltage is typically modeled as a distribution around the nominal value. Figure 6 is a schematic diagram of the node voltages of the memristor in this embodiment. This is the reset voltage. This is the set voltage. This is the complete reset voltage. The maximum threshold voltage required for a complete reset. To quantitatively evaluate the reliability of the state logic gate, this embodiment defines five key parameters to describe the switching characteristics and margins of the device, including the reset voltage ratio. Set voltage ratio Ratio of the full reset voltage and the set voltage range and reset voltage range As shown in Table 4.

[0079] Table 4: Five key parameters for quantitatively assessing reliability and their definitions

[0080]

[0081] In Table 4, ρ RES ρ SET and ρ CLRUsed to describe the relative relationship between different nominal threshold voltage values, reflecting the basic physical characteristics of the device. SET and RES These represent the V values ​​that the set or reset state logic gates can tolerate, respectively. SET and V RESET Variation range. These two parameters directly quantify the reliability margin of a specific logic gate and are the core evaluation metrics of this framework. The larger the range of threshold voltage variation that the logic gate can tolerate, the better. SET or RES The higher the value, the higher its reliability when faced with device differences.

[0082] S203, for each state logic gate, calculate its set voltage range under various parameter assumptions based on the node voltage conditions that must be met for its successful execution. Or reset voltage range Its calculation function expression is:

[0083] ;

[0084] ;

[0085] In this embodiment, the triggering conditions for the memristor to successfully perform logic operations are shown in Tables 5 and 6.

[0086] Table 5: Conditions required for a set gate to successfully perform a logic operation

[0087]

[0088] Table 6: Conditions required for the reset gate to successfully perform logic operations

[0089]

[0090] Based on the triggering conditions for successful logic operations of memristors, the node voltage conditions that must be met for successful execution of each state logic gate can be derived, combined with the preset device parameter relationships (ρ). RES ρ SET ρ CLR The reliability assessment framework is used to evaluate and calculate the tolerance margin of threshold voltage for logic gates in different states. SET or RESUltimately, state logic gates that consistently exhibit a large tolerance margin under various device parameter assumptions can be selected as a high-reliability state logic gate cell library. Using the typical devices and circuit parameters shown in Table 3, a systematic reliability assessment was performed on all possible single-input and dual-input state logic gates. Based on the relative magnitudes between nominal values, a series of ρ values ​​consistent with the physical characteristics of actual devices can be assumed. RES ρ SET and ρ CLR Parameter combinations, and for each parameter combination, calculate the maximum value of various state logic gates. SET or RES The value is calculated, and the result is shown in Figure 7, where (a) is the value of the SET gate with respect to ρ. RES The reliability assessment results of the changes; (b) is ρ SET When ρ = 1.3, the RESET gate follows ρ CLR The reliability assessment results of the change; (c) is ρ SET When ρ = 1.4, the RESET gate follows ρ CLR The reliability assessment results of the changes; (d) is ρ CLR When ρ = 1.2, the RESET gate follows ρ SET The reliability assessment results of the change; (e) is ρ CLR When ρ = 1.3, the RESET gate follows ρ SET The results of the reliability assessment were changed.

[0091] S204 will set the voltage range and reset voltage range As an evaluation metric for the tolerance margin of threshold voltage for state logic gates, the set voltage range under all parameter assumption combinations is selected. Or reset voltage range State logic gates whose voltages are all greater than a preset threshold are considered to have a tolerance margin that meets the requirements for threshold voltage, and the simple logic functions corresponding to these state logic gates can be obtained.

[0092] In this embodiment, based on the above calculation results, those devices that consistently exhibit large performance under various device parameter assumptions can be selected. SET or RESState logic gates with values. These gates are considered more reliable because they have lower requirements for the accuracy of device parameters. After screening, a high-reliability state logic gate cell library can be determined, including SET type NOT, NOR, and AND gates, and RESET type NOR, NOT, COPY, NAND, and OR gates, as the basis for subsequent state logic synthesis mapping. The simple logic functions corresponding to these state logic gates can also be obtained, serving as the basis for subsequent logic function set partitioning.

[0093] In this embodiment, steps S101 and S102 further include verifying the correctness of the logic function of the state logic gates based on a given device model: For the selected set of high-reliability state logic gates and composite gates extended from simple gates, circuit-level simulation verification is required based on the given device model. The applied voltage of the state logic gate circuit is determined through theoretical analysis and experimental verification, and the feasibility and functional correctness of the state logic gates are verified based on the expected changes in device states, laying the foundation for the subsequent synthesis mapping process. After screening by the aforementioned reliability assessment framework, the state logic gates used are finally determined to include SET type NOT, NOR, and AND gates, and RESET type NOR, NOT, COPY, NAND, and OR gates. Among them, the COPY gate is used to solve the circular dependency problem later, and its extension into a composite gate is not considered. Therefore, the two types of state logic gates for functional verification are simple gates and composite gates: COPY gates ( Logic functions), ANOT logic gates ( The logic function, which includes reset-type NOT logic gates, logic functions), IMP logic gates ( The logic function, which includes a set NOT logic gate. Logic functions), ANAND logic gates ( The logic function, which includes reset-type NAND logic gates, Logic functions), ANOR logic gates ( The logic function, which includes reset-type NOR logic gates, Logic functions), OAND logic gates ( The logic function, which includes set AND logic gates, logic functions), ONOR logic gates ( The logic functions, which include set-type NOR logic gates, (logic functions) and AOR logic gates ( The logic function, which includes a reset-type OR logic gate. (Logical functions).

[0094] To more accurately reflect the device state, the gap length between the tip of the conductive filament and the electrode inside the device is used directly as the state variable in the circuit-level simulation, rather than the resistance value. This is because the resistance value of a memristor is non-linear and will exhibit different values ​​under different read / write voltages, while the gap length is a more fundamental physical state quantity. This paper defines a long gap as HRS (logic "0"), which is 1.7 nm in the device, and a short gap as LRS (logic "1"), which is 0.2 nm in the device. During the simulation, based on the triggering conditions of the state logic gates mentioned above, and considering both the condition transitions of the output device and the invariance of the input device, the control voltage pulses required for each state logic gate are determined, as shown in Table 7. To simplify operation and maintain consistency, the width of all voltage pulses is uniformly 500 ns.

[0095] Table 7: Control voltage pulses required for logic gates in different states and their corresponding circuit structures

[0096]

[0097] In Table 7, the circuit structures of the state logic gates corresponding to the logic functions in the first three rows of the first column are shown in Figure 8(b), and the circuit structures of the state logic gates corresponding to the logic functions in the remaining rows are shown in Figure 8(c). Based on the parameters in Table 7, the functions of all the simple and composite gates mentioned above were verified. The simulation results are shown in Figure 8(a). The circuit structures of the copy gate (COPY), the set / reset NOT gate (NOT), the NOT AND gate (ANOT), and the implicating gate (IMP) are shown in Figure 8(b), and the circuit structures of the remaining state logic gates are shown in Figure 8(c). In this embodiment, the given memristor simulation model is Stanford RRAMModel v1.0.0, and the circuit simulation tool is HSPICE (but not limited to this) to verify the correctness of the state logic gate functions.

[0098] In Figure 8(a), each column represents the simulation results of a state logic gate. The first row shows the waveform of the pulse voltage, while the remaining rows show the change in the gap length between the end of the conductive wire and the electrode in the device under each specific input condition, reflecting the change in the device's resistance state. Except for the first column, the upper half of each column represents the verification results of simple gates, while the entire column represents the verification results of composite gates. During the simulation, for reset-type COPY, NOT, OR, NAND, and NOR gates, the logic output needs to be initialized to LRS before execution, and the logic function is based on the conditional reset transition of the output device; for set-type AND, NOT, and NOR gates, the logic output needs to be initialized to HRS before execution, and the logic function is based on the conditional set transition of the output device. By expanding the logic output of simple gates to the opposite value of the original, the simulation results of composite gates can be obtained. Except for the first column, each column from left to right represents the simulation results of seven composite gates: ANOT, IMP, ANAND, ANOR, OAND, ONOR, and AOR. The simulation results show that all 15 state logic gates correctly perform their expected functions, proving that these state logic gates can be implemented in a cross-array composed of the same memristor, providing support for the use of state logic gates in the subsequent synthesis mapping process. Meanwhile, during the SPICE simulation, the instantaneous total power consumption P(t) provided by the power supply in the circuit at each time t during the simulation can be obtained through the built-in keyword "src_pwr". When the simulation step size Δt is sufficiently small, the total energy consumption E of the calculation process can be obtained by accumulating the product of the instantaneous power consumption P(t) at each time point and the simulation step size Δt. In this embodiment, the simulation step size is set to 0.1 ns, and the simulation process is executed under different input state combinations. The instantaneous power consumption at each simulation time is extracted. The power consumption information of different state logic gates under all input conditions is shown by the "Power" curve in Figure 8(a). Then, the total energy consumption of the state logic gate under each input condition is calculated by multiplying and summing the power consumption and step size. Finally, for each state logic gate, the average energy consumption under all input conditions is taken as the final energy consumption of that state logic. Since the synthesis mapping method for single-row arrays results in an execution sequence within the array that includes re-initialization operations for unused cells, these re-initialization operations also generate energy consumption. Therefore, in this embodiment, the same method is used to determine the energy consumption generated by the set / reset operation under different input conditions using the SPICE tool. To minimize energy consumption, the applied voltage for the set / reset operation should be as small as possible while ensuring that the set / reset operation is completed. The applied voltage parameters are shown in Table 8.

[0099] Table 8: External Voltage Parameters for Set / Reset Operations

[0100]

[0101] Based on the applied voltage parameters determined in Tables 7 and 8, the energy consumption calculation results for the set / reset operation and the 15 state logic gates are shown in Table 9.

[0102] Table 9: Energy Consumption Information for Set / Reset Operations and 15 State Logic Gates

[0103]

[0104] In this embodiment, step S102 includes:

[0105] S301, under the constraints of the synthesis tool, by changing the number of simple logic functions selected, all the selected simple logic functions are divided into multiple logic function sets;

[0106] For example, in this embodiment, the set of high-reliability state logic gates includes five different simple logic functions: NOT, NOR, AND, NAND, and OR. These logic functions can be divided into 15 different logic function sets, including {NOT, AND}, {NOT, AND, NAND}, {NOT, AND, NAND, NOR}, {NOT, AND, NAND, NOR, OR}, {NOT, AND, NAND, OR}, {NOT, AND, NOR}, {NOT, AND, NOR, OR}, {NOT, AND, OR}, {NOT, NAND, NOR}, {NOT, NAND, NOR, OR}, {NOT, NAND, OR}, {NOT, NOR, OR}, {NOT, NOR, OR}, {NOT, NOR, OR}, {NOT, NOR, OR}, and {NOT, OR}. These logic function sets will be used to drive the subsequent synthesis mapping process. It is worth noting that due to the internal limitations of CMOS synthesis tools (this article uses the open-source CMOS synthesis tool ABC, but synthesis tools are not limited to this; the specific tool can be selected according to actual needs), all logic function sets must include NOT functions, and independent {NOT} sets cannot complete logic synthesis. Also, the COPY function does not perform specific calculations and will not be considered here.

[0107] S302, for each logic function set, the logic gates corresponding to all simple logic functions in that set are used as the standard cell library (.lib file) for the synthesis tool. The area attribute value of the logic gate corresponding to each simple logic function is set to the energy consumption value of its corresponding state logic gate, and the maximum load capacitance is set to a preset maximum value so that the load size does not affect the circuit construction. For example, using the aforementioned first logic function set, which includes the NOT function and the AND function, the area value of the NOT function can be set to its energy consumption value of 2.46 J (the NOT function has two implementation methods: SET and RESET; the smaller value is taken to reduce energy consumption, and the energy consumption value of all state logic functions is uniformly multiplied by 10). 9 Similarly, the area value of the AND function is set to its energy consumption value of 3.79 J, and the maximum load capacitance of all logic functions is set to 999.

[0108] S303: For each different standard cell library, the maximum delay in the synthesis constraints is set to a preset maximum value, and the maximum area is set to 0. The synthesis process of the synthesis tool is set to area optimization to achieve energy-driven functional decomposition. The iterative synthesis process of the synthesis tool is started, thereby transforming the original complex calculation functions in the input state logic design file into functional netlists composed of simple logic functions. For each different standard cell library, by setting the synthesis process to area optimization, energy-saving optimization is achieved, and the iterative synthesis process of the synthesis tool is started, thereby transforming the original complex calculation functions into multiple diverse netlists composed of different types of simple logic functions. For example, in this embodiment, the ABC synthesis tool is used to complete the functional decomposition, and logic synthesis commands such as "resyn", "resyn2", and "resyn2rs" are used to complete the synthesis. Then, in its technology mapping stage, the "map -a" command is used to achieve area-first synthesis optimization and output functional netlists composed of logic functions in the cell library.

[0109] In this embodiment, the processing of the functional netlist under each logical function set in step S103 includes:

[0110] S401: For the current functional netlist, based on each preset merging type, sequentially search the current functional netlist for possible simple logic function combinations to be merged. If a merging simple logic function combination exists and the energy consumption is reduced after merging, then the merging operation is performed first, and the netlist structure is adjusted to ensure the correctness of the netlist function; otherwise, the merging operation is not performed. If a circular dependency problem occurs during the merging process, the energy consumption before and after merging is used to determine whether merging is possible. If it is determined that merging is possible, the location of the circular dependency problem is recorded and the merging operation is completed; otherwise, the merging operation is not performed, and the search continues. The circular dependency problem refers to the situation where, among all logic functions driven by the covered input, the composite logic function must be executed last. If other logic functions need to use both the covered input and the output of the composite logic function simultaneously, the correctness of the result will be affected regardless of the execution order, resulting in an irreconcilable contradiction. The merging operation keeps the calculated input and output signals unchanged. If the original input and output signals are about to be covered during the merging process, then this merging operation is not performed.

[0111] S402, after completing all preset merge type searches in the current functional netlist, according to the location of the circular dependency problem recorded, a copy gate COPY is added between the overwritten state logic gate and the composite state logic gate generated by the merge to back up the data of the originally overwritten state logic gate to avoid conflicts, and then the reconstructed new functional netlist is output.

[0112] S403. After completing the merging operation, the equivalence checking tool is used to perform formal equivalence verification on the new functional netlist that introduces composite state logic gates to ensure the logical correctness of the reconstructed netlist.

[0113] In step S401, each merging case is processed iteratively. Once the search for one merging case is completed, the search for the next merging case is automatically performed until all cases have been searched. The search and merging operation for each merging case is repeated until no new merging combinations appear in the new round, at which point step S402 is executed.

[0114] In step S401, the merging possibilities of simple logic function combinations are preset and can be defined as needed. For example, as an optional implementation, the merging possibilities of simple logic function combinations in this embodiment include:

[0115] NOR / NOT / AND+OR, whose corresponding compound logic functions are ONOR / IMP / OAND, where ONOR is the NOR logic function, IMP is the implied logic function, and OAND is the AND-OR logic function, as shown in Figure 9(a), can be represented as:

[0116] NOR / NOT / AND+OR → ONOR / IMP / OAND,

[0117] Because OR(NOR(a, b), c) == ONOR(a, b, c), OR(NOT(a), b) == IMP(a, b), and OR(AND(a, b), c) == OAND(a, b, c), the logical functions are consistent before and after the merge operation. In ONOR and OAND, a, b, and c are the inputs of the logic gates, and c is the logic output. In IMP, a and b are the inputs of the logic gates, and b is the logic output.

[0118] NOR / NOT / NAND / OR+AND, their corresponding compound logic functions are ANOR / ANOT / ANAND / AOR, where ANOR is an OR-NOT-AND logic gate, ANOT is a NOT-AND logic gate, ANAND is a NAND-NOT-AND logic gate, and AOR is an OR-AND logic gate, as shown in Figure 9(b), which can be represented as:

[0119] NOR / NOT / NAND / OR+AND → ANOR / ANOT / ANAND / AOR,

[0120] Because AND(NOR(a, b), c) == ANOR(a, b, c), AND(NOT(a), b) == ANOT(a, b), AND(NAND(a, b), c) == ANAND(a, b, c), and AND(OR(a, b), c) == AOR(a, b, c), the logical functions are consistent before and after the merging operation. In ANOR, ANAND, and AOR, a, b, and c are the inputs of the logic gates, and c is the logic output. In ANOT, a and b are the inputs of the logic gates, and b is the logic output.

[0121] NOR / NOT / AND+NOR, whose corresponding compound logic function is ONOR / IMP / OAND+NOT, as shown in Figure 9(c), can be represented as:

[0122] NOR / NOT / AND+NOR → ONOR / IMP / OAND+NOT,

[0123] Since a NOR gate can be seen as a combination of OR and NOT, similar to point 1, the logical function before and after the merge operation is consistent, and it is set as the default merge operation.

[0124] NOR / NOT / NAND / OR+NAND, their corresponding compound logic functions are ANOR / ANOT / ANAND / AOR+ NOT, as shown in Figure 9(d), which can be represented as:

[0125] NOR / NOT / NAND / OR+NAND → ANOR / ANOT / ANAND / AOR+NOT,

[0126] Since a NAND gate can be seen as a combination of AND and NOT, similar to point 2, the logic function before and after the merge operation is consistent, and it is set as the default merge operation.

[0127] NOR / OR / NAND / AND+NOT, whose corresponding merging logic function is OR / NOR / AND / NAND, as shown in Figure 9(e), can be represented as:

[0128] NOR / OR / NAND / AND+NOT → OR / NOR / AND / NAND,

[0129] Because NOT(NOR(a, b)) == OR(a, b), NOT(OR(a, b)) == NOR(a, b), NOT(NAND(a, b)) == AND(a, b), NOT(AND(a, b)) == NAND(a, b), the logical functions are consistent before and after the merge operation. Here, a and b are the inputs of the logic gate, and there is a unit outside a and b as the output of the logic gate.

[0130] NOT+NOT, whose corresponding merging logic function is NOT, as shown in Figure 9(f), can be represented as:

[0131] NOT + NOT → NOT

[0132] Since NOT(NOT(a)) == a, the signal remains unchanged after passing through two consecutive NOT gates. Therefore, the latter NOT gate can be deleted, and the circuit after it can be connected to the input of the first NOT gate.

[0133] NOR / NOT / AND+NOR+NOT, whose corresponding compound logic function is ONOR / IMP / OAND+NOT, as shown in Figure 9(g), can be represented as:

[0134] NOR / NOT / AND+NOR+NOT → ONOR / IMP / OAND+NOT,

[0135] Because NOT(NOR(NOR(a, b), c)) == NOT(NOT(ONOR(a, b, c))) and NOT(NOR(AND(a,b), c)) == NOT(NOT(ONOR(a, b, c))), where a, b, and c are logical inputs and c is also a logical output, and NOT(NOR(NOT(a),b)) == NOT(NOT(IMP(a, b))), where a and b are logical inputs and b is also a logical output, after completing the above merging, it can be found that there are two consecutive NOT gates connected. It is possible to consider using the NOT+NOT merging operation to further simplify the netlist. This merging situation actually includes two merging operations: NOR / NOT / AND+NOR and NOT+NOT. The reason for considering this merging scenario is that a circular dependency problem in a standalone NOR / NOT / AND+NOR merging operation introduces a COPY gate. If the merging operation is not performed because the energy consumption is not reduced after merging, however, if a NOT gate is closely connected after the merging operation and both merging scenarios are considered simultaneously, the energy consumption may still be reduced after the circular dependency problem occurs, and the merging operation can then be performed.

[0136] NOR / NOT / NAND / OR+NAND+NOT, whose corresponding compound logic functions are ANOR / ANOT / ANAND / AOR+NOT, as shown in Figure 9(h), can be represented as:

[0137] NOR / NOT / NAND / OR+NAND+NOT → ANOR / ANOT / ANAND / AOR+NOT,

[0138] The principle of this merge operation is the same as that of the previous merge operation, and it can be set as a preset merge operation.

[0139] In this embodiment, the execution order of the merging operations in the above-mentioned merging scenarios is as follows:

[0140] (1) NOR / OR / NAND / AND+NOT → OR / NOR / AND / NAND;

[0141] (2) NOR / NOT / AND+OR → ONOR / IMP / OAND;

[0142] (3) NOR / NOT / NAND / OR+AND → ANOR / ANOT / ANAND / AOR;

[0143] (4) NOR / NOT / AND+NOR → ONOR / IMP / OAND+NOT;

[0144] (5) NOR / NOT / NAND / OR+NAND → ANOR / ANOT / ANAND / AOR+NOT;

[0145] (6) NOR / NOT / AND+NOR+NOT → ONOR / IMP / OAND+NOT;

[0146] (7) NOR / NOT / NAND / OR+NAND +NOT → ANOR / ANOT / ANAND / AOR+NOT;

[0147] (8) NOT + NOT → NOT.

[0148] In this embodiment, when combining simple logic functions that meet the preset merging conditions into a composite logic function, the following constraints must be met: (1) The output of the first simple gate function cannot drive other functions; (2) An input cannot be used as an overridden input twice; (3) The input and output of the original calculation function cannot be overridden.

[0149] In this embodiment, step S104 includes:

[0150] S501, determine the minimum number of units (CU) required for each node to complete the calculation based on the node connection relationship of the new functional netlist;

[0151] In this embodiment, the minimum number of units (CU) required for each node to complete the calculation is calculated by analyzing the connection relationships of the nodes in the functional netlist obtained from S103. The node connection relationships of the new functional netlist can be represented as a tree structure. The calculation of the minimum number of units (CU) of each node is recursively calculated from the bottom (leaf nodes) upwards. The minimum number of units (CU) of the original input node (leaf node) of the complex calculation function is fixed at 1. For the other nodes besides the leaf nodes, the minimum number of units (CU) is defined as the maximum value of the sum of the minimum number of units (CU) of each child node and its sorting index (starting from 1) minus 1 after arranging the N child nodes of the node in descending order of minimum number of units (CU). A calculation example is shown in Figure 10. The minimum number of units (CU) of the leaf node (the original input node of the calculation function) is fixed at 1. Taking node g11 as an example, its three child nodes are g6, g7 and g9. Arranging them in descending order of CU value, the sequence is as follows:<g9,g7,g6> The minimum unit number CU of child nodes g6, g7, and g9 are 1, 2, and 3 respectively, and the sorting numbers of child nodes g6, g7, and g9 are 3, 2, and 1 respectively. Therefore, the sum of the minimum unit number CU of child node g6 and its sorting number minus 1 is 1+3-1=3, the sum of the minimum unit number CU of child node g7 and its sorting number minus 1 is 2+2-1=3, and the sum of the minimum unit number CU of child node g9 and its sorting number minus 1 is 3+1-1=3. Therefore, the minimum unit number CU of node g11 is max{1+3-1, 2+2-1, 3+1-1}, which is 3.

[0152] S502, set the array width of the memristor storage array, and use a single row of the memristor storage array for mapping. Divide a row of memristor cells into two parts. One part of the memristor cells directly stores the original input and does not need to be initialized. The other memristor cells serve as intermediate nodes and outputs. Considering the ratio of the number of set gates to reset gates in the new functional netlist and the ratio of the minimum number of cells (CU) of set gates to the maximum number of cells (CUs) of reset gates, the memristor cells are initialized to 0 and 1 respectively according to the initialization ratio shown in the following formula:

[0153] ;

[0154] in, To initialize the ratio, This indicates the number of memristor cells initialized to 1. This indicates the number of memristor cells initialized to 0. This indicates the total number of reset gates in the new functional netlist. This represents the total number of simple state logic gates in the new functional netlist. This represents the maximum value of the minimum unit number CU in the reset gate. This represents the maximum value of the minimum number of cells CU in the set gate; based on this initialization ratio multiplied by the total number of memristor cells that need to be initialized, the number of memristor cells initialized to 1 is calculated and rounded up, and the number of memristor cells initialized to 0 is the total number of memristor cells that need to be initialized minus the number of memristor cells initialized to 1.

[0155] S503, for the new functional netlist, a recursive approach is used to complete the mapping process of state logic gates from their logical functions in the new functional netlist to specific memristor cells. This includes: representing the new functional netlist as a directed acyclic graph (DAG), and then allocating resources to the current node from top to bottom, starting from the root node of the DAG used to represent the output node; the parent node can only allocate resources after all child nodes have been allocated resources, thus recursively allocating resources to all its input child nodes; simultaneously, when mapping composite state logic gates, the memristor cells occupied by the covered child nodes are directly allocated to them, and the allocation of the composite state logic gate can only be performed after all other nodes driven by its covered input have been allocated; all child nodes of a node are allocated in descending order of their minimum number of cells (CU); memristor cells that are no longer needed are reinitialized, and memristor cells that were originally initialized to 0 are still initialized to 0, and memristor cells that were initialized to 1 are still initialized to 1; an example of mapping using the above method is shown in Figure 10.

[0156] S504 continuously reduces the array width of the memristor storage array until mapping cannot be completed to obtain the minimum mappable array width and the execution sequence of the state logic gates at this time. Under the current array width, if all nodes can be allocated, the execution sequence of the state logic gates in a single row of the memristor storage array is output, and the array width is reduced to continue the mapping process until mapping cannot be completed. If allocation cannot be completed, a mapping error message is printed, the process ends and exits, and the minimum array width that can be mapped and the execution sequence of the state logic gates under this array width are obtained.

[0157] The mapping process in step S104 of this embodiment is based on LOSSS, with the following improvements: 1. More composite state logic gates are introduced in the mapping process. It must be ensured that the composite state logic gate is the last logic gate to be mapped and executed among all the parent logic gates of the covered logic gate; 2. The ratio of memristor cells initialized to 0 and 1 is changed. When initializing cells other than inputs, the ratio of cells initialized to 0 and 1 is determined by the ratio of the number of set gates and reset gates in the netlist after merging and the ratio of the maximum CU value of set gates and reset gates.

[0158] In this embodiment, when calculating the performance indicators of the synthesis mapping process in step S105, the performance indicators of the synthesis mapping results include the minimum array width when each simple logic function set is used as a cell library, and the energy consumption and latency under the minimum array width. Latency is the number of calculation steps, which can be directly observed to complete the mapping. This embodiment uses a more refined energy consumption evaluation model for the mapping process. During the mapping process, there are both execution operations of state logic gates and initialization and re-initialization operations of devices. These operations consume energy, so they need to be considered during execution. This work will directly use the energy consumption results shown in Table 9 to strictly follow the mapping steps to calculate and evaluate the total energy consumption of the mapping process, including the energy consumed by device initialization and re-initialization operations (SET / RESET) in a single row array, and the energy consumed by the execution operation of each state logic gate. This evaluation method can accurately reflect the actual energy consumption level and provide support for the selection of energy optimization results.

[0159] In this embodiment, when calculating the performance indicators of the mapping results of complex computing functions under each logical function set in step S105, the performance indicators include the minimum array width when each logical function set is used as a standard cell library, as well as the energy consumption and latency under the minimum array width. The step of selecting the best-performing mapping result as the final output mapping result based on the principle of minimum energy consumption includes: obtaining the mapping result with the lowest energy consumption by comparing the energy consumption information of the mapping results obtained by the same complex computing function using different logical function sets. If the energy consumption of multiple logical function sets is the same, then their latency or the minimum mappable array width can be compared to select the best-performing result. If all performance indicators are the same, then the results obtained by multiple logical function sets can all be used as the final output mapping result. Therefore, the mapping result of one logical function set can be selected as the final output mapping result.

[0160] In summary, the purpose of the low-energy state logic synthesis method in this embodiment is to improve system reliability by using highly reliable state logic gates and to complete the low-energy synthesis mapping process from complex computational functions to state logic gate execution sequences. By introducing energy consumption information during the synthesis and merging process, the netlist is optimized towards low energy consumption. The multi-logic function set method is used to perform synthesis mapping to obtain state logic gate execution sequences with different performances. The mapping result with the best energy consumption is selected by comparison. The entire process includes: (1) Constructing a reliability evaluation framework for state logic gates, selecting a memristor device model, and using the framework to screen a set of state logic gates with high reliability based on the key parameters of the device model and the logic circuit. Specifically, it includes set-type NOT, NOR, and AND gates, as well as reset-type NOR, NOT, COPY, NAND, and OR gates. Then, it uses the SPICE simulation tool to perform circuit-level simulation verification to ensure its feasibility and functional correctness; (2) Using the five simple logic functions abstracted from the above state logic gates, constructing 15 logic function sets, and making each set a synthesis unit library for the synthesis tool, setting the area value of the logic gate corresponding to each function to the energy consumption value of its corresponding state logic gate, and using the synthesis tool to decompose the original complex calculation function into a functional netlist composed of logic functions within the state logic function set with the goal of minimizing the area, so as to realize multiple energy-driven function decomposition processes. (3) Introduce composite state logic gates to perform multiple merging operations on the functional netlist with the goal of reducing energy consumption, and adjust the netlist structure to make its logic correct. There are 8 merging cases. For each case, traverse the netlist to find whether there is a merging case, and determine whether merging will reduce energy consumption. If energy consumption is reduced, the merging operation is implemented. At the same time, a COPY gate is introduced to deal with the circular dependency problem that may occur during the merging process. (4) Improve the mapping method based on LOSSS to complete the mapping process from the functional netlist after the merging operation to the state logic gates in a single row of the memristor storage array. Determine the minimum array width required to complete the mapping and the execution sequence of the state logic gates in the memory at this time. (5) Statistically analyze the performance indicators of all comprehensive mapping results, including the minimum array width and the energy consumption and latency under the minimum array width. By comparing these performance indicators, select the best performance result as the final output mapping result based on the principle of the lowest energy consumption. This embodiment constructs a state logic gate reliability evaluation framework to screen a set of state logic gates with high reliability in order to improve the reliability of the computing system. It introduces the energy consumption information of state logic operations into the synthesis and merging process to achieve energy consumption optimization of the functional netlist. It uses a multi-logic function set method to obtain diverse mapping results, and can compare and select the mapping result with the best energy consumption, which can significantly reduce computing energy consumption.

[0161] Furthermore, this embodiment also provides a low-power state logic synthesis system, including a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to execute the low-power state logic synthesis method. Additionally, this embodiment provides a computer-readable storage medium storing a computer program or instructions programmed or configured to execute the low-power state logic synthesis method via a processor. Furthermore, this embodiment also provides a computer program product, including a computer program or instructions programmed or configured to execute the low-power state logic synthesis method via a processor.

[0162] Those skilled in the art will understand that the technical solutions provided by this invention may take the form of a method, system, or computer program product. Therefore, this invention may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this invention may take the form of a computer program product embodied on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams. These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0163] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A low-energy-consumption state logic synthesis method, characterized in that, The process includes the following steps: S101, for a given simple logic function, construct state logic gates based on a given device model and obtain the tolerance margin of the state logic gates to the threshold voltage, and select state logic gates with tolerance margins to the threshold voltage that meet the requirements and their corresponding simple logic functions; S102, by changing the number of selected simple logic functions used, divide all selected simple logic functions into multiple logic function sets; for each logic function set, use the logic gates corresponding to the simple logic functions in the set as the standard cell library of the synthesis tool, and perform synthesis using the synthesis tool to achieve energy-efficient functional decomposition, transforming the original complex calculation functions in the input state logic design file into a functional netlist composed of simple logic functions; S103, for the functional netlist under each logic function set, find the simple logic function combinations that can be merged in the functional netlist and merge them into corresponding simple logic functions or composite logic functions through energy-efficient merging processing, and reconstruct the netlist to make its logic functions correct. S104. For each logic function set, a new functional netlist containing composite logic functions is obtained; S105. For each logic function set, the new functional netlist is mapped using a mapping tool. During the mapping process, the array size of the memristor memory array is continuously reduced until the mapping tool can no longer complete the mapping of the new functional netlist, thereby obtaining a mapping result consisting of a sequence of state logic gates under the minimum memristor memory array size; S106. For the mapping results of complex computing functions under each logic function set, the performance indicators are statistically analyzed. By comparing the performance indicators of the mapping results of the same complex computing function under different logic function sets, the mapping result with the best performance is selected as the final output mapping result based on the principle of lowest energy consumption; Step S107 includes: S201. For a given simple logic function, state logic gates are constructed based on a given device model; S202. For each state logic gate, a combination of hypothetical parameters for various device relationship indicators is generated based on the threshold voltage of the device. The device relationship indicators include the reset voltage ratio. Set voltage ratio Ratio of the full reset voltage Its calculation function expression is: ， ， ;in, and These are the maximum and minimum values ​​of the reset threshold voltage, respectively. and These are the maximum and minimum values ​​of the set threshold voltage, respectively. S203: For each state logic gate, calculate its set voltage range under various parameter assumptions, based on the node voltage conditions that must be met for its successful execution. This is the minimum threshold voltage required for a complete reset. Or reset voltage range Its calculation function expression is: ； S204 sets the voltage range. and reset voltage range As an evaluation metric for the tolerance margin of threshold voltage for state logic gates, the set voltage range under all parameter assumption combinations is selected. Or reset voltage range State logic gates with voltages greater than a preset threshold are considered to have a tolerance margin that meets the requirements for threshold voltage, and the simple logic functions corresponding to these state logic gates can be obtained.

2. The low-energy state logic synthesis method according to claim 1, characterized in that, Step S102 includes: S301, under the constraints of the synthesis tool, by changing the number of selected simple logic functions used, all selected simple logic functions are divided into multiple logic function sets; S302, for each logic function set, the logic gates corresponding to all simple logic functions in the set are used as the standard cell library of the synthesis tool, and the area attribute value of the logic gate corresponding to each simple logic function is set to the energy consumption value of its corresponding state logic gate, and the maximum load capacitance is set to a preset maximum value; S303, for each different standard cell library, the maximum delay in the synthesis constraints is set to a preset maximum value, the maximum area is set to 0, the synthesis process of the synthesis tool is set to area optimization to achieve energy consumption-driven functional decomposition, and the iterative synthesis process of the synthesis tool is started, thereby transforming the original complex calculation functions in the input state logic design file into a functional netlist composed of simple logic functions.

3. The low-energy-consumption state logic synthesis method according to claim 1, characterized in that, The process after step S101 and before step S102 also includes verifying the correctness of the selected state logic gates based on the given device model: performing circuit-level simulation on the selected state logic gates based on the given device model. During the circuit-level simulation, the gap length between the tip of the conductive filament inside the device and the electrode is directly used as the state variable to define logic "0" and logic "1". Logic "0" indicates that the gap length is greater than or equal to a preset value and the memristor cell is in a high-resistance state, while logic "1" indicates that the gap length is less than the preset value and the memristor cell is in a low-resistance state. The process also includes performing circuit-level simulation verification on composite logic gates derived from simple logic gates to ensure the correctness of their composite logic functions.

4. The low-energy-consumption state logic synthesis method according to claim 1, characterized in that, Step S103, the processing of the functional netlist under each logical function set, includes: S401, for the current functional netlist, according to each preset merging type, sequentially searching the current functional netlist for possible simple logical function combinations to be merged. If a possible simple logical function combination exists and the energy consumption is reduced after merging, the merging operation is performed first, and then the netlist structure is adjusted to ensure the correctness of the netlist function; otherwise, the merging operation is not performed. If a circular dependency problem occurs during the merging process, the energy consumption before and after merging is used to determine whether merging is possible. If it is determined that merging is possible, the location of the circular dependency problem is recorded and the merging operation is completed; otherwise, the merging operation is not performed, and the search continues. The circular dependency problem refers to the situation where, among all logical functions driven by the covered input, the composite logical function must be executed last, and other logical functions need to be used simultaneously. Overridden inputs and outputs of composite logic functions will affect the correctness of the result regardless of the execution order, creating irreconcilable contradictions. The merging operation keeps the input and output signals unchanged. If the original input and output signals are about to be overridden during the merging process, the merging operation will not be performed. S402: After completing all preset merging type searches for the current functional netlist, based on the location of the recorded circular dependency problem, a copy gate (COPY) is added between the overridden state logic gate and the composite state logic gate generated by the merging. The data of the originally overridden state logic gate is backed up to avoid conflicts, and then the reconstructed new functional netlist is output. S403: After completing the merging operation, an equivalence checking tool is used to perform formal equivalence verification on the new functional netlist that introduces composite state logic gates to ensure the logical correctness of the reconstructed netlist.

5. The low-energy-consumption state logic synthesis method according to claim 1, characterized in that, Step S104, the processing of the new functional netlist for each logic function set includes: S501, determining the minimum number of cells (CU) required for each node to complete the calculation based on the node connection relationship of the new functional netlist; S502, setting the array width of the memristor storage array, mapping using a single row of the memristor storage array, dividing a row of memristor cells into two parts, one part of the memristor cells directly storing the original input without initialization, and the other memristor cells serving as intermediate nodes and outputs, taking into account the ratio of the number of set gates to reset gates and the ratio of the maximum value of the minimum number of cells (CU) of set gates to reset gates in the new functional netlist, and initializing the memristor cells to 0 and 1 respectively according to the initialization ratio shown in the following formula: ;in, To initialize the ratio, This indicates the number of memristor cells initialized to 1. This indicates the number of memristor cells initialized to 0. This indicates the total number of reset gates in the new functional netlist. This represents the total number of simple state logic gates in the new functional netlist. This represents the maximum value of the minimum unit number CU in the reset gate. This represents the maximum value of the minimum unit number CU in the set gate; based on this initialization ratio multiplied by the total number of memristor units to be initialized, the number of memristor units initialized to 1 is calculated and rounded up, and the number of memristor units initialized to 0 is the total number of memristor units to be initialized minus the number of memristor units initialized to 1; S503, for the new functional netlist, the mapping process of the state logic gate from the logic function in the new functional netlist to the specific memristor units is completed recursively, including: representing the new functional netlist as a directed acyclic graph (DAG), and then allocating resources to the current node from top to bottom, starting from the root node of the DAG used to represent the output node; the parent node can only allocate resources after all child nodes have been allocated resources, thus recursively allocating resources to all its input child nodes; at the same time, the composite state logic gate directly allocates the memristor units occupied by the covered child nodes to it during mapping, only when The allocation of the composite state logic gate can only be performed after all other nodes driven by its covered input have been allocated; all child nodes of a node are allocated in descending order of their minimum unit number (CU); memristor units that are no longer needed are reinitialized, and memristor units that were originally initialized to 0 are still initialized to 0, and memristor units that were initialized to 1 are still initialized to 1; S504, the array width of the memristor storage array is continuously reduced until mapping cannot be completed to obtain its minimum mappable array width and the execution sequence of the state logic gate at this time. Under the current array width, if all nodes can be allocated, the execution sequence of the state logic gate in a single row of the memristor storage array is output, and the array width is reduced to continue the mapping process until mapping cannot be completed; if allocation cannot be completed, a mapping error message is printed, the process ends and exits, and the minimum array width that can be mapped and the execution sequence of the state logic gate under this array width are obtained.

6. The low-energy-consumption state logic synthesis method according to claim 1, characterized in that, In step S105, when calculating the performance indicators of the mapping results of complex computing functions under each logical function set, the performance indicators include the minimum array width when each logical function set is used as a standard cell library, as well as the energy consumption and latency under the minimum array width. The step of selecting the best-performing mapping result as the final output mapping result based on the principle of minimum energy consumption includes: obtaining the mapping result with the lowest energy consumption by comparing the energy consumption information of the mapping results obtained by the same complex computing function using different logical function sets. If the energy consumption of multiple logical function sets is the same, then the latency or the minimum mappable array width is compared to select the best-performing result. If all performance indicators are the same, then the mapping result of one logical function set is selected as the final output mapping result.

7. A low-power state logic synthesis system, comprising a microprocessor and a memory interconnected, characterized in that, The microprocessor is programmed or configured to execute the low-power state logic synthesis method according to any one of claims 1 to 6.

8. A computer-readable storage medium storing a computer program or instructions, characterized in that, The computer program or instructions are programmed or configured to execute the low-power state logic synthesis method of any one of claims 1 to 6 via a processor.

9. A computer program product, comprising a computer program or instructions, characterized in that, The computer program or instructions are programmed or configured to execute the low-power state logic synthesis method of any one of claims 1 to 6 via a processor.

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