Memory device and driving method thereof

Abstract

A memory device and a method of driving the memory device are provided. The memory device includes a substrate, a channel layer on one surface of the substrate and including a semiconductor oxide, a gate electrode on the channel layer, a storage layer between the channel layer and the gate electrode, an electrolyte layer between the channel layer and the storage layer, and a gate oxide layer between the gate electrode and the storage layer, wherein the storage layer is capable of transferring oxygen vacancies in the storage layer to the channel layer or receiving oxygen vacancies transferred from the channel layer according to a voltage applied to the gate electrode, and a thickness of the electrolyte layer is less than 5 nm.

Description

Technical Field

[0001] This disclosure relates to storage devices and driving methods thereof. Background Technology

[0002] The manufacturing technology of NAND flash memory devices is developing towards improving the integration density, operating speed, and / or yield of semiconductor memory devices. To further enhance the integration of semiconductor memory devices, vertical NAND (VNAND) flash memory devices have been proposed.

[0003] NAND flash memory devices, including vertical NAND flash memory devices, implement memory functionality using the charge-trapped flash (CTF) method, which applies a voltage to the gate electrode to move electrons present in the channel layer to the trap layer via tunneling. However, the CTF method requires a relatively high voltage to be applied to the gate electrode, which leads to interference problems between unit cells, thus limiting the reduction of the thickness of the gate electrode and / or the trap layer.

[0004] Meanwhile, an electrochemical random access memory (ECRAM) device is known to realize memory function by applying a voltage to the gate electrode and moving ions present in the channel layer to change the conductivity and / or threshold voltage of the channel layer. Summary of the Invention

[0005] Some exemplary embodiments of this disclosure provide memory devices and / or methods for driving memory devices that improve upon charge-trap flash memory (CTF) methods, which are prone to technical problems due to interference between unit cells, by borrowing the operating principles of electrochemical random access memory devices. These memory devices are able to achieve memory functionality and / or increase integration density even when a relatively small voltage is applied to the gate electrode.

[0006] The effects of this disclosure are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

[0007] According to an exemplary embodiment of the present disclosure, a memory device may include a substrate, a channel layer on one surface of the substrate and including a semiconductor oxide, a gate electrode on the channel layer, a storage layer between the channel layer and the gate electrode, an electrolyte layer between the channel layer and the storage layer, and a gate oxide layer between the gate electrode and the storage layer, wherein the storage layer is capable of transferring oxygen vacancies in the storage layer to the channel layer or receiving oxygen vacancies transferred from the channel layer according to a voltage applied to the gate electrode, and the thickness of the electrolyte layer is less than 5 nm.

[0008] According to an exemplary embodiment of this disclosure, a method for driving a memory device is provided. The memory device includes a substrate, a channel layer comprising a semiconductor oxide on one surface of the substrate, a gate electrode on the channel layer, a storage layer between the channel layer and the gate electrode, an electrolyte layer between the channel layer and the storage layer and having a thickness of less than 5 nm, and a gate oxide layer between the gate electrode and the storage layer. The method may include: when a voltage is applied to the gate electrode, transferring oxygen vacancies present in the storage layer to the channel layer or transferring oxygen vacancies present in the channel layer to the gate electrode, such that the conductivity of the channel layer and the threshold voltage (V) are equal. th The conductivity and threshold voltage (V) of the channel layer are changed to be different from those before the voltage is applied to the gate electrode. th Furthermore, write or erase operations are performed when the conductivity and threshold voltage of the channel layer change.

[0009] Details of other example implementations are included in the specific implementation and the accompanying drawings. Attached Figure Description

[0010] The accompanying drawings illustrate some exemplary embodiments of this disclosure, and the ratios of the width, height, or thickness of each component are used to describe the disclosure in detail, and these ratios may differ from actual ratios. Furthermore, each component shown in the drawings may be exaggerated to describe the disclosure in detail. Additionally, in the coordinate system shown in the drawings, each axis may be perpendicular to the other axes, the direction in which the arrow points may be a positive direction, and the direction opposite to the direction in which the arrow points (the direction of 180 degrees rotation) may be a negative direction, as shown in the drawings:

[0011] Figure 1 At least a portion of a storage device according to an exemplary embodiment of the present disclosure is illustrated schematically;

[0012] Figure 2 It shows along Figure 1 A cross-sectional view of line AA';

[0013] Figure 3 It shows along Figure 1 A cross-sectional view taken from line B-B';

[0014] Figure 4 yes Figure 1 A magnified view of part P in the image;

[0015] Figure 5 At least a portion of a storage device according to an exemplary embodiment of the present disclosure is illustrated schematically;

[0016] Figure 6 It shows along Figure 5 A cross-sectional view taken from line C-C';

[0017] Figure 7 yes Figure 5 A magnified view of part of Q in the image;

[0018] Figure 8 At least a portion of a storage device according to an exemplary embodiment of the present disclosure is illustrated schematically;

[0019] Figure 9 At least a portion of a storage device according to an exemplary embodiment of the present disclosure is illustrated schematically;

[0020] Figures 10 to 13 At least a portion of the storage device is schematically shown to describe a method of driving the storage device according to an exemplary embodiment of the present disclosure;

[0021] Figure 14 This is a perspective view schematically showing at least a portion of a storage device according to an exemplary embodiment of the present disclosure;

[0022] Figure 15 It is along Figure 14 A cross-sectional view taken from line D-D';

[0023] Figure 16 and Figure 17 This illustrates the drain-source current (Id) of a memory device according to some examples of this disclosure. DS ) relative to the gate-source voltage (V GS A graph showing the characteristics of ).

[0024] Figure 18 and Figure 19 This illustrates the drain-source current (Id) of a memory device according to some examples of this disclosure. DS ) relative to the gate-source voltage (V GS A graph showing the characteristics of ).

[0025] Figure 20 It is a graph showing the characteristics of the current relative to the number of times the voltage is applied in pulses when a voltage is applied to the gate electrode in an example of a memory device according to the present disclosure.

[0026] Figure 21 This illustrates the drain-source current (Id) in the memory device according to Comparative Example 1. DS ) relative to the gate-source voltage (V GS A graph showing the characteristics of ) and

[0027] Figure 22 This illustrates the drain-source current (Id) in the memory device according to Comparative Example 2. DS ) relative to the gate-source voltage (V GS A graph showing the characteristics of ). Detailed Implementation

[0028] Although the terms “identical,” “equal,” or “same” are used in the description of the exemplary embodiments, it should be understood that some imprecision may exist. Therefore, when one element is referred to as being identical to another element, it should be understood that the element is identical to the other element within a desired range of manufacturing or operational tolerances (e.g., ±10%).

[0029] When the terms “about,” “substantially,” or “approximately” are used in conjunction with numerical values ​​in this specification, the numerical values ​​intended to be associated include manufacturing or operational tolerances (e.g., ±10%) around said numerical value. Furthermore, when the terms “about,” “substantially,” or “approximately” are used in conjunction with geometry, it is intended that the precision of the geometry is not required, but rather the tolerance of the shape is within the scope of this disclosure. Moreover, regardless of whether a numerical value or shape is modified with “about” or “substantially,” it should be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around said numerical value or shape.

[0030] As used herein, when expressions such as “one of…”, “any one of…”, “at least one of…”, and “one or more of…” follow a list of elements, they modify the entire list of elements, not individual elements within the list. Thus, for example, “at least one of A, B, or C” and “at least one of A, B, and C” both mean A, B, C, or any combination thereof. Similarly, A and / or B means A, B, or A and B.

[0031] Figure 1 At least a portion of a storage device 100 according to an exemplary embodiment of the present disclosure is shown schematically. Figure 2 It shows along Figure 1 A cross-sectional view taken from line A-A'. Figure 3 It shows along Figure 1 The cross-sectional view taken by line B-B'. Figure 4 yes Figure 1 A magnified view of part P in the image.

[0032] The storage device 100 according to an exemplary embodiment of this disclosure may be, for example, a non-volatile storage device. In one example, the non-volatile storage device may be flash memory, read-only memory (ROM), hard disk, floppy disk drive, magnetic tape, or optical disk, but is not limited thereto. In one example, the non-volatile storage device may be flash memory. In one example, the flash memory may be NAND flash memory, and specifically, it may be vertical NAND flash memory. In one example, storage device 100 may be a vertical NAND flash memory device.

[0033] The memory device 100 according to an exemplary embodiment of the present disclosure may include a substrate 101, a gate electrode 120, a gate oxide layer 130, a storage layer 140, an electrolyte layer 150, and a channel layer 160.

[0034] The substrate 101 according to the exemplary embodiments of this disclosure is not particularly limited, but may be a silicon semiconductor substrate, a plastic substrate, a glass substrate, a compound semiconductor substrate, a ceramic substrate, or a silicon-on-insulator (SOI) substrate. In one example, although not shown separately, the substrate 101 may include impurity regions due to doping, peripheral circuitry for selecting and / or controlling electronic components such as transistors or memory cells, etc. In one example, a gate electrode 120, a gate oxide layer 130, a storage layer 140, an electrolyte layer 150, and a channel layer 160 may be disposed on the surface 101S of the substrate.

[0035] In this specification, the first direction D1 can be a direction parallel to the surface 101S of the substrate, such as... Figure 1 As shown. The second direction D2 can refer to the direction intersecting with the first direction D1, and specifically, the second direction D2 can be a direction perpendicular to the substrate surface 101S and intersecting with the first direction D1. The third direction D3 can be as follows: Figure 1 The direction shown intersects with the first direction D1, but is parallel to the surface 101S of the substrate.

[0036] According to an exemplary embodiment of this disclosure, the gate electrode 120 can be electrically connected to a word line. In one example, the gate electrode 120 may include a metallic material, a metal nitride, or silicon doped with impurities, having relatively high conductivity. In one example, as a metallic material having relatively high conductivity, the gate electrode 120 may include one or more of, but is not limited to, materials selected from the group consisting of gold (Au), silver (Ag), aluminum (Al), titanium (Ti), indium (In), cadmium (Cd), copper (Cu), zinc (Zn), tantalum (Ta), and / or tungsten (W).

[0037] According to an exemplary embodiment of the present disclosure, the gate electrode 120 may be disposed on the channel layer 160. In one example, the gate electrode 120 may surround at least a portion of the channel layer 160. In one example, there may be a plurality of gate electrodes 120, with adjacent gate electrodes 120 spaced apart from each other in the second direction D2.

[0038] The storage device 100 according to an exemplary embodiment of the present disclosure may include an insulating layer 110. In one example, the insulating layer 110 may surround at least a portion of the channel layer 160. In one example, the insulating layer 110 may include an insulating material. For example, the insulating material is not particularly limited as long as it has electrical insulating properties, but may include one or more selected from the group consisting of silicon oxides, silicon nitrides, and / or silicon nitrides.

[0039] According to an exemplary embodiment of this disclosure, a plurality of insulating layers 110 may be present, and adjacent insulating layers 110 may be spaced apart from each other in the second direction D2. In one example, the insulating layers 110 may be configured such that the space between adjacent gate electrodes 120 is filled with the insulating layer. In one example, when viewed in the second direction D2, the insulating layers 110 may overlap with the gate electrodes 120 at least in a partial region.

[0040] refer to Figure 1 In one example, the insulating layer 110 and the gate electrode 120 may be stacked alternately on top of each other, and the insulating layer 110 and the gate electrode 120 may be in contact with each other in the second direction D2. (See reference) Figure 2 The insulating layer 110 may surround at least a portion of the channel layer 160. (See reference) Figure 3 The gate electrode 120 may surround at least a portion of the channel layer 160.

[0041] According to an exemplary embodiment of the present disclosure, the channel layer 160 may be disposed on a surface 101S of a substrate. In one example, the channel layer 160 may extend along a second direction D2.

[0042] The channel layer 160 according to an exemplary embodiment of the present disclosure may include a semiconductor oxide. In one example, the channel layer 160 may be a semiconductor oxide and includes one or more oxides selected from the group consisting of tantalum (Ta), hafnium (Hf), aluminum (Al), zinc (Zn), tungsten (W), vanadium (V), titanium (Ti), niobium (Nb), silicon (Si), germanium (Ge), arsenic (As), tellurium (Te), antimony (Sb), gallium (Ga), indium (In), zirconium (Zr), tin (Sn), and / or nickel (Ni). In one example, the channel layer 160 may include indium gallium zinc oxide (IGZO). However, this is not the only possibility; the channel layer 160 may include indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO), tungsten oxide (WO), indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), magnesium zinc oxide (MgZnO), and indium zinc oxide (InZnO). It is one or more of the following: indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and / or indium gallium silicon oxide (InGaSiO). In one example, the channel layer 160 may include oxygen vacancies.

[0043] A storage layer 140 according to an exemplary embodiment of this disclosure may be disposed between a channel layer 160 and a gate electrode 120. In one example, the storage layer 140 may include oxygen vacancies. In one example, the storage layer 140 may receive or transfer oxygen vacancies from the channel layer 160 depending on a voltage applied to the gate electrode 120. In other words, the storage layer may be able to transfer oxygen vacancies therein to the channel layer or receive oxygen vacancies transferred from the channel layer depending on a voltage applied to the gate electrode. That is, depending on the voltage applied to the gate electrode 120, the storage layer 140 may include oxygen vacancies to be transferred to or transferred from the channel layer 160. In this specification, the movement of oxygen vacancies is performed in the opposite direction to the movement of oxygen ions, and the ions present in the channel layer 160 may be, for example, oxygen ions. In one example, storage layer 140 may exchange oxygen vacancies with channel layer 160, and the conductivity and / or threshold voltage of channel layer 160 may be varied depending on the degree of oxygen vacancy exchange.

[0044] Storage layer 140 according to an exemplary embodiment of this disclosure may include an oxide having a metal-oxygen bond. In one example, the oxide having a metal-oxygen bond included in storage layer 140 may be an oxide of one or more of the metal elements selected from the group consisting of hafnium (Hf), cerium (Ce), tantalum (Ta), gallium (Ga), nickel (Ni), aluminum (Al), zinc (Zn), tungsten (W), vanadium (V), titanium (Ti), niobium (Nb), germanium (Ge), arsenic (As), tellurium (Te), antimony (Sb), indium (In), zirconium (Zr), and / or tin (Sn), but is not limited thereto. In one example, the oxide having a metal-oxygen bond included in storage layer 140 may include a single metal oxide in which one metal element selected from the above-mentioned metal element group is bonded to oxygen, or a composite metal oxide in which two or more metal elements selected from the above-mentioned metal element group are bonded to oxygen. In one example, the oxide containing a metal-oxygen bond included in storage layer 140 may include one or more selected from the group consisting of hafnium oxide, cerium oxide, tantalum oxide, gallium oxide and / or nickel oxide.

[0045] According to an exemplary embodiment of this disclosure, the storage layer 140 can transfer oxygen vacancies to the channel layer 160 when a positive voltage is applied to the gate electrode 120. In one example, oxygen vacancies can be transferred from the channel layer 160 when a negative voltage is applied to the gate electrode 120. During this process, the storage layer 140 can exchange oxygen vacancies with the channel layer 160, and the conductivity and / or threshold voltage of the channel layer 160 changes depending on the degree of oxygen vacancies exchange. Details will be described below.

[0046] According to an exemplary embodiment of this disclosure, the electrolyte layer 150 may be disposed between the channel layer 160 and the storage layer 140. In one example, the electrolyte layer 150 may allow oxygen vacancies to pass smoothly through, depending on the voltage applied to the gate electrode 120, such that oxygen vacancies are transferred from the channel layer 160 to the storage layer 140 or from the storage layer 140 to the channel layer 160. That is, the electrolyte layer 150 may allow oxygen vacancies to pass through, either from the storage layer 140 to the channel layer 160 or from the channel layer 160 to the storage layer 140, depending on the voltage applied to the gate electrode 120. In one example, the electrolyte layer 150 may allow the channel layer 160 and the storage layer 140 to exchange oxygen vacancies smoothly with each other, and the conductivity and / or threshold voltage of the channel layer 160 may be varied according to the degree of oxygen vacancies exchange.

[0047] According to an exemplary embodiment of this disclosure, the concentration of oxygen vacancies in the storage layer 140 can be higher than the concentration of oxygen vacancies in the electrolyte layer 150. Therefore, oxygen vacancies in the storage layer 140 can be readily transferred through the electrolyte layer 150 to the channel layer 160. The concentration of oxygen vacancies can be calculated, for example, as the ratio of the amount of oxygen (O) actually bonded to the metals included in the storage layer 140 to the number of bondable sites of oxygen (O) calculated by multiplying the valence of the metal by the amount of the corresponding metal, but is not limited thereto.

[0048] The thickness T1 of the electrolyte layer 150 according to an exemplary embodiment of this disclosure may be less than about 5 nanometers (nm), about 4.9 nm or less, about 4.8 nm or less, about 4.7 nm or less, about 4.6 nm or less, about 4.5 nm or less, about 4.4 nm or less, about 4.3 nm or less, about 4.2 nm or less, about 4.1 nm or less, or 4 nm or less. In one example, the thickness T1 of the electrolyte layer 150 may refer to... Figure 4 The electrolyte layer 150 has a length along the first direction D1. In one example, the thickness T1 of the electrolyte layer 150 can be greater than or equal to the minimum thickness that can be deposited, for example, by atomic layer deposition (ALD). In one example, the thickness T1 of the electrolyte layer 150 can be about 0.1 nm or greater. In one example, when the thickness T1 of the electrolyte layer 150 meets the above range, oxygen vacancies can be smoothly exchanged between the channel layer 160 and the storage layer 140, and the conductivity and threshold voltage of the channel layer 160 can be changed according to the degree of oxygen vacancy exchange, thereby realizing the memory function.

[0049] Meanwhile, in one example, in addition to atomic layer deposition (ALD) method, the remaining layers of the layers constituting the storage device 100, other than the electrolyte layer 150, can be formed by chemical vapor deposition (CVD) method or physical vapor deposition (PVD) method.

[0050] According to the exemplary embodiments of this disclosure, the sum of the thicknesses T2 of the storage layer 140, electrolyte layer 150, and gate oxide layer 130 can be about 30 nm or less, about 29 nm or less, about 28 nm or less, about 27 nm or less, about 26 nm or less, or about 25 nm or less, but is not limited thereto. In one example, when the sum of the thicknesses T2 of the storage layer 140, electrolyte layer 150, and gate oxide layer 130 satisfies the above ranges, memory functionality can be achieved, and integration density can be increased. In one example, the thicknesses T3 of the storage layer 140, T1 of the electrolyte layer 150, and the gate oxide layer 130 can refer to... Figure 4 The length of each component along the first direction D1.

[0051] According to an exemplary embodiment of this disclosure, the ratio T1 / T2 of the thickness T1 of the electrolyte layer 150 to the sum T2 of the thicknesses T2 of the storage layer 140, the electrolyte layer 150, and the gate oxide layer 130 can be about 0.3 or less, about 0.29 or less, about 0.28 or less, about 0.27 or less, about 0.26 or less, or about 0.25 or less, but is not limited thereto. In one example, when the ratio T1 / T2 meets the above range, the memory function of the memory device 100 can be realized, and the integration density can be improved.

[0052] According to an exemplary embodiment of this disclosure, the thickness T1 of the electrolyte layer 150 can be thinner than the thickness T3 of the storage layer 140. Therefore, oxygen vacancies can easily move from the electrolyte layer 150 to the storage layer 140 and the channel layer 160. In other words, oxygen vacancies can move relatively easily between the storage layer 140 and the channel layer 160 via the electrolyte layer 150.

[0053] According to an exemplary embodiment of this disclosure, the ratio T1 / T3 of the thickness T1 of the electrolyte layer 150 to the thickness T3 of the storage layer 140 can be about 0.5 or less, about 0.45 or less, about 0.4 or less, about 0.35 or less, about 0.3 or less, about 0.25 or less, about 0.2 or less, about 0.15 or less, or about 0.1 or less, but is not limited thereto. In one example, when the ratio T1 / T3 meets the above ranges, the memory function of the storage device 100 can be realized, and the integration density can be improved.

[0054] The electrolyte layer 150 according to an exemplary embodiment of this disclosure may include an oxide having a metal-oxygen bond. In one example, the oxide having a metal-oxygen bond included in the electrolyte layer 150 may be an oxide of one or more of the metal elements selected from the group consisting of hafnium (Hf), cerium (Ce), tantalum (Ta), gallium (Ga), nickel (Ni), aluminum (Al), zinc (Zn), tungsten (W), vanadium (V), titanium (Ti), niobium (Nb), germanium (Ge), arsenic (As), tellurium (Te), antimony (Sb), indium (In), zirconium (Zr), and / or tin (Sn), but is not limited thereto. In one example, the oxide having a metal-oxygen bond included in the electrolyte layer 150 may include a single metal oxide in which one metal element selected from the above-mentioned metal element group is bonded to oxygen, or a composite metal oxide in which two or more metal elements selected from the above-mentioned metal element group are bonded to oxygen. In one example, the oxide containing a metal-oxygen bond included in the electrolyte layer 150 may include one or more selected from the group consisting of hafnium oxide, cerium oxide, tantalum oxide, gallium oxide, nickel oxide and / or aluminum oxide.

[0055] According to an exemplary embodiment of this disclosure, the oxygen concentration of the electrolyte layer 150 can be higher than that of the storage layer 140. Therefore, when oxygen vacancies are exchanged between the storage layer 140 and the channel layer 160, the trapping of oxygen vacancies in the electrolyte layer 150 can be reduced or prevented, thereby achieving the memory function.

[0056] According to an exemplary embodiment of the present disclosure, a gate oxide layer 130 may be disposed between a gate electrode 120 and a storage layer 140. In one example, the gate oxide layer 130 may include an oxide having a metal-oxygen bond. In one example, the oxide having a metal-oxygen bond included in the gate oxide layer 130 may be an oxide comprising, but is not limited to, one or more of the metal elements selected from the group consisting of tantalum (Ta), hafnium (Hf), aluminum (Al), zinc (Zn), tungsten (W), vanadium (V), titanium (Ti), niobium (Nb), germanium (Ge), arsenic (As), tellurium (Te), antimony (Sb), gallium (Ga), indium (In), zirconium (Zr), tin (Sn), and / or nickel (Ni). In one example, the oxide having a metal-oxygen bond included in the gate oxide layer 130 may include a single metal oxide in which one metal element selected from the above-mentioned metal element group is bonded to oxygen, or a composite metal oxide in which two or more metal elements selected from the above-mentioned metal element group are bonded to oxygen.

[0057] The storage device 100 according to an exemplary embodiment of the present disclosure may include a source electrode 200 and a drain electrode 300. In one example, a channel layer 160 may be electrically connected to the source electrode 200 and the drain electrode 300.

[0058] In one example, reference Figure 1The source electrode 200 and drain electrode 300 may be spaced apart from each other in the second direction D2. In one example, the source electrode 200 and drain electrode 300 may each independently comprise a conductive material. In one example, the conductive material may comprise one or more selected from the group consisting of doped polysilicon, metals, conductive metal nitrides, conductive metal silicides, and / or conductive metal oxides. In one example, the metal may comprise one or more selected from the group consisting of aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), rubidium (Ru), tungsten (W), molybdenum (Mo), platinum (Pt), nickel (Ni), and / or cobalt (Co). In one example, the conductive metal nitride may comprise one or more selected from TiAl or TiAlN. In one example, the conductive metal silicide may comprise one or more selected from the group consisting of TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, and / or CoSi. In one example, the conductive metal oxide may comprise one or more selected from IrOx and / or RuOx.

[0059] Figure 5 This is a schematic illustration of at least a portion of a storage device 100' according to an exemplary embodiment of the present disclosure. Figure 6 It shows along Figure 5 A cross-sectional view taken from line C-C'. Figure 7 yes Figure 5 A magnified view of part Q in the image. Figures 5 to 7 The content can be referenced. Figures 1 to 4 The descriptions, unless they contradict each other.

[0060] The storage device 100' according to an exemplary embodiment of the present disclosure may include a fill layer 170 surrounded by a channel layer 160. In one example, the fill layer 170 may include an insulating material, and the insulating material included in the fill layer 170 may include one or more selected from the group consisting of, for example, air, silicon oxide, silicon nitride and / or silicon nitride.

[0061] Figure 8 and Figure 9 At least a portion of a storage device according to some example embodiments of this disclosure is schematically shown. Figures 1 to 7 The storage devices 100 and 100' shown are different. Figure 8 and Figure 9 The memory device shown may have a channel layer 160 and a substrate 101 arranged parallel to each other. Below, Figure 8 and Figure 9 The content can be referenced. Figures 1 to 7 The descriptions, unless they contradict each other.

[0062] Figures 1 to 7The gate electrode 120 shown in the example embodiment of the present disclosure can be disposed between the substrate 101 and the channel layer 160 as described above. (See reference...) Figure 8 and Figure 9 In some example embodiments, the gate electrode 120 may be disposed parallel to at least a portion of the channel layer 160, the channel layer 160 may be disposed parallel to the substrate 101, and / or the channel layer 160 may be disposed parallel to the substrate 101 along a first direction D1.

[0063] A memory device according to an exemplary embodiment of the present disclosure may include a source electrode 200 and a drain electrode 300. In one example, the source electrode 200 and the drain electrode 300 may be spaced apart from each other in a first direction D1. For example, the source electrode 200 and the drain electrode 300 may be disposed on the channel layer 160 and / or within the substrate 101. Reference Figure 8 and Figure 9 , Figures 1 to 7 The thickness T1 of the electrolyte layer 150 described herein may refer to the length of the electrolyte layer 150 along the second direction D2, and the thickness T3 of the storage layer 140 and the thickness of the gate oxide layer 130 may refer to the length of each component along the second direction D2.

[0064] Figures 10 to 13 schematically shown Figure 1 At least a portion of the storage device 100 is used to describe a method of driving the storage device 100 according to an exemplary embodiment of the present disclosure.

[0065] In a method for driving a memory device 100 according to an exemplary embodiment of the present disclosure, when a voltage is applied to the gate electrode 120, the channel layer 160 and the storage layer 140 can exchange oxygen vacancies Ov with each other. In one example, when a voltage is applied to the gate electrode 120, oxygen vacancies present in the storage layer 140 can be transferred to the channel layer 160, or oxygen vacancies present in the channel layer 160 can be transferred to the storage layer 140. Thus, the conductivity and threshold voltage of the channel layer 160 can differ from those of the channel layer 160 before the voltage is applied to the gate electrode 120.

[0066] In one example, when a voltage is applied to the gate electrode 120, the electrolyte layer 150 allows oxygen vacancies to pass through smoothly, enabling oxygen vacancies to be transferred from the channel layer 160 to the storage layer 140 or from the storage layer 140 to the channel layer 160.

[0067] In one example, when a voltage is applied to the gate electrode 120, the gate oxide layer 130 can allow the storage layer 140 to smoothly exchange oxygen vacancies with the channel layer 160 and reduce or prevent oxygen vacancies present in the storage layer 140 from being transferred to the gate electrode 120.

[0068] In one example, a method of driving the memory device 100 may include transferring oxygen vacancies Ov present in the storage layer 140 to the channel layer 160 or transferring oxygen vacancies Ov present in the channel layer 160 to the storage layer 140 when a voltage is applied to the gate electrode 120. In this case, the conductivity and threshold voltage of the channel layer 160 may be changed from those of the channel layer 160 before the voltage is applied to the gate electrode 120. Because the conductivity and threshold voltage of the channel layer 160 are different (e.g., changed), the method of driving the memory device 100 may include performing a write (or program) operation or an erase operation.

[0069] In one example, a method of driving the memory device 100 may include: when a positive voltage is applied to the gate electrode 120, transferring oxygen vacancies Ov from the storage layer 140 to the channel layer 160, and performing a write operation by the channel layer 160, through which the conductivity increases. Alternatively, a method of driving the memory device 100 may include: when the voltage changes from positive to negative and the changed voltage is applied to the gate electrode 120, transferring oxygen vacancies Ov from the channel layer 160 to the storage layer 140, and performing an erase operation, through which the conductivity of the channel layer 160 decreases as oxygen vacancies Ov present in the channel layer 160 are restored to the storage layer 140.

[0070] In one example, a method of driving the memory device 100 may include: when a negative voltage is applied to the gate electrode 120, transferring oxygen vacancies Ov from the channel layer 160 to the storage layer 140, and performing a write operation by the channel layer 160, through which the conductivity decreases. Alternatively, a method of driving the memory device 100 may include: when the voltage changes from negative to positive and the changed voltage is applied to the gate electrode 120, transferring oxygen vacancies Ov from the storage layer 140 to the channel layer 160, and performing an erase operation, through which the conductivity of the channel layer 160 increases as oxygen vacancies Ov present in the storage layer 140 are restored to the channel layer 160.

[0071] In one example, a method of driving the memory device 100 may include: when a voltage is applied to the gate electrode 120, at a threshold voltage V th When a change occurs, a write or erase operation is performed. In one example, the threshold voltage may change due to a variation in the conductivity of the channel layer 160. In one example, a method of driving the memory device 100 may include performing a write operation when a positive voltage is applied to the gate electrode 120, thereby lowering the threshold voltage. In one example, a method of driving the memory device 100 may include performing an erase operation when a negative voltage is applied to the gate electrode 120, thereby increasing the threshold voltage.

[0072] In one example, a method of driving the memory device 100 may include performing a read operation by applying a voltage to the gate electrode 120 to check the extent of oxygen vacancy Ov inclusion (i.e., the state of data) via the conductivity of the channel layer 160. Here, it may be desirable that the voltage applied to the gate electrode 120 is low enough that no movement of oxygen vacancy Ov occurs. Furthermore, in one example, the extent of oxygen vacancy Ov inclusion can be measured by a current-voltage curve through resistance and conductivity through the channel layer 160, and a read operation can be performed by measuring the extent of oxygen vacancy Ov inclusion. In one example, a method of driving the memory device 100 may include performing a read operation by applying a voltage to the gate electrode 120 to check the extent of oxygen vacancy Ov inclusion present in the channel layer 160 via the conductivity of the channel layer 160.

[0073] Figure 14 This is a perspective view schematically showing at least a portion of a storage device 100'' according to an exemplary embodiment of the present disclosure. Figure 15 It is along Figure 14 The cross-sectional view taken by line D-D'. Unless contradicted, the following description may be referenced to the preceding content. In one example, the storage device 100'' may have a structure similar to that of a capacitorless DRAM.

[0074] In one example, storage device 100'' may include a substrate 101 and an insulating layer 110 in contact with the substrate 101.

[0075] In one example, the storage device 100'' may include source electrodes 200 spaced apart from each other in a second direction D2, a drain electrode 300 spaced apart from the source electrodes 200 along a first direction D1, and a gate electrode 120 disposed between the source electrodes 200 and the drain electrodes 300. In one example, each of the source electrodes 200 and the drain electrodes 300 may extend along a third direction D3. In one example, the source electrode 200 may extend parallel to the drain electrode 300 along the third direction D3. In one example, the gate electrode 120 may intersect the source electrodes 200 and the drain electrodes 300. In one example, the gate electrode 120 may be spaced apart from each other in the third direction D3 between the source electrodes 200 and the drain electrodes 300, and may extend in the second direction D2.

[0076] In one example, the memory device 100'' may include a channel layer 160 surrounding a side surface of each of the gate electrodes 120. In one example, the channel layer 160 may surround the side surface of the respective gate electrode 120 and may be spaced apart from the gate electrode 120 in a first direction D1. In one example, the channel layer 160 may be disposed between the source electrode 200 and the drain electrode 300. In one example, the source electrode 200 and the drain electrode 300 may each be electrically connected to the channel layer 160.

[0077] In one example, memory device 100'' may include a storage layer 140 disposed between gate electrode 120 and channel layer 160. In one example, memory device 100'' may include an electrolyte layer 150 disposed between channel layer 160 and storage layer 140. In one example, memory device 100'' may include a gate oxide layer 130 disposed between gate electrode 120 and storage layer 140.

[0078] The present application is further described below with reference to specific examples. The examples and comparative examples are intended to illustrate the application only and not to limit the scope of the appended claims. It will be apparent to those skilled in the art that various changes and modifications can be made to the examples within the scope and technical concept of the present application. Such changes and modifications should be included within the scope of the appended claims.

[0079] Example

[0080] Manufacturing with such Figure 1 The memory device 100 shown includes: a channel layer 160 comprising IGZO, an electrolyte layer 150 comprising hafnium oxide, a storage layer 140 comprising hafnium oxide, and a gate oxide layer 130 comprising aluminum oxide (AlO). The electrolyte layer 150 has a thickness T1 of approximately 1 nm, the storage layer 140 has a thickness T3 of approximately 8 nm, and the gate oxide layer 130 has a thickness of approximately 10 nm. The electrolyte layer 150, the storage layer 140, and the gate oxide layer 130 are formed using atomic layer deposition (ALD).

[0081] Comparison Example 1

[0082] The storage device is manufactured in the same manner as in the example above, except that the electrolyte layer 150 is omitted.

[0083] Comparison Example 2

[0084] The memory device is manufactured in the same manner as in the example above, except that the electrolyte layer 150 is deposited with a thickness of 5 nm at T1.

[0085] Evaluation Example

[0086] The drain-source current I is shown.DS relative to the gate-source voltage V GS The characteristic curve (0 to +3V) is obtained by varying the magnitude of the voltage applied to the gate electrode 120 and the drain-source voltage V. DS This was created by repeatedly applying a voltage to the gate electrode 120 of the example memory device 100 ten times at a pulse of 20ms while maintaining a voltage of 3V, and the result is... Figure 16 and Figure 17 As shown in the image.

[0087] refer to Figure 16 It can be confirmed that the threshold voltage V is achieved when 5V, 6V, and 7V are applied to the gate electrode 120. th The increase can be interpreted as electrons existing in the channel layer moving to the storage layer and the charge-trapped flash memory (CTF) phenomenon occurring.

[0088] refer to Figure 17 It can be confirmed that when 8V is applied to the gate electrode 120, the threshold voltage V th The decrease can be interpreted as indicating that oxygen vacancies present in the storage layer are being transferred to the channel layer via electrochemical (EC) properties.

[0089] The gate-source voltage V of the example memory device 100 was measured. GS Drain-source current I (-6V to +6V) DS The characteristics of the drain-source voltage V. DS A graph was created after performing one and ten voltage sweeps under the above conditions while maintaining a voltage of 3V, and the results were... Figure 18 and Figure 19 As shown in the image.

[0090] refer to Figure 18 It can be confirmed that the write and erase operations of the storage device 100 are possible.

[0091] refer to Figure 19 It can be confirmed that repeated write and erase operations of the storage device 100 are possible.

[0092] When a positive voltage is applied to the gate electrode 120 of the memory device 100 of the example embodiment at a pulse of 0.64 ms for 5 or 10 times under the above conditions, and a negative voltage is applied at a pulse of 20 ms for 8, 10, or 40 times, a drain-source voltage V is created. DS While maintaining 3V, apply V GS (+0.6V) to read current I DS A graph obtained relative to the number of pulsed voltages applied, and the results are in Figure 20 As shown in the image.

[0093] refer to Figure 20 It can be confirmed that repeated write and erase operations of the storage device 100 are possible.

[0094] The drain-source current I is shown. DS relative to the gate-source voltage V GS The characteristic curve (0 to +3V) is obtained by varying the magnitude of the voltage applied to the gate electrode 120 and the drain-source voltage V. DS The device was created by repeatedly applying a voltage to the gate electrode of the memory device 100 of Comparative Example 1 ten times at a pulse of 20ms while maintaining a voltage of 3V, and the result was... Figure 21 As shown in the image.

[0095] refer to Figure 21 It can be confirmed that the threshold voltage V is achieved when 5V and 6V are applied to the gate electrode 120. th Increase. However, when 7V was applied, memory device 100 broke down. No threshold voltage V was observed prior to breakdown. th The reduction. When the memory device 100 does not include the electrolyte layer 150, the memory function may not be realized because the channel layer 160 and the storage layer 140 only exchange electrons and do not exchange oxygen vacancies, and the memory device 100 may break down before the exchange of oxygen vacancies between the channel layer 160 and the storage layer 140 occurs, even when the voltage applied to the gate electrode 120 is gradually increased.

[0096] The drain-source current I is shown. DS relative to the gate-source voltage V GS The characteristic curve (0 to +3V) is obtained by varying the magnitude of the voltage applied to the gate electrode 120 and the drain-source voltage V. DS The memory device 100 of Comparative Example 2 was created by repeatedly applying a voltage to its gate electrode ten times at a pulse of 20ms per second while maintaining a voltage of 3V, and the result is... Figure 22 As shown in the image.

[0097] refer to Figure 22 It can be confirmed that when 5V to 13V is applied to the gate electrode 120, the threshold voltage V th Further, it was confirmed that the storage device 100 of Comparative Example 2 broke down at a higher voltage of 14V compared to Comparative Example 1. However, as with Comparative Example 1, the phenomenon of a decrease in the threshold voltage Vth prior to breakdown was not confirmed.

[0098] Some exemplary embodiments of this disclosure can provide memory devices that enable memory functionality and / or increase integration density even when a relatively small voltage is applied to the gate electrode, as well as driving methods for the memory devices.

[0099] The effects of this disclosure are not limited to those mentioned above, and those skilled in the art will clearly understand from the above description other effects not mentioned.

[0100] This disclosure is not limited to the exemplary embodiments disclosed, and can be made in various different forms. Those skilled in the art will understand that additional or alternative exemplary embodiments may be implemented in other specific forms without departing from the technical spirit or essential characteristics of this disclosure. Therefore, it should be understood that the above exemplary embodiments are intended to be illustrative in all respects and not restrictive.

[0101] Related Application This application claims priority to Korean Patent Application No. 10-2024-0130273, filed on September 25, 2024, the contents of which are incorporated herein by reference in their entirety.

Claims

1. A storage device, comprising: Substrate; A trench layer on one surface of the substrate, the trench layer comprising a semiconductor oxide; The gate electrode is located on the channel layer. A storage layer is disposed between the channel layer and the gate electrode; An electrolyte layer is located between the channel layer and the storage layer; as well as A gate oxide layer is located between the gate electrode and the storage layer. The storage layer is capable of transferring oxygen vacancies from the storage layer to the channel layer or receiving oxygen vacancies transferred from the channel layer, depending on the voltage applied to the gate electrode. The thickness of the electrolyte layer is less than 5 nm.

2. The storage device according to claim 1, wherein When the first direction refers to a direction parallel to one surface of the substrate, the channel layer extends along a second direction intersecting the first direction. The gate electrode surrounds at least a portion of the channel layer.

3. The storage device according to claim 2, further comprising: The source and drain electrodes are electrically connected to the channel layer. The source electrode and the drain electrode are spaced apart from each other in the second direction.

4. The storage device according to claim 2, further comprising: An insulating layer, when viewed in the second direction, overlaps with the gate electrode in at least a partial region, and the insulating layer surrounds at least a portion of the channel layer.

5. The storage device according to claim 4, wherein The gate electrode includes multiple gate electrodes. Adjacent pairs of gate electrodes in the plurality of gate electrodes are spaced apart from each other in the second direction, and The insulating layer fills the space between adjacent pairs of gate electrodes in the plurality of gate electrodes.

6. The memory device of claim 1, wherein the channel layer is parallel to the substrate.

7. The storage device according to claim 6, further comprising: The source and drain electrodes are electrically connected to the channel layer. The source electrode and the drain electrode are spaced apart from each other in a first direction parallel to one surface of the substrate.

8. The memory device of claim 1, wherein the storage layer is capable of transferring the oxygen vacancy to the channel layer when a positive voltage is applied to the gate electrode, and receiving the oxygen vacancy from the channel layer when a negative voltage is applied to the gate electrode.

9. The memory device of claim 1, wherein the sum of the thicknesses of the storage layer, the electrolyte layer, and the gate oxide layer is 30 nanometers (nm) or less.

10. The memory device of claim 1, wherein the ratio (T1 / T2) of the thickness (T1) of the electrolyte layer to the sum of the thicknesses (T2) of the storage layer, the electrolyte layer and the gate oxide layer is 0.3 or less.

11. The storage device of claim 1, wherein the thickness of the electrolyte layer is thinner than the thickness of the storage layer.

12. The storage device of claim 1, wherein the storage layer and the electrolyte layer each independently comprise an oxide having a metal-oxygen bond, the oxide comprising one or more elements selected from the group consisting of hafnium (Hf), cerium (Ce), tantalum (Ta), gallium (Ga), nickel (Ni), aluminum (Al), zinc (Zn), tungsten (W), vanadium (V), titanium (Ti), niobium (Nb), silicon (Si), germanium (Ge), arsenic (As), tellurium (Te), antimony (Sb), indium (In), zirconium (Zr), and tin (Sn).

13. The memory device of claim 1, wherein the gate oxide layer comprises an oxide having a metal-oxygen bond, the oxide comprising one or more metals selected from the group consisting of tantalum (Ta), hafnium (Hf), aluminum (Al), zinc (Zn), tungsten (W), vanadium (V), titanium (Ti), niobium (Nb), germanium (Ge), arsenic (As), tellurium (Te), antimony (Sb), gallium (Ga), indium (In), zirconium (Zr), tin (Sn), and nickel (Ni).

14. The memory device of claim 1, wherein the channel layer comprises a semiconductor oxide, the semiconductor oxide comprising one or more of the following: tantalum (Ta), hafnium (Hf), aluminum (Al), zinc (Zn), tungsten (W), vanadium (V), titanium (Ti), niobium (Nb), silicon (Si), germanium (Ge), arsenic (As), tellurium (Te), antimony (Sb), gallium (Ga), indium (In), zirconium (Zr), tin (Sn), and nickel (Ni).

15. The memory device of claim 14, wherein the channel layer comprises selected from indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO), tungsten oxide (WO), indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), magnesium zinc oxide (MgZnO), indium zinc oxide (IWO), etc. It is one or more of the following: InZnO, InGaZnO, ZrInZnO, HfInZnO, SnInZnO, AlSnInZnO, SiInZnO, ZnSnO, AlZnSnO, GaZnSnO, ZrZnSnO, and InGaSiO.

16. The storage device of claim 1, wherein the oxygen concentration of the electrolyte layer is higher than the oxygen concentration of the storage layer.

17. A method of driving a memory device, the memory device comprising a substrate, a channel layer comprising a semiconductor oxide on one surface of the substrate, a gate electrode on the channel layer, a storage layer between the channel layer and the gate electrode, an electrolyte layer between the channel layer and the storage layer and having a thickness of less than 5 nm, and a gate oxide layer between the gate electrode and the storage layer, the method comprising: When a voltage is applied to the gate electrode, oxygen vacancies present in the storage layer are transferred to the channel layer, or oxygen vacancies present in the channel layer are transferred to the gate electrode, causing the conductivity and threshold voltage (Vth) of the channel layer to change to be different from those of the channel layer before the voltage was applied to the gate electrode. A write operation or an erase operation is performed when the conductivity and threshold voltage of the channel layer change.

18. The method of claim 17, wherein when the voltage is applied to the gate electrode, at the threshold voltage (V th The write operation or the erase operation is performed when the change occurs.

19. The method of claim 17, wherein The write operation is performed by applying a positive voltage to the gate electrode to transfer oxygen vacancies present in the storage layer to the channel layer, such that the conductivity of the channel layer and the threshold voltage (V) before the voltage is applied to the gate electrode are equal. th Compared to, the increased conductivity of the channel layer or the increased threshold voltage (V) th ) decrease, or The erasure operation is performed by applying a negative voltage to the gate electrode to transfer the oxygen vacancies present in the channel layer to the storage layer, such that the conductivity of the channel layer and the threshold voltage (V) before the voltage is applied to the gate electrode are similar. th Compared to the previous method, the conductivity of the channel layer decreases or the threshold voltage (V) decreases. th )Increase.

20. The method of claim 17, further comprising: A readout operation is performed by applying the voltage to the gate electrode to check the extent of oxygen vacancy inclusion by means of the conductivity of the channel layer.

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