Write-once locking circuit and method

Abstract

The invention discloses a write-once locking circuit and a write-once locking method, and relates to the technical field of integrated circuit design and information security. The circuit comprises a data storage unit, a state locking unit and a logic control module. The logic control module provides an effective signal for the data storage unit to allow writing when the state signal indicates that the data storage unit has the writing permission and the external writing enable signal is effective, and simultaneously triggers the state locking unit to overturn to a state of forbidding the writing permission and keep the state; thereafter, the logic control module continuously blocks the provision of the valid write signal to the data storage unit based on the write prohibition state. On the premise of not increasing additional process steps and manufacturing cost, the standard digital logic circuit can be used for realizing data single-time writing and locking functions similar to OTP (One Time Programmable).

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit design and information security technology, and in particular to a single-write locking circuit and method. Background Technology

[0002] In modern consumer electronics chips, to ensure chip security and traceability, it is typically necessary to store some fixed, user-unmodifiable data, such as the chip's unique identifier (ChipID), vendor identifier (VendorID), factory configuration information, verification data, and calibration parameters of the RF or SerDes modules. This data is crucial for the chip's normal operation, anti-counterfeiting traceability, and secure startup. Current technologies typically use dedicated devices such as one-time programmable memories (OTPs) or electronic fuses (eFuses) to permanently store this data. While OTPs and eFuses offer the functionality of one-time write-once, non-lossable, and irreversible modification, they have significant drawbacks in terms of security and cost.

[0003] First, these devices typically occupy a large layout area, hindering chip miniaturization. Second, they often have specific power supply requirements, such as needing higher programming voltages, increasing the complexity of power management circuitry. More importantly, devices like eFuses usually require additional photolithography mask layers during mass production, directly leading to a significant increase in manufacturing costs. Furthermore, for certain cost-sensitive applications or those that only need to lock data during runtime, using expensive OTP or eFuse devices is a waste of resources.

[0004] Therefore, how to implement a single data write and lock function similar to OTP using standard digital logic circuits without adding extra process steps and manufacturing costs has become an urgent technical problem to be solved. Summary of the Invention

[0005] The main objective of this invention is to provide a single-write locking circuit and method, which aims to achieve a single-write and locking function similar to OTP using standard digital logic circuits without adding extra process steps and manufacturing costs.

[0006] To achieve the above objectives, this invention proposes a single-write locking circuit, comprising: a data storage unit having a data input terminal, a data write enable terminal, and a data output terminal; a state locking unit having a state input terminal and a state output terminal, the state output terminal being used to output a state signal indicating current write permission; and a logic control module coupled to an external write enable signal input terminal, the state locking unit, and the data storage unit, respectively; wherein, the logic control module is configured to perform the following operations: when the state signal indicates write permission and the external write enable signal is valid, providing a valid signal to the data write enable terminal of the data storage unit to allow data writing, and simultaneously providing a lock signal to the state input terminal of the state locking unit; the state locking unit, in response to the lock signal, flips the state signal to indicate write permission prohibited and maintains it in this state; the logic control module, based on the state signal indicating write permission prohibited, continuously blocks the provision of a valid signal to the data write enable terminal of the data storage unit.

[0007] Preferably, both the data storage unit and the state locking unit are D-type triggers.

[0008] Preferably, the status locking unit is configured to have a reset function; after power-on reset, the status output terminal of the status locking unit outputs the status signal indicating that it has write permission.

[0009] Preferably, the status signal indicating write permission is a high-level signal, and the status signal indicating write permission is prohibited is a low-level signal.

[0010] Preferably, the logic control module includes a first logic gate circuit, which is configured to perform an AND operation on the external write enable signal and the status signal output by the status output terminal, and the output terminal of the first logic gate circuit is connected to the data write enable terminal of the data storage unit.

[0011] Preferably, the logic control module includes a multiplexer, the selection control terminal of which is connected to the status output terminal of the status locking unit; the multiplexer is configured to: when the status output terminal indicates that write permission is granted, select a first input path to conduct to the status input terminal of the status locking unit, and the signal on the first input path is used to flip the status locking unit to a state where write permission is prohibited after a write operation occurs.

[0012] Preferably, the logic control module includes combinational logic gates, which include NOT gates and AND gates; the combinational logic gates are configured to perform logical operations on the external write enable signal and the state signal output by the state locking unit, and provide the operation result to the state input terminal of the state locking unit, so as to lock the state locking unit after the write operation is completed.

[0013] Preferably, the data storage unit and the state locking unit are both connected to the same write clock signal source, and the state locking unit is configured to toggle its state in the next clock cycle after receiving the locking signal.

[0014] Preferably, the data stored in the data storage unit includes at least one of chip identifier, manufacturer identifier, configuration information, verification information, or radio frequency calibration data.

[0015] Preferably, the circuit is configured to receive the external write enable signal during the chip startup phase or during the execution of initialization code to complete the data write.

[0016] This application also discloses a single-write locking method using the circuit described above, comprising: providing the state locking unit in a state indicating write permission; receiving an external write enable signal; allowing data to be written to the data storage unit when the state locking unit indicates write permission and the external write enable signal is valid, and synchronously triggering the state locking unit to flip to a state indicating write permission is prohibited; and using the state locking unit indicating write permission is prohibited to continuously block subsequent write operations to the data storage unit.

[0017] The above technical solution has the following advantages: This invention provides a single-write locking circuit and method, and its application in chip information storage, which offers the following advantages: By employing standard data storage units and state locking units in conjunction with a logic control module, a hardware self-locking loop based on write action triggering is constructed. When an external write enable signal is valid and the state indication allows, data is written to the storage unit, simultaneously triggering the state locking unit to flip and maintain itself in a write-prohibited state. This achieves one-time data writing and permanent locking using conventional digital logic gate circuits. This solution eliminates the need for large-area OTP or eFuse devices requiring additional mask layers, significantly reducing chip manufacturing costs and circuit area, simplifying power supply design, and providing data security and tamper-proof capabilities comparable to traditional OTP devices. It is particularly suitable for applications such as chip ID storage, secure boot configuration, and calibration data persistence. Attached Figure Description

[0018] The present invention will now be described in detail with reference to specific embodiments and accompanying drawings, wherein: Figure 1 This is a schematic diagram of the single-write locking circuit provided in Embodiment 1 of the present invention. Detailed Implementation To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0019] Example 1 This embodiment provides a single-write locking circuit based on standard logic gate circuits. In the prior art, consumer chips often use OTP (One-Time Programmable Memory) or eFuse (Electronic Fuse) to store ID or configuration information. However, these devices not only occupy a large circuit area and have special requirements for power supply, but also often require an additional mask layer during mass production, increasing manufacturing costs. This embodiment aims to achieve one-time data writing and permanent locking functions without relying on the aforementioned special device processes, using only conventional digital logic design, thereby effectively saving mask layer costs and reducing circuit area footprint.

[0020] See appendix Figure 1 The single-write lockout circuit mainly includes a data storage unit FF2, a state lockout unit FF1, and a logic control module. The data storage unit FF2 is used to actually store the data to be written, such as chip configuration information or ID information. In this embodiment, the data storage unit FF2 is implemented using a standard D-type flip-flop, which has a data input terminal D, a data write enable terminal E, and a data output terminal Q. According to the characteristics of a D-type flip-flop, when the E terminal is high, the signal at the D terminal is registered in the flip-flop, and the Q terminal outputs the registered signal level. The state lockout unit FF1 is also constructed using a D-type flip-flop, and its function is to act as a state machine to record whether the current circuit has been written to, thereby controlling subsequent write permissions. The state lockout unit FF1 has a state input terminal D, a state output terminal Q, and a reset terminal.

[0021] The logic control module is the core component connecting the external control signals to the two memory units mentioned above. It is coupled to the external write enable signal input terminal write_enable, the state locking unit FF1, and the data storage unit FF2, respectively. In the specific circuit structure of this embodiment, the logic control module is mainly implemented through a multiplexer (MUX) in conjunction with related connection lines and AND gate logic.

[0022] The specific connection relationships are as follows: The selection control terminal of the multiplexer is connected to the external write enable signal `write_enable`. The first input channel of the multiplexer (when the selection terminal is low level 0) is connected to the status output terminal Q of the status locking unit FF1, forming a feedback loop. The second input channel of the multiplexer (when the selection terminal is high level 1) is connected to a low-level signal source, i.e., logic 0. Furthermore, the status output terminal Q of the status locking unit FF1 is ANDed with the external write enable signal `write_enable`, and then connected to the data write enable terminal E of the data storage unit FF2.

[0023] The initial state setting of the circuit is crucial for implementing the single-write function. When the chip is powered on and reset, the state locking unit FF1 is set via its reset pin, causing its state output pin Q to output a high-level signal, i.e., logic 1. In this embodiment, the high level is defined as the permit_access state signal indicating write permission. At this time, if the external write enable signal is low, i.e., not written, the multiplexer selects the first input channel and feeds back the high level of the state output pin Q to the state input pin D, thereby maintaining the "write allowed" state.

[0024] When the system needs to write data, the external circuit provides the write data signal `write_data` and sets the external write enable signal `write_enable` to a valid high level. At this time, the following logical actions occur: Data writing: Since the current output of the state locking unit FF1 is high (permit_access=1), this signal is ANDed with the valid external write enable signal, causing the data write enable terminal E of the data storage unit FF2 to receive a valid high-level signal. Driven by the write clock write_clk, the written data is latched into the data storage unit FF2.

[0025] Trigger Locking: Simultaneously, as the external write enable signal goes high, the selector of the multiplexer changes from low to high, switching to select the second input channel. The signal input to this channel is low (0), therefore the state input D of the state lock unit FF1 receives 0.

[0026] At the arrival of the next clock cycle, the state lock unit FF1 responds to the low-level input at terminal D by toggling its state output Q to a low level (0). Once the state output Q becomes 0, it indicates "write permission disabled". Thereafter, the circuit will remain locked regardless of changes in the external write enable signal. If the external write enable signal is removed (becomes 0), the multiplexer switches back to the first input channel, feeding back the current low level 0 of the status output terminal Q to the D terminal, so that the status lock unit FF1 remains in the 0 state.

[0027] Meanwhile, after the low level of the status output terminal Q is ANDed, the enable terminal E of the data storage unit FF2 will no longer have the possibility of being high, continuously blocking the provision of a valid write enable signal to the data storage unit FF2, thereby achieving the effect that the data cannot be modified again at the physical level.

[0028] Example 2 This embodiment provides another specific hardware implementation of the single-write lock circuit, which uses discrete logic gate combinations to replace the multiplexer structure in Embodiment 1, and can also achieve the above-mentioned technical concept.

[0029] The logic control module in this embodiment includes combinational logic gates. Specifically, the combinational logic gates include NOT gates and AND gates. The selection of the data storage unit FF2 and the state locking unit FF1 is consistent with that in Embodiment 1, both using D-type flip-flops and sharing the same write clock signal source write_clk to ensure timing synchronization.

[0030] In this embodiment, the external write enable signal `write_enable` is introduced into the logic control module. First, this signal is inverted by a NOT gate. Then, the output of the NOT gate is connected to one input of an AND gate, while the other input of the AND gate is connected to the current state output Q of the state locking unit FF1. Finally, the output of the AND gate is connected back to the state input D of the state locking unit FF1.

[0031] Its working principle is as follows: In the initial stage after power-on reset, the state lock unit FF1 outputs a high level, i.e., logic 1, indicating that access is allowed. At this time, if the external write enable signal is low, i.e., no write is performed, the NOT gate outputs a high level, and both inputs of the AND gate are high, so the output is high. The state lock unit FF1 remains high under clock drive, maintaining the write-allowed state.

[0032] When an external circuit initiates a write operation and sets the external write enable signal to a high level, on the one hand, this high level acts directly or after buffering on the enable terminal of the data storage unit FF2, allowing data to be written; on the other hand, it becomes a low-level input to the AND gate after passing through a NOT gate. According to the logic characteristics of the AND gate, as long as one input is low, its output is low. Therefore, the AND gate provides a low-level signal to the state input terminal D of the state lock unit FF1. On the subsequent clock edge, the state lock unit FF1 toggles, and its output Q becomes low, i.e., logic 0.

[0033] Once Q becomes 0, since one input of the AND gate is directly connected to Q, the output of the AND gate will be permanently locked at a low level of 0, regardless of subsequent changes in the external write enable signal (i.e., regardless of whether the NOT gate outputs 0 or 1). This means that the state-locking unit FF1 will remain in a write-prohibited state. This low-level state signal also acts as a shielding signal, eliminating the write enable validity of the data storage unit FF2. Through this simplified logic gate design, this embodiment effectively solves the problems of large area occupation and the need for additional photomasks in traditional eFuses, achieving the self-locking function of the logic circuit at extremely low cost.

[0034] Example 3 This embodiment further illustrates the application scenarios and data configuration of the above-mentioned single-write lock circuit in actual chip systems.

[0035] The circuit of this invention is particularly suitable for the identification and key configuration parameters of memory chips. The data stored in the data storage unit FF2 may specifically include at least one of the following: chip identifier, manufacturer identifier, configuration information, chip tracking and tracing information, verification information, or calibration data from modules such as RF and SerDes (serializer / deserializer). In existing consumer chip designs, this data is typically required to be fixed after leaving the factory and cannot be arbitrarily tampered with by the user. Using this solution to store calibration data can also effectively shorten chip calibration time and improve production efficiency.

[0036] For example, during the chip's production testing phase or the system's initialization phase before shipment, the test equipment sends a write command to the chip via an external interface. At this time, the circuit is in an initial enabled state after reset. The test equipment writes calibrated RF parameters or a unique serial number as input data to the data storage unit FF2. Once the write is complete, as the write enable signal is removed or the clock cycle advances, the state lock unit FF1 automatically toggles and locks. Afterward, even if the chip is delivered to the end user, and the user attempts to send a write command again via software, the contents of the data storage unit FF2 will not change due to the hardware-level logic blockade.

[0037] Furthermore, this circuit is configured to receive an external write enable signal during the chip boot phase or execution of initialization code. This provides a runtime security mechanism. For example, after the system powers on, the code in the BootROM runs first, writing some critical security configuration words into the registers of this invention, and then triggering a lock. This ensures that subsequent operating system or application code can only read these configurations and cannot modify them, thereby preventing malicious software from tampering with the system security policy or operating mode, acting as a hardware security lock. Simultaneously, this method can also be flexibly applied to mode disabling in applications. By writing and locking specific configurations during chip manufacturing or initialization, certain specific functional modes of the chip can be permanently disabled, meeting the market demands of different product tiers.

[0038] Example 4 This embodiment describes a method for implementing single-write locking using the above-described circuit. The method mainly includes the following steps: First, a status lock unit FF1 is provided to indicate that the register is in a write-enabled state. This is typically achieved via the chip's power-on reset (POR) signal. After reset, the status lock unit FF1 outputs a high level, indicating that the current register is in a writable state.

[0039] Next, it receives an external write enable signal. When the system decides to write data, it issues a valid write enable signal. At this time, the circuit performs a logical judgment: when the state locking unit FF1 indicates that write permission is available and the external write enable signal is valid, the logic path is opened.

[0040] Subsequently, data is allowed to be written to data storage unit FF2, and the state locking unit FF1 is triggered to toggle synchronously. This step is the core of this method, namely, "writing data" and "locking the door" are concurrent or closely related sequential actions. While the data is being stored in the register, the logic level used to lock the access has been sent to the input of the state locking unit FF1.

[0041] Finally, the state-locking unit FF1, which indicates that write permission is prohibited, continuously blocks subsequent write operations to the data storage unit FF2. In the next clock cycle after the first write is completed, the state of the state-locking unit FF1 flips to the prohibited state and maintains itself in this state using a feedback loop, thereby physically cutting off the write path of the data register and ensuring the immutability of the data.

[0042] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A single-write locking circuit, characterized in that, include: The data storage unit has a data input terminal, a data write enable terminal, and a data output terminal; A status locking unit has a status input terminal and a status output terminal, wherein the status output terminal is used to output a status signal indicating the current write permission; The system includes a logic control module, coupled to an external write enable signal input, a state locking unit, and a data storage unit, respectively. The logic control module is configured to perform the following operations: when the state signal indicates write permission and the external write enable signal is valid, it provides a valid signal to the data storage unit's write enable terminal to allow data writing, and simultaneously provides a lock signal to the state input terminal of the state locking unit. In response to the lock signal, the state locking unit flips the state signal to indicate write permission is prohibited and maintains this state. Based on the state signal indicating write permission is prohibited, the logic control module continuously blocks the provision of valid signals to the data storage unit's write enable terminal.

2. The single-write locking circuit according to claim 1, characterized in that, Both the data storage unit and the state locking unit are D-type triggers.

3. The single-write locking circuit according to claim 1, characterized in that, The status locking unit is configured to have a reset function; after power-on reset, the status output terminal of the status locking unit outputs the status signal indicating that write permission is granted.

4. The single-write locking circuit according to claim 3, characterized in that, The signal indicating write permission is a high-level signal, and the signal indicating write permission is a low-level signal.

5. The single-write locking circuit according to claim 4, characterized in that, The logic control module includes a first logic gate circuit, which is configured to perform an AND operation on the external write enable signal and the status signal output by the status output terminal. The output terminal of the first logic gate circuit is connected to the data write enable terminal of the data storage unit.

6. The single-write locking circuit according to claim 1, characterized in that, The logic control module includes a multiplexer, the selection control terminal of which is connected to the status output terminal of the status locking unit; the multiplexer is configured to: when the status output terminal indicates that write permission is granted, select a first input path to conduct to the status input terminal of the status locking unit, and the signal on the first input path is used to flip the status locking unit to disable write permission after a write operation occurs.

7. The single-write locking circuit according to claim 1, characterized in that, The logic control module includes combinational logic gates, which include NOT gates and AND gates. The combinational logic gates are configured to perform logical operations on the external write enable signal and the state signal output by the state locking unit, and provide the operation result to the state input terminal of the state locking unit so as to lock the state locking unit after the write operation is completed.

8. The single-write locking circuit according to claim 1, characterized in that, The data storage unit and the state locking unit are both connected to the same write clock signal source, and the state locking unit is configured to toggle its state in the next clock cycle after receiving the locking signal.

9. The single-write locking circuit according to claim 1, characterized in that, The data stored in the data storage unit includes at least one of the following: chip identifier, manufacturer identifier, configuration information, verification information, or radio frequency calibration data.

10. The single-write locking circuit according to claim 1, characterized in that, The circuit is configured to receive the external write enable signal during the chip startup phase or during the execution of initialization code to complete the data write.

11. A single-write locking method using the circuit as described in claim 1, characterized in that, include: Provides the state locking unit in a state indicating write permission; receives an external write enable signal; When the state locking unit indicates that write permission is granted and the external write enable signal is valid, data is allowed to be written to the data storage unit, and the state locking unit is simultaneously triggered to flip to the state indicating that write permission is prohibited. And by using the state locking unit that indicates write permission to be denied, subsequent write operations to the data storage unit are continuously blocked.

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