High-linearity adaptive delay chain type TDC based on FPGA

Abstract

The invention discloses a high-linearity self-adaptive delay chain type TDC based on an FPGA. The high-linearity self-adaptive delay chain type TDC comprises a signal conversion module and a linear compensation module, wherein the signal conversion module is arranged between an IDELAY delay module and a delay chain module; the linear compensation module is arranged between a code density calibration module and a data storage module; the IDELAY delay module is used for carrying out segmentation processing on a system clock and generating six paths of single-edge delay signals with fixed rising edge time intervals; the signal conversion module is used for carrying out time sequence conversion on the six paths of single-edge delay signals and outputting three paths of double-edge signals, and the time interval of adjacent rising edges is fixed; and the linear compensation module is used for calculating the standard resolution before linear compensation and then combining the small delay units of the delay time into the large delay units of the delay time, and N is a linear compensation coefficient so as to convert the code density data with relatively low linearity into the code density data with high linearity. The TDC architecture has high linearity, strong environmental adaptability and cross-platform portability, and meets the application requirements of a high-precision time measurement scene.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electric digital data processing, and particularly relates to a high-linearity self-adaptive delay chain type TDC (Time-to-Digital Converter) based on FPGA (Field-Programmable Gate Array). BACKGROUND

[0002] TDC is a key device for measuring time interval, and its core function is to capture the time difference Δt of two events (usually start pulse Start and stop pulse Stop) and quantize the continuous time domain signal into discrete digital output. TDC is widely used in nuclear physics experiment, medical imaging, laser radar, three-dimensional imaging, time interval analysis, high-energy physics and space exploration, etc. With the continuous improvement of the requirement of time measurement accuracy in the above fields, the design and implementation technology of TDC has also been significantly developed.

[0003] At present, the implementation carriers of TDC mainly include ASIC (Application-Specific Integrated Circuit) and FPGA. The TDC based on ASIC usually adopts combinational logic gates to construct basic delay units, and compensates the signal propagation delay through a delay-locked loop to ensure the stability in the PVT (Process-Voltage-Temperature) variation environment. Such TDC has excellent differential nonlinearity, integral nonlinearity characteristics and anti-environmental interference ability, but has the defects of high manufacturing cost and long design cycle, which is difficult to adapt to flexible application scenarios with small batch and multiple configurations. In contrast, the TDC based on FPGA has become the preferred platform for realizing high-performance time-to-digital conversion due to its high integration, short development cycle and strong reconfigurability.

[0004] Among various TDC topologies, tap-delay-chain (TDC) is widely used in communication, radar, signal processing and other fields by segmenting the input signal with fixed time intervals and extracting the delay signals from multiple taps to achieve time dimension distribution and multi-phase output. Its working mechanism can be compared to a signal delay pipeline with multiple intermediate output ports. When the input signal is transmitted in the pipeline, each tap can extract the signal segment at different time according to the preset delay timing. Due to its simple principle and high conversion rate, this structure has attracted much attention in TDC design. In practical applications, TDC usually uses the internal carry chain of FPGA to cascade long delay chains, and samples the delay chain state combined with the system clock to realize the interpolation measurement of time signal. However, due to the structural characteristics of the internal logic resources of FPGA, the delay time of each delay unit in the delay chain is significantly uneven, and at the same time, the long delay chain is easy to cause the problem of cross-clock domain, leading to the accumulation of nonlinear errors, and ultimately affecting the measurement accuracy.

[0005] To solve the performance degradation problem caused by the long delay chain, the existing optimization schemes are mainly divided into two categories: multi-stage interpolation and wave association combination. The multi-stage interpolation scheme divides the original fine measurement module into two-stage measurement. It usually generates multiple phase clocks by using the built-in MMCM (Mixed-Mode Clock Manager) of FPGA to segment the system clock, and then measures the time domain interval corresponding to each segmented clock or the segmented clock signal by using the delay chain. However, the measurement accuracy of this scheme depends on the accuracy of the system clock. The wave association combination scheme converts a single edge signal into a multi-edge signal, so that a single delay chain can realize multiple measurements, which is equivalent to achieving the function of a multi-chain parallel structure. With the help of the wave association combination transmitter, the large delay unit introduced by the cross-clock domain delay chain can be divided into small delay units, thereby improving the resolution and measurement accuracy of the TDC. However, the segmentation of delay units in this scheme is usually uneven, so it is easy to produce a small delay unit of femtosecond level, which in turn introduces a large nonlinear error.

[0006] In recent years, to solve the problem of large nonlinear error caused by uneven segmentation of delay units, the industry usually adopts two technical paths: reducing the number of delay chain taps and introducing a linear compensation module. Reducing the number of delay chain taps can improve the linearity of the TDC to some extent, but it cannot completely avoid the generation of small delay units. Therefore, introducing a linear compensation module has become the mainstream technical direction. However, the existing linear compensation strategy has problems such as complex compensation logic and the need to adjust the compensation threshold adaptively according to different development boards, which weakens the adaptability of this scheme and is not conducive to porting on different hardware platforms.

[0007] In general, the traditional delay chain type TDC based on FPGA has a long delay chain built by cascading the carry chain inside the FPGA, which has a cross clock domain problem, and uneven segmentation of delay units, which easily introduces large nonlinear error; at the same time, the traditional linear compensation strategy has poor environmental adaptability, and it is difficult to achieve efficient transplantation across hardware platforms. SUMMARY

[0008] The application provides a high linearity adaptive delay chain type TDC based on FPGA, which makes up for the deficiencies of traditional delay chain type TDC in high linearity and environmental adaptability.

[0009] The application provides a high linearity adaptive delay chain type TDC based on FPGA, which sequentially includes a fine measurement module, a coarse measurement module, a code density calibration module, a data storage module and a serial sending module, the fine measurement module is provided with an IDELAY delay module and a delay chain module, and the fine measurement module further includes a signal conversion module arranged between the IDELAY delay module and the delay chain module; and a linear compensation module is further included between the code density calibration module and the data storage module. The IDELAY delay module is used for segmenting the system clock to generate 6 single-edge delay signals with fixed time interval of rising edge, so that the physical length of each delay chain does not cross the clock domain of the FPGA. The signal conversion module is used for timing conversion of the 6 single-edge delay signals to output 3 double-edge signals with fixed time interval of adjacent rising edges, so that a single delay chain realizes cyclic measurement of double rising edge signals. The linear compensation module is used for calculating the standard resolution before linear compensation , and combining the small delay units with delay time into large delay units with delay time , wherein is a linear compensation coefficient, so as to convert the code density data with low linearity into code density data with high linearity.

[0010] Optionally, the signal conversion module includes three CARRY8 modules, which are one-to-one corresponding to the three delay chains in the delay chain module, and each CARRY8 module is connected in series with the delay chain corresponding thereto.

[0011] Optionally, one CARRY8 module includes 8 MUXs, the DI0 of the CARRY8 is set to 0, the DI1 is set to 1, and the DI2 is set to 0; the value of i is 0-7, when Si is 0, the MUX outputs DIi; when Si is 1, the first MUX outputs CIN, and the other MUXs output the result of the previous MUX.

[0012] Optionally, the standard resolution The calculation process includes: The number of non-zero delay units stored in the code density calibration module is accumulated to obtain the number of non-zero delay units in TDC before linear compensation. Based on the clock cycle of TDC and the number of non-zero delay units before linear compensation, the standard resolution is calculated. .

[0013] Optionally, the linear compensation module uses a calibration RAM for data processing. To calibrate the RAM storage width, To calibrate the RAM address, The number of non-zero delay units before linear compensation. For standard resolution, To calibrate the RAM output data, the standard resolution is... The calculation process includes: (1) Scan calibration RAM, when detected When the delay is non-zero, it is determined that there is a non-zero delay unit, and execution is performed. operate; (2) When detected When it is zero, then it remains. The current value remains unchanged; (3) When At that time, execution is performed after each test is completed. Continue the operation until a complete scan of the calibration RAM is finished; (4) When When, that is, when a complete scan of the calibration RAM is completed, the calculation is performed. and will Reset to 0 to enter the linear compensation process.

[0014] Optionally, the standard resolution The calculation formula is as follows: , In the above formula, For TDC clock measurement period, The number of non-zero delay units before linear compensation.

[0015] Optionally, the linear compensation module uses two dual-port RAMs, calibration RAM and compensation RAM, to process data. The calibration RAM stores the raw data of the code density test, i.e., the data before linear compensation, while the compensation RAM stores the optimized data after linear compensation.

[0016] Optional, set The linear compensation coefficient is... To calibrate the RAM storage width, To calibrate the RAM address, For standard resolution, To calibrate the RAM output data, To compensate for RAM addresses, To compensate for the input data in RAM, If the value is the register value, then the compensation logic of the linear compensation module is as follows: (1) Address loop control: when season Otherwise execute Operation, then command ; (2) Data merging determination: When the conditions are met or season Otherwise, let .

[0017] Optionally, the linear compensation module is further configured to, when detecting the delay time of the merged large delay unit, If so, the merge operation will be cancelled.

[0018] Optionally, in the TDC, the first linearly compensated... Integral nonlinearity of a nonzero delay unit The calculation formula is as follows: , In the above formula, For the first linearly compensated The delay time of a non-zero delay unit. This represents the resolution after linear compensation.

[0019] One or more technical solutions provided by this invention have at least the following technical effects or advantages: This invention proposes a high-linearity adaptive delay chain type TDC based on FPGA. Through a design that shortens the delay chain, performs cyclic measurement of the delay chain, and coordinates the optimization of the linear compensation module, it achieves the required high linearity performance. Specifically, an IDELAY delay module and a signal conversion module are used to segment and perform timing conversion on the signal under test, shortening the time domain coverage required for the delay chain to complete the measurement and reducing its maximum measurement time span. This ensures that the physical length of each delay chain does not cross the clock domain of the FPGA, effectively reducing nonlinear errors caused by crossing clock domains. Simultaneously, relying on the cyclic measurement strategy of the delay chain, the hardware resource utilization is significantly reduced. Specifically, the signal conversion module converts the 6 single rising edge signals generated by the IDELAY delay module into 3 double-edge signals, simplifying the original 6 parallel delay chains to 3, enabling a single delay chain to perform cyclic measurement of double rising edge signals, improving measurement efficiency. To address the nonlinearity problem caused by uneven delay units, a linear compensation module integrates small delay units into large delay units of uniform size, eliminating the nonlinearity error caused by small delay units at its source.

[0020] The linear compensation module innovatively performs compensation calculations based on the original resolution (i.e., standard resolution) before linear compensation. This not only effectively reduces the resolution loss introduced by the compensation process and meets the performance requirements of high resolution, but also automatically adapts to the dynamic changes of the process environment by relying on the inherent characteristics of standard resolution. As a result, the TDC structure has both excellent environmental adaptability and cross-platform portability.

[0021] In addition, the signal conversion module based on the CARRY8 architecture has the advantages of low resource consumption and short processing latency. It can accurately monitor the signal status inside the delay chain, reduce interference during signal transmission, and prevent bit errors during the encoding process. Attached Figure Description

[0022] Figure 1 This diagram illustrates the segmentation and timing conversion of the system clock using the IDELAY delay module and signal conversion module. Figure 2 This is an overall architecture diagram of a high linearity adaptive delay chain type TDC based on FPGA according to the present invention; Figure 3 Standard resolution before linear compensation The computational logic diagram; Figure 4 This is a diagram showing the processing logic structure of the linear compensation module; Figure 5 This is a processing logic structure diagram of the signal conversion module based on CARRY8; Figure 6 This is a graph showing the integral nonlinearity distribution without linear compensation. Figure 7 Linear compensation coefficient The integral nonlinear distribution plot at time; Figure 8 Linear compensation coefficient The integral nonlinear distribution plot at time. Detailed Implementation

[0023] This invention provides a high linearity adaptive delay chain TDC based on FPGA, which overcomes the shortcomings of traditional delay chain TDC in terms of high linearity and environmental adaptability.

[0024] First, the terms appearing in the instruction manual will be explained.

[0025] CARRY8 is a dedicated 8-bit fast carry chain primitive within a slice in a Xilinx UltraScale / UltraScale+ architecture FPGA. Its core is used to efficiently implement arithmetic operations such as addition and subtraction, and it can also be reused as a high-precision delay chain for TDC fine measurement.

[0026] The KCU116 is a Kintex UltraScale+ XCKU5P-2FFVB676E FPGA development board launched by Xilinx. It is designed for high-performance logic design, high-speed interface verification, digital signal processing and TDC scenarios, and is the core hardware carrier for the 400MHz TDC deployment and verification of this invention.

[0027] To better understand, a detailed description will be provided in conjunction with the accompanying drawings and specific embodiments. Obviously, the embodiments described in this invention are only a part of the embodiments of this invention, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention.

[0028] The following section will use the deployment and verification on the KCU116 development board as an example to illustrate the structure, processing logic, and performance advantages of the FPGA-based high linearity adaptive delay chain TDC (hereinafter referred to as the new TDC).

[0029] 1. Overall Architecture Design of the New TDC 1.1 Core Module Composition like Figure 2 As shown, the new TDC includes multiple functional modules, namely a fine measurement module, a coarse measurement module, a code density calibration module, a linear compensation module, a data storage module, and a serial port transmission module. The fine measurement module contains an IDELAY delay module, a signal conversion module, and a delay chain module connected in series.

[0030] 1.2 Technical Issues and Solutions To address the critical issue in existing technologies where long delay chains constructed through cascaded carry chains within FPGAs cross clock domains, leading to significant nonlinear errors, the fine measurement module of this invention employs a combined strategy of clock segmentation and cyclic delay chain measurement. Segmentation shortens the physical length of a single delay chain, reducing its time-domain coverage and avoiding the use of long delay chains. Simultaneously, it utilizes a multi-phase clock scale and dual-edge signal conversion to achieve precise cyclic measurement, suppressing nonlinear errors at the hardware level. Specifically, a fixed-time delay signal is generated using the IDELAY delay unit to segment the TDC system clock, generating a multi-phase time scale; then, a signal conversion module converts the segmented system clock into a dual-edge signal.

[0031] To address the technical problem of uneven segmentation of delay units in existing technologies, which may result in femtosecond-level micro-delay units on the same delay chain and thus lead to large nonlinear errors, this invention designs a dedicated linear compensation module. By integrating micro-delay units into large delay units of uniform size, linearity is improved.

[0032] To address the technical problem that traditional linear compensation strategies have weak environmental adaptability and are difficult to efficiently port across hardware platforms, the linear compensation module of this invention innovatively performs compensation calculations based on the standard resolution before linear compensation, which can automatically adapt to dynamic changes in the process environment.

[0033] 2. Working principle of the fine measurement module 2.1 Structure and characteristics of key hardware units 2.1.1 IDELAY Delay Module The IDELAY delay module is an inherent module integrated within the FPGA. Its typical operating modes can be divided into three categories, and the characteristics of each mode are as follows: Adjustable delay mode: The signal delay can be dynamically adjusted by configuring parameters; Initial delay preset mode: An initial delay value can be configured via a register after power-on, and can be dynamically modified during operation; Fixed latency value mode: The latency value is fixed through hardware burning or configuration file, and cannot be adjusted in real time during runtime. It is suitable for fixed latency compensation scenarios.

[0034] This invention adopts an initial delay preset mode, which applies a precise initial delay to the system clock by configuring the initial delay value through the port CNTVALUEIN, thereby achieving uniform segmentation of the system clock and generating a multi-phase clock scale.

[0035] In the IDELAY delay module, the formula for calculating the total delay time is as follows: , In the above formula, This represents the total delay time. Due to inherent latency, this embodiment has a latency of 127 ps; The initial number of delay taps configured for the CNTVALUEIN port; The delay step size for a single tap is 4 ps in this embodiment.

[0036] 2.1.2 Delay Chain Module The delay chain module includes three delay chains ( Figure 2 In this diagram, each triangle represents a delay chain tap, and multiple triangles are chained together to form a delay chain. Each delay chain consists of... The CARRY8 modules within a CLB (Configurable Logic Block) are cascaded together. Each CLB contains one CARRY8 module (an 8-bit wide carry chain module integrated in mainstream FPGAs). A CARRY8 module consists of 8 MUX (Multiplexer) and 8 XOR gates, providing 16 tapped outputs that are connected to D flip-flops. Given the differences in signal delay from the CIN port to each tapped output and from the tapped output to the D flip-flops, this invention cascades the CO7 output port of the preceding CARRY8 module with the CIN input port of the following CARRY8 module, thereby constructing a picosecond-level precision delay chain.

[0037] 2.1.3 Signal Conversion Module The signal conversion module is deployed between the IDELAY delay module and the delay chain module. A CARRY8-based signal conversion module, such as... Figure 5 As shown, each CLB has a built-in CARRY8 module, which consists of 8 MUXs and 8 XOR gates.

[0038] The new TDC is configured with three delay chains, and the corresponding signal conversion modules include three CARRY8 modules. The three CARRY8 modules correspond one-to-one with the three delay chains in the delay chain module, and each CARRY8 module is connected in series with its corresponding delay chain.

[0039] 2.2 Clock Segmentation and Signal Conversion Process Please also refer to Figure 1 and Figure 2By segmenting the system clock using the IDELAY delay module, six single-edge delay signals with a rising edge interval of 600ps are generated. This ensures that the physical length of each delay chain does not cross the FPGA's clock domain, thereby effectively suppressing nonlinear errors caused by crossing clock domains and reducing the number of large-size delay units used.

[0040] Subsequently, the signal conversion module performs timing conversion on the 6 single-edge delayed signals and outputs 3 double-edge signals, with the time interval between adjacent rising edges remaining unchanged at 600ps.

[0041] Configure the input ports of the CARRY8 module as follows: Set DI0 to 0, DI1 to 1, and DI2 to 0. When Si (where i takes the value 0-7) is 0, the MUX outputs DII; when Si is 1, the first MUX outputs CIN, and the other MUXs output the result of the previous MUX.

[0042] Delay signal 3 is input to S0, delay signal 2 to S1, and delay signal 1 to S2, enabling the carry output port CO2 to generate a precisely timed double-edge signal based on the delay signal output by the IDELAY delay module. Simultaneously, S3-S7 are set to 1, and the CO2 signal is transmitted through a multi-stage MUX cascade path to the CIN input port at the beginning of a delay chain constructed by M CARRY8 modules with all S terminals set to 1. Through this configuration, the single-edge signal generated by the IDELAY delay module can be converted into a double-edge signal with an extremely short delay and synchronously transmitted to the delay chain.

[0043] Taking the first delay chain as an example, after the signal under test is input into the IDELAY delay module, three key delay signals are generated: delay signal 1, which is converted from 0 to 1 at 0ps; delay signal 2, which is converted from 0 to 1 at 1200ps; and delay signal 3, which is converted from 0 to 1 at 1800ps.

[0044] By setting the levels of S0, S1, and S2, the signal conversion module achieves precise switching of the output state: When the delay signals 1, 2, and 3 are all 0, S0, S1, and S2 are all 0, and the output result is DI3=0; When the delayed signal 1 is 1, S0=S1=0, S2=1, and the output result is DI2=1; When both delayed signals 1 and 2 are 1, S0=0, S1=S2=1, and the output result is DI1=0; When the delayed signals 1, 2, and 3 are all 1, S0=S1=S2=1, and the output result is CIN=1.

[0045] The cyclic measurement is achieved through the precise switching logic of the output state described above, as follows: The output result is 0 before the signal to be tested arrives; At 0ps, the output is 1, triggering a delay chain measurement of 0~ The time domain interval; exist When the output is 0, the delay chain is cleared and reset. exist When the output is 1, the delay chain measurement is triggered. to The time domain interval.

[0046] In addition, since the delay time of CARRY8 is about 30ps, it ensures that the latching signal of the D flip-flop and the signal entering the delay chain are basically consistent, avoiding bit error problems caused by the signal arriving too early or too late.

[0047] 2.3 Loop Measurement Strategy for Three Delay Chains When the system receives a reset signal with a period of 1200ps, it performs a zeroing operation on the delay chains. During the measurement phase, a 3-delay-chain cyclic operation mode is adopted, and the time domain coverage of each delay chain is as follows: The first delay chain is responsible for the two time domain intervals of 0ps-600ps and 1800ps-2400ps. The second delay chain is responsible for the two time domain intervals of 600ps-1200ps and 2400ps-3000ps. The third delay chain is responsible for the two time domain intervals of 1200ps-1800ps and 3000ps-3600ps.

[0048] By multiplexing two different time domain intervals using bilateral edge signals on the same delay chain, this invention simplifies the original 6 parallel delay chains to 3, and the effective measurement range of each delay chain only needs to meet 600ps.

[0049] 2.4 Detailed Measurement Performance Verification Using the KCU116 development board as the hardware verification platform, the system's measurement clock frequency is 400MHz, corresponding to a clock period of 2.5ns. Therefore, the system's fine measurement range needs to cover the 2.5ns time domain interval.

[0050] like Figure 1 As shown, through the collaborative operation of the IDELAY delay module and signal conversion module, the signal under test is divided into 6 segments for measurement. The effective measurement time of each delay chain is 600ps, and the total system measurement time reaches [amount missing]. The total measurement duration is greater than the 2.5ns measurement requirement corresponding to a 400MHz clock, i.e. This fully meets the fine measurement performance requirements of TDC.

[0051] 3. Working mechanism and performance optimization of the linear compensation module 3.1 Calculation of standard resolution before linear compensation The structure of the linear compensation module is as follows: Figure 4 As shown, two dual-port RAMs, calibration RAM and compensation RAM, are used to implement data processing: the calibration RAM stores the raw data of the code density test, that is, the data before linear compensation, while the compensation RAM stores the optimized data after linear compensation.

[0052] like Figure 3 As shown, before performing linear compensation, the standard resolution of the data stored in the calibration RAM must be calculated. The standard resolution refers to the original resolution before linear compensation.

[0053] set up To calibrate the RAM storage width, To calibrate the RAM address, The number of non-zero delay units before linear compensation. For standard resolution, To calibrate the RAM output data, the standard resolution is... The calculation process includes: (1) Scan calibration RAM, when detected When the delay is non-zero, it is determined that there is a non-zero delay unit, and execution is performed. operate.

[0054] (2) When detected When it is zero, then it remains. The current value remains unchanged.

[0055] (3) When At that time, execution is performed after each test is completed. Continue the operation until the complete scan of the calibration RAM is finished.

[0056] (4) When When, that is, when a complete scan of the calibration RAM is completed, the calculation is performed. and will Reset to 0 to enter the linear compensation process.

[0057] Standard resolution The calculation formula is as follows: , In the above formula, For TDC clock measurement period, The number of non-zero delay units before linear compensation.

[0058] In summary, by accumulating the non-zero delay units stored in the code density calibration module, the number of non-zero delay units in the TDC before linear compensation can be obtained. Then, based on the standard resolution... The calculation formula is used to obtain the standard resolution. .

[0059] 3.2 Compensation Logic of Linear Compensation set up For linear compensation coefficients, ( The larger the value, the stronger the compensation and the higher the linearity of TDC. To calibrate the RAM storage width, To calibrate the RAM address, For standard resolution, To calibrate the RAM output data, To compensate for RAM addresses, To compensate for the input data in RAM, This is the value stored in the register.

[0060] The compensation logic of the linear compensation module is as follows: (1) Address loop control: when season Otherwise execute Operation, then command .

[0061] (2) Data merging determination: When the conditions are met or season Otherwise, let .

[0062] The above compensation logic is simple and directly binds the compensation mechanism to the actual physical characteristics of the delay chain, so that the compensation can automatically follow the changes in PVT.

[0063] The core principle of the linear compensation module is: to reduce the delay time The tiny delay units are combined to meet the delay time. Large delay units; if the delay time of the merged large delay units is detected. If the merging is cancelled, the low linearity code density data can be converted into high linearity code density data.

[0064] 3.3 Optimization effect of integral nonlinearity In TDC, the first linearly compensated... Integral nonlinearity of a nonzero delay unit The calculation formula is as follows: , In the above formula, For the first linearly compensated The delay time of a non-zero delay unit. This represents the resolution after linear compensation.

[0065] To analyze the impact of the linear compensation module on integral nonlinearity Figure 6 to Figure 8 Different linear compensation coefficients are shown respectively. The integral nonlinear distribution plot below. Among them, Figure 6 For the case without linear compensation (i.e.) The integral nonlinear distribution plot of (time) Figure 7 for The integral nonlinear distribution plot at time, Figure 8 for The integral nonlinear distribution plot at time.

[0066] from Figure 6 It can be seen that when At that time, the integral nonlinearity fluctuates greatly and has poor linearity.

[0067] from Figure 7 It can be seen that when When the integral nonlinearity fluctuation amplitude is significantly reduced, the linearity is improved.

[0068] from Figure 8 It can be seen that when When the integral nonlinearity approaches zero, the linearity reaches its optimal level.

[0069] Therefore, it can be seen that with the linear compensation coefficient As the value increases, the number of non-zero delay units will decrease accordingly, the overall fluctuation amplitude will decrease, and the curve will become flatter.

[0070] 4. The complete data processing flow of the new TDC like Figure 2 As shown, the delay chain data acquired by the D flip-flop (D-FF in the figure) is first input into the encoder for encoding, and then transmitted sequentially to the code density calibration module, the linear compensation module, and the data storage module. Finally, the measurement data is output through the serial port transmission module, realizing a closed loop of the entire process of "signal measurement - data optimization - result output".

[0071] The rising edge of the output signal from the first delay unit is used as a D flip-flop ( Figure 2 The D flip-flop (D-FF) and the coarse measurement module enable signal are used. When the output signal of the signal conversion module is detected to enter the delay chain, the stop1 signal changes from 0 to 1 after the next rising edge of the system clock, that is, the stop1 signal flips from low level to high level. At this time, the D flip-flop stops sampling, and the coarse measurement module stops counting synchronously.

[0072] The raw data collected by the D flip-flop is encoded by the encoder and then transmitted sequentially to the code density calibration module, the linear compensation module, and the data storage module. Finally, the data is output by the serial port transmission module.

[0073] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this invention and their equivalents, then this invention also includes such modifications and variations.

Claims

1. A high linearity adaptive delay chain type TDC based on FPGA, comprising, in sequence, a fine measurement module, a coarse measurement module, a code density calibration module, a data storage module, and a serial port transmission module, wherein the fine measurement module includes an IDELAY delay module and a delay chain module, characterized in that, The fine measurement module also includes a signal conversion module, located between the IDELAY delay module and the delay chain module; a linear compensation module is also included between the code density calibration module and the data storage module. The IDELAY delay module is used to segment the system clock and generate 6 single-edge delay signals with fixed rising edge time intervals, so that the physical length of each delay chain will not cross the clock domain of the FPGA. The signal conversion module is used to perform timing conversion on 6 single-edge delayed signals and output 3 double-edge signals with a fixed time interval between adjacent rising edges, so that a single delay chain can realize the cyclic measurement of double-rising edge signals. The linear compensation module is used to first calculate the standard resolution before linear compensation. Then delay time The tiny delay units are combined into a delay time. Large delay unit, where It is a linear compensation coefficient used to transform low-linearity code density data into high-linearity code density data.

2. The TDC as described in claim 1, characterized in that, The signal conversion module includes three CARRY8 modules, which correspond one-to-one with the three delay chains in the delay chain module, and each CARRY8 module is connected in series with its corresponding delay chain.

3. The TDC as described in claim 2, characterized in that, A CARRY8 module consists of 8 MUXs. Set DI0 of CARRY8 to 0, DI1 to 1, and DI2 to 0. The value of i is 0-7. When Si is 0, the MUX outputs DII. When Si is 1, the first MUX outputs CIN, and the other MUXs output the result of the previous MUX.

4. The TDC as described in claim 1, characterized in that, Standard resolution The calculation process includes: The number of non-zero delay units stored in the code density calibration module is accumulated to obtain the number of non-zero delay units in TDC before linear compensation. Based on the clock cycle of TDC and the number of non-zero delay units before linear compensation, the standard resolution is calculated. .

5. The TDC as described in claim 4, characterized in that, The linear compensation module uses a calibration RAM for data processing. To calibrate the RAM storage width, To calibrate the RAM address, The number of non-zero delay units before linear compensation. For standard resolution, To calibrate the RAM output data, the standard resolution is... The calculation process includes: (1) Scan calibration RAM, when detected When the delay is non-zero, it is determined that there is a non-zero delay unit, and execution is performed. operate; (2) When detected When it is zero, then it remains. The current value remains unchanged; (3) When At that time, execution is performed after each test is completed. Continue the operation until a complete scan of the calibration RAM is finished; (4) When When, that is, when a complete scan of the calibration RAM is completed, the calculation is performed. and will Reset to 0 to enter the linear compensation process.

6. The TDC as described in claim 5, characterized in that, The standard resolution The calculation formula is as follows: ， In the above formula, For TDC clock measurement period, The number of non-zero delay units before linear compensation.

7. The TDC as described in claim 1, characterized in that, The linear compensation module uses two dual-port RAMs, calibration RAM and compensation RAM, to process data. The calibration RAM stores the raw data of the code density test, i.e. the data before linear compensation, while the compensation RAM stores the optimized data after linear compensation.

8. The TDC as described in claim 7, characterized in that, set up The linear compensation coefficient is... To calibrate the RAM storage width, To calibrate the RAM address, For standard resolution, To calibrate the RAM output data, To compensate for RAM addresses, To compensate for the input data in RAM, If the value is the register value, then the compensation logic of the linear compensation module is as follows: (1) Address loop control: when season Otherwise execute Operation, then command ; (2) Data merging determination: When the conditions are met or season Otherwise, let .

9. The TDC as described in claim 1, characterized in that, The linear compensation module is also used to detect the delay time of the merged large delay unit. If so, the merge operation will be cancelled.

10. The TDC as claimed in claim 1, characterized in that, In the TDC, the first linearly compensated... Integral nonlinearity of a nonzero delay unit The calculation formula is as follows: ， In the above formula, For the first linearly compensated The delay time of a non-zero delay unit. This represents the resolution after linear compensation.

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