Multi-chip structure including memory die stacked on die having programmable integrated circuit

Abstract

Some examples described herein provide a multi-chip structure that includes one or more memory dies stacked on a die having a programmable integrated circuit (IC). In one example, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable IC, and the programmable IC includes a memory controller. The first die is on and attached to the package substrate. The second die includes a memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

Description

[0001] This application is a continuation-in-part of International Application No. PCT / US2020 / 026032, International Filing Date, March 31, 2020, entered into the National Stage in the United States on October 22, 2021, under International Application No. 202080030688.1, entitled “Multi-Chip Structure Including Memory Die Stacked on Die with Programmable Integrated Circuit,” the disclosure of which is incorporated by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to a multi-chip structure and a method of forming such a structure, and in particular to a multi-chip structure including one or more memory dies stacked on a die with a programmable integrated circuit and a method of forming such a structure. BACKGROUND

[0003] A programmable integrated circuit (IC) refers to a type of IC that includes programmable circuitry. One example of a programmable IC is a field programmable gate array (FPGA). An FPGA is characterized by including programmable circuit blocks. A circuit design can be physically implemented in the programmable circuitry of a programmable IC by loading configuration data (sometimes referred to as a configuration bitstream) into the device. The configuration data can be loaded into internal configuration memory cells of the device. The collective state of the individual configuration memory cells determines the functionality of the programmable IC. For example, the particular operations performed by the various programmable circuit blocks and the connectivity between the programmable circuit blocks of a programmable IC are defined by the collective state of the configuration memory cells once loaded with configuration data. SUMMARY

[0004] Some examples described herein provide a multi-chip structure including one or more memory dies stacked on a die with a programmable integrated circuit (IC). Some examples described herein can avoid the use of an interposer and / or a physical layer (PHY) interface, which can reduce processing costs, power consumption, and / or die area usage.

[0005] One example is a multi-chip structure. The multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable integrated circuit, and the programmable integrated circuit includes a memory controller. The first die is on and attached to the package substrate. The second die includes a memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

[0006] Another example is a method of forming a multi-chip structure. A first die is stacked on a second die. The first die includes a memory. The second die includes a programmable integrated circuit, and the programmable integrated circuit includes a memory controller. The memory controller is communicatively coupled to the memory through the first die stacked on the second die. The first die is attached to a package substrate.

[0007] Another example is a multi-chip structure. The multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a field programmable gate array (FPGA) and a memory controller. The first die is on and attached to the package substrate. The second die includes a memory. The second die is stacked on a side of the first die opposite the package substrate. The memory is communicatively coupled to the memory controller.

[0008] These and other aspects can be understood with reference to the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0009] So that the above-recited features can be understood in detail, a more particular description, briefly summarized above, can be had by reference to one example implementation, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope.

[0010] Figure 1 is a block diagram depicting a programmable integrated circuit (IC) connected to an external memory, in accordance with some examples.

[0011] Figure 2 depicts a field programmable gate array (FPGA) of a programmable IC, in accordance with some examples.

[0012] Figure 3 、 Figure 4 and Figure 5 are circuit schematics of respective multi-chip structures, in accordance with some examples.

[0013] Figure 6 、 Figure 7 and Figure 8 are configurations of multi-chip structures on a printed circuit board (PCB), in accordance with some examples.

[0014] Figure 9 is a flowchart of a method for forming a multi-chip structure, in accordance with some examples.

[0015] To facilitate the understanding of this description, like reference numerals are used to identify like elements among the figures. It is contemplated that elements from one example can be advantageously incorporated in other examples. DETAILED DESCRIPTION

[0016] Some examples described herein provide a multi-chip structure that includes one or more memory dies stacked on a die having a programmable integrated circuit (IC). In some examples, the memory dies can implement memory for high bandwidth memory (HBM). In some examples, the programmable IC includes a programmable logic region, such as the fabric of a field programmable gate array (FPGA). The programmable IC allows a user configurable front end process to read or write data from or to the memory of any of the memory dies.

[0017] Some examples described herein can avoid the use of an interposer. By stacking the memory dies on a base die that includes a programmable IC, an interposer is not implemented (the base die and the memory die stack would otherwise be individually attached to the interposer). By eliminating the interposer, the costs associated with processing and including the interposer in the multi-chip stack are also avoided. Further, without the interposer, the processing for forming the multi-chip stack can be less, which in addition to reducing costs, can also reduce processing cycle time. Eliminating the interposer and stacking the memory dies on the base die can also result in a package having a smaller footprint and a smaller vertical profile.

[0018] Some examples described herein can avoid the use of a physical layer (PHY) interface, such as an HBM interface, in the multi-chip structure. A physical layer interface consumes power and chip area. By avoiding the use of a physical layer interface, such as an HBM interface, the physical layer interface on both dies (e.g., one on either side of an HBM physical layer connection) can be avoided, which can reduce power and reduce the area usage of both dies. Further, reducing the area usage of the dies can reduce the costs associated with the processing for forming the dies.

[0019] Some examples can obtain additional benefits. For example, a composite device formed from the multi-chip structure can be easier to test and easier to place in a multi-chip module, such as with other packages and / or dies. Further, a multi-chip structure having a programmable IC as described herein can allow for customization of the logic and functionality adjacent to the one or more memory dies (e.g., adjacent to one or more HBM dies). Such a multi-chip structure can allow a user to create a deployable customized device with, for example, high memory bandwidth and low power consumption in a single package. Further, such a multi-chip structure can maintain the programmability and flexibility of the programmable logic region and the boundary circuitry (e.g., input / output circuitry, transceiver circuitry, and / or other circuitry).

[0020] Various features will be described below with reference to the drawings. It should be noted that the figures can be drawn to scale, or not to scale, and that elements of similar structure or function can be represented by like reference numerals throughout the figures. It should be noted that these figures are merely meant to facilitate the description of the features. They are not intended to be limiting of the scope of the claimed invention or to be the only diagram in which the features can be practiced. Further, the illustrated examples need not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular example can be practiced in any other example even though it can not be explicitly described in that example. Further, the methods described herein can be described in a particular order, but other methods according to other examples can be practiced in other orders using more or less operations, in various other sequences (e.g., including various serial or parallel execution of the various operations).

[0021] Figure 1 is a block diagram depicting a programmable integrated circuit (IC) 102 connected to external memory according to some examples. The programmable IC 102 can be a system on a chip (SoC) and can include or be an IC that is a programmable logic device, such as a field programmable gate array (FPGA). The programmable IC 102 includes a processing system 104, a network on chip (NoC) 106, a configuration interconnect 108, one or more programmable logic regions 110a-110n (collectively, individually, or jointly referred to as “programmable logic region(s) 110”), a memory controller 112, a multi-gigabit transceiver (MGT) 114, an input / output block (IO) 116, and other IP circuitry 118. The NoC 106 includes a routing network 120 and a NoC peripheral interconnect (NPI) 122.

[0022] Typically, processing system 104 is connected to programmable logic regions (PLRs) 110 via configuration interconnect 108. Processing system 104, PRLs 110, memory controller 112, MGT 114, I / O 116, and other IP circuitry 118 are also connected to NoC 106 (e.g., routing network 120) and are therefore communicatively coupled to each other via NoC 106 (e.g., routing network 120). Processing system 104, memory controller 112, MGT 114, I / O 116, and other IP circuitry 118 are also connected to corresponding subsets of PRLs 110. For example, each of processing system 104, I / O 116, and other IP circuitry 118 is connected to programmable logic region 110a, and each of memory controller 112 and MGT 114 is connected to programmable logic region 110n. Various circuits can be connected to any subset of the programmable logic regions 110, and circuits can be connected to a given subset of the programmable logic regions 110 in any combination with any other circuits. Additionally, in some examples, the memory controller 112 can be connected to at least one of the I / O 116.

[0023] The processing system 104 may include one or more processor cores. For example, the processing system 104 may include multiple ARM-based embedded processor cores.

[0024] The programmable logic regions 110 may include any number of configurable logic blocks, lookup tables (LUTs), digital signal processing blocks, random access memory blocks, and programmable interconnect elements, as described below. The programmable logic regions 110 can be programmed or configured using the processing system 104 via configuration interconnect 108. For example, configuring interconnect 108 can enable frame-based programming of the structure of the programmable logic regions 110, for example, by a processor core of the processing system 104 (e.g., a platform management controller (PMC)).

[0025] The routing network 120 of the NoC 106 provides routing of NoC packets between different systems or circuits. The routing network 120 includes NoC packet switches interconnected by wire segments between NoC master units (NMUs) and NoC slave units (NSUs). Each NMU is an ingress circuit that connects a master circuit to the NoC 106. Each NSU is an egress circuit that connects the NoC 106 to a slave endpoint circuit. Each NoC packet switch performs switching of NoC packets. Thus, the NMUs, NoC packet switches, and NSUs can be configured to provide channels for communication between master endpoint circuits to slave endpoint circuits via the NMUs, NoC packet switches interconnected by wire segments, and NSUs. The NMUs, NoC packet switches, and NSUs also include register blocks that are written to configure the respective NMUs, NoC packet switches, and NSUs. The register blocks can be written to via the NPI 122. For example, the PMC of the processing system 104 can transmit memory-mapped write requests to the NMUs, NoC packet switches, and NSUs via the NPI 122 to write to the register blocks to configure the NMUs, NoC packet switches, and NSUs. The NPI 122 can include interconnected NPI switches that can route the memory-mapped write requests to the appropriate register blocks.

[0026] The IO 116 can be any input / output circuitry for communicatively coupling the programmable IC 102 with other circuits and / or systems. In some examples, the IO 116 can include high bandwidth memory (HBM) interface circuitry, high density input / output (HDIO) circuitry, peripheral component interconnect express (PCIe) circuitry, extreme performance input / output (XPIO) circuitry, etc. The other IP circuitry 118 can be, for example, a digital clock manager, an analog-to-digital converter, system monitoring logic, and / or any circuitry for a given implementation. In some examples, at least some of the memory controller 112, the MGT 114, the IO 116, and / or the other IP circuitry 118 are configurable. For example, the memory controller 112, the MGT 114, the IO 116, and / or the other IP circuitry 118 can be configurable via the NPI 122 of the NoC 106.

[0027] In some examples, the programmable IC 102 includes interface and control logic circuitry 124. In other examples, the interface and control logic circuitry 124 is on a separate IC from the programmable IC 102 (e.g., as shown by the dashed line). The interface and control logic circuitry 124 is connected to external memory 126. For example, the external memory 126 can be memory in a single or multiple dies. In some examples, the external memory 126 is random access memory (RAM), such as dynamic RAM (DRAM) that can be implemented as high bandwidth memory (HBM).

[0028] In some examples, the interface and control logic circuit 124 is directly connected to the memory controller 112, while in other examples, the interface and control logic circuit 124 is communicatively coupled to the memory controller 112 via the IO 116 of the programmable IC 102 and the IO 128 of another IC (e.g., as shown by the dashed arrow in FIG. 1). Figure 1 In some examples where the programmable IC 102 includes the interface and control logic circuit 124, the memory controller 112 is directly connected to the interface and control logic circuit 124 (e.g., without an intervening physical layer (PHY) interface), which is in turn connected to the external memory 126. In some examples where the interface and control logic circuit 124 is in a separate IC from the programmable IC 102, the memory controller 112 is directly connected to the interface and control logic circuit 124 (e.g., without an intervening physical layer (PHY) interface), which is in turn connected to the external memory 126. In some examples where the interface and control logic circuit 124 is in a separate IC from the programmable IC 102, the memory controller 112 is directly connected to the IO 116 (e.g., an HBM interface), and the IO 116 is connected to the IO 128 (e.g., an HBM interface) of a separate IC, which is connected to the interface and control logic circuit 124. The interface and control logic circuit 124 is in turn connected to the external memory 126. Thus, in these examples, the memory controller 112 is communicatively coupled to the external memory 126.

[0029] In some examples, and as detailed below, the programmable IC 102, the interface and control logic circuit 124 (if on a separate IC), and the external memory 126 can be included in dies that are stacked to form a multi-chip structure. Such a multi-chip structure can have a smaller package size and can be manufactured using reduced processing, which can increase yield and reduce the time to manufacture the multi-chip structure.

[0030] Figure 2 FIG. 1 shows a system 100 that includes a programmable IC 102, an interface and control logic circuit 124, and an external memory 126, according to some examples. Figure 1A field programmable gate array (FPGA) of a programmable IC 102 of the programmable IC 200. The programmable IC 200 includes a large number of different programmable tiles, including configurable logic blocks (CLBs) 202, random access memory blocks (BRAMs) 204, digital signal processing blocks (DSPs) 206, input / output blocks (IOBs) 208, configuration and clocking logic (CONFIG / CLOCKS) 210, dedicated input / output blocks (I / O) 212 (e.g., configuration ports and clock ports), and other programmable logic 214, such as digital clock managers, system monitoring logic, and the like. The programmable IC 200 can also include a boundary circuit, such as MGTs 216, memory controller (MC) 218, interface and control logic (INT / CNTL) 220, and other IP circuitry 222, such as PCIe interfaces, analog-to-digital converters (ADCs), and the like. The boundary circuit can also be programmable.

[0031] In some FPGAs, each programmable tile can include at least one programmable interconnect element (INT) 230 having connections to input and output terminals 232 of programmable logic elements within the same tile, as shown in the example included in Figure 2 Each programmable interconnect element 230 can also include connections to interconnect segments 234 of adjacent programmable interconnect elements in the same tile or other tile(s). Each programmable interconnect element 230 can also include connections to interconnect segments 236 of general routing resources between logic blocks (not shown). The general routing resources can include routing channels between a logic block (not shown) that includes a track of interconnect segments (e.g., interconnect segments 236) and a switch block (not shown) for connecting the interconnect segments. The interconnect segments (e.g., interconnect segments 236) of the general routing resources can span one or more logic blocks. The programmable interconnect elements 230, along with the general routing resources, implement a programmable interconnect structure for the illustrated FPGA.

[0032] In an example implementation, a CLB 202 can include a configurable logic element (CLE) 240, plus a single programmable interconnect element 230 that can be programmed to implement user logic. In addition to one or more programmable interconnect elements 230, a BRAM 204 can also include a BRAM logic element (BRL) 242. Typically, the number of programmable interconnect elements 230 included in a tile depends on the height of the tile. In the depicted example, a BRAM 204 has the same height as five CLBs 202, but other numbers (e.g., four) can also be used. As

[0033] In the illustrated example, a horizontal area near the center of the die is used for configuration and clock logic (CONFIG / CLOCKS) 210, and can also be used for other control logic. The vertical columns 248 extending from this horizontal area or column are used to distribute clocks and configuration signals across the FPGA.

[0034] With Figure 2 Some FPGAs of the illustrated architecture can include additional logic blocks that disrupt the regular columnar structure that makes up most of the FPGA. The additional logic blocks can be programmable blocks and / or dedicated logic.

[0035] Note that, Figure 2 The illustrated example is intended to illustrate an example FPGA architecture. For example, the number of logic blocks in a row included at the top of the FPGA, the relative width of the rows, the number and order of rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect / logic implementation are just one example. For example, in an actual FPGA, more than one row of adjacent CLBs is typically included at any location where a CLB appears to facilitate efficient implementation of user logic, but the number of rows of adjacent CLBs varies with the overall size of the FPGA. Figure 2

[0036] Figure 3 is a circuit schematic of a multi-chip structure according to some examples. Figure 3 The multi-chip structure of includes a programmable IC 102 and a memory 302, where the memory 302 can be in multiple dies stacked on a die that includes the programmable IC 102. As Figure 3 ​The simplified, programmable IC 102 includes a programmable logic region 110, a bus 304, a memory controller 112, and an interface and control logic circuit 124. For example, the programmable logic region 110 (or other subsystems, such as the processing system 104 and / or the NoC 106) is connected to the memory controller 112 via the bus 304, which can be an Advanced eXtensible Interface (AXI) bus. The memory controller 112 is connected to the interface and control logic circuit 124.

[0037] Each of the memories 302 includes a plurality of memory slices 306. In some examples, each memory slice 306 can be 2 gigabytes (Gb) of memory or other size. Each of the memories 302 can implement DRAM, and can further implement HBM. In some examples, each of the memories 302 can implement 32 Gb of HBM DRAM. The interface and control logic circuit 124 is connected to the memory slices 306 of the memories 302. The interface and control logic circuit 124 can decode read and write requests from the memory controller 112 and responsively transmit native signals to the memories 302 to read from or write to the memories 302. There is no standardized physical layer interface circuit between the memory controller 112 and the memory slices 306 of the memories 302 to encapsulate and decapsulate the read and write requests with and from the standardized form. For example, if the memories 302 implement HBM, there is no HBM interface between the memory controller 112 and the memory slices 306.

[0038] Figure 4 is a circuit schematic of another multi-chip structure according to some examples. Figure 4 The multi-chip structure of Figure 3 is similar to the multi-chip structure of

[0039] In the examples of Figure 3 and 4 the interface and control logic circuit 124 is included in the respective die that includes the programmable IC 102. In other examples, another control die (separate from the die that includes the programmable IC 102) can include the interface and control logic circuit(s) 124 and can be interposed between the die that includes the programmable IC 102 and the die(s) stack that includes the memories 302. The circuit schematic of such an example would be the same as Figure 3 and 4 except indicating the separate control die.

[0040] Figure 5 is a circuit schematic of yet another multi-chip structure according to some examples. Figure 5 The multi-chip structure of implements an HBM interface (e.g., as a PHY interface) between the memory controller 112 and the memory slices 306. Figure 5 The multi-chip structure of includes the programmable IC 102, a control IC 502, and the memory 302, where the control IC 502 is in a die stacked on and separate from the die including the programmable IC 102, and the memory 302 can be in multiple dies stacked on the die including the control IC 502. As Figure 5 As simplified in, the programmable IC 102 includes the programmable logic region 110, the bus 304, the memory controller 112, and an HBM interface (HBM PHY) 504. The programmable logic region 110 (or other subsystems, such as the processing system 104 and / or the NoC 106) is connected to the memory controller 112 via the bus 304, and the memory controller 112 is connected to the HBM interface 504. The HBM interface 504 is configured to encapsulate read and write requests from the memory controller 112 into, for example, a standardized HBM format, and to unpackage responses from the memory 302 from the standardized HBM format into a format usable by the memory controller 112.

[0041] The control IC 502 includes an HBM interface (HBM PHY) 506, and the interface and control logic circuit 124. The HBM interface 506 of the control IC 502 is connected to the HBM interface 504 of the programmable IC 102. The HBM interface 506 is configured to unpackage read and write requests from the HBM interface 504 from, for example, a standardized HBM format into a native format usable by the interface and control logic circuit 124, and to package responses from the memory 302 into the standardized HBM format for transmission to the HBM interface 504 of the programmable IC 102. The interface and control logic circuit 124 can decode read and write requests from the HBM interface 506, and responsively transmit native signals to the memory 302 to read from or write to the memory 302 on various memory dies. Figure 5 The circuit schematic of can be modified to implement a single memory die stack similar to the differences between Figure 3 and Figure 4

[0042] Figure 6 ​is a configuration of a multi-chip structure on a printed circuit board (PCB) 602 according to some examples. The multi-chip structure includes a package substrate 604, a base die 606 on the package substrate 604, and memory dies 608 stacked on the base die 606. The base die 606 includes a programmable IC 102, such as in Figure 3 and / or 4, and the memory dies 608 each include a memory 302, such as in Figure 3 and / or 4.

[0043] The multi-chip structure includes a stack of four memory dies 608, but other examples can implement any number of memory dies 608 in any number of stacks. Each memory die 608 has external connectors 610, such as micro-bumps, attached to an active side of the memory die 608 and to a backside of an underlying die. Each memory die 608 can include a through- semiconductor substrate via (TSV) through a semiconductor substrate on which the memory 302 of the respective memory die 608 is formed. The TSVs can be implemented to electrically connect the memory 302 of an overlying memory die 608 to the respective memory die 608 and / or an underlying die.

[0044] The programmable IC 102 of the base die 606 includes an interface and control logic circuit 124 as shown in Figure 3 and / or 4. A bottom memory die 608 of the stack of memory dies 608 has external connectors 610 attached to an active side of the bottom memory die 608 and to a backside of the base die 606. The base die 606 can include a TSV through a semiconductor substrate on which the programmable IC 102 is formed. The TSV can be implemented to electrically connect the memory 302 of an overlying memory die 608 to the programmable IC 102. The base die 606 also has external connectors 612, such as controlled collapse chip connection (C4) bumps, attached to the base die 606 and to a first side of the package substrate 604. A second side of the package substrate 604, opposite the first side, has external connectors 614, such as ball grid array (BGA) balls, attached thereto that are further attached to the PCB 602.

[0045] Figure 7 is another configuration of a multi-chip structure on a PCB 602 according to some examples. The multi-chip structure includes a package substrate 604, a base die 606 on the package substrate 604, a control die 702 on the base die 606, and memory dies 608 stacked on the control die 702. The base die 606 includes a programmable IC 102 without an interface and control logic circuit 124, such as in Figure 3 and / or 4. The control die 702 includes a control IC with an interface and control logic circuit 124, such as in Figure 3and / or 4. The memory dies 608 each include a memory 302, such as in Figure 3 and / or 4.

[0046] As in Figure 6 , Figure 7 The multi-chip structure of includes a stack of four memory dies 608, but other examples can implement any number of memory dies 608 in any number of stacks. The bottom memory die 608 of the stack of memory dies 608 has an external connector 610 attached to an active side of the bottom memory die 608 and a backside of the control die 702. The control die 702 can include TSVs through a semiconductor substrate on which, for example, logic structures (e.g., transistors) of the control die 702 are formed. The TSVs can be implemented to electrically connect the memories 302 of the overlying memory dies 608 to the control die 702 and / or a control IC (e.g., the interface and control logic circuit 124) of the programmable IC 102. An active side of the control die 702 is attached to a backside of the base die 606. For example, the active side of the control die 702 can be bonded to the backside of the base die 606 via, for example, oxide-to-oxide and / or metal-to-metal bonding through wafer bonding or other bonding techniques. The base die 606 has an external connector 612 attached to an active side of the base die 606 and attached to a first side of the package substrate 604. A second side of the package substrate 604 opposite the first side has an external connector 614 attached thereto, which is further attached to the PCB 602.

[0047] Figure 8 is another configuration of a multi-chip structure on a PCB 602 according to some examples. The multi-chip structure includes a package substrate 604, a base die 606 on the package substrate 604, a control die 802 on the base die 606, and memory dies 608 stacked on the control die 802. The base die 606 includes a programmable IC 102, such as in Figure 5 . More specifically, the programmable IC 102 also includes an HBM interface 504 as shown in Figure 5 . The control die 802 includes a control IC 502, such as in Figure 5 . More specifically, the control IC 502 of the control die 802 includes an interface and control logic circuit 124 and an HBM interface 506 as shown in Figure 5 . The memory dies 608 each include a memory 302, such as in Figure 5 .

[0048] As in Figure 6 , Figure 8The multi-chip structure described above can be a programmable access dense memory device. Programmable devices with dense memory utilizing HBM logic and stacking technology can be implemented with the structures described above. Performance advantages associated with programmable ICs (e.g., FPGAs) can be maintained while enabling faster and simpler manufacturing, lower manufacturing costs, and lower power consumption.

[0049] Although various chips have been described above with respect to the specified orientations (e.g., certain active sides of chips attached to the back sides of other chips), the multi-chip structures described above can be implemented with any number of chips in any number of orientations. Figures 6 to 8 The various multi-chip structures described above, but these orientations are provided as examples. Any chip (e.g., any base chip 606, memory chip 608, control chip 702, and / or control chip 802) can be flipped, for example, with respect to the descriptions provided above or can have any other orientation.

[0050] The multi-chip structures described above can be programmable access dense memory devices. Programmable devices with dense memory utilizing HBM logic and stacking technology can be implemented with the structures described above. Performance advantages associated with programmable ICs (e.g., FPGAs) can be maintained while enabling faster and simpler manufacturing, lower manufacturing costs, and lower power consumption.

[0051] Some examples can be implemented with any kind of programmable IC. For example, the programmable IC can be an application specific standard part (ASSP) IC with configurable input / output circuitry and interfaces, for example. Some examples can be implemented using multi-port memories with host interfaces, such as n x PCIe Gen x, n x 100GE, n x 40G, n x 10GE, 112G PAM4, etc.

[0052] Figure 9 is a flowchart of a method 900 for forming a multi-chip structure according to some examples. In block 902, a base chip is formed. For example, the base chip can be a Figures 6 to 8The base die is 606, and it can be formed through front and back semiconductor processes to realize programmable ICs and TSVs in the base die.

[0053] Optionally, a control die is formed in block 904. For example, the control die could be... Figure 7 Control dies 702 and / or 802, and similarly, can be formed using front and back semiconductor processes to implement the control IC and TSV within the control die. Optionally, in block 906, the control die is attached to the base die. For example, the control die can be bonded to the base die via wafer-to-wafer bonding during the processing of the control die and the base die (e.g., prior to monolithic die formation). As another example, the control die can be attached to the base die using an external connector (e.g., microbumps), which may include a return flow external connector for attaching the control die to the base die. In some examples, no control die is implemented, for example, to form Figure 6 The multi-chip structure eliminates the need to form a control die in block 904 and attach the control die to the base die in block 906.

[0054] In box 908, a memory die stack is formed. For example, the memory die stack could be... Figures 6 to 8 The memory die 608, and each memory die can be formed by front and back semiconductor processes to realize memory and TSV in the memory die, except that the back semiconductor process and TSV can be omitted for the top memory die. The memory dies can be attached to each other in a stack, for example by using external connectors such as microbumps, which may include return external connectors to attach the memory dies together.

[0055] In box 910, the memory die stack is attached to a base die or control die (if implemented). An external connector (e.g., microbumps) can be used to attach the memory die stack to the base die (e.g., as shown in Figure 910). Figure 6 (in the middle) or control die (e.g., such as Figure 7 (Or 8), this can include a return external connector to attach the memory die stack to the base die or control die. As mentioned above, the order of operations can vary. For example, when implementing a control die, such as in Figure 8 In this process, memory dies can be stacked and attached to the control die before the control die is attached to the base die.

[0056] In box 912, the base die is attached to the packaging substrate. For example, the packaging substrate could be... Figures 6 to 8 The packaging substrate 604 can be attached to the base die using an external connector (e.g., a C4 bump), which may include a return external connector to attach the base die to the packaging substrate.

[0057] In block 914, the package substrate is attached to the PCB. For example, the PCB substrate can be Figures 6 to 8 the PCB 602 and can be attached to the package substrate using external connectors (e.g., BGA balls), which can include reflowing the external connectors to attach the package substrate to the PCB.

[0058] According to some examples, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable integrated circuit. The programmable integrated circuit includes a memory controller. The first die is on and attached to the package substrate. The second die includes a memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

[0059] In some examples of the above multi-chip structure, the first die can include a semiconductor substrate. A through-substrate via (TSV) can pass through the semiconductor substrate. The memory controller can be communicatively coupled to the memory via the TSV.

[0060] In some examples of the above multi-chip structure, the second die can be attached to a side of the first die opposite the package substrate by an external electrical connector.

[0061] In some examples of the above multi-chip structure, there can be no communication and electrical setup physical layer interface between the memory controller and the memory.

[0062] In some examples of the above multi-chip structure, the first die can include a control logic circuit, and the control logic circuit can be communicatively disposed between the memory controller and the memory.

[0063] In some examples, the above multi-chip structure can further include a third die including a control logic circuit. The third die can be stacked on and attached to a side of the first die opposite the package substrate. The second die can be stacked on and attached to a side of the third die opposite the first die. The control logic circuit can be communicatively disposed between the memory controller and the memory. The third die can be bonded to the first die. The third die can be attached to the side of the first die opposite the package substrate by an external electrical connector. The second die can be attached to the side of the third die opposite the first die by an external electrical connector. There can be no communication and electrical setup physical layer interface between the memory controller and the memory. The first die can include a first physical layer interface communicatively coupled to the memory controller. The third die can include a second physical layer interface communicatively coupled to the first physical layer interface and the control logic circuit and between them.

[0064] In some examples of the above multi-chip structure, the programmable integrated circuit includes a field programmable gate array (FPGA).

[0065] According to some examples, a method of forming a multi-chip structure includes stacking a first die on a second die and attaching the first die to a package substrate. The first die includes a memory. The second die includes a programmable integrated circuit. The programmable integrated circuit includes a memory controller. The memory controller is communicatively coupled to the memory through the first die stacked on the second die.

[0066] In some examples of the above method, stacking the first die on the second die can include attaching the first die to the second die through external electrical connectors; the second die can include a control logic circuit communicatively disposed between the memory controller and the memory. And there can be no communication and electrical setup physical layer interface between the memory controller and the memory.

[0067] In some examples, the above method can further include attaching a third die to the second die. The first die can be attached to the third die. The third die can include a control logic circuit. The control logic circuit can be communicatively disposed between the memory controller and the memory.

[0068] According to some examples, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a field programmable gate array (FPGA) and a memory controller. The first die is on and attached to the package substrate. The second die includes a memory. The second die is stacked on a side of the first die opposite the package substrate. The memory is communicatively coupled to the memory controller.

[0069] In some examples of the above multi-chip structure, there can be no communication and electrical setup physical layer interface between the memory controller and the memory.

[0070] In some examples of the above multi-chip structure, the first die can include a control logic circuit. The control logic circuit can be communicatively disposed between the memory controller and the memory.

[0071] In some examples, the above multi-chip structure can further include a third die including a control logic circuit. The third die can be stacked on and attached to a side of the first die opposite the package substrate. The second die can be stacked on and attached to a side of the third die opposite the first die. The control logic circuit can be communicatively disposed between the memory controller and the memory. The first die can include a first physical layer interface communicatively coupled to the memory controller. The third die can include a second physical layer interface communicatively coupled to and between the first physical layer interface and the control logic circuit.

[0072] While the foregoing is directed to specific examples, other and additional examples may be devised without departing from the basic scope of the disclosure. The scope of the disclosure is determined by the claims that follow.

Claims

1. A multi-chip structure, comprising: Packaging substrate; The first die is directly mounted on the packaging substrate, and the first die includes a programmable integrated circuit. A second die includes a memory controller, which is stacked on the first die, and the memory controller is communicatively coupled to the package substrate via the programmable integrated circuit. as well as A third die, including a memory, is stacked on top of the second die, and the memory is sequentially coupled to the package substrate via the memory controller and the programmable integrated circuit.

2. The multi-chip structure according to claim 1, wherein the first die includes a semiconductor substrate, a substrate via (TSV) passes through the semiconductor substrate, and the memory controller is communicatively coupled to the memory via the TSV.

3. The multi-chip structure according to claim 1, wherein the fourth die is attached to the side of the third die opposite to the packaging substrate via an external electrical connector.

4. The multi-chip structure according to claim 1, wherein there is no communication setup and electrical setup physical layer interface between the memory controller and the memory.

5. The multi-chip structure according to claim 1, wherein the programmable integrated circuit includes a field-programmable gate array (FPGA).

6. A method for forming a multi-chip structure, the method comprising: The first die is directly stacked on the packaging substrate without an interlayer, and the first die includes a programmable integrated circuit. A second die is stacked on top of the first die, the second die including a memory controller, the memory controller being communicatively coupled to the package substrate via the programmable integrated circuit; as well as A third die is stacked on top of the second die, the third die including a memory, the memory being sequentially coupled to the package substrate via the memory controller and the programmable integrated circuit.

7. The method according to claim 6, wherein: Stacking the first die on the second die includes: attaching the first die to the second die via an external electrical connector; The first die includes a control logic circuit, which is communicatively disposed between the memory controller and the memory; and There is no communication or electrical physical layer interface between the memory controller and the memory.

8. The method of claim 6, wherein the first die includes control logic circuitry communicatively coupled between the memory controller and the memory.

9. A multi-chip structure, comprising: Packaging substrate; The first die includes a field-programmable gate array (FPGA) having a programmable integrated circuit, and the first die is located on the packaging substrate and directly attached to the packaging substrate without an intermediate layer. A second die includes a memory controller, which is stacked on the first die, and the memory controller is communicatively coupled to the package substrate via the programmable integrated circuit. as well as Multiple memory dies are stacked on the second die, and the memory dies are sequentially coupled to the packaging substrate via the memory controller and the programmable integrated circuit.

10. The multi-chip structure according to claim 9, wherein there is no communication setup and electrical setup physical layer interface between the memory controller and the plurality of memory dies.

11. The multi-chip structure according to claim 9, wherein the second die further includes a control logic circuit, the control logic circuit being communicatively disposed between the memory controller and the plurality of memory dies.

12. The multi-chip structure according to claim 9, wherein the second die is bonded to the first die.

13. The multi-chip structure of claim 9, wherein the second die is attached to the side of the first die opposite to the packaging substrate via an external electrical connector.

14. The multi-chip structure of claim 9, wherein the second die is attached to one of the plurality of memory dies via an external electrical connector.

15. The multi-chip architecture of claim 14, wherein there is no communication setup and electrical setup physical layer interface between the memory controller and the memory.

16. The multi-chip structure according to claim 14, wherein: The first die includes a first physical layer interface that is communicatively coupled to the memory controller; as well as One of the plurality of memory dies includes a second physical layer interface, which is communicatively coupled to the first physical layer interface and the control logic circuit, and is located between the first physical layer interface and the control logic circuit.

17. A method for forming a multi-chip structure, the method comprising: A first die is stacked on a second die, the first die including a memory, the second die including a programmable integrated circuit, the programmable integrated circuit including a memory controller, the memory controller being communicatively coupled to the memory via the first die stacked on the second die, wherein the second die includes control logic circuitry communicatively disposed between the memory controller and the memory, and configured to decode read and write requests from the memory controller, and responsively transmit native signals to the memory to read from or write to the memory; as well as The first die is directly attached to the packaging substrate without an interlayer, wherein the memory controller is communicatively coupled to the packaging substrate via the programmable integrated circuit.

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