Light emitting diode and light emitting device

Abstract

The invention provides a light-emitting diode and a light-emitting device, the light-emitting diode sequentially comprises a substrate, a semiconductor lamination layer, a current expansion layer and an insulating layer, the insulating layer is arranged above the semiconductor lamination layer and the current expansion layer and on the side wall and is provided with a through hole, and the through hole comprises a top opening, a bottom opening and a through hole wall, the wall of the through hole is of a multi-section structure and comprises a first inclined section and a second inclined section which are connected, the first inclined section is closer to the bottom opening than the second inclined section, and the included angle between the first inclined section and the horizontal direction is larger than that between the second inclined section and the horizontal direction. According to the technical scheme, the through hole wall of the insulating layer is subjected to multi-section and multi-angle design to optimize the structure of the insulating layer, the multi-section step structure provides gentle step transition for electrode metal deposition, the hidden danger that an electrode film is broken due to poor coverage in a deep hole is eliminated, the reflection area of the DBR can be reserved to the maximum extent, and the service life of the DBR is prolonged. Contact voltage is reduced, and light extraction efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a light-emitting diode and a light-emitting device. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor device whose basic structure includes a PN junction between a P-type semiconductor and an N-type semiconductor. When a forward voltage is applied to the LED, electrons and holes recombine at the junction of the PN junction, releasing energy. This energy is emitted in the form of photons, forming light radiation.

[0003] To improve light extraction efficiency, a distributed Bragg reflector (DBR) is usually fabricated on the light-emitting surface of the chip as an insulating reflective layer. By increasing its thickness and number of layers, the reflectivity of light can be effectively improved, thereby increasing the brightness of the chip.

[0004] However, increasing the thickness of the insulating layer presents significant challenges to the manufacturing process. When forming electrode vias, a larger via tilt angle, while preserving more DBR reflective area, can lead to localized thinning or even breakage of the metal film at step corners due to poor coverage during subsequent electrode metal deposition. This can result in open circuits or reliability failures. Furthermore, for ultra-thick DBRs, the bottom of the vias is difficult to completely etch, posing a risk of poor contact between the electrode metal and the underlying current spreading layer. This can increase contact voltage and affect product lifespan. Therefore, an improved technical solution is needed to address the shortcomings of the existing technology. Summary of the Invention

[0005] In view of the defects and deficiencies in the prior art described above, this application provides a light-emitting diode and a light-emitting device to ensure that the electrode layer of the chip has good stepped coverage and achieves stable and reliable ohmic contact, thereby fundamentally solving the technical problem that it is difficult to balance brightness, voltage and reliability in chips with thicker DBRs.

[0006] In a first aspect, this application provides a light-emitting diode, comprising at least: Substrate; A semiconductor stack covering the substrate includes a first semiconductor layer, an active layer and a second semiconductor layer stacked sequentially. A current spreading layer is disposed on the second semiconductor layer; An insulating layer covers the top and sidewalls of the semiconductor stack and the current spreading layer. The insulating layer has vias, each via including opposing top and bottom openings and via walls. The bottom opening exposes the current spreading layer and the first semiconductor layer. The through-hole wall has a multi-segment structure, including a first inclined segment and a second inclined segment that are connected. The first inclined segment is closer to the bottom opening than the second inclined segment, and the angle between the first inclined segment and the horizontal direction is greater than the angle between the second inclined segment and the horizontal direction.

[0007] Secondly, this application also provides a light-emitting device, the light-emitting device comprising: Packaging substrate; At least one light-emitting diode is disposed on the surface of the packaging substrate, and the packaging substrate and the electrode structure of the light-emitting diode are electrically connected; the light-emitting diode is the light-emitting diode provided by the above technical solution.

[0008] Compared with the prior art, the light-emitting diode and light-emitting device provided in this application have at least the following beneficial effects: The technical solution of this application optimizes the insulation layer structure by designing the through-hole wall of the insulation layer in a multi-segment, multi-angle manner. The angle between the first inclined segment and the horizontal direction is greater than the angle between the second inclined segment and the horizontal direction. The stepped structure with decreasing angle from bottom to top provides a smooth step transition for electrode metal deposition, eliminates the risk of electrode film breakage caused by poor coverage in deep holes, and can maximize the preservation of the reflective area of ​​the DBR, reduce contact voltage, and maximize light extraction efficiency.

[0009] In addition, the light-emitting device provided in this application includes the light-emitting diode provided in the above-mentioned technical solution. Therefore, the light-emitting device also has the above-mentioned good technical effects. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the structure of a light-emitting diode in the prior art; Figure 2 This is a schematic diagram of the structure of the light-emitting diode provided in Embodiment 1; Figure 3 for Figure 2 A partially enlarged structural diagram; Figure 4 This is a schematic diagram of the structure of the light-emitting diode provided in Embodiment 2; Figure 5 for Figure 4 A partially enlarged structural diagram; Figure 6 This is a schematic diagram of the insulating layer in the light-emitting diode provided in this application; Figure 7 This is a schematic diagram of the structure of the light-emitting diode provided in Embodiment 3; Figure 8 for Figure 7 A partially enlarged structural diagram; Figure 9 This is a schematic diagram of the light-emitting device provided in Embodiment 4.

[0011] List of reference numerals in the attached diagram: 100, Substrate; 200, Semiconductor stack; 210, First semiconductor layer; 220, Active layer; 230, Second semiconductor layer; 300, Current spreading layer; 400, Insulating layer; 401, First material layer; 402, Second material layer; 410, Through-hole wall; 411, First inclined section; 412, Second inclined section; 413, Third inclined section; 500, Electrode layer; 510, First electrode; 511, First contact electrode layer; 520, Second electrode; 521, Second contact electrode layer; OP1, Bottom opening; OP2, Top opening; 10, Light-emitting device; 101, Encapsulation substrate; 102, Light-emitting element. Detailed Implementation

[0012] See Figure 1 In existing technologies, the sidewalls of the etched holes in the insulating layer, i.e., the electrode channels, have only one angle, typically between 40° and 50° with the horizontal plane. Firstly, during electrode channel etching, incomplete etching at the bottom of the channel may occur. Secondly, when depositing pad electrodes in the electrode channel, uneven deposition of electrode material at the junction of the sidewall steps can occur, even posing a risk of electrode layer breakage. Furthermore, to form a good current path, the opening size of the electrode channel is usually large, and a contact electrode layer is placed between the pad electrode and the current spreading layer to increase the contact area between the electrode structure and the current spreading layer, optimize the current transmission path, and reduce the contact voltage. However, none of these measures optimize the insulating layer or its electrode channel structure itself, and do not fundamentally solve the problem of difficulty in improving the brightness of chips with thick insulating layers. Based on the background technology and the above-mentioned technical defects, this application provides a light-emitting diode, comprising at least: Substrate; A semiconductor stack is disposed on the substrate, comprising a first semiconductor layer, an active layer and a second semiconductor layer stacked sequentially. A current spreading layer is disposed on the second semiconductor layer; An insulating layer is disposed above and on the sidewalls of the semiconductor stack and the current spreading layer. The insulating layer has vias, each via including a top opening, a bottom opening, and a via wall. The bottom opening exposes the current spreading layer and the first semiconductor layer. The through-hole wall has a multi-segment structure, including a first inclined segment and a second inclined segment that are connected. The first inclined segment is closer to the bottom opening than the second inclined segment, and the angle between the first inclined segment and the horizontal direction is greater than the angle between the second inclined segment and the horizontal direction. This multi-segment through-hole wall design allows for a larger inclination angle near the bottom while controlling the bottom size of the through-hole, reducing the reflective area loss of the insulating layer. A smaller angle is used near the top, providing a smooth transition for electrode deposition and preventing electrode metal breakage due to insufficient coverage at steep steps, thus improving the reliability of the electrode structure.

[0013] In some embodiments, the angle between the first inclined segment and the horizontal direction is 45° to 65°; the angle between the second inclined segment and the horizontal direction is 30° to 50°. This provides a preferred angle range, achieving a balance between electrode coverage and via size.

[0014] In some embodiments, the through-hole wall further includes a third inclined section, which connects to the second inclined section and is closer to the top opening; the angle between the second inclined section and the horizontal direction is greater than the angle between the third inclined section and the horizontal direction. By continuously adding a third inclined section to form a multi-segment transition structure, the opening channel with an angle increasing from top to bottom can significantly reduce the stress concentration of the electrode film in the continuous deep hole, effectively preventing electrode film breakage without sacrificing the insulation layer coverage area.

[0015] In some embodiments, the first inclined section makes an angle of 55° to 65° with the horizontal direction; the second inclined section makes an angle of 45° to 55° with the horizontal direction; and the third inclined section makes an angle of 30° to 40° with the horizontal direction. The uppermost gentle slope provides optimal electrode coverage, the middle section serves as a transition, and the lowermost layer determines the via size and insulating layer coverage area, thereby maximizing overall performance.

[0016] In some embodiments, the sum of the heights of the first inclined segment and the second inclined segment accounts for 50% to 90% of the total thickness of the insulating layer. By limiting the total height of the first and second inclined segments with larger inclination angles, the loss of reflective area of ​​the insulating layer is minimized.

[0017] In some embodiments, the insulating layer is a distributed Bragg reflector structure, comprising several alternately stacked first and second material layers, wherein the refractive index of the first material layer is less than that of the second material layer; the first and / or second material layers are one or more of SiO2, TiO2, NbO2, ZrO2, or Ti2O5. The DBR, as an insulating layer, is fundamental to achieving its reflective function and chip brightness.

[0018] In some embodiments, the insulating layer comprises 15 to 30 pairs of alternately stacked dielectric layers. The greater the number of stacked layers, the thicker the insulating layer becomes, in order to maximize the reflectivity of the material layer to light.

[0019] In some embodiments, the thickness of a single layer of the first or second material layer is between 20 nm and 400 nm; the total thickness of the insulating layer is between 4.0 μm and 7.0 μm. The thickness of the insulating layer is positively correlated with its reflectivity, and the lower limit of the total thickness ensures its minimum reflectivity to the target wavelength.

[0020] In some implementations, the width of the bottom opening is defined as D1, where 3μm≤D1≤10μm; The width of the top opening is defined as D2, where 15μm ≤ D2 ≤ 22μm. The bottom opening width D1 is controlled between 3-10μm to ensure sufficient contact area with the current spreading layer to reduce contact resistance without sacrificing too much reflective area. The top opening width D2 is controlled between 15μm and 22μm to achieve the aforementioned multi-segment morphology, balancing the electrode contact area and light reflection capability.

[0021] In some implementations, the width of the bottom opening is defined as D1, and the width of the top opening is defined as D2, where 0.2 ≤ D1 / D2 ≤ 0.5. The applicability of this multi-segment angle structure is broadened by defining the taper range of the through-hole.

[0022] In some embodiments, the top opening and / or bottom opening of the via is shaped as one or a combination of several of the following: circular, elliptical, elongated, or a polygon with rounded chamfers. This technical solution is adaptable to various via structures, meets the needs of chips of different specifications, and can effectively prevent electric field concentration at sharp corners, thereby improving the ESD capability of the device.

[0023] In some embodiments, the thickness of the current spreading layer is between 20 Å and 200 Å. The current spreading layer also has a groove extending from its upper surface into its interior, the groove engaging with the bottom opening of the insulating layer, and the ratio of the groove's depth to the thickness of the current spreading layer is between 0.01 and 0.05. The groove enhances electrode bonding and electrical connection reliability, reduces the risk of electrode peeling, and further optimizes ohmic contacts.

[0024] In some embodiments, an electrode layer is also included, which covers a portion of the upper surface of the insulating layer and fills the via to be electrically connected to the current spreading layer.

[0025] In some implementations, the height of the first inclined segment is less than the thickness of the electrode layer. This ensures that the electrode material at the steepest section at the bottom of the via can completely fill the via, forming a continuous and unbroken conductive channel, thus guaranteeing chip yield and reliability.

[0026] In some embodiments, the electrode layer has a recessed region located above the through-hole of the insulating layer, forming a corresponding multi-segment recessed structure with the through-hole wall. The electrode structure is attached to the through-hole structure, forming a uniform and well-defined electrode cover layer.

[0027] This application also provides a light-emitting device, the light-emitting device comprising: Packaging substrate; At least one light-emitting diode (LED) is disposed on the surface of the encapsulation substrate, and the encapsulation substrate and the electrode structure of the LED are electrically connected; the LED is any of the LEDs provided in the above-described technical solutions. This light-emitting device has higher brightness, longer lifespan, and better stability in terminal products such as displays and backlight modules.

[0028] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0029] The composition and dopants of each layer of the light-emitting diode in this application can be analyzed using any suitable method, such as secondary ion mass spectrometry (SIMS). The thickness of each layer of the light-emitting diode in this application can be analyzed using any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscopy (SEM), in conjunction with, for example, the depth positions of each layer on a SIMS spectrum.

[0030] Example 1: This embodiment provides a light-emitting diode (LED), see [link]. Figure 2 , Figure 3 and Figure 6 The light-emitting diode includes at least a substrate 100, a semiconductor stack 200, a current spreading layer 300, an insulating layer 400, and an electrode layer 500. The specific structure and technical solution of the light-emitting diode provided in this embodiment will be described in detail below.

[0031] See Figure 2The substrate 100 is a growth substrate on which the light-emitting structure can be grown. The substrate 100 includes a sapphire substrate, a silicon carbide substrate, a silicon substrate, a gallium nitride substrate, or an aluminum nitride substrate, etc. One side of the substrate 100 is the growth surface of the semiconductor stack 200 and has a reflective structure for reflecting light; the opposite side is the light-emitting surface of the light-emitting diode. As an example, using a sapphire substrate or a patterned sapphire substrate for the substrate 100 is beneficial for improving the luminous efficacy and luminous intensity of the LED.

[0032] See also Figure 2 A semiconductor stack 200 is disposed on a substrate 100. The semiconductor stack 200 includes a first semiconductor layer 210, an active layer 220, and a second semiconductor layer 230 stacked sequentially. The first semiconductor layer 210 is composed of a III-V or II-VI compound semiconductor and is doped with N-type dopants such as Si, Ge, Sn, Se, or Te, and is an N-type semiconductor layer used to provide electrons for recombination light emission. The second semiconductor layer 230 is composed of a III-V or II-VI compound semiconductor and is doped with P-type dopants such as Mg, Zn, Ca, Sr, or Ba, and is a P-type semiconductor layer used to provide holes for recombination light emission. The active layer 220 may have any structure, but is not limited to, a single-well structure, a multi-well structure, a single quantum well structure, or a multi-quantum well structure, and is used for electron and hole recombination light emission.

[0033] See Figure 2 and Figure 3 A current spreading layer 300 is disposed on the second semiconductor layer 230. The current spreading layer 300 serves as a channel for current flow, allowing the current to spread as widely as possible across the surface of the second semiconductor layer 230, thereby improving luminous efficiency. As an example, the material of the current spreading layer 300 can be ITO (indium tin oxide), ZnO (zinc oxide), AZO (aluminum-doped zinc oxide), or IZO (indium zinc oxide). As a conductive layer in direct contact with the second electrode 520, the thickness and conductivity of the current spreading layer 300 have a significant impact on the brightness of the light-emitting diode. Further, the current spreading layer 300 is made of ITO, with a thickness between 20 Å and 300 Å.

[0034] See also Figure 2 and Figure 3An insulating layer 400 is provided above and on the sidewalls of the semiconductor stack 200 and the current spreading layer 300. Through holes are formed in the insulating layer 400 on the first semiconductor layer 210 and the second semiconductor layer 230 respectively to expose the first semiconductor layer 210 and the second semiconductor layer 230. The through hole on the second semiconductor 230 includes a top opening OP2 and a bottom opening OP1 and a through hole wall 410. The bottom opening OP1 exposes the current spreading layer 300. The through hole wall 410 has a two-section structure, specifically including a first inclined section 411 and a second inclined section 412 that are connected. The first inclined section 411 is closer to the bottom opening OP1 than the second inclined section 412, and the angle ∠A between the first inclined section 411 and the horizontal direction is greater than the angle ∠A between the second inclined section 412 and the horizontal direction. By designing the traditional via wall in two sections, with a larger angle near the bottom and a smaller angle near the top, a smooth transition is provided for electrode deposition. This avoids electrode metal breakage due to insufficient coverage at steep steps, improving the reliability of the electrode structure and chip products. Typically, the included angle ∠A of the first inclined section 411 is greater than the inclined angle of the traditional via wall, and the width of its bottom opening OP1 can be greater than the bottom opening width of the traditional via, further increasing the contact area between the second electrode 520 and the current spreading layer 300 and reducing the operating voltage.

[0035] See also Figure 2 and Figure 3 In some embodiments, the angle ∠A between the first inclined segment 411 and the horizontal direction is 45° to 65°, and the angle ∠B between the second inclined segment 412 and the horizontal direction is 30° to 50°. For example, by controlling the etching process parameters, the angle ∠A can be formed to be 48°, 50°, 55°, or 60°, while the angle ∠B can be formed to be 35°, 40°, 45°, or 48°. It is known that the inclination angle of conventional through-hole walls is in the range of 40° to 50°. The angle range of the two-segment morphology provided in this embodiment is greater than and less than the inclination angle of conventional through-hole walls, respectively, to achieve a balance between electrode coverage and through-hole size. Furthermore, the thickness of the first inclined segment 411 is between 1 μm and 4 μm, and the thickness of the second inclined segment 412 is between 1 μm and 4 μm. For example, the thickness of the first inclined segment 411 can be 1.5 μm, 2.0 μm, 2.5 μm or 3.5 μm, and the thickness of the second inclined segment 412 can be 1.5 μm, 2.0 μm, 2.5 μm or 3.5 μm.

[0036] See also Figure 2 and Figure 3In some embodiments, the width of the bottom opening OP1 of the insulating layer 400 is defined as D1, which is also the width of the contact surface between the second electrode 520 and the current spreading layer 300. 3μm ≤ D1 ≤ 10μm. This opening width indirectly determines the contact area between the second electrode 520 and the current spreading layer 300, ensuring sufficient contact area between the electrode material and the current spreading layer 300 to reduce contact resistance without sacrificing excessive reflective area. For example, the width D1 of the bottom opening OP1 can be 4μm, 5μm, 6μm, or 8μm. The bottom opening OP1 should not be too small; sufficient physical dimensions at the bottom of the via are required to ensure reliable electrical connections in subsequent processes such as electrode deposition, avoiding increased processing difficulty and contact resistance due to excessively small apertures. Furthermore, the width D1 of the bottom opening OP1 is preferably in the range of 4μm to 8μm. The width of the top opening of the insulating layer 400 is defined as D2, where 15μm ≤ D2 ≤ 22μm. The top opening width D2 is controlled between 15 μm and 22 μm to achieve a two-section morphology of the via wall 410. Both the first inclined section 411 and the second inclined section 412 have suitable thicknesses and inclination angles to balance the electrode contact area and light reflection capability. The top opening OP2 should not be too large to ensure that the insulating layer 400 has sufficient structural support and reflective area, especially for the reflective layer of the DBR structure, preventing damage due to insufficient structural strength during manufacturing or use. Furthermore, the width D2 of the top opening OP2 is preferably in the range of 16 μm to 20 μm.

[0037] See also Figure 2 and Figure 3 For products of different sizes or with multiple through holes, due to their structural limitations, the relative dimensions of D1 and D2 can be adjusted according to the actual current density requirements and process capabilities for flexible design. For example, the ratio range of 0.2≤D1 / D2≤0.5 can be met. Regardless of how the absolute size of the chip is scaled proportionally, as long as D1 / D2 is kept between 0.2 and 0.5, it is possible to balance low contact resistance and good electrode coverage, thereby broadening the applicability of this multi-segment angle structure. Its improvement in product performance such as brightness and reliability is similar to the principle of the above implementation method and can be expected, so it will not be elaborated here.

[0038] The improved via wall 410 provided in this embodiment is adaptable to various via shapes to meet the needs of chips of different specifications. The bottom opening OP1 of the via is a combination of one or more of the following shapes: circular, elliptical, elongated, or polygonal with curved chamfers. The shape of its top opening OP2 is usually adapted to the bottom opening OP1 to form a good transition of the multi-segment sidewall structure, and can effectively avoid the electric field concentration at sharp corners, further improving the ESD capability of the device.

[0039] See Figure 6The insulating layer 400 is a distributed Bragg reflector structure, also known as a DBR structure. The DBR, as an insulating layer, is the basis for achieving its good reflective properties and chip brightness. This DBR structure includes several alternately stacked first material layers 401 and second material layers 402. The first material layer 401 or the second material layer 402 is one or more of SiO2, TiO2, NbO2, ZrO2, or Ta2O5. The refractive index of the first material layer 401 is less than that of the second material layer 402. As an example, the first material layer 401 is a SiO2 layer, and the second material layer 402 is a TiO2 layer.

[0040] See also Figure 6 In some embodiments, the insulating layer 400 includes 15 to 30 pairs of alternately stacked dielectric layer pairs, such as 16, 18, 20, or 24 pairs of alternately stacked dielectric layer pairs. To achieve a high reflectivity of over 95%, at least 15 pairs of dielectric layer pairs should be provided. It is understood that, with the single film layer thickness remaining constant, a larger number of stacked layers will correspondingly increase the thickness of the insulating layer to improve the reflectivity of the insulating layer 400. However, a larger number of layers also brings difficulties to its fabrication process and subsequent etching process. Deposition time, cost, and structural layer yield all increase with the increase in thickness, and too many layers will lead to the continuous accumulation of internal stress. Further, the insulating layer 400 includes 20 to 30 pairs or 24 to 36 pairs of alternately stacked SiO2 / TiO2 dielectric layer pairs.

[0041] In some embodiments, the thickness of a single layer of the first material layer 401 is between 20 nm and 400 nm; the thickness of a single layer of the second material layer 402 is between 20 nm and 400 nm; and the total thickness of the insulating layer 400 is between 4.0 μm and 7.0 μm. The thickness of the insulating layer is positively correlated with its reflectivity, and a lower limit of 4.0 μm for the total thickness ensures that the minimum reflectivity meets the preset requirements. Further, the thickness of a single layer of both the first material layer 401 and the second material layer 402 is between 30 nm and 300 nm or between 60 nm and 200 nm, the total thickness of the insulating layer 400 is between 5.0 μm and 6.0 μm, and it includes 20 to 30 pairs of dielectric layers.

[0042] See Figure 2 and Figure 3 An electrode layer 500 is formed on the upper surface of the insulating layer 400 and at the through-holes. The electrode layer 500 includes a first electrode 510 and a second electrode 520. The first electrode 510 is electrically connected to the first semiconductor layer 210, and the second electrode 520 is electrically connected to the second semiconductor layer 230 through the current spreading layer 300. The electrode material includes gold, germanium, beryllium, nickel, palladium, zinc, or alloys thereof. The first electrode 510 and the second electrode 520 can be metal layers or multiple metal stacks with the same material and structure.

[0043] See also Figure 2 and Figure 3 The second electrode 520 is in direct contact with the current spreading layer 300. Further, the thickness of the current spreading layer 300 is between 20 Å and 200 Å, and the current spreading layer 300 also has a groove extending from its upper surface into its interior. The groove is connected to the bottom opening OP1 of the insulating layer 400, and the ratio of the groove depth to the thickness of the current spreading layer 300 is between 0.01 and 0.05. For example, if the thickness of the current spreading layer 300 is 100 Å, its groove depth is 5 Å. The groove enhances the electrode bonding strength and electrical connection reliability of the current spreading layer 300, reduces the risk of electrode peeling, and further optimizes the ohmic contact.

[0044] See also Figure 2 and Figure 3 In some embodiments, the height of the first inclined segment 411 is less than the thickness of the electrode layer 500, specifically less than the thickness of the second electrode 520. This ensures that the electrode material at the steepest section at the bottom of the via can completely fill the via, forming a continuous and unbroken conductive channel, thus guaranteeing chip yield and reliability. If the height of the first inclined segment 411 is greater than the electrode thickness, the electrode metal may become extremely thin or even broken on the upper surface of the electrode when filling the bottom of the via, leading to a surge in resistance or an open circuit. Further, the thickness of the electrode layer 500 is 0.5 μm to 4.0 μm, and the height of the first inclined segment 411 is 0.1 μm to 2.0 μm.

[0045] See also Figure 2 and Figure 3 Since the electrode structure is attached to the through-hole structure, the second electrode 520 has a recessed area located above the through-hole of the insulating layer 400, forming a corresponding two-segment recessed structure with the through-hole wall 410. It is understood that the through-hole sidewalls of traditional light-emitting diodes have a large slope, resulting in high internal stress during electrode deposition. Furthermore, uneven electrode coverage at the junction of the through-hole wall 410 and the upper and lower surfaces leads to numerous problems such as increased resistance, decreased luminous efficiency, and pits on the electrode surface. The technical solution provided in this embodiment optimizes the structure of the through-hole wall 410 of the insulating layer 400, thereby improving the morphology of the upper surface of the second electrode 520. The upper surface of the second electrode 520 naturally forms a two-segment recess corresponding to the through-hole wall 410, proving that the electrode is completely filled without breakage, ultimately resulting in a more uniform electrode coverage structure.

[0046] Example 2: This embodiment also provides a light-emitting diode, see [link to example]. Figures 4 to 6The light-emitting diode (LED) includes at least a substrate 100, a semiconductor stack 200, a current spreading layer 300, an insulating layer 400, and an electrode layer 500. The similarities to Embodiment 1 are not repeated here. This embodiment, based on Embodiment 1, further optimizes the via wall 410 into a three-segment structure to accommodate a thicker DBR structure reflective layer and achieve better electrode coverage. The differences between the LED provided in this embodiment and Embodiment 1 are described in detail below.

[0047] See Figure 4 and Figure 5 In some embodiments, an insulating layer 400 is provided above and on the sidewalls of the semiconductor stack 200 and the current spreading layer 300. The insulating layer 400 has through holes, which include opposing top openings OP2 and bottom openings OP1 and a through hole wall 410. The bottom opening OP1 contacts the current spreading layer 300. The through hole wall 410 has a three-segment structure, specifically including a first inclined segment 411, a second inclined segment 412, and a third inclined segment 413 connected in sequence. The first inclined segment 411 is closer to the bottom opening OP1 than the third inclined segment 413, and the angles ∠C between the first inclined segment 411 and the horizontal direction, ∠D between the second inclined segment 412 and the horizontal direction, and ∠E between the third inclined segment 413 and the horizontal direction decrease sequentially. By designing the traditional via wall in three sections—a larger angle near the bottom and a smaller angle near the top, with the second inclined section 412 as the middle section—a smoother transition for electrode deposition can be provided. This avoids electrode metal breakage due to insufficient coverage at steep steps, improving the reliability of the electrode structure and chip products. Typically, the included angle ∠C of the first inclined section 411 is larger than the inclined angle of the traditional via wall, and the width of its bottom opening OP1 can be larger than the bottom opening width of a traditional via, further increasing the contact area between the second electrode 520 and the current spreading layer 300 and reducing the operating voltage. The included angle ∠D of the second inclined section 412 is similar to or slightly larger than the inclined angle of the traditional via wall. The opening channel with decreasing angles from bottom to top significantly reduces stress concentration of the electrode film in continuous deep holes, effectively preventing electrode film breakage without sacrificing the insulating layer coverage area.

[0048] The three-section via wall structure provided in this embodiment can be achieved by controlling the etching selectivity. Specifically, the photoresist and DBR material have different etching selectivity under different etching parameters. The higher the selectivity, the steeper the sidewall angle; conversely, the lower the selectivity, the gentler the sidewall angle. The via fabrication process is divided into three stages: in the first etching stage, the steepest sidewall is formed with a high etching selectivity; after reaching the depth of the first inclined section 411, the second etching stage is entered, forming a sidewall with a transition angle with a medium etching selectivity; and after the cumulative depth reaches the depth of the first inclined section 411 and the second inclined section 412, the third etching stage is entered, forming the gentlest sidewall with a low etching selectivity, providing a good slope structure for electrode coverage.

[0049] See also Figure 4 and Figure 5 In some embodiments, the angle ∠C between the first inclined segment 411 and the horizontal direction is 55° to 65°, the angle ∠D between the second inclined segment 412 and the horizontal direction is 45° to 55°, and the angle ∠E between the third inclined segment 413 and the horizontal direction is 30° to 40°. For example, by controlling the etching process parameters, the angle ∠C can be formed to be 58°, 60°, 62°, or 64°, while the angle ∠D can be formed to be 46°, 48°, 50°, or 54°, and the angle ∠E can be formed to be 32°, 35°, or 38°. The gentle slope of the uppermost third inclined segment 413 provides optimal electrode coverage conditions, the middle segment serves as a transition, and the bottom layer determines the via size and insulating layer coverage area, thereby maximizing overall performance. Further, the thickness of the first inclined segment 411 is between 0.1 μm and 1.5 μm, and the thickness of the first inclined segment 411 accounts for 10% to 50% of the total thickness of the insulating layer; the thickness of the second inclined segment 412 is between 1 μm and 5 μm, and the thickness of the second inclined segment 412 accounts for 30% to 80% of the total thickness of the insulating layer; the thickness of the third inclined segment 413 is between 0.1 μm and 1.5 μm, and the thickness of the third inclined segment 413 accounts for 10% to 50% of the total thickness of the insulating layer. For example, the thickness of the first inclined segment 411 can be 0.2 μm, 0.5 μm, 1.0 μm, or 1.2 μm; the thickness of the second inclined segment 412 can be 1.5 μm, 2.0 μm, 3.0 μm, or 4.0 μm; and the thickness of the third inclined segment 413 can be 0.2 μm, 0.5 μm, 1.0 μm, or 1.2 μm. Furthermore, the thickness of the second electrode 520 is greater than the height of the first inclined segment 411 to ensure that the metal can be completely filled at the bottom of the through hole, forming a good continuous conductive path.

[0050] See Figure 6The insulating layer 400 is a distributed Bragg reflector (DBR) structure, which includes 15 to 40 pairs of alternately stacked dielectric layers. The first material layer 401 is a SiO2 layer, and the second material layer 402 is a TiO2 layer. The thickness of each single layer of the first material layer 401 and the second material layer 402 is between 20 nm and 400 nm, and the total thickness of the insulating layer 400 is between 4.0 μm and 7.0 μm. Further, the first inclined segment 411 has 2 to 8 dielectric layer pairs, the second inclined segment 412 has 4 to 25 dielectric layer pairs, and the third inclined segment 413 has 2 to 8 dielectric layer pairs.

[0051] See Figure 4 and Figure 5 In some embodiments, the first inclined segment 411 and the second inclined segment 412 are relatively steep sections within the via, together forming the main sidewall structure of the via. The sum of the heights of the first inclined segment 411 and the second inclined segment 412 accounts for 50% to 90% of the total thickness of the insulating layer, ensuring a compact via body to retain the reflective area, while leaving sufficient gentle slope at the top, i.e., the third inclined segment 413, to ensure electrode coverage. For example, for a DBR with a thickness of 5.1 μm, the total height of the first inclined segment 411 and the second inclined segment 412 can be set to 2.6 μm to 4.6 μm. Further, the sum of their heights accounts for 70% to 85% of the total thickness of the insulating layer. By limiting the total height of the first inclined segment 411 and the second inclined segment 412 with larger tilt angles, the loss of reflective area of ​​the insulating layer is minimized, thereby improving the luminous brightness of the chip. If this proportion is too low, the corresponding gently sloping third inclined section 413 will account for a large proportion, leading to a sharp increase in the top opening size of the via and a loss of more reflective area. The sum of the heights of the third inclined sections 413 should account for 20% to 50% of the total thickness of the insulating layer to ensure a smooth, non-sharp transition of the electrode metal from the upper surface of the DBR to the interior of the via. Furthermore, the sum of the heights of the third inclined sections 413 should account for 15% to 30% of the total thickness of the insulating layer.

[0052] See also Figure 4 and Figure 5 Since the electrode structure is attached to the through hole structure, the second electrode 520 also has a recessed area. The recessed area is located above the through hole of the insulating layer 400 and forms a corresponding three-segment recessed structure with the through hole wall 410, proving that the electrode is completely filled and without breakage, and finally a more uniform electrode coverage structure is obtained.

[0053] Example 3: This embodiment also provides a light-emitting diode, see [link to example]. Figure 7 and Figure 8The light-emitting diode (LED) includes at least a substrate 100, a semiconductor stack 200, a current spreading layer 300, an insulating layer 400, and an electrode layer 500. The via wall 410 of the insulating layer 400 has a three-segment structure to accommodate a thicker DBR structure reflective layer and achieve better electrode coverage. The specific structure and technical solution of the LED provided in this embodiment will be described in detail below.

[0054] See Figure 7 and Figure 8 A current spreading layer 300 is disposed on the second semiconductor layer 230. Unlike the technical solution provided in Embodiment 2, a contact electrode layer is also required. The contact electrode layer includes a first contact electrode layer 511 disposed on the mesa of the first semiconductor layer 210 and a second contact electrode layer 522 disposed on the current spreading layer 300. The first contact electrode layer 511 can form a low-resistance ohmic contact with the first semiconductor layer, such as an N-type GaN layer. The second contact electrode layer 521 can form a low-resistance ohmic contact with the current spreading layer 300, such as an ITO layer, and can improve the adhesion between the current spreading layer 300 and the upper electrode structure, ensuring efficient and stable current transmission. Further, the ohmic contact layer is made of materials such as Ni / Au or Ag alloy, and its thickness is between 5 nm and 100 nm.

[0055] See also Figure 7 and Figure 8 An insulating layer 400 is provided above and on the sidewalls of the semiconductor stack 200 and the current spreading layer 300. Through-holes are formed in the insulating layers 400 on the first semiconductor layer 210 and the second semiconductor layer 230, respectively, to expose the first contact electrode layer 511 and the second contact electrode layer 521. The through-hole on the second ohmic contact layer 521 includes a top opening OP2 and a bottom opening OP1, as well as a through-hole wall 410. The bottom opening OP1 exposes the second ohmic contact layer 521. It is understood that the insulating layer 400 above the first ohmic contact layer 511 also has through-holes, which will not be elaborated here.

[0056] The through-hole wall 41 can be a two-section structure or a three-section structure. The through-hole wall 41 provided in this embodiment is a three-section structure, specifically including a first inclined section 411, a second inclined section 412 and a third inclined section 413 connected in sequence. The first inclined section 411 is closer to the bottom opening OP1 than the third inclined section 413, and the angles ∠C between the first inclined section 411 and the horizontal direction, ∠D between the second inclined section 412 and the horizontal direction, and ∠E between the third inclined section 413 and the horizontal direction decrease sequentially.

[0057] This embodiment also provides a specific product structure of a light-emitting diode, which includes, from bottom to top: Substrate 100: includes a patterned sapphire substrate with a thickness of 100 μm.

[0058] Semiconductor stack 200: sequentially includes an N-type GaN layer with a thickness of 3 μm, and an In layer. x Ga 1-x The N / GaN multi-quantum-well structure and the 0.2μm thick P-type GaN layer emit blue light with a wavelength of 450nm.

[0059] Current spreading layer 300: An ITO material layer with a thickness of 150 Å disposed on top of the P-type GaN layer.

[0060] Contact electrode layer: includes a first ohmic contact layer 511 disposed on the mesa of the N-type GaN layer and a second ohmic contact layer 521 disposed on the current spreading layer 300.

[0061] Insulating layer 400: Includes a distributed Bragg reflector (DBR) structure disposed above and on the sidewalls of the first ohmic contact layer 511, the current spreading layer 300, and the exposed semiconductor stack 200. The DBR layer is composed of 28 pairs of alternating SiO2 and TiO2 layers. The thickness of a single SiO2 layer is approximately 100 nm, the thickness of a single TiO2 layer is approximately 80 nm, and the total thickness of the DBR layer can reach approximately 5.1 μm, which is an ultra-thick DBR structure. Insulating layer 400 has vias, which include opposing top openings OP1 and bottom openings OP2, as well as via walls 410. The bottom opening OP1 contacts the current spreading layer 300, and the bottom opening size of the via is 4.0 μm. The through-hole wall 410 has a three-section structure, consisting of a first inclined section 411, a second inclined section 412, and a third inclined section 413 connected sequentially from the bottom opening OP1 to the top opening OP2. The first inclined section 411 has a height of 0.8 μm and an angle of 55° to 65° with the horizontal direction. The second inclined section 412 has a height of 3 μm and an angle of 45° to 55° with the horizontal direction. The third inclined section 413 has a height of 1.3 μm and an angle of 30° to 40° with the horizontal direction.

[0062] Electrode layer 500: includes an N electrode electrically connected to the N-type GaN layer and a P electrode electrically connected to the P-type GaN layer via ITO. The electrode materials are both Cr / Al / Ti / W composite metal stacks with a total thickness of 2.0 μm.

[0063] The above-mentioned products employ a three-section design for the insulating layer through-hole wall of the light-emitting diode, ensuring that the metal electrode is completely filled at the bottom and that the electrode is uniformly covered without breaks. This minimizes the loss of the reflective layer area while ensuring its contact area with the current spreading layer, achieving the effect of reducing voltage and increasing brightness. The ultra-thick DBR structure with the above three-section through-hole wall design has a light reflectivity of up to 98%.

[0064] Example 4: See Figure 9 This embodiment provides a light-emitting device 10, which is a flip-chip LED product, including a packaging substrate 101; at least one light-emitting diode disposed on the surface of the packaging substrate 101, and the packaging substrate 101 and the electrode structure of the light-emitting diode are electrically connected. The light-emitting element 102 is the light-emitting diode provided in Embodiment 1 or Embodiment 2. This light-emitting device has higher brightness, longer service life and better stability in terminal products such as displays and backlight modules.

[0065] In summary, the light-emitting diode and light-emitting device provided in this application have high industrial application value because they effectively overcome the various shortcomings of the prior art.

[0066] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A light-emitting diode, characterized in that, At least including: Substrate; A semiconductor stack is disposed on the substrate, comprising a first semiconductor layer, an active layer and a second semiconductor layer stacked sequentially. A current spreading layer is disposed on the second semiconductor layer; An insulating layer is disposed above and on the sidewalls of the semiconductor stack and the current spreading layer. The insulating layer has through-holes, each through-hole including opposing top and bottom openings and a through-hole wall. The through-hole wall has a multi-segment structure, including a first inclined segment and a second inclined segment that are connected. The first inclined segment is closer to the bottom opening than the second inclined segment, and the angle between the first inclined segment and the horizontal direction is greater than the angle between the second inclined segment and the horizontal direction.

2. The light-emitting diode according to claim 1, characterized in that, The angle between the first inclined segment and the horizontal direction is 45° to 65°; the angle between the second inclined segment and the horizontal direction is 30° to 50°.

3. The light-emitting diode according to claim 1, characterized in that, The through-hole wall also includes a third inclined section, which is connected to the second inclined section and is closer to the top opening; the angle between the second inclined section and the horizontal direction is greater than the angle between the third inclined section and the horizontal direction.

4. The light-emitting diode according to claim 3, characterized in that, The first inclined segment has an angle of 55° to 65° with the horizontal direction; the second inclined segment has an angle of 45° to 55° with the horizontal direction; and the third inclined segment has an angle of 30° to 40° with the horizontal direction.

5. The light-emitting diode according to claim 3, characterized in that, The sum of the heights of the first inclined segment and the second inclined segment accounts for 50% to 90% of the total thickness of the insulating layer.

6. The light-emitting diode according to claim 1, characterized in that, The insulating layer is a distributed Bragg reflection structure, comprising several alternately stacked first and second material layers, wherein the thickness of a single first or second material layer is between 20 nm and 400 nm; and the total thickness of the insulating layer is between 4.0 μm and 7.0 μm.

7. The light-emitting diode according to claim 1, characterized in that, The width of the bottom opening is defined as D1, where 3μm≤D1≤10μm; The width of the top opening is defined as D2, where 15μm≤D2≤22μm.

8. The light-emitting diode according to claim 1, characterized in that, The width of the bottom opening is defined as D1, and the width of the top opening is defined as D2, where 0.2 ≤ D1 / D2 ≤ 0.

5.

9. The light-emitting diode according to claim 1, characterized in that, The top opening and / or bottom opening of the through hole are in the shape of one or more of the following: circular, elliptical, elongated, or polygonal with curved chamfers.

10. The light-emitting diode according to claim 1, characterized in that, The thickness of the current spreading layer is between 20 Å and 200 Å, and the current spreading layer also has a groove extending from its upper surface to its interior, the groove being connected to the bottom opening of the insulating layer, and the ratio of the depth of the groove to the thickness of the current spreading layer is between 0.01 and 0.

05.

11. The light-emitting diode according to claim 1, characterized in that, It also includes an electrode layer that covers a portion of the upper surface of the insulating layer and fills the via for electrical connection with the current spreading layer.

12. The light-emitting diode according to claim 11, characterized in that, The height of the first inclined segment is less than the thickness of the electrode layer.

13. The light-emitting diode according to claim 11, characterized in that, The electrode layer has a recessed area located above the through hole of the insulating layer, and forms a corresponding multi-segment recessed structure with the through hole wall.

14. A light-emitting device, characterized in that, The light-emitting device includes: Packaging substrate; At least one light-emitting diode is disposed on the surface of the packaging substrate, and the packaging substrate and the electrode structure of the light-emitting diode are electrically connected; the light-emitting diode is the light-emitting diode according to any one of claims 1 to 13.

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