Waveform aware mixed signal measurement system for bus traffic reduction in system-on-chip devices

Abstract

A processor-implemented method for managing bus traffic of a system-on-chip (SoC) includes receiving a mixed signal in a computing device including the SoC. One or more polarity changes in a slope of a waveform corresponding to the mixed signal are detected. One or more of an analog-to-digital converter (ADC) or a portion of SoC bus traffic associated with ADC operation is selectively disabled between one or more polarity changes in a slope of a waveform.

Description

Cross-references to related applications

[0001] This application claims priority to U.S. Patent Application No. 18 / 464,136, filed September 8, 2023, entitled “WAVEFORM-AWARE MIXED SIGNALMEASUREMENT SYSTEM FOR BUS TRAFFIC REDUCTION IN SYSTEM-ON-A-CHIP DEVICES,” the entire disclosure of which is expressly incorporated herein by reference. Technical Field

[0002] Various aspects of this disclosure relate to computing devices, and more specifically to power optimization and waveform-aware mixed-signal measurement systems for reducing bus traffic in system-on-chip (SoC) devices. Background Technology

[0003] Mobile or portable computing devices include mobile phones, laptops, handheld computers and tablets, portable digital assistants (PDAs), portable game consoles, and other portable electronic devices. Mobile computing devices consist of numerous power-consuming and heat-generating electronic components. These components (or computing devices) can include system-on-a-chip (SoC) devices, graphics processing units (GPUs), neural processing units (NPUs), digital signal processors (DSPs), and modems, among others.

[0004] Measuring and monitoring power and thermal conditions in mobile computing devices and automotive applications is crucial for mitigating safety issues. Power, thermal, and sensor parameters of SoC devices can be periodically monitored, both on-chip and off-chip, for auxiliary chipsets. However, such measurements and monitoring can introduce significant sparsity in data collection, as well as additional traffic on the SoC bus, along with heat and power dissipation, potentially hindering SoC performance. Summary of the Invention

[0005] In some aspects of this disclosure, a processor-implemented method includes receiving a mixed signal in a computing device including a system-on-chip (SoC). The processor-implemented method further includes detecting one or more polarity changes in the slope of a waveform corresponding to the mixed signal. The processor-implemented method further includes selectively disabling one or more of an analog-to-digital converter (ADC) or SoC bus traffic associated with ADC operation between the one or more polarity changes in the slope of the waveform.

[0006] Various aspects of this disclosure relate to an apparatus including components for receiving a mixed signal in a computing device including a system-on-chip (SoC). The apparatus further includes components for detecting one or more polarity changes in the slope of a waveform corresponding to the mixed signal. The apparatus further includes components for selectively disabling at least a portion of an analog-to-digital converter (ADC) or SoC bus traffic associated with ADC operation between the one or more polarity changes in the slope of the waveform.

[0007] In some aspects of this disclosure, a non-transitory computer-readable medium having non-transitory program code recorded thereon is disclosed. This program code is executed by a processor and includes program code for receiving a mixed signal in a computing device including a system-on-chip (SoC). The program code also includes program code for detecting one or more polarity changes in the slope of a waveform corresponding to the mixed signal. The program code further includes program code for selectively disabling at least a portion of an analog-to-digital converter (ADC) or SoC bus traffic associated with ADC operation between the one or more polarity changes in the slope of the waveform.

[0008] Various aspects of this disclosure relate to a system for mixed-signal management. The system includes a detection device for detecting one or more polarity changes in the slope of a waveform corresponding to one or more mixed signals in a computing device including a system-on-chip (SoC). The system also includes a mixed-signal controller for controlling SoC bus traffic or an analog-to-digital converter (ADC) based on the one or more polarity changes in the slope of the waveform corresponding to the one or more mixed signals.

[0009] This has provided a broad overview of the features and technical advantages of this disclosure in order to facilitate a better understanding of the following detailed description. Additional features and advantages of this disclosure will be described below. Those skilled in the art will understand that this disclosure can be readily used as the basis for modifying or designing other structures for implementing the same purposes as this disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the teachings of this disclosure as set forth in the appended claims. Novel features considered characteristic of this disclosure, in both their organization and manner of operation, along with further objects and advantages, will be better understood when the following description is considered in conjunction with the accompanying drawings. However, it is to be clearly understood that each drawing is provided for illustrative and descriptive purposes only and is not intended to be a definition of a limitation of this disclosure. Attached Figure Description

[0010] To gain a more complete understanding of this disclosure, reference is now made to the following description in conjunction with the accompanying drawings.

[0011] Figure 1Example implementations of a host system-on-chip (SoC) including a mixed-signal waveform sensing measurement system according to certain aspects of this disclosure are illustrated.

[0012] Figure 2 This is a block diagram illustrating example computing systems according to various aspects of this disclosure.

[0013] Figure 3A This is a block diagram illustrating various aspects of a mixed signal peak and valley monitor (PDM) according to this disclosure.

[0014] Figure 3B This is a diagram illustrating example waveforms of the power supply voltage Vdd according to various aspects of this disclosure.

[0015] Figure 3C This is a diagram illustrating an example architecture of a peak and trough monitor (PDM) according to various aspects of this disclosure.

[0016] Figure 4 This illustrates various aspects including those according to this disclosure. Figure 3A A block diagram of an example system for reducing bus traffic using PDM.

[0017] Figure 5 This illustrates various aspects including those according to this disclosure. Figure 3A A block diagram of an example system for reducing bus traffic using PDM.

[0018] Figure 6 This illustrates various aspects including those according to this disclosure. Figure 3A A block diagram of an example system for reducing bus traffic using PDM.

[0019] Figure 7 This is a flowchart illustrating various aspects of an example process according to this disclosure, which is performed, for example, by a processor for waveform-aware mixed-signal measurements for bus traffic reduction.

[0020] Figure 8 This is a block diagram illustrating an exemplary wireless communication system in which the configurations of this disclosure may be advantageously employed.

[0021] Figure 9 This is a block diagram illustrating a design workstation for circuit, layout, and logic design of components according to various aspects of this disclosure. Detailed Implementation

[0022] The detailed description following, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and not as representing only configurations in which the described concepts can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0023] As described, the term "and / or" is used to indicate "inclusive or," and the term "or" is used to indicate "exclusive or." As described, the term "exemplary" as used throughout the description means "used as an example, instance, or illustration" and is not necessarily to be construed as preferred or advantageous over other exemplary configurations. As described, the term "coupled" as used throughout the description means "directly or indirectly connected via an intermediary connection (e.g., a switch), electrical, mechanical, or otherwise," and is not necessarily limited to physical connections. Furthermore, a connection can result in objects being permanently or releasably connected. Connections can be made via switches. As described, the term "proximity" as used throughout the description means "adjacent, very close, adjacent, or near." As described, the term "on" as used throughout the description means "directly on" in some configurations and "indirectly on" in others.

[0024] As described, measuring and monitoring power and thermal conditions in mobile computing devices and automotive applications is important for mitigating safety issues. Power, thermal, and sensor parameters of SoC devices can be periodically monitored, both on-chip and off-chip, for auxiliary chipsets. For example, digital power meters, current sensors, internal processing analog-to-digital converters (ADCs), and other sensors and monitoring devices can be used in conjunction with SoC, application-specific integrated circuits (ASICs), or associated power management integrated circuits (PMICs).

[0025] A single ADC can be used with a multiplexer (MUX) to periodically sample and monitor the outputs of internal on-chip current and voltage sensors, as well as off-chip parameters. The ADC uses the MUX to periodically sample multiple inputs in different time slots. However, managing the occasional high activity of the power rails can be challenging for a single ADC.

[0026] In automotive applications, the bus traffic of the SoC can be further increased for safety and SoC power measurement. For example, automotive integrated circuits (ICs) can have extensive test and safety features, such as error correction and triple modular redundancy. In addition, automotive ICs may include real-time monitoring of regulator output voltage, current and temperature, as well as watchdog timers, frequency monitors and built-in self-test (BIST) for various subsystems for power-on or other safety checks.

[0027] Conventional methods for addressing intermittent activity may involve increasing the clock frequency. However, increasing the clock frequency can significantly increase power and heat dissipation on the SoC bus and constrain the ADC specifications.

[0028] Additionally, periodic sampling can lead to inefficiency and potentially introduce significant sparsity and additional overhead in data collection if sensors are idle. Specifically, the ADC may inefficiently oversample some idle sensor parameters, generating redundant or unnecessary overhead, and may also increase power dissipation in data transmission between Advanced Driver Assistance Systems (ADAS) devices and edge / cloud systems.

[0029] Therefore, various aspects of this disclosure relate to intelligent data collection and measurement systems for SoCs and associated subsystems. In various aspects, a waveform-aware mixed-signal measurement system is proposed. Changes in the mixed-signal waveform can be monitored and used to regulate SoC bus traffic.

[0030] Specific aspects of the subject matter described in this disclosure may be implemented to achieve one or more of the following potential advantages. In some examples, the described techniques can achieve reduced SoC bus throughput as well as reduced heat dissipation and power dissipation.

[0031] Figure 1 Example implementations of a host system-on-chip (SoC) 100, including a mixed-signal waveform sensing measurement system, are illustrated according to various aspects of this disclosure. The host SoC 100 includes processing blocks tailored for specific functions, such as a connectivity block 110. The connectivity block 110 may include fifth-generation (5G) connectivity, fourth-generation LTE (4G LTE) connectivity, Wi-Fi connectivity, Universal Serial Bus (USB) connectivity, and Bluetooth. ® Connectivity, Secure Digital (SD) connectivity, etc.

[0032] In this configuration, the host SoC 100 includes various processing units that support multi-threaded operation. Figure 1As shown in the configuration, the host SoC 100 includes a multi-core central processing unit (CPU) 102, a graphics processing unit (GPU) 104, a digital signal processor (DSP) 106, and a neural processing unit (NPU) 108. The host SoC 100 may also include a sensor processor 114, an image signal processor (ISP) 116, a navigation module 120, and a memory 118, which may include a Global Positioning System (GPS). The multi-core CPU 102, GPU 104, DSP 106, NPU 108, and multimedia engine 112 support various functions such as video, audio, graphics, games, and artificial intelligence networks. Each processor core of the multi-core CPU 102 can be a Reduced Instruction Set Computing (RISC) machine, an Advanced RISC machine (ARM), a microprocessor, or some other type of processor. The NPU 108 may be based on the ARM instruction set.

[0033] Figure 2 This is a block diagram illustrating an example computing system 200 according to various aspects of this disclosure. For example... Figure 2 As shown, the example computing system 200 may include a host SoC 202. The host SoC 202 may include components and functions similar to those of SoC 100 (figure). Figure 2 As shown, the host SoC 202 includes interface circuits 204a-204b and an ADC 206. The interface circuits 204a-204b provide connectivity to one or more power management integrated circuits (PMICs) 214a-214b. Furthermore, the interface circuits provide connectivity to one or more external chipsets 210a-210z and external sensor or auxiliary integrated circuit devices 220a-220z. In some aspects, the external chipsets 210a-210z may, for example, include additional processors, such as one or more external GPUs 210 or one or more wireless communication devices that facilitate communication such as 5G, 6G, vehicle-to-everything (V2X) communication, wireless local area network (WLAN), etc. Furthermore, in various aspects, the external chipsets 210a-210z may, for example, relate to vehicle control and safety systems.

[0034] The sensor / auxiliary IC devices 220a-220z can power sensors (e.g., digital power meters), thermal sensors, current sensors, voltage sensors, and transmit power level sensors.

[0035] SoC 202 may include a single ADC 206. ADC 206 may periodically sample and monitor mixed signals, such as the outputs of an internal on-chip current sensor and voltage sensor. Additionally, ADC 206 may periodically sample and monitor off-chip parameters, such as sensor output parameters associated with sensor / auxiliary IC devices 220a-220z. In an example, for instance, ADC 206 may receive analog voltage signals (e.g., via interface circuitry 204a) from a power supply (e.g., PMICs 214a-214b). ADC 206 may digitally encode the analog signals to convert the analog voltage signals into digital outputs. ADC 206 may include both analog and digital circuitry and can therefore be considered a mixed-signal integrated circuit. In some aspects, ADC 206 may also convert other analog signals provided to computing system 200 into digital outputs. For example, ADC 206 may convert signals from sensors (e.g., Figure 1 Analog signals from 114 or sensor / auxiliary IC devices 220a-220z (such as temperature sensors, light sensors, sonar signals, video signals, gyroscope sensors, etc.).

[0036] For example, ADC 206 can use bus transmission protocols such as Advanced Microcontroller Bus Architecture (AMBA) and Advanced High Performance Bus (AHB) protocols to distribute digital outputs to digital components of computing system 200. Therefore, ADC 206 facilitates bus traffic on SoC 100 when it performs the operation of converting an analog signal into a digital output and distributing that output to another component of computing system 200.

[0037] Figure 3A This is a block diagram illustrating a mixed-signal peak and valley monitor (PDM) 300 according to various aspects of this disclosure. Reference Figure 3A The PDM 300 can be coupled to the ADC 302, the host SoC (e.g., 100 or 202), and the supply voltage Vdd. The ADC 302 has... Figure 2 It has a similar configuration to the ADC 206 and can function in a similar way to the ADC 206.

[0038] The PDM 300 can monitor the supply voltage Vdd (or other mixed signals). For example, the PDM 300 can monitor voltage drops or overshoot conditions. Periodic signaling by the ADC 302 (e.g., power conversion and related signals) can overload the memory and / or cause significant power consumption.

[0039] In various aspects of this disclosure, the PDM 300 can monitor the power supply voltage Vdd or other mixed signals on a periodic or non-periodic basis. The PDM 300 can monitor the polarity of the slope of the power supply voltage Vdd waveform. The PDM 300 can send a signal to the ADC 302 to trigger control signaling based on the timing of the peaks and valleys of the power supply voltage waveform, rather than allowing the ADC 302 to perform repetitive signaling due to voltage transitions. For example, the PDM 300 signal can trigger the ADC 302 to stop analog-to-digital conversion operations associated with the monitored waveform (e.g., the power supply voltage signal). Furthermore, in various aspects, the PDM 300 signal can trigger the ADC 302 to reduce and, in some respects, stop downstream bus traffic associated with the monitored waveform.

[0040] although Figure 3A The example described relates to monitoring of the supply voltage Vdd, but this disclosure is not limited thereto, and the PDM 300 can monitor any other mixed signals. Furthermore, although... Figure 3A This includes one PDM 300, but it should be understood that multiple PDMs may also be included in the computing system (e.g., 200). For example, multiple PDMs (e.g., 300) may monitor different mixed-signal and / or sensor parameters of the computing system (e.g., 200) and manage the associated ADC operations or bus traffic of the monitored mixed signals.

[0041] Figure 3B This is a diagram illustrating an example waveform 350 of the power supply voltage Vdd according to various aspects of this disclosure. For example... Figure 3B As shown, the waveform 350 of the power supply voltage Vdd can be a non-periodic signal with many variations in the polarity of its slope. Points 352a-352f can indicate variations in the polarity of the slope of the power supply voltage Vdd waveform 350. When the PDM 300 detects variations in the polarity of the slope (such as peaks (e.g., 352a, 352c, and 352e) or valleys (e.g., 352b, 352d, and 352f)), the PDM 300 can send a signal to the ADC 302 to enable the ADC 302 to perform power conversion and related signaling. That is, for example, the ADC 302 can receive the power supply voltage Vdd and, for example, the computing system (e.g., Figure 2 The corresponding device of the ADC 302 (200) performs the power conversion. Otherwise, the PDM 300 may command the ADC 302 to skip such power conversion or related signaling.

[0042] Figure 3C This is a diagram illustrating an example architecture of a peak and trough monitor (PDM) 300 according to various aspects of this disclosure. Reference Figure 3CExample PDM 300 may include a multiplexer 372, a sample and hold circuit 374, a comparator 376, a D flip-flop (DFF) 378, a delay circuit 380, and an XOR gate 382.

[0043] PDM 300 can receive input signals. Input signals may include mixed signals. Mixed signals may include (but are not limited to) power supply voltage signals (Vdd), sensor signals (e.g., current sensor, temperature sensor), or other mixed signals. Sample and hold circuit 374 can sample the input signal, which may be a continuously varying analog signal. Sample and hold circuit 374 can hold or fix the value of the input signal at a constant level for a predefined time period. For example, the input signal may include (but is not limited to) the power supply voltage Vdd. Sample and hold circuit 374 can sample the power supply voltage Vdd at times n-2 and n-1. The power supply voltage (Vdd) sampled at times n-2 and n-1 can be provided to comparator 376.

[0044] Comparator 376 compares the supply voltages Vdd(n-2) and Vdd(n-1) at time n. Comparator 376 generates an output indicating whether the supply voltage Vdd(n-2) is greater than Vdd(n-1). If the supply voltage Vdd(n-2) is less than Vdd(n-1), the peak value of the supply voltage Vdd waveform may not have been reached (e.g., if both values ​​are positive). On the other hand, if the supply voltage Vdd(n-2) is greater than Vdd(n-1), the peak value of the supply voltage Vdd waveform may have been reached (e.g., if both values ​​are positive), and the polarity of the slope of the supply voltage Vdd waveform may have changed.

[0045] The output of comparator 376 can be provided to DFF 378. DFF 378, delay circuit 380, and XOR gate 382 then extract peak-to-valley or valley-to-peak polarity changes from the waveform of the input signal (e.g., Vdd). DFF 378 stores the output of comparator 376. The comparator output at time n can be provided to delay circuit 380 to generate a delayed output. The delayed comparator output (e.g., the comparator output at time n-1) and the current comparator output (e.g., the comparator output at time n) can be provided to XOR gate 382.

[0046] XOR gate 382 can compare the current comparator output (e.g., the comparator output at time n) with the delayed comparator output (e.g., the comparator output at time n-1) to generate a trigger signal. For example, if the current comparator output (e.g., at time n) is different from the delayed comparator output (e.g., at time n-1), XOR gate 382 can output 1 to indicate that the polarity of the slope of the input signal (e.g., Vdd) waveform has changed. On the other hand, if the current comparator output (e.g., at time n) is the same as the delayed comparator output (e.g., at time n-1), XOR gate can output 0 to indicate that the polarity of the slope of the input signal (e.g., Vdd) waveform has not changed. The output of XOR gate 382 can also be a trigger signal controlling the operation of an ADC (e.g., 302). For example, if XOR gate 382 outputs 1, a trigger signal can be generated to enable the operation of the ADC (e.g., 302). Conversely, if the XOR gate 382 outputs 0, a trigger signal may not be generated, and the operation of the ADC (e.g., 302) or bus traffic associated with the input signal may be disabled.

[0047] Figure 4 This illustrates various aspects including those according to this disclosure. Figure 3A Block diagram of an example system 400 for bus traffic reduction using the PDM 300. (Reference) Figure 4 The PDM 300 can be coupled to the ADC 302 via multiplexers (MUX) 402a and 402b. As described, for example, the PDM 300 can monitor voltage drops or overshoot conditions of the supply voltage Vdd. However, by including MUX 402a and 402b, the PDM 300 can more finely customize the limitations on ADC conversions. That is, using MUX 402a and 402b, the PDM 300 can selectively limit ADC conversions and / or associated signaling for some blocks while allowing periodic signaling for other blocks. For example, the PDM 300 can advantageously implement such power conversions associated with certain automotive safety systems between polarity changes while limiting similar power conversions in other systems of the computing system (e.g., 200).

[0048] Additionally, such as Figure 4 As shown in the example, additional PDMs may be included for monitoring other mixed-signal inputs (e.g., sensor outputs, battery levels, temperature sensors, or current sensors). The output of such additional PDMs may be provided to the MUX402b to trigger the operation of the ADC with respect to a corresponding mixed-signal input among the respective mixed-signal inputs.

[0049] Figure 5 This illustrates various aspects including those according to this disclosure. Figure 3AA block diagram of an example system 500 for bus traffic reduction using the PDM 300. Example system 500 includes... Figure 4 The components shown. However, as Figure 5 As shown, the example system 500 for bus traffic reduction may further include delay elements 504a and 504b. Delay elements 504a and 504b can operate under the control of PDM 300. For example, during periods between polarity changes, PDM 300 can limit (e.g., disable) some power conversions performed by ADC 302. Furthermore, PDM 300 can control the delay elements to disable DFF 502 and driver 506 from sending relevant signals to the SoC 100 bus, thereby reducing SoC bus traffic. Additionally, DFF 502 and delay element 504 can synchronize data with the clock / enable (EN) to reduce and, in some respects, eliminate glitches and improve ADC performance.

[0050] Figure 6 This illustrates various aspects including those according to this disclosure. Figure 3A A block diagram of an example system 600 for bus traffic reduction using the PDM 300. Example system 600 includes... Figure 4 The components shown. However, as Figure 6 As shown, the example system 600 for bus traffic reduction may further include a counter 602 and an interpolator 604. In some respects, the slope of the power supply waveform Vdd may be important for certain applications (e.g., automotive safety applications). To provide such information, counter 602 may count the time periods (e.g., clock cycles) between polarity changes. Counter 602 can then be reset when a polarity change occurs. The count by counter 602 may indicate the number of clock cycles between polarity changes (e.g., peaks and valleys). The count indicated by counter 602 can be used to calculate the slope of the waveform.

[0051] Since the ADC can provide accurate values ​​for the peak and / or subsequent valley, the waveform between the peak and valley can be linearly reconstructed by determining the count.

[0052] Figure 7 This is a flowchart illustrating, for example, an example process 700 executed by a processor according to various aspects of this disclosure. Example process 700 is an example of waveform-sensing mixed-signal measurement for reduced bus traffic.

[0053] like Figure 7 As shown, at block 702, the processor can receive mixed signals in a computing device including a system-on-a-chip (SoC). For example, as referenced... Figure 3CAs described, the PDM 300 can receive input signals. Input signals may include mixed signals. Mixed signals may include (but are not limited to) power supply voltage signals (Vdd), sensor signals (e.g., current sensor, temperature sensor), or other mixed signals.

[0054] At box 704, the processor detects one or more polarity changes in the slope of the waveform corresponding to the mixed signal. For example, as referenced... Figure 3C As described, comparator 376 compares supply voltages Vdd(n-2) and Vdd(n-1) at time n. Comparator 376 generates an output indicating whether supply voltage Vdd(n-2) is greater than Vdd(n-1). The output of comparator 376 can be provided to DFF 378. DFF 378, delay circuit 380, and XOR gate 382 then extract peak-to-trough polarity changes or valley-to-peak polarity changes from the waveform of the input signal (e.g., Vdd).

[0055] At box 706, the processor selectively disables one or more of the analog-to-digital converter (ADC) or SoC bus traffic associated with ADC operation between one or more polarity changes in the slope of the waveform. For example, as referenced Figure 3C As described, the comparator output at time n can be provided to delay circuit 380 to generate a delayed output. The delayed comparator output (e.g., the comparator output at time n-1) and the current comparator output (e.g., the comparator output at time n) can be provided to XOR gate 382. XOR gate 382 can compare the current comparator output (e.g., the comparator output at time n) with the delayed comparator output (e.g., the comparator output at time n-1) to generate a trigger signal. If XOR gate 382 outputs 1, a trigger signal can be generated to enable the operation of the ADC (e.g., 302). Conversely, if XOR gate 382 outputs 0, no trigger signal can be generated, and the operation of the ADC (e.g., 302) or bus traffic associated with the input signal can be disabled.

[0056] Figure 8 This is a block diagram illustrating an exemplary wireless communication system 8 in which aspects of this disclosure may be advantageously employed. For illustrative purposes, Figure 8 Three remote units 820, 830, and 850, and two base stations 840 are shown. It should be understood that the wireless communication system may have more remote units and base stations. Remote units 820, 830, and 850 include integrated circuit (IC) devices 825A, 825B, and 825C, which include the disclosed bus traffic reduction system. It should be understood that other devices may also include the disclosed bus traffic reduction system, such as base stations, switching devices, and network equipment. Figure 8The forward link signal 880 from base station 840 to remote units 820, 830 and 850 is shown, as well as the reverse link signal 890 from remote units 820, 830 and 850 to base station 840.

[0057] exist Figure 8 In this diagram, remote unit 820 is shown as a mobile phone, remote unit 830 is shown as a portable computer, and remote unit 850 is shown as a fixed-location remote unit in a wireless local loop system. For example, a remote unit may be a mobile phone, a handheld personal communication system (PCS) unit, a portable data unit (such as a personal data assistant), a GPS-enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a fixed-location data unit (such as a meter reading device), or other devices that store or retrieve data or computer instructions, or combinations thereof. Figure 8 Remote units according to aspects of this disclosure are illustrated, but this disclosure is not limited to these exemplary illustrated units. Aspects of this disclosure may be adapted for use in a variety of devices, including the disclosed bus traffic reduction system.

[0058] Figure 9 This is a block diagram illustrating a design workstation 900 for circuit, layout, and logic design of semiconductor components, such as the PDM 300 disclosed above. The design workstation 900 includes a hard disk 901 containing operating system software, support files, and design software (such as Cadence or OrCAD). The design workstation 900 also includes a display 902 to facilitate the design of circuits 910 or semiconductor components 912 (such as the PDM 300). A storage medium 904 is provided for tangibly storing the design of circuits 910 or semiconductor components 912 (e.g., the PDM 300). The design of circuits 910 or semiconductor components 912 can be stored on the storage medium 904 in file formats such as GDSII or GERBER. The storage medium 904 can be a CD-ROM, DVD, hard disk, flash memory, or other suitable device. Furthermore, the design workstation 900 includes a drive device 903 for accepting input from the storage medium 904 or writing output to the storage medium.

[0059] Data recorded on storage medium 904 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial writing tools such as electron beam lithography. Data may also include logic verification data, such as timing diagrams or network circuits associated with logic simulations. Providing data on storage medium 904 facilitates the design of circuit 910 or semiconductor assembly 912 by reducing the number of processes required for designing semiconductor wafers.

[0060] Specific implementation examples are provided in the following numbered clauses.

[0061] 1. A processor-implemented method, the processor-implemented method comprising: Receive mixed signals in computing devices including System-on-Chip (SoC); Detect one or more polarity changes in the slope of the waveform corresponding to the mixed signal; and Selectively disable one or more of the analog-to-digital converter (ADC) or SoC bus traffic associated with ADC operation between one or more polarity changes of the slope of the waveform.

[0062] 2. The processor-implemented method according to Clause 1, the method further comprising: enabling the SoC bus traffic associated with the ADC operation when a peak or a trough occurs in the waveform corresponding to the mixed signal.

[0063] 3. The processor-implemented method according to Clause 1 or 2, wherein the mixed signal includes a power signal, a sensor signal, a reference voltage signal, a reference current signal, a transmit power level, a battery level, or an SoC temperature.

[0064] 4. A method implemented by a processor according to any one of Clauses 1 to 3, wherein all SoC bus traffic in the SoC bus traffic associated with the ADC operation is disabled between the one or more polarity changes of the slope of the waveform.

[0065] 5. A method implemented by a processor according to any one of Clauses 1 to 4, the method further comprising: disabling analog-to-digital conversion for at least one device between one or more polarity changes of the slope of the waveform.

[0066] 6. A processor-implemented method according to any one of Clauses 1 to 5, wherein the processor-implemented method is implemented in an automotive application.

[0067] 7. A processor-implemented method according to any one of Clauses 1 to 6, wherein the processor-implemented method is implemented in a mobile device.

[0068] 8. A system for mixed-signal management, the system comprising: A detection device is used to detect one or more polarity changes in the slope of a waveform corresponding to one or more mixed signals in a computing device including a system-on-a-chip (SoC); and A mixed-signal controller for controlling SoC bus flow or analog-to-digital converter (ADC) based on one or more polarity changes of the slope of the waveform corresponding to one or more mixed signals.

[0069] 9. The system according to Clause 8, wherein the mixed-signal controller enables the SoC bus traffic or ADC operation associated with the mixed signal when a peak or trough occurs in the waveform corresponding to the one or more mixed signals.

[0070] 10. The system according to Clause 8 or 9, wherein the mixed signal includes a power signal, a sensor signal, a reference voltage signal, a reference current signal, a transmit power level, a battery level, or an SoC temperature.

[0071] 11. The system according to any one of Clauses 8 to 10, wherein the mixed-signal controller disables one or more of the SoC bus traffic or ADC operations associated with the mixed signal between one or more polarity changes of the slope of the waveform corresponding to the one or more mixed signals.

[0072] 12. The system according to any one of clauses 8 to 11, the system further comprising: disabling analog-to-digital conversion for at least one device between the one or more polarity changes of the slope of the waveform.

[0073] 13. The system according to any one of Clauses 8 to 12, wherein the system is implemented in an automotive application.

[0074] 14. The system according to any one of Clauses 8 to 13, wherein the system is implemented in a mobile device.

[0075] 15. An apparatus comprising: Components used to receive mixed signals in computing devices, including System-on-Chip (SoC); A component for determining whether the polarity of the slope of the waveform corresponding to the mixed signal has changed; and A component for selectively disabling one or more of the analog-to-digital converter (ADC) or at least a portion of the SoC bus traffic associated with ADC operation between one or more variations in the polarity of the slope of the waveform.

[0076] 16. The apparatus according to Clause 15, the apparatus further comprising a component for enabling the SoC bus traffic associated with the ADC operation when a peak or a trough occurs in the waveform corresponding to the mixed signal.

[0077] 17. The apparatus according to Clause 15 or 16, wherein the mixed signal includes a power signal, a sensor signal, a reference voltage signal, a reference current signal, a transmit power level, a battery level, or an SoC temperature.

[0078] 18. The apparatus according to any one of Clauses 15 to 17, the apparatus further comprising a component for disabling the SoC bus traffic associated with the ADC operation between one or more variations in the polarity of the slope of the waveform.

[0079] 19. The apparatus according to any one of Clauses 15 to 18, the apparatus further comprising a component for disabling ADC operation for at least one device between one or more variations in the polarity of the slope of the waveform.

[0080] 20. The device according to any one of Clauses 15 to 19, wherein the device is included in an automotive application.

[0081] 21. The device according to any one of Clauses 15 to 20, wherein the device is included in a mobile device.

[0082] 22. A non-transitory computer-readable medium having program code recorded thereon, the program code being executed by a processor and comprising: Program code used to receive mixed signals in computing devices, including System-on-Chip (SoC); Program code for detecting one or more polarity changes in the slope of the waveform corresponding to the mixed signal; and Program code for selectively disabling one or more of the analog-to-digital converter (ADC) or SoC bus traffic associated with ADC operation between one or more polarity changes of the slope of the waveform.

[0083] 23. The non-transitory computer-readable medium according to Clause 22, wherein the program code includes program code for enabling the SoC bus traffic associated with the ADC operation when a peak or a trough occurs in the waveform corresponding to the mixed signal.

[0084] 24. The non-transitory computer-readable medium as described in Clause 22 or 23, wherein the mixed signal includes a power signal, a sensor signal, a reference voltage signal, a reference current signal, a transmit power level, a battery level, or a SoC temperature.

[0085] 25. A non-transitory computer-readable medium according to any one of Clauses 22 to 24, wherein the program code includes program code for disabling the SoC bus traffic associated with the ADC operation between the one or more polarity changes of the slope of the waveform.

[0086] 26. A non-transitory computer-readable medium according to any one of clauses 22 to 25, wherein the program code includes program code for disabling analog-to-digital conversion for at least one device between one or more polarity changes of the slope of the waveform.

[0087] 27. The non-transitory computer-readable medium according to any one of clauses 22 to 26, wherein the program code is implemented in an automotive application.

[0088] 28. The non-transitory computer-readable medium as described in Clause 22, wherein the program code is implemented in a mobile device.

[0089] For specific firmware and / or software implementations, these methodologies can be implemented using modules (e.g., procedures, functions, etc.) that perform the described functions. Machine-readable media that tangibly embody instructions can be used to implement the described methodologies. For example, software code can be stored in memory and executed by a processor unit. Memory can be implemented within or outside the processor unit. As used, the term "memory" refers to any type of long-term, short-term, volatile, non-volatile, or other memory, and is not limited to a particular type or quantity of memory, or the type of medium on which memory is stored.

[0090] If implemented in firmware and / or software, the functionality may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoding data structures and computer-readable media encoding computer programs. Computer-readable media include physical computer storage media. Storage media can be any available medium that a computer can access. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable read-only memory (EEPROM), compressed optical disc read-only memory (CD-ROM) or other optical disc storage, disk storage or other magnetic storage devices, or other media that may be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. As used, disks and optical discs include: compressed optical discs (CD), laser discs, optical discs, digital versatile discs (DVD), floppy disks, and Blu-ray discs. ® Optical discs, where magnetic disks typically reproduce data magnetically, utilize lasers to optically reproduce data. Combinations of these should also be included within the scope of computer-readable media.

[0091] In addition to being stored on a computer-readable medium, instructions and / or data may also be provided as signals included on a transmission medium in a communication apparatus. For example, a communication apparatus may include a transceiver having signals indicating instructions and data. These instructions and data are configured to cause one or more processors to perform the functions outlined in the claims.

[0092] Although this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and modifications can be made without departing from the technology of this disclosure as defined in the appended claims. For example, relational terms such as "above" and "below" are used for substrates or electronic devices. Of course, if the substrate or electronic device is inverted, above becomes below, and vice versa. Additionally, if it is laterally oriented, above and below may refer to the sides of the substrate or electronic device. Furthermore, the scope of this disclosure is not intended to be limited to the specific configurations of the processes, machines, manufactures, material compositions, components, methods, and steps described in the specification. As will be readily understood by those skilled in the art from the content of this disclosure, processes, machines, manufactures, material compositions, components, methods, or steps that currently exist or will be developed later can be utilized to perform substantially the same function or achieve substantially the same result as the corresponding configuration described. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, components, methods, or steps within their scope.

[0093] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with this disclosure can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0094] The various exemplary logic blocks, modules, and circuits described in this disclosure may be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof, designed to perform the described functions. While the general-purpose processor may be a microprocessor, in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0095] The steps or algorithms of the methods described in this disclosure may be directly embodied in hardware, a software module executed by a processor, or a combination of both. The software module may reside in RAM, flash memory, ROM, erasable programmable read-only memory (EPROM), EEPROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal. Alternatively, the processor and storage medium may reside as discrete components in the user terminal.

[0096] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the described examples and designs, but is accorded the widest scope consistent with the disclosed principles and novel features.

Claims

1. A processor-implemented method, the processor-implemented method comprising: Receive mixed signals in computing devices including System-on-Chip (SoC); Detect one or more polarity changes in the slope of the waveform corresponding to the mixed signal; as well as Selectively disable one or more of the analog-to-digital converter (ADC) or SoC bus traffic associated with ADC operation between one or more polarity changes of the slope of the waveform.

2. The processor-implemented method according to claim 1, the method further comprising: When a peak or a trough occurs in the waveform corresponding to the mixed signal, the SoC bus traffic associated with the ADC operation is enabled.

3. The processor-implemented method of claim 1, wherein the mixed signal includes a power signal, a sensor signal, a reference voltage signal, a reference current signal, a transmit power level, a battery level, or an SoC temperature.

4. The processor-implemented method of claim 1, wherein the SoC bus traffic associated with the ADC operation is disabled between the one or more polarity changes of the slope of the waveform.

5. The processor-implemented method according to claim 1, the method further comprising: Disabling analog-to-digital conversion for at least one device between the one or more polarity changes of the slope of the waveform.

6. The processor-implemented method according to claim 1, wherein the processor-implemented method is implemented in an automotive application.

7. The processor-implemented method according to claim 1, wherein the processor-implemented method is implemented in a mobile device.

8. A system for mixed-signal management, the system comprising: A detection device for detecting one or more polarity changes in the slope of a waveform corresponding to one or more mixed signals in a computing device including a system-on-a-chip (SoC); and A mixed-signal controller for controlling SoC bus flow or analog-to-digital converter (ADC) based on one or more polarity changes of the slope of the waveform corresponding to one or more mixed signals.

9. The system of claim 8, wherein the mixed-signal controller enables the SoC bus traffic or ADC operation associated with the mixed signal when a peak or trough occurs in the waveform corresponding to the one or more mixed signals.

10. The system of claim 8, wherein the mixed signal includes a power signal, a sensor signal, a reference voltage signal, a reference current signal, a transmit power level, a battery level, or an SoC temperature.

11. The system of claim 8, wherein the mixed-signal controller disables one or more of the SoC bus traffic or ADC operations associated with the mixed signal between one or more polarity changes of the slope of the waveform corresponding to the one or more mixed signals.

12. The system of claim 8, further comprising: Disabling analog-to-digital conversion for at least one device between the one or more polarity changes of the slope of the waveform.

13. The system of claim 8, wherein the system is implemented in an automotive application.

14. The system according to claim 8, wherein the system is implemented in a mobile device.

15. An apparatus comprising: Components used to receive mixed signals in computing devices, including System-on-Chip (SoC); A component for determining whether the polarity of the slope of the waveform corresponding to the mixed signal has changed; and A component for selectively disabling one or more of the analog-to-digital converter (ADC) or at least a portion of the SoC bus traffic associated with ADC operation between one or more variations in the polarity of the slope of the waveform.

16. The apparatus of claim 15, further comprising a component for enabling the SoC bus traffic associated with the ADC operation when a peak or a trough occurs in the waveform corresponding to the mixed signal.

17. The apparatus of claim 15, wherein the mixed signal includes a power signal, a sensor signal, a reference voltage signal, a reference current signal, a transmit power level, a battery level, or an SoC temperature.

18. The apparatus of claim 15, further comprising a component for disabling the SoC bus traffic associated with the ADC operation between one or more variations in the polarity of the slope of the waveform.

19. The apparatus of claim 15, further comprising a component for disabling ADC operation for at least one device between one or more variations in the polarity of the slope of the waveform.

20. The apparatus of claim 15, wherein the apparatus is included in an automotive application.

21. The apparatus of claim 15, wherein the apparatus is included in a mobile device.

22. A non-transitory computer-readable medium having program code recorded thereon, the program code being executed by a processor and comprising: Program code used to receive mixed signals in computing devices, including System-on-Chip (SoC); Program code for detecting one or more polarity changes in the slope of the waveform corresponding to the mixed signal; and Program code for selectively disabling one or more of the analog-to-digital converter (ADC) or SoC bus traffic associated with ADC operation between one or more polarity changes of the slope of the waveform.

23. The non-transitory computer-readable medium of claim 22, wherein the program code includes program code for enabling the SoC bus traffic associated with the ADC operation when a peak or a trough occurs in the waveform corresponding to the mixed signal.

24. The non-transitory computer-readable medium of claim 22, wherein the mixed signal includes a power signal, a sensor signal, a reference voltage signal, a reference current signal, a transmit power level, a battery level, or an SoC temperature.

25. The non-transitory computer-readable medium of claim 22, wherein the program code includes program code for disabling the SoC bus traffic associated with the ADC operation between the one or more polarity changes of the slope of the waveform.

26. The non-transitory computer-readable medium of claim 22, wherein the program code includes program code for disabling analog-to-digital conversion for at least one device between one or more polarity changes of the slope of the waveform.

27. The non-transitory computer-readable medium of claim 22, wherein the program code is implemented in an automotive application.

28. The non-transitory computer-readable medium of claim 22, wherein the program code is implemented in a mobile device.

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