Method, device, equipment and system for improving wafer flatness and storage medium

Abstract

The invention provides a method, a device, equipment and a system for improving the flatness of a wafer and a storage medium. The method comprises the following steps: acquiring thickness distribution data of the wafer subjected to double-sided polishing; determining a first morphology slope based on the thickness distribution data; based on the current tool state parameter, a final second morphology slope of the polishing equipment is determined; and determining a process control condition of final polishing equipment according to a matching relationship between the first morphology slope and the second morphology slope, so that the morphology slope of the wafer after final polishing meets a set flatness convergence condition.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method, apparatus, device, system and storage medium for improving wafer flatness. Background Technology

[0002] As integrated circuit manufacturing processes evolve to more advanced nodes, the requirements for the flatness of the wafer surface in photolithography are becoming increasingly stringent. The silicon wafer, as the substrate, must have extremely high global backside ideal range (GBIR), as well as local flatness (Site Front least sQuares Range, SFQR) or edge site flatness (Edge Site Flatness Front-side Least Squares Range, ESFQR).

[0003] In existing wafer manufacturing processes, double-side polishing (DSP) and final polishing (FP) are key processes that determine the final geometry of the wafer. DSP is mainly responsible for removing the damaged layer from the grinding stage and establishing initial flatness, while FP is used to eliminate micro-roughness to achieve an atomically smooth surface.

[0004] However, DSP processes are prone to producing roll-off or ski-slope characteristics at the wafer edges. Meanwhile, the removal rate distribution in FP processes is not constant; it drifts significantly with the lifespan of consumables, such as polishing pads.

[0005] When the effects of the aforementioned DSP and FP processes on wafer flatness are coupled, it can lead to a deterioration in wafer flatness. Summary of the Invention

[0006] This disclosure provides a method, apparatus, device, system, and storage medium for improving wafer flatness; capable of improving wafer flatness.

[0007] The technical solution disclosed herein is implemented as follows: In a first aspect, this disclosure provides a method for improving wafer flatness, including: Obtain thickness distribution data of the wafer after double-sided polishing; Based on the thickness distribution data, a first morphology slope is determined, which represents the thickness distribution of the wafer within a defined radial region. Obtain the current tool status parameters of the final polishing equipment; Based on the current tool state parameters, a second morphology slope of the final polishing device is determined, wherein the second morphology slope represents the removal rate distribution of the final polishing device within the set radial region; Based on the matching relationship between the first morphology slope and the second morphology slope, the process control conditions of the final polishing equipment are determined so that the morphology slope of the wafer after the final polishing process meets the set flatness convergence condition.

[0008] Secondly, this disclosure provides an apparatus for improving wafer flatness, comprising: a first acquisition module, a first determination module, a second acquisition module, a second determination module, and a third determination module; wherein, The first acquisition module is configured to acquire thickness distribution data of the wafer after double-sided polishing; The first determining module is configured to determine a first morphology slope based on the thickness distribution data, wherein the first morphology slope represents the thickness distribution of the wafer within a defined radial region; The second acquisition module is configured to acquire the current tool status parameters of the final polishing equipment; The second determining module is configured to determine a second morphology slope of the final polishing device based on the current tool state parameters, wherein the second morphology slope represents the removal rate distribution of the final polishing device within the set radial region; The third determining module is configured to control the process control conditions of the final polishing equipment according to the matching relationship between the first morphology slope and the second morphology slope, so that the morphology slope of the wafer after the final polishing process meets the set flatness convergence condition.

[0009] Thirdly, this disclosure provides a computing device, including: a processor; and a memory storing a computer program; wherein the processor is configured to, when executing the computer program, implement the method for improving wafer flatness as described in the first aspect.

[0010] Fourthly, this disclosure provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the method for improving wafer flatness as described in the first aspect.

[0011] Fifthly, this disclosure provides a system for improving wafer flatness, comprising: a double-sided polishing apparatus for performing double-sided polishing on a wafer to be processed, thereby obtaining a double-sided polished wafer; Inspection equipment is used to collect thickness distribution data of wafers after double-sided polishing; The apparatus for improving wafer flatness as described in the second aspect; The final polishing equipment is used to perform final polishing on wafers that have been polished on both sides, according to the process control conditions determined by the device for improving wafer flatness. The device for improving wafer flatness is communicatively connected to the inspection equipment and the final polishing equipment. This disclosure provides a method, apparatus, device, system, and storage medium for improving wafer flatness; it simplifies the complex 3D wafer edge morphology problem into a control scheme targeting the slope parameter, making process optimization mathematically predictable, avoiding blind trial and error based on experience, and improving the accuracy of process optimization. Furthermore, by correlating the wafer thickness distribution data after DSP with the tool state parameters of the final polishing equipment, the process control conditions of the final polishing equipment can be adjusted based on the tool state parameters adapted to the wafer flatness characteristics after DSP during the final polishing process. This ensures that the final polishing process is no longer passively receiving material from the DSP, thereby improving wafer flatness. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the architecture of a system for improving wafer flatness provided in this disclosure.

[0013] Figure 2 This is a schematic diagram of the composition of a final polishing device provided in this disclosure.

[0014] Figure 3 This is a schematic flowchart of a method for improving wafer flatness provided in this disclosure.

[0015] Figure 4 The radial thickness distribution curve of the wafer provided in this disclosure.

[0016] Figure 5 This is a schematic diagram of the morphology curve of the polishing pad removal provided in this disclosure.

[0017] Figure 6 This is a schematic diagram of the composition of an apparatus for improving wafer flatness provided in this disclosure.

[0018] Figure 7 This is a structural block diagram of a computing device provided in this disclosure. Detailed Implementation

[0019] The technical solutions in this disclosure will now be clearly and completely described with reference to the accompanying drawings.

[0020] Figure 1This is a schematic diagram of the architecture of a system 100 for improving wafer flatness provided in this disclosure. The system 100 integrates key process equipment in wafer manufacturing, mainly including a double-sided polishing (DSP) device 110, a metrology tool 120, a wafer flatness improvement device 130, and a final polishing (FP) device 140. Figure 1 In the diagram, blank arrows indicate the physical transport path of the wafer, while solid arrows indicate the flow of information or data.

[0021] exist Figure 1 In this process, the double-sided polishing equipment 110 is used for primary planarization of the raw wafer after polishing. During this primary planarization process, the wafer is placed in a planetary gear-driven carrier and moves between two rotating polishing disks. The stress distribution during the DSP process is affected by the carrier thickness, polishing slurry distribution, and disk flatness, which causes a non-linear thickness variation at the wafer edges, especially in the region 140mm to 150mm from the wafer center. This variation typically manifests as edge roll-off, such as a sharp decrease in wafer thickness at the edge, or edge lifting, such as an abnormal increase in wafer thickness at the edge. Understandably, since DSP is a batch process, wafers within the same batch usually have similar edge characteristics.

[0022] exist Figure 1 In this process, the inspection equipment 120 is positioned after the DSP process and before the FP process. This inspection equipment 120 can be, exemplarily, an inspection equipment employing full-wafer scanning interferometry technology, such as an inspection equipment employing infrared interferometry or capacitive sensing technology. Figure 1 As indicated by the blank arrows, the detection device 120 is capable of generating high-resolution wafer thickness maps with sub-millimeter radial resolution, thereby accurately resolving minute topographic changes within the edge exclusion (EE) region.

[0023] In this disclosure, the final polishing apparatus 140 employs single-sided chemical mechanical polishing (CMP) technology. For example... Figure 2As shown, the core components of the FP device 140 include a rotating polishing plate 141 on which a polyurethane polishing pad 142 is attached; and a polishing carrier head 143. In this disclosure, the polishing carrier head 143 has fine pressure adjustment capabilities. For example, the polishing carrier head 143 employs multi-zone pressure control technology, and its interior contains a flexible diaphragm 145. The diaphragm 145 is divided into several concentric independent pressure chambers, such as Zone 1 to Zone 5, where Zone 1 covers the central region of the wafer, and Zone 5 covers the outermost edge region of the wafer (e.g., a region with a radius of 140mm-150mm).

[0024] The back pressure of each zone is independently adjusted by a pneumatic control system, thereby changing the material removal rate at different radii of the wafer at a microscale.

[0025] In addition, a rigid retaining ring 146 is provided at the lower edge of the polishing head 143. The retaining ring 146 presses against the polishing pad 142 during the polishing process and surrounds the wafer 144. The main function of the retaining ring is to prevent the wafer from slipping out, but the pressure it applies can cause local compression or springback effects on the polishing pad, thereby affecting the removal rate of the wafer edge.

[0026] In this disclosure, the device 130 for improving wafer flatness is communicatively connected to the inspection device 120 and the FP device 140, respectively. Figure 1 In this process, the wafer flatness improvement device 130 receives thickness distribution data of the double-sided polished wafer from the inspection device 120, and determines the process control conditions of the FP device 140 based on the tool status parameters reported by the FP device 140 using the wafer production control method provided in this disclosure, and transmits the process control conditions back to the FP device 140 so that the FP device 140 performs FP processing on the double-sided polished wafer.

[0027] Figure 3 This is a schematic flowchart of a method for improving wafer flatness provided in this disclosure. The method is performed by a wafer flatness improving apparatus 130.

[0028] See Figure 3 In step S310, the thickness distribution data of the wafer after double-sided polishing is obtained.

[0029] Specifically, the wafer flatness improvement device 130 receives global thickness data of the wafer from the inspection device 120. Exemplarily, this global thickness data is stored in polar or Cartesian coordinates. In some examples, to eliminate measurement noise and extract radial features, the device 130 first performs denoising processing on the global thickness data and calculates the average radial thickness distribution curve within a defined radial region. .

[0030] Step S320: Determine the first morphological slope based on the thickness distribution data.

[0031] In this disclosure, the radial region is defined as being located inside the wafer edge removal area. Taking a 300mm wafer as an example, this defined radial region refers to an annular region located at a distance of -148mm to -143mm from the wafer center. This region corresponds to the Site Flatness Front-side Least Squares Range (SFQR).

[0032] like Figure 4 The radial thickness distribution curve of the wafer shown. First morphological slope This refers to the rate of change of thickness with radius within a defined radial region, used to represent the thickness distribution of the wafer within that defined radial region. In this disclosure, the first morphology slope... It is calculated using the following formula.

[0033]

[0034] in, and These represent the maximum and minimum thicknesses of the wafer within the defined radial region, respectively. and These represent the endpoints of the defined radial region, for example... , In some examples, the least squares method can be used to linearly fit the thickness curve within the defined radial region, and the slope of the resulting straight line is the first morphological slope. .

[0035] For the slope of the first morphology, when When the thickness increases with the radius, it indicates that the wafer edge has a raised shape (Edge Elevation), such as... Figure 4 The solid curve in the image is shown. When When the thickness decreases as the radius increases, it indicates the edge roll-off morphology of the wafer, such as... Figure 4 The dashed curve in the figure is shown.

[0036] Step S330: Obtain the current tool status parameters of the final polishing equipment.

[0037] Specifically, tool condition parameters mainly refer to factors affecting the removal rate distribution in the final polishing apparatus 140. In this disclosure, these tool condition parameters include the cumulative lifespan of the polishing pad.

[0038] In detail, polishing pads are typically made of porous polyurethane material, and their physical properties evolve over prolonged use and grinding by diamond dressing discs (conditioners). For example, the groove depth of the polishing pad decreases with its service life, affecting the flow efficiency of the slurry. The viscoelastic modulus softens due to fatigue from immersion in the surface material. The surface roughness of the polishing pad also determines the contact area and mechanical removal efficiency.

[0039] Step S340: Determine the second morphology slope of the final polishing equipment based on the current tool state parameters.

[0040] In this disclosure, the second morphological slope This characterizes the removal rate profile exhibited by the FP device 140 in its current state for a standard flat wafer within a defined radial region. Specifically, the second morphology slope... It can be calculated using the following formula.

[0041]

[0042] in, This indicates the removal rate of the polishing pad for the edge region of a standard flat wafer, expressed in nm / min. This indicates the removal rate of the polishing pad for the central region of a standard flat wafer. In this disclosure, the second morphology slope... The slope represents the removal rate; a positive value indicates that the polishing pad removes material at the wafer edge faster than at the center.

[0043] like Figure 5 As shown, the lifespan of the polishing pad affects This has a significant impact. For example, in the initial stage of polishing pad use (e.g., 0-20% lifetime), the new polishing pad is harder and has deeper grooves, resulting in good slurry flow. However, the pad has poor compressibility and does not easily wrap around the wafer edge. This manifests as a convex removal profile where removal is faster at the wafer center and slower at the wafer edge. Figure 5The solid line curve in the figure shows that the amount of material removed at the wafer edge is less than that removed at the wafer center. In this case, The values ​​are usually small or even negative.

[0044] In the final stage of polishing pad use, such as after 80% of its lifespan, the polishing pad becomes thinner and softer, and is prone to rebound under the pressure of the retaining ring. This leads to increased contact stress on the wafer edges, resulting in edge over-polishing. This manifests as a concave removal profile, such as... Figure 5 The dashed curve in the figure shows that the amount of material removed at the wafer edge is greater than that removed at the wafer center. In this case, The value is a large positive value.

[0045] Step S350: Based on the matching relationship between the first morphology slope and the second morphology slope, determine the process control conditions of the final polishing equipment so that the morphology slope of the wafer after the final polishing process meets the set flatness convergence conditions.

[0046] In this disclosure, the purpose of the final polishing process is to flatten the wafer surface. Therefore, the flatness convergence condition may include the local flatness index SFQR of the final polished wafer within a defined radial region being less than a preset threshold. In this disclosure, the preset threshold may be set to 30 nm or even lower. When the final thickness slope of the wafer surface within the defined radial region... Small enough, for example Only when this condition is met can the SFQR value within the specified radial region be guaranteed to satisfy the convergence condition.

[0047] In detail, according to the superposition principle, we can obtain In some examples, the flatness convergence condition described in step S350 can also be equivalent to... .

[0048] Specifically, when When the wafer edge is warped, due to the excessive thickness of the wafer edge, more material needs to be removed at the edge during the final polishing process. Substituting the final thickness slope into the flatness convergence condition yields the following inequality. Based on this inequality, we can obtain: Expanding this inequality, we can obtain In other words, when To improve flatness, the final polishing process should eliminate edge lifting without excessive polishing that could lead to reverse roll-off and depressions. Therefore, this can be achieved by adjusting process control conditions. .

[0049] when When the wafer edge exhibits roll-off or thinning, the edge is so thin that minimal material removal is required at the edge during the final polishing process. This means that in such cases, a slow or even non-existent edge removal process must be implemented during final polishing, where the edge removal rate is significantly lower than that of the central region. .because Substituting the final thickness slope into the flatness convergence condition yields the following result: .

[0050] In other words, when In order to improve flatness, it is desirable for the final polishing process to eliminate the edges very slowly in order to compensate for the fact that the wafer edges are very thin.

[0051] pass Figure 3 The technical solution presented herein simplifies the complex problem of 3D wafer edge morphology into a control scheme targeting the slope parameter. This makes process optimization mathematically predictable, avoids blind trial and error based on experience, and improves the accuracy of process optimization. Furthermore, by correlating the wafer thickness distribution data after DSP with the tool state parameters of the final polishing equipment, the process control conditions of the final polishing equipment can be adjusted based on the tool state parameters adapted to the wafer flatness characteristics after DSP during the final polishing process. This ensures that the final polishing process is no longer passively receiving material from the DSP, thereby improving wafer flatness.

[0052] for Figure 3 The technical solution shown is for the purpose of achieving This disclosure provides two exemplary implementations for adjusting process conditions.

[0053] In some examples, when the first morphology slope is greater than zero, the wafer is finally polished using a polishing pad that satisfies that the second morphology slope is greater than the first morphology slope but less than twice the first morphology slope; and when the first morphology slope is less than zero, the wafer is finally polished using a polishing pad that satisfies that the second morphology slope is greater than twice the first morphology slope but less than the first morphology slope.

[0054] Understandably, this example is applicable to large-scale production lines with multiple FP devices. Specifically, the wafer flatness improvement device 130 can pre-maintain a status table for the FP devices, recording the polishing pad lifetime of each FP device and its corresponding second morphology slope.

[0055] When the first morphological feature of the wafer after DSP is detected satisfy At that time, polishing pads nearing the end of their service life have a stronger edge removal capability, i.e., higher efficiency. Therefore, the wafer flatness improvement device 130 can schedule the wafer to be processed in an FP device where the polishing pad is at the end of its service life, such as when the pad life is >80%, thus meeting the requirements. Requirements.

[0056] When the first morphological feature of the wafer after DSP is detected satisfy At that time, the edge removal ability of the polishing pad is weak at the beginning of its service life, i.e., low efficiency. Therefore, the wafer flatness improvement device 130 can schedule the wafer to be processed in FP equipment where the polishing pad is in the early stages of its lifespan, such as when the pad life is <20%, thus maximizing the preservation of edge thickness and meeting the requirements. Requirements.

[0057] The technical solution in this example utilizes the characteristics of consumables to adapt and select FP equipment without changing the process control conditions of a single FP equipment, thus reducing the operational difficulty and complexity of the FP process.

[0058] The above examples are for large-scale production lines with multiple FP devices. However, for production lines with a limited number of FP devices, or even only a single FP device, the wafer flatness improvement apparatus 130 in this disclosure can adjust the process control conditions of the FP to meet the target of a second morphology slope. These process control conditions include one or more of the following: back pressure distribution applied by the polishing head in different radial regions, retaining ring pressure, and polishing disk rotation speed.

[0059] In some examples, such as Figure 2 As shown, the polishing head 143 of the FP device 140 has 5 pressure zones, labeled Zone 1, Zone 2, ..., Zone 5 from the center of the wafer to the edge of the wafer. The removal rate of the wafer area in each pressure zone is proportional to the pressure.

[0060] Based on this, in order to increase The device 130, which improves wafer edge removal rate and wafer flatness, can instruct the FP device 140 to increase the back pressure of the outermost periphery of the wafer, such as Zone 5 and Zone 4, for example, increasing the pressure of Zone 5 from 4.0 psi to 5.5 psi, while maintaining or reducing the back pressure of the central region, such as Zone 1.

[0061] In order to reduce The device 130, which reduces the amount of material removed from the wafer edge and improves wafer flatness, can instruct the FP device 140 to reduce the back pressure of the outermost part of the wafer, such as Zone 5, for example, by reducing the pressure of Zone 5 from 4.0 psi to 2.5 psi.

[0062] In some examples, the retaining ring pressure (RRP) of the retaining ring 146 also affects the edge removal rate. Specifically, the retaining ring 146 presses against the polishing pad 142, compressing the material of the polishing pad 142 beneath the retaining ring 146. When the RRP is low, the polishing pad 142 rebounds rapidly after passing the retaining ring 146, squeezing the wafer edge and causing an increase in the wafer edge removal rate. Increase.

[0063] When the RRP is high, the retaining ring 146 not only compresses the polishing pad 142 below it, but also causes the polishing pad near the wafer edge to sink, reducing the contact stress between the wafer edge and the polishing pad 142, thereby reducing the removal rate of the wafer edge. Decrease.

[0064] In other words, when At that time, the wafer flatness improvement device 130 can instruct the FP device 140 to reduce the pressure of the retaining ring 146 and use the springback effect of the polishing pad 142 to cut the thick edge. When At the same time, the device 130 for improving wafer flatness can instruct the FP device 140 to increase the pressure of the retaining ring 146 to press down the polishing pad 142 near the edge and reduce over-polishing of the thin edge.

[0065] In some examples, the slurry flow rate and rotation speed also affect the edge removal rate. Specifically, increasing the rotation speed of the polishing disk 140 typically increases centrifugal force, promoting slurry delivery to the edge and increasing the edge removal rate. Decreasing the rotation speed of the polishing disk 140 reduces centrifugal force, decreases slurry delivery to the wafer edge, and reduces the edge removal rate.

[0066] Figure 6 This is a schematic diagram of the composition of an apparatus 130 for improving wafer flatness provided in this disclosure. The apparatus 130 includes: a first acquisition module 131, a first determination module 132, a second acquisition module 133, a second determination module 134, and a third determination module 135; wherein, The first acquisition module 131 is configured to acquire thickness distribution data of the wafer after double-sided polishing; The first determining module 132 is configured to determine a first topography slope based on thickness distribution data, the first topography slope representing the thickness distribution of the wafer in a defined radial region; The second acquisition module 133 is configured to acquire the current tool status parameters of the final polishing device; The second determining module 134 is configured to determine a second morphological slope of the final polishing device based on the current tool state parameters. The second morphological slope represents the removal rate distribution of the final polishing device within the set radial region. The third determining module 135 is configured to determine the process control conditions of the final polishing equipment based on the matching relationship between the first morphology slope and the second morphology slope, so that the morphology slope of the wafer after the final polishing process meets the set flatness convergence condition.

[0067] In some examples, the current tool status parameters include the cumulative lifespan of the polishing pad of the final polishing device; the second determining module 134 is configured to: When the cumulative lifespan of the polishing pad is in the initial stage, the second morphology slope corresponds to the first removal morphology where the removal amount in the edge region of the wafer is less than the removal amount in the center region of the wafer. When the cumulative lifespan of the polishing pad is nearing its end, the second morphology slope corresponds to a second removal morphology where the removal amount in the edge region of the wafer is greater than the removal amount in the center region of the wafer.

[0068] In some examples, the third determining module 135 is configured as follows: When the first morphology slope is greater than zero, the wafer is finally polished using a polishing pad that satisfies that the second morphology slope is greater than the first morphology slope but less than twice the first morphology slope. When the slope of the first morphology is less than zero, the wafer is finally polished using a polishing pad that satisfies that the slope of the second morphology is greater than twice the slope of the first morphology and less than the slope of the first morphology.

[0069] In some examples, the third determining module 135 is configured as follows: When the slope of the first morphology is greater than zero, adjust the process control conditions so that the slope of the second morphology is greater than the slope of the first morphology but less than twice the slope of the first morphology. When the slope of the first morphology is greater than zero, the process control conditions are adjusted so that the slope of the second morphology is greater than twice the slope of the first morphology and less than the slope of the first morphology. Wherein, a first morphology slope greater than zero indicates that the thickness of the wafer in the set radial region increases with the increase of the radial distance from the wafer center, and a first morphology slope less than zero indicates that the thickness of the wafer in the set radial region decreases with the increase of the radial distance from the wafer center.

[0070] In some examples, the third determining module 135 is configured as follows: Adjust one or more of the following: the back pressure distribution applied by the polishing head of the final polishing equipment in different radial regions, the retaining ring pressure of the final polishing equipment, and the polishing disc rotation speed of the final polishing equipment.

[0071] In some examples, this radial region is located inside the edge removal region of the wafer.

[0072] In some examples, when the wafer diameter is 300 mm, the defined radial region includes an annular region ranging from -148 mm to -143 mm from the center of the wafer.

[0073] In some examples, the first determining module 132 is configured as follows: Obtain the maximum and minimum thickness values ​​of the wafer within the defined radial region; The first morphological slope is obtained by the difference between the maximum and minimum thickness values ​​and the radial distance of the set radial region.

[0074] In some examples, the flatness convergence condition set includes: the local flatness index SFQR of the finally polished wafer in the set radial region is less than a preset threshold.

[0075] Please refer to Figure 7 This illustration shows a structural block diagram of a computing device provided in an exemplary embodiment of the present disclosure. In some examples, the device 130 for improving wafer flatness can be implemented by the computing device 70, which can be at least one of devices such as a smartphone, smartwatch, desktop computer, laptop, virtual reality terminal, augmented reality terminal, wireless terminal, and laptop computer. The computing device 70 has communication capabilities and can access wired or wireless networks. The computing device 70 can refer to one of a plurality of terminals, and those skilled in the art will understand that the number of such terminals can be more or less. In some examples, the computing device 70 can receive data based on the accessed wired or wireless network. It is understood that the computing device 70 undertakes the calculation and processing work of the technical solution of the present disclosure, and the present disclosure does not limit it in this respect.

[0076] like Figure 7 As shown, the computing device in this disclosure may include one or more of the following components: processor 710 and memory 720.

[0077] Optionally, the processor 710 connects various parts within the computing device using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 720, and by calling data stored in the memory 720. Optionally, the processor 710 can be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 710 can integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and baseband chip. Specifically, the CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display on the touch screen; the NPU is used to implement Artificial Intelligence (AI) functions; and the baseband chip is used for wireless communication. It is understandable that the aforementioned baseband chip may not be integrated into the processor 710, but may be implemented using a separate chip.

[0078] The memory 720 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 720 may include a non-transitory computer-readable storage medium. The memory 720 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 720 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area may store data created according to the use of the computing device, etc.

[0079] In addition, those skilled in the art will understand that the structure of the computing device shown in the above figures does not constitute a limitation on the computing device. The computing device may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, the computing device may also include a display screen, camera assembly, microphone, speaker, radio frequency circuit, input unit, sensors (such as accelerometer, angular velocity sensor, light sensor, etc.), audio circuit, WiFi module, power supply, Bluetooth module, etc., which will not be described in detail here.

[0080] This disclosure also provides a computer-readable storage medium storing at least one instruction that is executed by a processor to implement the methods for improving wafer flatness as described in the various embodiments above.

[0081] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computing device to perform the methods for improving wafer flatness as described in the above embodiments.

[0082] Those skilled in the art will recognize that the functions described in this disclosure in one or more of the examples above can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0083] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0084] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for improving wafer flatness, comprising: The method comprises: acquiring thickness distribution data of a wafer after double-side polishing; determining a first profile slope based on the thickness distribution data, the first profile slope representing a thickness distribution of the wafer within a set radial region; acquiring a current tool state parameter of a final polishing device; determining a second profile slope of the final polishing device based on the current tool state parameter, the second profile slope representing a removal rate distribution of the final polishing device within the set radial region; determining a process control condition of the final polishing device according to a matching relationship between the first profile slope and the second profile slope, so that a profile slope of the wafer after final polishing processing meets a set flatness convergence condition.

2. The method of claim 1, wherein, The current tool state parameter comprises a cumulative service life of a polishing pad of the final polishing device. The determination of the second profile slope of the final polishing device based on the current tool state parameter comprises: when the cumulative service life of the polishing pad is in an initial stage, the second profile slope corresponds to a first removal profile in which an edge region removal amount of a wafer is less than a center region removal amount of the wafer; when the cumulative service life of the polishing pad is in a final stage, the second profile slope corresponds to a second removal profile in which the edge region removal amount of the wafer is greater than the center region removal amount of the wafer.

3. The method of claim 1, wherein, The determination of the process control condition of the final polishing device according to the matching relationship between the first profile slope and the second profile slope comprises: when the first profile slope is greater than zero, using a polishing pad that meets the second profile slope greater than the first profile slope and less than twice the first profile slope to perform final polishing processing on the wafer; when the first profile slope is less than zero, using a polishing pad that meets the second profile slope greater than twice the first profile slope and less than the first profile slope to perform final polishing processing on the wafer.

4. The method of claim 1, wherein, The determination of the process control condition of the final polishing device according to the matching relationship between the first profile slope and the second profile slope comprises: when the first profile slope is greater than zero, adjusting the process control condition so that the second profile slope is greater than the first profile slope and less than twice the first profile slope; when the first profile slope is less than zero, adjusting the process control condition so that the second profile slope is greater than twice the first profile slope and less than the first profile slope; wherein the first profile slope greater than zero indicates that the thickness of the wafer within the set radial region increases with the radial distance from the center of the wafer, and the first profile slope less than zero indicates that the thickness of the wafer within the set radial region decreases with the radial distance from the center of the wafer.

5. The method of claim 4, wherein, The adjustment of the process control condition comprises: adjusting one or more of a back pressure distribution applied by a polishing head of the final polishing device in different radial regions, a retaining ring pressure of the final polishing device, and a polishing disc rotation speed of the final polishing device.

6. The method of claim 1, wherein, The set radial region is located inside an edge removal region of the wafer.

7. The method of claim 6, wherein, When the diameter of the wafer is 300 mm, the set radial region comprises an annular region with a radial distance of -148 mm to -143 mm from the center of the wafer.

8. The method of claim 1, wherein, The first topography slope is determined based on the thickness distribution data, comprising: obtaining a thickness maximum value and a thickness minimum value of the wafer in the set radial region; obtaining the first topography slope according to the difference between the thickness maximum value and the thickness minimum value and the radial distance of the set radial region.

9. The method of claim 1, wherein, The set flatness convergence condition comprises that a local flatness index SFQR of the wafer after the final polishing in the set radial region is less than a preset threshold.

10. An apparatus for improving wafer flatness, comprising: The device comprises a first obtaining module, a first determining module, a second obtaining module, a second determining module, and a third determining module, wherein: The first obtaining module is configured to obtain thickness distribution data of a wafer after double-sided polishing; The first determining module is configured to determine a first topography slope based on the thickness distribution data, the first topography slope representing a thickness distribution of the wafer in a set radial region; The second obtaining module is configured to obtain a current tool state parameter of a final polishing device; The second determining module is configured to determine a second topography slope of the final polishing device based on the current tool state parameter, the second topography slope representing a removal rate distribution of the final polishing device in the set radial region; The third determining module is configured to determine a process control condition of the final polishing device according to a matching relationship between the first topography slope and the second topography slope, so that a topography slope of the wafer after the final polishing process satisfies a set flatness convergence condition.

11. A computing device, comprising: The computing device comprises a processor and a memory having a computer program stored therein; wherein the processor is configured to implement the method for improving wafer flatness according to any one of claims 1 to 9 when executing the computer program.

12. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the method for improving wafer flatness according to any one of claims 1 to 9.

13. A system for improving wafer flatness, the system comprising: The system comprises a double-sided polishing device for performing double-sided polishing on a wafer to be processed to obtain a wafer after double-sided polishing; a detection device for collecting thickness distribution data of the wafer after double-sided polishing; The device for improving wafer flatness according to claim 10; a final polishing device for performing final polishing on the wafer after double-sided polishing according to the process control condition determined by the device for improving wafer flatness; wherein The device for improving wafer flatness is communicatively connected to the detection device and the final polishing device, respectively. The device for improving wafer flatness is communicatively connected to the detection device and the final polishing device, respectively.

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