Flash memory burning circuit and method

Abstract

The invention discloses a flash memory burning circuit and method. The flash memory burning circuit comprises a flat cable base used for being connected with a flash memory burner in an inserted mode and further connected with a flash memory chip, and the flash memory burner is used for outputting flash memory burning data to the flash memory chip through the flat cable base; the access detection module is connected with the flat cable seat, and the access detection module is used for outputting a first level signal after the flat cable seat is plugged with the flash memory burner, or outputting a second level signal when the flat cable seat is not plugged with the flash memory burner; a programmable logic module and a main control module, the programmable logic module is connected with the access detection module and is also connected with the main control module, the main control module is also connected with the flash memory chip, and the programmable logic module is used for resetting the main control module when receiving the first level signal; or when the second level signal is received, the reset of the main control module is relieved. According to the technical scheme provided by the embodiment of the invention, the reliability of burning the flash memory chip is improved.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and more particularly to a flash memory programming circuit and method. Background Technology

[0002] In fields such as industrial control, consumer electronics, and automotive electronics, onboard flash memory serves as the core storage medium for firmware programs, configuration parameters, and log data. Its burning efficiency and reliability directly affect the product's production cycle and on-site maintenance costs.

[0003] However, the existing technology provides a burning method that suffers from significant interference during the burning process, resulting in poor reliability of the burned data. Summary of the Invention

[0004] This invention provides a flash memory programming circuit and method to solve the problem of poor programming reliability.

[0005] According to one aspect of the present invention, a flash memory programming circuit is provided, characterized in that it comprises:

[0006] The ribbon cable connector is used to plug in a flash memory programmer and also connects to a flash memory chip. The flash memory programmer is used to output flash memory programming data to the flash memory chip through the ribbon cable connector.

[0007] An access detection module is connected to the ribbon cable connector. The access detection module is used to output a first level signal after the ribbon cable connector is plugged into the flash memory programmer, or to output a second level signal when the ribbon cable connector is not plugged into the flash memory programmer.

[0008] The system includes a programmable logic module and a main control module. The programmable logic module is connected to the access detection module and also to the main control module. The main control module is also connected to the flash memory chip. The programmable logic module is used to reset the main control module when it receives the first level signal, or to release the reset of the main control module when it receives the second level signal.

[0009] Optionally, the ribbon cable connector includes: a first interface and a second interface;

[0010] The first interface is connected to the access detection module and is used to transmit an insertion detection signal. The access detection module generates the first level signal or the second level signal according to the insertion detection signal.

[0011] The second interface is connected to the flash memory chip and is used to transmit the flash memory programming data.

[0012] Optionally, the access detection module includes: a first resistor, a second resistor, a third resistor, a first transistor, and a first capacitor;

[0013] The first end of the second resistor is connected to the first interface of the ribbon cable connector, the second end of the second resistor is connected to the first end of the third resistor, the second end of the third resistor is grounded, the second end of the second resistor is also connected to the control terminal of the first transistor, the first end of the first resistor is connected to the first power supply and also to the first end of the first capacitor, the second end of the first capacitor is grounded, the second end of the first resistor is connected to the first end of the first transistor, the second end of the first transistor is grounded, and the second end of the first resistor is also connected to the programmable logic module.

[0014] Optionally, the programmable logic module includes: a programmable logic chip;

[0015] The programmable logic chip includes: a plug-in detection interface, a reset interface, and a power interface;

[0016] The power interface is used to connect to the first power source;

[0017] The plug-in detection interface is connected to the second end of the first resistor and is used to receive the first level signal or the second level signal.

[0018] The reset interface is connected to the main control module and is used to output a reset signal to reset the main control module; or, output a de-reset signal to release the reset of the main control module.

[0019] Optionally, the main control module includes: a main control chip;

[0020] The main control chip includes a reset control interface and a data transmission interface;

[0021] The reset control interface of the main control chip is connected to the reset interface of the programmable logic chip, and the data transmission interface is connected to the flash memory programmer.

[0022] Optionally, the flash memory programming circuit further includes: a level conversion module connected between the main control module and the flash memory chip, and also connected to the programmable logic module; the level conversion module is used to convert the data voltage of the main control module into a first level voltage and transmit it to the flash memory chip, or to convert the data voltage of the flash memory chip into a second level voltage and read it by the main control module;

[0023] The programmable logic module is configured to turn off the level conversion module when receiving the first level signal; or to turn on the level conversion module when receiving the second level signal.

[0024] Optionally, the level conversion module includes: an input unit and an output unit;

[0025] The input unit is connected between the main control module and the flash memory chip, and the input unit is also connected to the programmable logic module; the input unit is used to convert the data voltage of the main control module into a first level voltage and transmit it to the flash memory chip.

[0026] The output unit is connected between the main control module and the flash memory chip; the output unit is used to convert the data voltage of the flash memory chip into a second level voltage and read by the main control module; the second level voltage is less than the first level voltage.

[0027] Optionally, the input unit includes: an input chip; the input chip includes: a data input interface, a data output interface, an enable interface, a first power interface, and a second power interface;

[0028] The data input interface is connected to the main control module, the data output interface is connected to the flash memory chip, and the enable interface is connected to the programmable logic module.

[0029] The first power interface is used to connect to a first power source, and the second power interface is used to connect to a second power source.

[0030] According to another aspect of the present invention, a flash memory programming method is provided, applied to a flash memory programming circuit as described in any embodiment of the present invention, the flash memory programming method comprising:

[0031] When the ribbon cable connector is plugged into the flash memory programmer, the access detection module outputs a first level signal to the programmable logic module;

[0032] The programmable logic module controls the main control module to reset;

[0033] The flash memory programmer outputs flash memory programming data to the flash memory chip through the ribbon cable connector.

[0034] Optionally, the flash memory programming method further includes:

[0035] The connection detection module determines the connection status between the ribbon cable connector and the flash memory programmer. When the ribbon cable connector is not connected to the flash memory programmer, the connection detection module outputs a second level signal to the programmable logic module.

[0036] The programmable logic module controls the main control module to release the reset, and the main control module is put into operation.

[0037] The technical solution provided by this invention allows for flash memory chip programming simply by plugging the flash memory programmer into the ribbon cable connector, eliminating the need to solder the flash memory chip to the circuit board after programming. This simplifies the operation, reduces time consumption, and eliminates the need for repeated disassembly. Furthermore, by incorporating an access detection module and a programmable logic module, the connection between the flash memory programmer and the ribbon cable connector is detected. When the flash memory programmer is connected to the connector, the main control module is reset, stopping its operation and preventing data read / write operations between the main control module and the flash memory programmer. This ensures the programming quality and reliability of the flash memory chip. When the flash memory programmer is not connected to the connector, the main control module is deactivated, allowing it to continue operating. This invention eliminates the need for the main control module as an intermediate medium for data programming, ensuring that flash memory chip programming can continue even if the main control module malfunctions.

[0038] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of a flash memory programming circuit according to an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of a ribbon cable connector according to an embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of the structure of a flash memory chip according to an embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of the structure of an access detection module according to an embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of the structure of a programmable logic chip according to an embodiment of the present invention;

[0045] Figure 6 This is a schematic diagram of the structure of a main control chip according to an embodiment of the present invention;

[0046] Figure 7This is a schematic diagram of another flash memory programming circuit provided according to an embodiment of the present invention;

[0047] Figure 8 This is a schematic diagram of the structure of an input chip according to an embodiment of the present invention;

[0048] Figure 9 This is a schematic diagram of the structure of an output chip according to an embodiment of the present invention;

[0049] Figure 10 This is a flowchart of a flash memory programming method provided according to an embodiment of the present invention;

[0050] Figure 11 This is a flowchart of another flash memory programming method provided according to an embodiment of the present invention. Detailed Implementation

[0051] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0053] This invention provides a flash memory programming circuit. Figure 1 This is a schematic diagram of a flash memory programming circuit provided in an embodiment of the present invention. (Reference) Figure 1The flash memory programming circuit includes: a ribbon cable connector 1, an access detection module 2, a programmable logic module 3, and a main control module 4. The ribbon cable connector 1 is used to connect the flash memory programmer 5 and also connects to the flash memory chip 6. The flash memory programmer 5 outputs flash memory programming data to the flash memory chip 6 through the ribbon cable connector 1. The access detection module 2 is connected to the ribbon cable connector 2. The access detection module 2 outputs a first-level signal after the ribbon cable connector 1 is connected to the flash memory programmer 5, or outputs a second-level signal when the ribbon cable connector 1 is not connected to the flash memory programmer 5. The programmable logic module 3 is connected to the access detection module 2 and also connects to the main control module 4. The main control module 4 is also connected to the flash memory chip 6. The programmable logic module 3 resets the main control module 4 upon receiving the first-level signal, or releases the reset of the main control module 4 upon receiving the second-level signal.

[0054] When the flash memory programmer 5 programs data into the flash memory chip 6, it is first connected to the ribbon cable connector 1. At this point, after the access detection module 2 detects a reliable connection between the flash memory programmer 5 and the ribbon cable connector 1, it outputs a first-level signal to the programmable logic module 3. For example, the voltage of the first-level signal is the same as the operating power supply voltage of the programmable logic module 3.

[0055] The programmable logic module 3 can determine the reliable connection between the flash memory programmer 5 and the ribbon cable connector 1 based on the first level signal. At this time, in order to ensure that the main control module 4 does not affect the process of the flash memory programmer 5 burning data to the flash memory chip 6, the programmable logic module 3 controls the main control module 4 to be reset. The main control module 4 cannot transmit data and will not transmit data to the flash memory chip 6. The flash memory chip 6 can only receive the flash memory burning data output by the flash memory programmer 5, which has a better data burning effect.

[0056] After the flash memory programmer 5 completes the data programming of the flash memory chip 6, it can be disconnected from the ribbon cable connector 1. At this time, the detection module 2 detects that the flash memory programmer 5 is not connected to the ribbon cable connector 1 and outputs a second-level signal to the programmable logic module 3. When the programmable logic module 3 receives the second-level signal, it indicates that the connection between the flash memory programmer 5 and the ribbon cable connector 1 is broken. At this time, the flash memory programmer 5 does not need to program the flash memory chip 6. The programmable logic module 3 releases the reset of the main control module 4, and the main control module 4 starts to operate normally.

[0057] The technical solution provided by this invention allows for flash memory chip programming simply by plugging the flash memory programmer into the ribbon cable connector, eliminating the need to solder the flash memory chip to the circuit board after programming. This simplifies the operation, reduces time consumption, and eliminates the need for repeated disassembly. Furthermore, by incorporating an access detection module and a programmable logic module, the connection between the flash memory programmer and the ribbon cable connector is detected. When the flash memory programmer is connected to the connector, the main control module is reset, stopping its operation and preventing data read / write operations between the main control module and the flash memory programmer. This ensures the programming quality and reliability of the flash memory chip. When the flash memory programmer is not connected to the connector, the main control module is deactivated, allowing it to continue operating. This invention eliminates the need for the main control module as an intermediate medium for data programming, ensuring that flash memory chip programming can continue even if the main control module malfunctions.

[0058] Figure 2 This is a schematic diagram of a ribbon cable connector provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a flash memory chip provided in an embodiment of the present invention. (In conjunction with...) Figures 1 to 3 Based on the above embodiments, optionally, the ribbon cable connector 1 includes: a first interface 11 and a second interface 12. The first interface 11 is connected to the access detection module 2 and is used to transmit an insertion detection signal. The access detection module 2 generates a first level signal or a second level signal based on the insertion detection signal. The second interface 12 is connected to the flash memory chip 6 and is used to transmit flash memory programming data.

[0059] The first interface 11 includes pin 1, which is used to transmit the insertion detection signal PLUG_IN_detect. When the access detection module 2 receives the insertion detection signal PLUG_IN_detect, it indicates that the ribbon cable connector 1 is successfully connected to the flash memory programmer 5, and at this time, the access detection module 2 generates a first-level signal. When the access detection module 2 does not receive the insertion detection signal PLUG_IN_detect, it indicates that the ribbon cable connector 1 is not connected to the flash memory programmer 5, and at this time, the access detection module 2 generates a second-level signal.

[0060] The second interface 12 also includes pins 3, 4, 5, and 7, used to transmit flash memory programming data to the flash memory chip 6. Pin 1 of the flash memory chip 6 is connected to the first power supply through the tenth resistor R10 and is also connected to pin 5 of the ribbon cable connector 1. The ribbon cable connector 1 also includes pins 2, 6, and 8, all of which are grounded.

[0061] Pin 2 of flash memory chip 6 is connected to pin 3 of ribbon cable connector 1. Pin 3 of flash memory chip 6 is connected to the first power supply through the twelfth resistor R12, and pin 4 of flash memory chip 6 is grounded. Pin 5 of flash memory chip 6 is connected to the first power supply and is also grounded through the sixth capacitor C6. Pin 6 of flash memory chip 6 is connected to the first power supply through the eleventh resistor R11. Pin 7 of flash memory chip 6 is connected to pin 7 of ribbon cable connector 1, and pin 8 of flash memory chip 6 is connected to pin 4 of ribbon cable connector 1. Pins 1, 2, 7, and 8 of flash memory chip 6 are used to receive flash memory programming data, which consists of FLASH_MISO, FLASH_MOSI, FLASH_CSn, and FLASH_SCLK.

[0062] Figure 4 This is a schematic diagram of an access detection module provided in an embodiment of the present invention. (In conjunction with...) Figure 1 and Figure 4 Based on the above embodiments, optionally, the access detection module 2 includes: a first resistor R1, a second resistor R2, a third resistor R3, a first transistor Q1, and a first capacitor C1. The first end of the second resistor R2 is connected to the first interface of the ribbon cable connector 1; the second end of the second resistor R2 is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is grounded; the second end of the second resistor R2 is also connected to the control terminal of the first transistor Q1; the first end of the first resistor R1 is connected to the first power supply and also to the first end of the first capacitor C1, and the second end of the first capacitor C1 is grounded; the second end of the first resistor R1 is connected to the first end of the first transistor Q1, and the second end of the first transistor Q1 is grounded; the second end of the first resistor R1 is also connected to the programmable logic module 3.

[0063] When the first terminal of the second resistor R2 receives the insertion detection signal PLUG_IN_detect, after isolation by the first transistor Q1, the first terminal of the first resistor R1 outputs the FLASH_Reset signal, which can be either a first-level signal or a second-level signal.

[0064] Figure 5 This is a schematic diagram of a programmable logic chip provided in an embodiment of the present invention. Figure 1 and Figure 5Based on the above embodiments, optionally, the programmable logic module includes a programmable logic chip 31. The programmable logic chip 31 includes a connection detection interface 311, a reset interface 312, and a power interface 313. The power interface 313 is used to connect to a first power supply. The connection detection interface 311 is connected to the second end of a first resistor R1 and is used to receive a first level signal or a second level signal. The reset interface 312 is connected to the main control module 4 and is used to output a reset signal to reset the main control module 4; or, output a de-reset signal to de-reset the main control module 4.

[0065] The programmable logic chip 31 can be an FPGA (Field-Programmable Gate Array). The plug-in detection interface 311 includes pin 1, the reset interface 312 includes pin 2, and the power interface 313 includes pins 4, 5, 6, and 7. Pin 1 is used to receive the FLASH_Reset signal output from the first terminal of the first resistor R1, and pin 2 is used to output the SYSRST_n signal, which includes a reset signal and a de-reset signal. The FLASH_Reset signal can be a first-level signal or a second-level signal. For example, the voltage levels of the first-level signal and the second-level signal are different.

[0066] Pins 4, 5, 6, and 7 are connected to the ground terminal via capacitors C7 (seventh capacitor), C8 (eighth capacitor), C9 (ninth capacitor), and C10 (tenth capacitor), respectively. Pins 4, 5, 6, and 7 are also connected to a first power supply. For example, the first power supply can be used to provide a voltage of 3.3V.

[0067] When the FLASH_Reset signal is at its first level, the SYSRST_n signal is the reset signal. At this time, the flash programmer 5 is connected to the ribbon cable connector 1, and the flash programmer 5 outputs flash programming data to the flash memory chip 6. The main control module 4 resets according to the reset signal and stops running; the main control module 4 does not output data.

[0068] When the FLASH_Reset signal is at the second level, the SYSRST_n signal is the reset signal. At this time, the flash programmer 5 is not connected to the ribbon cable connector 1, and the flash programmer 5 does not output flash programming data. The main control module 4 releases the reset according to the reset signal and restarts operation, and the main control module 4 outputs data.

[0069] This invention, through the configuration of a programmable logic chip and the detection of the connection status between the flash memory programmer and the ribbon cable connector, achieves reset control of the main control module, thereby improving the programming effect of the flash memory programmer on the flash memory chip.

[0070] Figure 6 This is a schematic diagram of a main control chip provided in an embodiment of the present invention. Figure 1 , Figure 5 and Figure 6 Based on the above embodiments, optionally, the main control module includes a main control chip 41. The main control chip 41 includes a reset control interface 411 and a data transmission interface 412. The reset control interface of the main control chip 41 is connected to the reset interface of the programmable logic chip, and the data transmission interface is connected to the flash memory programmer.

[0071] Among them, the main control chip 41 can be a CPU (Central Processing Unit) or an MCU (Micro Controller Unit).

[0072] The reset control interface 411 includes pin 1. Pin 1 is connected to pin 2 of the programmable logic chip 31 via resistor R16 (sixteenth resistor) and grounded via resistor R17 (seventeenth resistor). Pin 1 is used to receive the SYSRST_n signal and reset or de-reset based on the SYSRST_n signal. The data transmission interface 412 includes pins 2, 3, 4, and 5. Pins 2, 4, and 5 can be used to output data SI_CLK, SI_DO, and SI_nCS0 respectively, and pin 3 is used to receive data SI_DI.

[0073] For example, if the data voltage output by the main control chip 41 is the same as the operating power supply voltage of the flash memory chip 6, then pin 2 of the main control chip 41 can be directly connected to pin 7 of the flash memory chip 6, pin 3 of the main control chip 41 can be connected to pin 2 of the flash memory chip 6, pin 4 of the main control chip 41 can be connected to pin 8 of the flash memory chip 6, and pin 5 of the main control chip 41 can be connected to pin 1 of the flash memory chip 6, and data reading and writing between the main control chip 41 and the flash memory chip 6 can be performed.

[0074] Figure 7 This is a schematic diagram of another flash memory programming circuit provided in an embodiment of the present invention. (Reference) Figure 7 Based on the above embodiments, optionally, the flash memory programming circuit further includes: a level conversion module 7, connected between the main control module 4 and the flash memory chip 6, and also connected to the programmable logic module 3. The programmable logic module 3 is used to turn off the level conversion module 7 when it receives a first level signal, or to turn on the level conversion module 7 when it receives a second level signal. The level conversion module 7 is used to convert the data voltage of the main control module 4 into a first level voltage and transmit it to the flash memory chip 6, or to convert the data voltage of the flash memory chip 6 into a second level voltage and have it read by the main control module 4.

[0075] When reading and writing data between the main control module 4 and the flash memory chip 6, if their power domains are different, level conversion is required during data interaction. For example, the first voltage level can be 3.3V, and the second voltage level can be 1.8V or 2.5V. The voltage of the data output from the main control module 4 can be converted from the second voltage level to the first voltage level by the level conversion module 7 before being transmitted to the flash memory chip 6. Similarly, the data voltage of the flash memory chip 6 can be converted from the first voltage level to the second voltage level by the level conversion module 7 before being read by the main control module 4.

[0076] To prevent abnormal data output of the level conversion module 7 due to power domain incompatibility between the main control chip 41 and the flash memory chip 6 during reset, the programmable logic module 3 can control the level conversion module 7 to shut down after the flash memory programmer 5 is connected to the ribbon cable connector 1, thereby ensuring the programming effect of the flash memory chip 6.

[0077] For example, after the flash memory programmer 5 is plugged into the ribbon cable connector 1, the programmable logic module 3 shuts down the level conversion module 7. After the flash memory programmer 5 is unplugged from the ribbon cable connector 1, the level conversion module 7 can be turned on again after a delay of 100ms, and the main control module 4 can be reset. This setting method can improve the reliability of data transmission.

[0078] Based on the above embodiments, optionally, the level conversion module includes an input unit and an output unit. The input unit is connected between the main control module and the flash memory chip, and is also connected to the programmable logic module; the input unit is used to convert the data voltage of the main control module into a first level voltage and transmit it to the flash memory chip. The output unit is connected between the main control module and the flash memory chip; the output unit is used to convert the data voltage of the flash memory chip into a second level voltage and read by the main control module; the second level voltage is lower than the first level voltage.

[0079] Figure 8 This is a schematic diagram of the structure of an input chip provided in an embodiment of the present invention. Figure 9 This is a schematic diagram of an output chip provided in an embodiment of the present invention. (Reference) Figure 8 and Figure 9 Based on the above embodiments, optionally, the input unit includes an input chip 71; the input chip 71 includes a data input interface 711, a data output interface 712, an enable interface 713, a first power interface 714, and a second power interface 715. The data input interface 711 is connected to the main control module 4, the data output interface 712 is connected to the flash memory chip 6, and the enable interface 713 is connected to the programmable logic module 3. The first power interface 714 is used to connect to a first power supply, and the second power interface 715 is used to connect to a second power supply.

[0080] The second power interface 715 includes pin 1 and pin 2. Pin 1 is connected to a second power supply, which, exemplarily, may have a voltage of 2.5V. Pin 1 is also grounded through a fourth capacitor C4. Pin 1 is connected to the fourth capacitor C4 through a fourth resistor R4. The data input interface 711 includes pins 3, 4, and 5, which are connected to pins 2, 4, and 5 of the main control chip 41, respectively, for receiving output data SI_CLK, SI_DO, and SI_nCS0 from the main control chip 41. Exemplarily, the data SI_CLK, SI_DO, and SI_nCS0 all have a voltage of 2.5V.

[0081] The input chip 71 also includes pins 6-12 and pins 19-24, all of which are grounded.

[0082] The first power interface 714 includes pins 13 and 14. Pin 13 is connected to a first power supply, which, exemplarily, may have a voltage of 3.3V. Pin 13 is also grounded through a fifth capacitor C5. Pin 14 is connected to the fifth capacitor C5.

[0083] The enable interface 713 includes pin 15, which is connected to pin 3 of the programmable logic chip 31 through a fifth resistor R5, and is also grounded through a ninth resistor R9. The enable interface 713 is used to receive the enable signal FLASH_Buffer_OE output by the programmable logic chip 31, and to turn on or off according to the signal.

[0084] For example, when the input chip 71 is turned on, the data input interface 711 receives data SI_CLK, SI_DO, and SI_nCS0 at a voltage of 2.5V, and converts them into data FLASH_SCLK, FLASH_MOSI, and FLASH_CSn at a voltage of 3.3V through the input chip 71 and outputs them to the flash memory chip 6.

[0085] Optionally, the output unit includes an output chip 72. The output chip 72 includes pin 1, pin 2, pin 3, pin 4, and pin 5.

[0086] In this circuit, pin 1 of output chip 72 is connected to the first power supply and is also grounded through the second capacitor C2. Pin 2 of output chip 72 is connected to pin 2 of flash memory chip 6. Pin 3 of output chip 72 is grounded. Pin 4 of output chip 72 is connected to the second power supply and is also grounded through the third capacitor C3. Pin 5 of output chip 72 is connected to pin 3 of main control chip 41.

[0087] The output chip 72 is used to convert the data FLASH_MISO with the second voltage into data SI_DI with the first voltage when the main control chip 41 reads the data from the flash memory chip 6, and then transmit it to the main control chip 41.

[0088] Figure 10 This is a flowchart illustrating a flash memory programming method provided in an embodiment of the present invention. (See reference...) Figure 10 The flash memory programming method is applied to the flash memory programming circuit provided in any embodiment of the present invention. The flash memory programming method includes:

[0089] S110. When the ribbon cable connector is plugged into the flash memory programmer, the access detection module outputs a first level signal to the programmable logic module.

[0090] S120, the programmable logic module controls the main control module to reset.

[0091] S130, the flash programmer outputs flash programming data to the flash chip through the ribbon cable connector.

[0092] Figure 11 This is a flowchart illustrating a flash memory programming method provided in an embodiment of the present invention. (See reference...) Figure 11 Optionally, based on the above embodiments, the flash memory programming method further includes:

[0093] S140. Determine the connection status between the ribbon cable connector and the flash memory programmer. When the ribbon cable connector and the flash memory programmer are not connected, the access detection module outputs a second level signal to the programmable logic module.

[0094] S150, the programmable logic module controls the main control module to release the reset, and the main control module is put into operation.

[0095] In various embodiments of the flash memory programming circuit, specific descriptions of flash memory programming methods are provided. These flash memory programming methods can all be considered as programming methods for the flash memory programming circuit provided in the embodiments of the present invention, and repeated content will not be described here.

[0096] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0097] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A flash memory programming circuit, characterized in that, The application relates to a flash memory chip and a flash memory chip interface device. The application comprises: a flat cable seat used for connecting a flash memory burner, the flat cable seat being used for outputting flash memory burning data to the flash memory chip through the flat cable seat; an access detection module connected with the flat cable seat, the access detection module being used for outputting a first level signal when the flat cable seat is connected with the flash memory burner, or outputting a second level signal when the flat cable seat is not connected with the flash memory burner; 2. The flash burning circuit according to claim 1, characterized in that, a programmable logic module and a main control module, the programmable logic module being connected with the access detection module and the main control module, the main control module being connected with the flash memory chip, the programmable logic module being used for resetting the main control module when the first level signal is received, or being used for unresetting the main control module when the second level signal is received. The flat cable seat comprises a first interface and a second interface. The first interface is connected with the access detection module and is used for transmitting an insertion detection signal, the access detection module generating the first level signal or the second level signal according to the insertion detection signal; 3. The flash programming circuit of claim 2, wherein, the second interface is connected with the flash memory chip and is used for transmitting the flash memory burning data. The access detection module comprises a first resistor, a second resistor, a third resistor, a first transistor and a first capacitor.

4. The flash burning circuit of claim 3, wherein, The first end of the second resistor is connected with the first interface of the flat cable seat, the second end of the second resistor is connected with the first end of the third resistor, the second end of the third resistor is grounded, the second end of the second resistor is also connected with the control end of the first transistor, the first end of the first resistor is connected with a first power supply and a first end of the first capacitor, the second end of the first capacitor is grounded, the second end of the first resistor is connected with the first end of the first transistor, the second end of the first transistor is grounded, and the second end of the first resistor is also connected with the programmable logic module. The programmable logic module comprises a programmable logic chip. The programmable logic chip comprises a plug-in detection interface, a reset interface and a power supply interface. The power supply interface is used for connecting a first power supply. The plug-in detection interface is connected with the second end of the first resistor and is used for receiving the first level signal or the second level signal.

5. The flash programming circuit of claim 4, wherein, The reset interface is connected with the main control module and is used for outputting a reset signal to reset the main control module or outputting an unreset signal to unreset the main control module. The main control module comprises a main control chip. The main control chip comprises a reset control interface and a data transmission interface. The reset control interface of the main control chip is connected with the reset interface of the programmable logic chip, and the data transmission interface is connected with the flash memory burner.

6. The flash burn-in circuit of claim 1, wherein, The flash burning circuit further comprises a level conversion module connected between the master control module and the flash memory chip and also connected with the programmable logic module; the level conversion module is configured to convert the data voltage of the master control module into a first level voltage and transmit the first level voltage to the flash memory chip, or convert the data voltage of the flash memory chip into a second level voltage and read the second level voltage by the master control module. The programmable logic module is configured to turn off the level conversion module when the first level signal is received, or turn on the level conversion module when the second level signal is received.

7. The flash programming circuit of claim 6, wherein, The level conversion module comprises an input unit and an output unit. The input unit is connected between the master control module and the flash memory chip and also connected with the programmable logic module; the input unit is configured to convert the data voltage of the master control module into a first level voltage and transmit the first level voltage to the flash memory chip. The output unit is connected between the master control module and the flash memory chip; the output unit is configured to convert the data voltage of the flash memory chip into a second level voltage and read the second level voltage by the master control module; the second level voltage is less than the first level voltage.

8. The flash burn-in circuit of claim 7, wherein, The input unit comprises an input chip; the input chip comprises a data input interface, a data output interface, an enable interface, a first power supply interface and a second power supply interface. The data input interface is connected with the master control module, the data output interface is connected with the flash memory chip, and the enable interface is connected with the programmable logic module. The first power supply interface is configured to access a first power supply, and the second power supply interface is configured to access a second power supply.

9. A flash burn-in method, characterized by, The flash burning method is applied to the flash burning circuit according to any one of claims 1-8, and the flash burning method comprises: When the wire harness seat is plugged with the flash burning device, the access detection module outputs a first level signal to the programmable logic module; The programmable logic module controls the master control module to reset; The flash burning device outputs flash burning data to the flash memory chip through the wire harness seat.

10. The flash burn-in method of claim 9, wherein, The flash burning method further comprises: judging the plugging state of the wire harness seat with the flash burning device; when the wire harness seat is not plugged with the flash burning device, the access detection module outputs a second level signal to the programmable logic module; The programmable logic module controls the master control module to be reset, and the master control module is put into operation.

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