Solar cell, preparation method thereof and photovoltaic module

Abstract

The embodiment of the invention relates to a solar cell, a preparation method thereof and a photovoltaic module. The preparation method of the solar cell comprises the following steps: providing a semiconductor substrate; forming a tunneling layer on the surface of the semiconductor substrate; sequentially forming an undoped initial intrinsic material layer and a doping layer containing a dopant on the surface of the tunneling layer; the dopant comprises any one of an N-type dopant and a P-type dopant; and performing heat treatment on the initial intrinsic material layer and the doped layer, so that the dopant in the doped layer is diffused to the initial intrinsic material layer, and the initial intrinsic material layer is at least partially crystallized, so that the initial intrinsic material layer is converted into a doped passivation layer.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to a solar cell, a method for preparing the same, and a photovoltaic module. Background Technology

[0002] With the continuous development of solar cell technology, the requirements for photoelectric conversion efficiency are becoming increasingly stringent. However, improving the efficiency of industrially produced solar cells still faces many challenges. To enhance the performance of solar cells, the semiconductor substrate is typically passivated, which involves forming passivated contact structures on the surface of the substrate to reduce the recombination of surface carriers and thus minimize the impact of internal defects in the semiconductor substrate on device performance. Therefore, further improving the passivation performance of the passivation contact structures has become a key research focus for those skilled in the art. Summary of the Invention

[0003] Therefore, it is necessary to provide a solar cell with good passivation performance, its preparation method, and a photovoltaic module.

[0004] In a first aspect, embodiments of this application provide a method for preparing a solar cell, comprising:

[0005] Provide semiconductor substrates;

[0006] A tunneling layer is formed on the surface of the semiconductor substrate;

[0007] An undoped initial intrinsic material layer and a doped layer containing a dopant are sequentially formed on the surface of the tunneling layer; the dopant includes either an N-type dopant or a P-type dopant.

[0008] The initial intrinsic material layer and the doped layer are subjected to heat treatment to diffuse the dopant in the doped layer into the initial intrinsic material layer and to at least partially crystallize the initial intrinsic material layer, thereby transforming the initial intrinsic material layer into a doped passivation layer.

[0009] In one embodiment, the sequential formation of an undoped initial intrinsic material layer and a doped layer containing a dopant on the surface of the tunneling layer includes:

[0010] Multiple undoped initial intrinsic material layers and multiple doped layers containing dopants are alternately formed on the surface of the tunneling layer.

[0011] In one embodiment, the thickness of the first doped layer is 5 nm to 30 nm; and / or

[0012] The thickness of the second doped layer is 1 nm to 10 nm;

[0013] Wherein, the first doped layer is the one furthest from the semiconductor substrate among the plurality of doped layers; the second doped layer is any of the other doped layers besides the first doped layer.

[0014] In one embodiment, when the thickness of the first doped layer is less than 10 nm, the preparation method further includes:

[0015] A mask layer is formed on the surface of the first doped layer; the sum of the thicknesses of the mask layer and the first doped layer is greater than 20 nm.

[0016] In one embodiment, the mask layer is made of undoped silicon compound.

[0017] In one embodiment, the doping concentration of the second doped layer is greater than the doping concentration of the first doped layer;

[0018] Wherein, the first doped layer is the one furthest from the semiconductor substrate among the plurality of doped layers, and the second doped layer is any of the other doped layers besides the first doped layer.

[0019] In one embodiment, the preparation method further includes:

[0020] After heat treatment of the initial intrinsic material layer and the doped layer, the barrier layer formed by the transformation of the first doped layer during the heat treatment process is removed.

[0021] The first doped layer is the one furthest from the semiconductor substrate among the plurality of doped layers.

[0022] In one embodiment, the thickness of the first doped layer is greater than the thickness of the tunneling layer, and the thickness of the second doped layer is greater than or equal to the thickness of the tunneling layer;

[0023] Wherein, the first doped layer is the one furthest from the semiconductor substrate among the plurality of doped layers, and the second doped layer is any of the other doped layers besides the first doped layer.

[0024] In one embodiment, both the doped layer and the tunneling layer are made of silicon oxide compounds, and the silicon-to-oxygen ratio of the second doped layer is greater than or equal to the silicon-to-oxygen ratio of the first doped layer and the tunneling layer.

[0025] Wherein, the first doped layer is the one furthest from the semiconductor substrate among the plurality of doped layers, and the second doped layer is any of the other doped layers besides the first doped layer.

[0026] In one embodiment, the silicon-to-oxygen ratio of the second doped layer is greater than 1:2, and the silicon-to-oxygen ratio of the tunneling layer is less than 1:5.

[0027] In one embodiment, the thickness of the tunneling layer is 0.5 nm to 2 nm.

[0028] In one embodiment, in one embodiment, in one embodiment, the step of sequentially forming an undoped initial intrinsic material layer and a doped layer containing a dopant on the surface of the tunneling layer includes:

[0029] In the same plasma-enhanced chemical vapor deposition apparatus, the initial intrinsic material layer and the doped layer are formed on the surface of the tunneling layer.

[0030] In one embodiment, the doping concentration of the doped layer is greater than 1e21 atoms / cm. 3 .

[0031] In one embodiment, the heat treatment is further used to diffuse the dopant into the semiconductor substrate to form an inner extension layer in the semiconductor substrate.

[0032] In one embodiment, the heat treatment conditions include a heat treatment temperature greater than 800°C and a heat treatment time greater than 20 minutes.

[0033] In one embodiment, the thickness of the inner expansion layer is 0.02 μm to 1 μm.

[0034] In one embodiment, the material of the initial intrinsic material layer includes any one of intrinsic amorphous silicon, intrinsic microcrystalline silicon, and intrinsic polycrystalline silicon.

[0035] In one embodiment, the preparation method further includes:

[0036] A buffer layer is formed in the initial intrinsic material layer; the buffer layer comprises an undoped silicon compound;

[0037] The heat treatment of the initial intrinsic material layer and the doped layer includes:

[0038] The initial intrinsic material layer, the buffer layer, and the doped layer are subjected to heat treatment; the heat treatment includes multiple processing stages, and the temperatures of the multiple processing stages are not exactly the same.

[0039] In one embodiment, the heat treatment includes a first processing stage and a second processing stage performed sequentially, wherein the temperature of the second processing stage is greater than the temperature of the first processing stage or the temperature of the second processing stage is less than the temperature of the first processing stage.

[0040] In one embodiment, one of the first processing stage and the second processing stage uses 800°C to 910°C, and the other of the first processing stage and the second processing stage uses 900°C to 1000°C.

[0041] In one embodiment, the heat treatment includes a first processing stage, a second processing stage, and a third processing stage performed sequentially, wherein the temperature of the second processing stage is greater than the temperature of the first processing stage and the temperature of the third processing stage.

[0042] In one embodiment, when there are multiple initial intrinsic material layers, forming a buffer layer in the initial intrinsic material layers includes:

[0043] A buffer layer is formed in one of the initial intrinsic material layers closest to the semiconductor substrate.

[0044] In one embodiment, the thickness of the buffer layer is 0.5 nm to 2 nm.

[0045] In one embodiment, the buffer layer is made of a silicon oxide compound.

[0046] In one embodiment, the preparation method further includes:

[0047] A dielectric layer is formed on the side of the doped passivation layer away from the semiconductor substrate;

[0048] A first electrode is formed on the side of the doped passivation layer away from the semiconductor substrate; one end of the first electrode penetrates the dielectric layer and is electrically connected to the doped passivation layer, and the other end of the first electrode extends in a direction away from the semiconductor substrate.

[0049] In one embodiment, when there are multiple doped passivation layers, one end of the first electrode extends to a target doped passivation layer among the multiple doped passivation layers and penetrates each film layer of the target doped passivation layer on the side away from the semiconductor substrate.

[0050] Secondly, embodiments of this application provide a solar cell, which is prepared using the solar cell preparation method described above.

[0051] Thirdly, embodiments of this application provide a solar cell, comprising:

[0052] Semiconductor substrate;

[0053] A tunneling layer is located on the surface of the semiconductor substrate;

[0054] A doped passivation layer is stacked on the side of the tunneling layer away from the semiconductor substrate;

[0055] A dielectric layer is disposed on the side of the doped passivation layer away from the tunneling layer;

[0056] A first electrode, one end of which is electrically connected to the doped passivation layer and penetrates the dielectric layer, and the other end of which extends away from the semiconductor substrate.

[0057] In one embodiment, the number of doped passivation layers is multiple, and the solar cell further includes at least one barrier layer located on the side of any of the doped passivation layers away from the semiconductor substrate;

[0058] One end of the first electrode extends to a target doped passivation layer among the plurality of doped passivation layers and penetrates each film layer of the target doped passivation layer on the side away from the semiconductor substrate, wherein the film layer penetrated by the first electrode includes the dielectric layer.

[0059] In one embodiment, the film layer through which the first electrode penetrates further includes at least one of the doped passivation layers and / or at least one of the barrier layers.

[0060] In one embodiment, the thickness of the barrier layer is from 0.5 nm to 10 nm.

[0061] In one embodiment, the thickness of the doped layer is greater than or equal to the thickness of the tunneling layer.

[0062] In one embodiment, the thickness of the tunneling layer is 0.5 nm to 2 nm.

[0063] In one embodiment, the thickness of the single layer of the doped passivation layer is from 2 nm to 150 nm.

[0064] Fourthly, embodiments of this application provide a photovoltaic module, including a battery string, wherein the battery string is formed by connecting multiple solar cells as described above.

[0065] In the aforementioned solar cells, their fabrication methods, and photovoltaic modules, the fabrication method of this application provides a doped layer with sufficient dopant to effectively fill grain boundary defects in the initial intrinsic material layer. Furthermore, the required doping concentration of the passivation layer can be flexibly adjusted by changing the doping concentration of the doped layer, thereby achieving better field passivation. Compared to in-situ doping, the intrinsic material's non-conductive nature prevents short circuits in the graphite boat's electrodes during deposition, thus extending the graphite boat's lifespan and reducing production costs. Moreover, the diffusion process of the dopant from the doped layer into the initial intrinsic material layer causes less damage to the tunneling layer, reducing the likelihood of defects and maintaining good tunneling efficiency and stability. Additionally, the fabrication method of this application has lower requirements for the annealing tube; only a uniform temperature field is needed to meet the fabrication environment requirements, without considering doping inhomogeneities caused by uneven gas fields. This allows for greater capacity and production output per tube. Therefore, this application provides a method for preparing a solar cell with good doping uniformity of the passivation layer and low manufacturing difficulty. Attached Figure Description

[0066] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0067] Figure 1 This is one of the flowcharts for a method of fabricating a solar cell according to an embodiment;

[0068] Figure 2 for Figure 1 A schematic diagram of the solar cell after step S310 in the embodiment;

[0069] Figure 3 for Figure 1 A schematic diagram of the solar cell after step S410 in the embodiment;

[0070] Figure 4 This is a second flowchart illustrating a method for fabricating a solar cell according to an embodiment;

[0071] Figure 5 for Figure 4 A schematic diagram of the solar cell after step S320 in the embodiment;

[0072] Figure 6 for Figure 4 A schematic diagram of the solar cell after step S410 in the embodiment;

[0073] Figure 7 This is the third flowchart of a method for fabricating a solar cell according to one embodiment;

[0074] Figure 8 for Figure 7 One of the schematic diagrams of a solar cell with an inner extension layer in an embodiment;

[0075] Figure 9 for Figure 7 A second schematic diagram of a solar cell with an inner expansion layer in an embodiment;

[0076] Figure 10 This is the fourth flowchart of a method for fabricating a solar cell according to one embodiment;

[0077] Figure 11 for Figure 10 A schematic diagram of the structure of the solar cell after step S330 in the embodiment;

[0078] Figure 12 for Figure 10 A schematic diagram of the structure of the solar cell after step S430 in the embodiment;

[0079] Figure 13 This is the fifth flowchart of a method for fabricating a solar cell according to one embodiment;

[0080] Figure 14 for Figure 13 One of the schematic diagrams of the structure of the solar cell after step S600 in the embodiment;

[0081] Figure 15 This is a second schematic diagram of the structure of the solar cell after step S600 in one embodiment;

[0082] Figure 16 This is the third schematic diagram of the structure of the solar cell after step S600 in one embodiment;

[0083] Figure 17 This is the fourth schematic diagram of the structure of the solar cell after step S600 in one embodiment.

[0084] Component designation explanation:

[0085] Semiconductor substrate: 100; tunneling layer: 200; initial intrinsic material layer: 310; doped passivation layer: 320; doped layer: 401; first doped layer: 410; second doped layer: 420; barrier layer: 402; buffer layer: 403; inner expansion layer: 500; dielectric layer: 600; first electrode: 700. Detailed Implementation

[0086] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0087] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0088] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0089] It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0090] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0091] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0092] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0093] This application provides a method for fabricating a solar cell. The method can be used, but is not limited to, fabricating tunnel oxide passivated contact (TOPCon) cells or interdigitated back contact (IBC) cells to form the passivated contact structure in these cells. Taking a TOPCon cell as an example, the passivated contact structure has the functions of surface passivation and selective collection of charge carriers, which can effectively improve the efficiency and stability of the solar cell.

[0094] Figure 1 This is one of the flowcharts for a method of fabricating a solar cell according to an embodiment. Figure 2 for Figure 1 A schematic diagram of the solar cell after step S310 in the embodiment. Figure 3 for Figure 1 A schematic diagram of the solar cell after step S410 of the embodiment, in conjunction with reference. Figures 1 to 3 The method for preparing a solar cell includes steps S100 to S410.

[0095] Step S100: Provide semiconductor substrate 100.

[0096] The semiconductor substrate 100 can be a silicon substrate.

[0097] In step S200, a tunneling layer 200 is formed on the surface of the semiconductor substrate 100.

[0098] The tunneling layer 200 can also be referred to as the tunneling oxide layer or the surface passivation layer. The tunneling layer 200 can be made of a dielectric material, including but not limited to any one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, or titanium oxide.

[0099] Furthermore, any of the processes such as atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), and plasma enhanced atomic layer deposition (PEALD) can be used to form the tunneling layer 200. Even further, a process with a lower reaction temperature can be used to form the tunneling layer 200, forming it at a reaction temperature below 600°C. This reduces the damage to the material caused by the high-temperature environment and makes it easier to control the film thickness and uniformity of the tunneling layer 200, thus improving film quality. For example, a silicon oxide tunneling layer 200 can be prepared using plasma enhanced chemical vapor deposition, with a chamber temperature of 300°C to 500°C and nitrous oxide as the process gas. Under the action of a microwave power supply, the ionized oxygen ions combine with silicon to form silicon oxide.

[0100] In step S310, an undoped initial intrinsic material layer 310 and a doped layer 401 containing dopant are sequentially formed on the surface of the tunneling layer 200.

[0101] The dopant in the doped layer 401 can be either an N-type dopant or a P-type dopant. N-type dopant includes, but is not limited to, phosphorus and arsenic, while P-type dopant includes, but is not limited to, boron. The initial intrinsic material layer 310 can be made of intrinsic materials, including, but not limited to, intrinsic amorphous silicon, intrinsic microcrystalline silicon, and intrinsic polycrystalline silicon. It is understood that intrinsic materials are non-conductive; therefore, regardless of the process equipment used to form the initial intrinsic material layer 310, the adhesion of the intrinsic material within the cavity of the process equipment will not cause short circuits, thereby improving the lifespan and reliability of the process equipment.

[0102] Step S410 involves heat-treating the initial intrinsic material layer 310 and the doped layer 401 to diffuse the dopant in the doped layer 401 into the initial intrinsic material layer 310 and to at least partially crystallize the initial intrinsic material layer 310, thereby transforming the initial intrinsic material layer 310 into a doped passivation layer 320.

[0103] The heat-treated doped layer 401 is transformed into a dopant-free barrier layer 402. The tunneling layer 200 and the doped passivation layer 320 together constitute a passivation contact structure. This structure allows majority carriers (electrons) to smoothly pass through the tunneling layer 200 via the tunneling effect, while simultaneously blocking the recombination of minority carriers (holes), thereby reducing the interface state density, increasing the open-circuit voltage and fill factor of the solar cell, and ultimately improving its performance. Specifically, the heat treatment promotes the movement of phosphorus, boron, and other atoms in the doped layer 401 towards the initial intrinsic material layer 310, thus achieving doping of the initial intrinsic material layer 310.

[0104] The crystallinity after heat treatment can exceed 60%, even reaching 90% to 93%. Specifically, achieving a higher degree of crystallinity in the intrinsic semiconductor through heat treatment helps reduce the disordered structure in the material, thereby lowering the defect state density of the doped passivation layer 320. It is understood that defect states typically act as recombination centers for charge carriers, trapping electrons and holes and causing them to recombine and disappear. Therefore, when the defect state density is high, the increased number of recombination centers reduces the lifetime and mobility of charge carriers, thus affecting the electrical performance of the material. Therefore, crystallizing the initial intrinsic material layer 310 through heat treatment to reduce the defect state density facilitates higher concentrations of effective doping and provides better field passivation, thereby improving the efficiency and stability of the solar cell.

[0105] Furthermore, the heat treatment temperature is positively correlated with the thickness of the initial intrinsic material layer 310 and the doped layer 401, and the heat treatment time is also positively correlated with the thickness of the initial intrinsic material layer 310 and the doped layer 401. In this embodiment, the specific time and temperature of the heat treatment are not limited, provided that the dopant can diffuse uniformly from the doped layer 401 into the initial intrinsic material layer 310.

[0106] In the embodiments of the application, the doped layer 401 can provide sufficient dopant to effectively fill grain boundary defects in the initial intrinsic material layer 310. The required doping concentration of the passivation layer 320 can be flexibly adjusted by changing the doping concentration of the doped layer 401, thereby achieving a better field passivation effect. Compared to in-situ doping, because the intrinsic material is non-conductive, it will not cause short circuits in the graphite boat electrodes during deposition, thus extending the lifespan of the graphite boat and reducing production costs. Furthermore, the diffusion process of the dopant from the doped layer 401 into the initial intrinsic material layer 310 causes less damage to the tunneling layer 200 and is less likely to cause defects in the tunneling layer 200, thus maintaining good tunneling efficiency and stability. In addition, the fabrication method of this application has lower requirements for the annealing tube; only a uniform temperature field is needed to meet the fabrication environment requirements, without considering doping inhomogeneities caused by gas field inhomogeneities, thereby increasing the loading capacity and production capacity of a single tube device. Therefore, this application provides a method for preparing a solar cell with good doping uniformity of the passivation layer 320 and low manufacturing difficulty.

[0107] Figure 4 This is the second flowchart of a method for fabricating a solar cell according to one embodiment. Figure 5 for Figure 4 A schematic diagram of the solar cell after step S320 in the embodiment. Figure 6 for Figure 4 A schematic diagram of the solar cell after step S410 of the embodiment, in conjunction with reference. Figures 4 to 6 In one embodiment, the method for fabricating a solar cell includes steps S100 to S410. Steps S100, S200, and S410 can be referred to the previous embodiment and will not be repeated here. The aforementioned steps of sequentially forming an undoped initial intrinsic material layer 310 and a doped layer 401 containing dopant on the surface of the tunneling layer 200 include step S320 of this embodiment.

[0108] Step S100: Provide semiconductor substrate 100.

[0109] In step S200, a tunneling layer 200 is formed on the surface of the semiconductor substrate 100.

[0110] In step S320, multiple undoped initial intrinsic material layers 310 and multiple doped layers 401 containing dopants are alternately formed on the surface of the tunneling layer 200.

[0111] The doping concentration in the multiple doped layers 401 can be different, and can be determined by factors such as the thickness of the doped layer 401 and the number of adjacent intrinsic material layers 310. For example, the same dopant dosage can be provided in different doped layers 401, and the thicker doped layer 401 can have a lower doping concentration. Alternatively, if the doped layer 401 is adjacent to two intrinsic material layers 310, a higher doping concentration can be set for that doped layer 401; if the doped layer 401 is adjacent to only one intrinsic material layer 310, a lower doping concentration can be set for that doped layer 401.

[0112] Optionally, the initial intrinsic material layer 310 and the doped layer 401 can have the same number of layers, and the film layer closest to the tunneling layer 200 can be the initial intrinsic material layer 310, while the film layer furthest from the tunneling layer 200 can be the doped layer 401. For example, it can be as follows: Figure 5 As shown, both the initial intrinsic material layer 310 and the doped layer 401 are three layers, and the initial intrinsic material layer 310, the doped layer 401, the initial intrinsic material layer 310, the doped layer 401, the initial intrinsic material layer 310, the doped layer 401, the initial intrinsic material layer 310, and the doped layer 401 are stacked alternately on the surface of the tunneling layer 200. The number of initial intrinsic material layers 310 and doped layers 401 can also be different, and the film layer closest to the tunneling layer 200 and the film layer furthest from the tunneling layer 200 can both be the initial intrinsic material layer 310. For example, the initial intrinsic material layer 310, the doped layer 401, the initial intrinsic material layer 310, the doped layer 401, and the initial intrinsic material layer 310 can be stacked alternately on the surface of the tunneling layer 200. That is, this embodiment does not limit the specific number of initial intrinsic material layers 310 and the doped layer 401 and their stacking method.

[0113] Step S410 involves heat-treating the initial intrinsic material layer 310 and the doped layer 401 to allow the dopant in the doped layer 401 to diffuse into the initial intrinsic material layer 310, thereby transforming the initial intrinsic material layer 310 into a doped passivation layer 320.

[0114] In the embodiments of the application, under the premise that the total thickness of the multiple initial intrinsic material layers 310 is the same as or similar to the thickness of the initial intrinsic material layer 310 in the related art, by stacking multiple initial intrinsic material layers 310 and multiple doped layers 401, the thickness of a single initial intrinsic material layer 310 can be effectively reduced, thereby avoiding the problem of uneven diffusion of dopants due to excessive thickness. This also avoids the situation where the doping concentration of the final initial intrinsic material layer 310 is high on the side near the doped layer 401 and low on the side near the semiconductor substrate 100, resulting in poor and uneven diffusion of dopants. Moreover, the doped layer 401 disposed between adjacent initial intrinsic material layers 310, after being transformed into a barrier layer 402 during heat treatment, can also reduce the impact of metallization ablation on the solar cell and prevent it from burning through to the semiconductor substrate 100, thereby achieving a thinner doped passivation layer 320. Taking the doped passivation layer 320 as a poly layer as an example, an excessively thick poly layer will increase the absorption of parasitic light and reduce the short-circuit current density of solar energy, thereby affecting the overall power conversion efficiency of the device. By using a thinner poly layer, this parasitic light absorption can be reduced, allowing more photons to reach the active layer and be effectively absorbed, thereby improving the long-wavelength response.

[0115] In one embodiment, the thickness of the second doped layer 420 is less than the thickness of the first doped layer 410. The first doped layer 410 is the one furthest from the semiconductor substrate 100 among the plurality of doped layers 401, and the second doped layer 420 is any of the other doped layers 401 besides the first doped layer 410. The thickness of the first doped layer 410 is 5 nm to 30 nm. For example, the thickness of the first doped layer 410 is 5 nm, 10 nm, 20 nm, 25 nm, or 30 nm. The thickness of the second doped layer 420 is 1 nm to 10 nm. For example, the thickness of the second doped layer 420 is 1 nm, 3 nm, 5 nm, 8 nm, or 10 nm. In the embodiments of the application, by setting the thickness of the doped layers 401 as described above, sufficient doping can be provided to the initial intrinsic material layer 310, and the impact of metallization ablation on the solar cell can be effectively reduced.

[0116] In one embodiment, if the thickness of the first doped layer 410 is less than 10 nm, for example, 5 nm or 7 nm, the fabrication method further includes forming a mask layer on the surface of the first doped layer 410. The sum of the thicknesses of the mask layer and the first doped layer 410 is greater than 20 nm. Specifically, since the formation of the first doped layer 410 requires the participation of PH3 for doping, and PH3 is expensive, this embodiment uses a thinner first doped layer 410, which can effectively save the amount of PH3 used and reduce process costs. It is understood that in some cases, the semiconductor substrate 100 may have a front-side plating, and the solar cell fabrication method also requires a wet etching step to remove the plating. Therefore, the first doped layer 410 is also used during the wet etching process to protect the doped passivation layer 320, tunneling layer 200, etc., located between the first doped layer 410 and the semiconductor substrate 100, to reduce the impact of the etching solution on the performance of the solar cell. However, if the thickness of the first doped layer 410 is less than 10 nm, it cannot completely resist the erosion of the etching solution, thereby causing damage to the doped passivation layer 320 and other films. Therefore, by further increasing the mask layer and making the sum of the thickness of the mask layer and the first doped layer 410 greater than 20 nm, the doped passivation layer 320 and other films can be better protected during wet etching, thereby improving the performance of the solar cell.

[0117] In one embodiment, the mask layer is made of an undoped silicon compound, such as undoped silicon oxide. Specifically, when the mask layer is made of undoped silicon oxide and the first doped layer 410 is made of doped silicon oxide, the barrier layer 402 formed by the transformation of the mask layer and the barrier layer 402 formed by the transformation of the first doped layer 410 can be removed by the same process after heat treatment, thereby simplifying the process. It is understood that in some embodiments, the mask layer may also be made of other materials that can resist etching solutions, which is not limited here.

[0118] In one embodiment, the thickness of the first doped layer 410 is greater than the thickness of the tunneling layer 200, and the thickness of the second doped layer 420 is greater than or equal to the thickness of the tunneling layer 200. A thinner tunneling layer 200 results in a significantly lower tunneling resistance, allowing electrons to more easily pass through the potential barrier and thus improving conductivity. However, the doped layer 401 provides dopant to the initial intrinsic material layer 310 to achieve sufficient and uniform doping. Furthermore, the doped layer 401 also protects the substrate during metallization ablation. Therefore, a relatively thick doped layer 401 is required to meet the fabrication requirements of the solar cell. Further, the thickness of the tunneling layer 200 is between 0.5 nm and 2 nm, for example, 0.5 nm, 1 nm, 1.5 nm, or 2 nm.

[0119] In one embodiment, both the doped layer 401 and the tunneling layer 200 are made of silicon oxide compounds, and the silicon-to-oxygen ratio (S / O ratio) of the second doped layer 420 is greater than that of the first doped layer 410 and the tunneling layer 200. Specifically, a lower S / O ratio can reduce the tunneling barrier of the tunneling layer 200, thereby improving the electron tunneling efficiency. Moreover, an appropriate S / O ratio can optimize passivation characteristics, further improving device performance. However, for the doped layer 401, the silicon content percentage in the doped layer 401 is positively correlated with the dopant dose. Therefore, increasing the S / O ratio of the second doped layer 420 can increase the dopant dose, thereby achieving sufficient doping of the initial intrinsic material layer 310. Further, the S / O ratio of the doped layer 401 is greater than 1:2, for example, 1:2 or 1:1. The S / O ratio of the tunneling layer 200 is less than 1:1.5, for example, 1:1.5, 1:1.8 or 1:2.

[0120] In one embodiment, the doping concentration of the second doped layer 420 is greater than the doping concentration of the first doped layer 410. The first doped layer 410 is the one furthest from the semiconductor substrate 100 among the multiple doped layers 401; the second doped layer 420 is any of the other doped layers 401 besides the first doped layer 410. Taking silicon oxide doped with dopant as an example, the lower the doping concentration of the doped layer 401, the lower the oxygen content in the doped layer 401, and correspondingly, the higher the silicon content in the doped layer 401. It is understood that the lower the oxygen content in the doped layer 401, the more difficult it is to remove the doped layer 401. Therefore, by setting the doping concentration of the second doped layer 420 to be greater than that of the first doped layer 410, it is easier to remove the barrier layer 402 formed during the heat treatment process of the first doped layer 410, provided that sufficient doping is provided, thus meeting the structural design requirements of the solar cell.

[0121] In one embodiment, the thickness of a single initial intrinsic material layer 310 is between 2 nm and 150 nm. Exemplarily, the thickness of the initial intrinsic material layer 310 is 2 nm, 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 100 nm, or 150 nm. The thickness of each initial intrinsic material layer 310 can be determined based on the total thickness and number of doped passivation layers 320 required in the solar cell to provide a better passivation effect.

[0122] In one embodiment, the preparation method further includes: after heat-treating the initial intrinsic material layer 310 and the doped layer 401, removing the barrier layer 402 formed by the first doped layer 410 during the heat treatment process. The first doped layer 410 is the one furthest from the semiconductor substrate 100 among the multiple doped layers 401. Specifically, any of hydrofluoric acid (HF), hydrochloric acid (HCl), etc., can be used to remove the barrier layer 402 formed by the first doped layer 410, which is made of materials such as silicon oxide. It should be noted that in some embodiments, if the thickness of the barrier layer 402 formed by the first doped layer 410 is small or difficult to remove, and its impact on the performance degradation of the solar cell is small, then the barrier layer 402 formed by the first doped layer 410 during the heat treatment process may not need to be removed.

[0123] In one embodiment, forming a plurality of undoped initial intrinsic material layers 310 and a plurality of doped layers 401 containing dopants on the surface of the tunneling layer 200 includes: forming the initial intrinsic material layers 310 and the doped layers 401 on the surface of the tunneling layer 200 in the same plasma-enhanced chemical vapor deposition apparatus.

[0124] Specifically, the deposition rate of the initial intrinsic material layer 310 and the doped layer 401 is between 2 nm / min and 20 nm / min. Exemplarily, the deposition rate can be 2 nm / min, 3 nm / min, 5 nm / min, 8 nm / min, 10 nm / min, 14 nm / min, 16 nm / min, 19 nm / min, or 20 nm / min. Further, the deposition rate can be between 3 nm / min and 10 nm / min. By keeping the deposition rate within the above range, the film quality of the initial intrinsic material layer 310 can be guaranteed, and the production capacity of the solar cell can be improved. When depositing the initial intrinsic material layer 310 and the doped layer 401, the chamber temperature of the plasma-enhanced chemical vapor deposition process can be the same and between 200°C and 700°C. Exemplarily, the chamber temperature can be 350°C, 380°C, 401°C, 410°C, 430°C, 450°C, 470°C, or 480°C. Furthermore, the chamber temperature can be between 350°C and 480°C. By keeping the chamber temperature within this range, the deposition rate of the initial intrinsic material layer 310 can be kept within a controllable range, thereby improving the uniformity of the initial intrinsic material layer 310 film. Moreover, after forming the initial intrinsic material layer 310 and the doped layer 401 using the above method, there is no need to cool the furnace tube; the initial contact structure can be further heat-treated in the same tube to transform the initial intrinsic material layer 310 into the doped passivation layer 320, thereby improving the fabrication efficiency.

[0125] In the embodiments of the application, multiple initial intrinsic material layers 310 and multiple doped layers 401 are completed within the same PECVD equipment, thereby effectively improving deposition efficiency and reducing production costs. Moreover, compared to in-situ doping, since the initial intrinsic material layer 310 uses undoped intrinsic material, the non-conductive intrinsic material will not cause short circuits in the graphite boat electrodes during deposition, thus extending the lifespan of the graphite boat and reducing production costs. Compared to in-situ doping, the process gas composition in this embodiment is more uniform, resulting in better thickness uniformity of the initial intrinsic material layer 310 and a faster deposition rate, which is beneficial for increasing production capacity.

[0126] Specifically, the process gases in plasma-enhanced chemical vapor deposition (PECVD) include a silicon source gas and a dilution gas. The silicon source gas can be excited and ionized to generate plasma for film deposition. The silicon source gas includes at least one of SiH4, Si2H6, SiCl3H, and SiH2Cl2. The dilution gas maintains the pressure inside the tube and also dilutes the silicon source gas to improve its distribution uniformity. The dilution gas includes at least one of H2, Ar, N2, He, and Xe. It should be noted that inert gases such as Ar, N2, He, and Xe can dilute the silicon source gas to improve uniformity and maintain the pressure inside the tube. H2 not only dilutes the silicon source gas to improve uniformity and maintain the pressure inside the tube, but also ionizes to provide hydrogen ions to improve passivation. For example, the reaction gas for forming the initial intrinsic material layer 310 may include SiH4 and H2, while the reaction gas for forming the doped layer 401 may include SiH4, N2O, and H2, as well as PH3 for doping. In some embodiments, the dilution gas includes a mixture of H2 and Ar.

[0127] Optionally, the ratio of the flow rate of the dilution gas to the flow rate of the silicon source gas is greater than or equal to 1.5. This ratio is between 1.5 and 4. For example, the ratio can be 1.5:1, 2:1, 3:1, or 4:1. By ensuring the ratio of the flow rate of the dilution gas to the flow rate of the silicon source gas is within the above range, better uniformity of the film thickness can be achieved. It should be noted that the flow rates of the dilution gas and the silicon source gas are related to the size of the reactor tube; however, this embodiment does not limit the flow rates of the dilution gas and the silicon source gas.

[0128] In one embodiment, the doping concentration of the doped layer 401 is greater than 1e21 atoms / cm². 3 For example, the doping concentration of the doped layer 401 is 1e21 atoms / cm². 3 2e21 atoms / cm 35e21 atoms / cm 3 or 1e22 atoms / cm 3 It is understandable that the higher the doping concentration of the doped layer 401, the more dopant atoms it can provide to the initial intrinsic material layer 310, thus the doping concentration of the doped layer 401 is positively correlated with the doping concentration of the doped passivation layer 320 formed after diffusion. With increasing doping concentration, the doped passivation layer 320 can form a stronger field effect, thereby enhancing its ability to block charge carriers (especially minority carriers) and reducing the surface recombination rate. Furthermore, a high doping concentration can form a lower barrier height at the interface, making it easier for electrons to pass through the interface between the metal electrode and the doped passivation layer 320, thereby helping to reduce the contact resistance between the metal electrode and the doped passivation layer 320. In the embodiments of the application, by providing a doped layer 401 with a higher doping concentration, the doping concentration of the finally formed doped passivation layer 320 can be effectively increased, thereby improving the conversion efficiency and performance of the solar cell.

[0129] In one embodiment, reference Figure 7 Heat treatment is also used to diffuse the dopant into the semiconductor substrate 100 to form an inner extension layer 500 in the semiconductor substrate 100. Figure 8 for Figure 7 One of the schematic diagrams of a solar cell with an inner extension layer 500 in the embodiment. Figure 9 for Figure 7 A second schematic diagram of a solar cell with an inner extension layer 500, as described in the embodiment. (Refer to reference...) Figure 8 and Figure 9 Dopant atoms can tunnel through the tunneling layer 200 and enter the semiconductor substrate 100 from the front or back side, thereby transforming the semiconductor substrate 100 of a certain thickness into an inner layer 500. The doping type of the inner layer 500 can be the same as or different from that of the semiconductor substrate 100. Specifically, the inner layer 500 can improve the carrier collection efficiency of the solar cell. Furthermore, the doping concentration of the inner layer 500 is greater than 1e21 atoms / cm³. 3 This allows for better carrier collection.

[0130] In one embodiment, the thickness of the inner expansion layer 500 is from 0.02 μm to 1 μm. Exemplarily, the thickness of the inner expansion layer 500 is 0.02 μm, 0.05 μm, 0.1 μm, 0.2 μm, 0.5 μm, or 1 μm. It is understood that a larger thickness of the inner expansion layer 500 means more dopants need to pass through the tunneling layer 200 to enter the semiconductor substrate 100, thus causing greater damage to the tunneling layer 200 and affecting the surface passivation effect of the passivation contact structure on the solar cell. Furthermore, an excessively thick inner expansion layer 500 can also generate carrier recombination centers, trapping electrons and holes and causing them to recombine and disappear, thereby reducing carrier lifetime and mobility, and thus affecting the electrical performance of the solar cell. Therefore, by reasonably controlling the thickness of the inner expansion layer 500, both the carrier collection effect and the surface passivation effect of the solar cell can be balanced.

[0131] In one embodiment, the heat treatment conditions include a heat treatment temperature greater than 800°C and a heat treatment time greater than 20 minutes. In the embodiments of the application, by keeping the heat treatment temperature and time within the above range, it is beneficial to achieve a higher concentration of effective doping of the initial intrinsic material layer 310, and also beneficial to the entry of dopant atoms into the substrate to form the inner extension layer 500.

[0132] Figure 10 This is the fourth flowchart of a method for fabricating a solar cell according to one embodiment. Figure 11 for Figure 10 A schematic diagram of the structure of the solar cell after step S330 in the embodiment. Figure 12 for Figure 10 A schematic diagram of the structure of the solar cell after step S430 in the embodiment, in conjunction with reference. Figures 10 to 12 In one embodiment, the method for fabricating a solar cell includes steps S100 to S430. Steps S100 and S200 are as described in the foregoing embodiments and will not be repeated here.

[0133] Step S100: Provide semiconductor substrate 100.

[0134] In step S200, a tunneling layer 200 is formed on the surface of the semiconductor substrate 100.

[0135] In step S330, an undoped initial intrinsic material layer 310 and a doped layer 401 containing dopant are sequentially formed on the surface of the tunneling layer 200, and a buffer layer 403 is formed in the initial intrinsic material layer 310.

[0136] The buffer layer 403 comprises an undoped silicon compound. The buffer layer 403 can be understood as dividing the initial intrinsic material layer 310 into two layers. Specifically, step S330 includes sequentially forming an undoped initial intrinsic material layer 310, a buffer layer 403, another initial intrinsic material layer 310, and a doped layer 401 containing a dopant on the surface of the tunneling layer 200. The buffer layer 403 can be made of the same material as the tunneling layer 200, such as an undoped silicon compound like silicon oxide. The thickness of the buffer layer 403 can be the same as or similar to the thickness of the tunneling layer 200, specifically from 0.5 nm to 2 nm. For example, the thickness of the buffer layer 403 is 0.5 nm, 1 nm, 1.5 nm, or 2 nm.

[0137] Step S430: Heat treatment is performed on the initial intrinsic material layer 310, the buffer layer 403 and the doped layer 401.

[0138] The heat treatment includes multiple stages, each with slightly different temperatures. After these stages, the dopant in the doped layer 401 diffuses into each of the initial intrinsic material layers 310, causing at least partial crystallization of the initial intrinsic material layer 310, thus transforming it into a doped passivation layer 320. Furthermore, both the doped layer 401 and the buffer layer 403 are transformed into barrier layers 402.

[0139] In the embodiments of the application, by setting a buffer layer 403 and performing multi-stage heat treatment, the dopant can sequentially enter an initial intrinsic material layer 310, the buffer layer 403, and another initial intrinsic material layer 310 along the direction close to the substrate during the diffusion process of the heat treatment. Therefore, the dopant will form a relatively uniform distribution in the buffer layer 403 before entering the initial intrinsic material layer 310 on the side of the buffer layer 403 close to the semiconductor substrate 100, thereby improving the uniformity of the dopant distribution in the doped passivation layer 320, that is, improving the doping uniformity of the finally formed doped passivation layer 320. Moreover, by making the distribution of the dopant more uniform, the situation where excessive dopant in a certain area leads to increased damage to the corresponding tunneling layer 200 during the heat treatment process can be reduced, thereby improving the performance of the tunneling layer 200, and thus improving the surface passivation effect of the passivation contact structure on the solar cell.

[0140] In one embodiment, the heat treatment includes a first processing stage and a second processing stage performed sequentially. In the first processing stage, the dopant reaches the vicinity of the buffer layer 403, with only a small amount or even no dopant entering the initial intrinsic material layer 310 of the buffer layer 403 near the semiconductor substrate 100, thereby homogenizing the dopant in the buffer layer 403. In the second processing stage, the homogenized dopant further enters the initial intrinsic material layer 310 of the buffer layer 403 near the semiconductor substrate 100, thereby achieving doping of the entire initial intrinsic material layer 310. The temperature of the second processing stage can be higher than the temperature of the first processing stage. For example, the temperature of the first processing stage is 800°C to 910°C, such as 800°C, 850°C, 900°C, or 910°C. The temperature of the second processing stage is 900°C to 1000°C, such as 900°C, 910°C, 950°C, or 1000°C. Specifically, by performing the first processing stage at a lower temperature and then increasing the temperature for the second processing stage, the doping rate and the efficiency of the preparation method can be further improved. Furthermore, by increasing the heat treatment temperature, the initial intrinsic material layer 310 can achieve a higher degree of crystallization, thereby further reducing the defect state density of the doped passivation layer 320. It is understood that an inner expansion layer 500 can be formed in the semiconductor substrate 100 during the second processing stage. It should be noted that the time of the two processing stages is temperature-dependent. As long as the dopant reaches the vicinity of the buffer layer 403 after the first processing stage and the doping of the entire initial intrinsic material layer 310 is completed after the second processing stage, it falls within the protection scope of this embodiment and is not limited here.

[0141] In one embodiment, the heat treatment includes a first processing stage and a second processing stage performed sequentially. In the first processing stage, the dopant reaches the vicinity of the buffer layer 403, with only a small amount or even no dopant entering the initial intrinsic material layer 310 of the buffer layer 403 near the semiconductor substrate 100, thereby homogenizing the dopant in the buffer layer 403. In the second processing stage, the homogenized dopant further enters the initial intrinsic material layer 310 of the buffer layer 403 near the semiconductor substrate 100, thereby achieving doping of the entire initial intrinsic material layer 310. The temperature of the second processing stage is lower than the temperature of the first processing stage. For example, the temperature of the first processing stage is 900°C to 1000°C, such as 900°C, 910°C, 950°C, or 1000°C. The temperature of the second processing stage is 800°C to 910°C, such as 800°C, 850°C, 900°C, or 910°C. Specifically, the first processing stage is performed at a higher temperature, which enables the initial intrinsic material layer 310 to achieve a higher degree of crystallization, thereby reducing the defect state density of the doped passivation layer 320 and increasing the effective doping concentration. The second processing stage is then performed at a lower temperature, allowing for more precise control of the diffusion depth through a low-temperature approach. This ensures that the required thickness of the inner expansion layer 500 is achieved when forming the inner expansion layer 500 in the semiconductor substrate 100, while minimizing damage to the tunneling layer 200. Furthermore, since the temperature of the second processing stage is higher than that of the first processing stage, this embodiment appropriately increases the thickness of the buffer layer 403. This reduces the amount of dopant penetrating the buffer layer 403 during the high-temperature first processing stage, thereby achieving better dopant homogenization in the buffer layer 403 during the first processing stage.

[0142] In one embodiment, the heat treatment includes a first processing stage, a second processing stage, and a third processing stage performed sequentially. The temperature of the second processing stage is higher than the temperature of the first processing stage, and also higher than the temperature of the third processing stage. Specifically, by setting more processing stages, multiple key indicators such as doping uniformity, doping depth, and crystallinity can be better balanced, thereby improving the performance of the solar cell. It is understood that in some embodiments, the heat treatment may also include more processing stages, which is not limited here. In addition, in some embodiments, in the absence of a buffer layer, staged heat treatment can also be used to improve the aforementioned key indicators of the solar cell. The specific temperature settings for different stages can be referred to the foregoing embodiments, and will not be repeated here.

[0143] In one embodiment, when there are multiple initial intrinsic material layers 310, a buffer layer 403 is formed in the initial intrinsic material layers 310, including forming the buffer layer 403 in the initial intrinsic material layer 310 closest to the semiconductor substrate 100. Specifically, the closer to the semiconductor substrate 100, the more pronounced the doping non-uniformity becomes. Therefore, forming a buffer layer 403 in the initial intrinsic material layer 310 closest to the semiconductor substrate 100 can improve the doping uniformity of the doped passivation layer 320 near the semiconductor substrate 100 and reduce the damage to the corresponding region in the tunneling layer 200 caused by non-uniformly distributed dopants.

[0144] Figure 13 This is the fifth flowchart of a method for fabricating a solar cell according to one embodiment. Figure 14 for Figure 13 One of the schematic diagrams of the structure of the solar cell after step S600 in the embodiment, in conjunction with reference. Figure 13 and Figure 14 In one embodiment, the method for fabricating a solar cell includes steps S100 to S600. Steps S100 to S410 are as described in the foregoing embodiments and will not be repeated here. It should be noted that this description only uses a single layer as an example, where the initial intrinsic material layer 310 and the doped layer 401 are single layers. In some embodiments, the initial intrinsic material layer 310 and the doped layer 401 can be multiple layers, and a buffer layer 403 can be formed in the initial intrinsic material layer 310.

[0145] S100 provides a semiconductor substrate 100;

[0146] S200, a tunneling layer 200 is formed on the surface of the semiconductor substrate 100;

[0147] S300, an undoped initial intrinsic material layer 310 and a doped layer 401 containing dopant are sequentially formed on the surface of the tunneling layer 200.

[0148] S401, heat treatment is performed on the initial intrinsic material layer 310 and the doped layer 401 to diffuse the dopant in the doped layer 401 to the initial intrinsic material layer 310, so as to transform the initial intrinsic material layer 310 into a doped passivation layer 320.

[0149] S500, a dielectric layer 600 is formed on the side of the doped passivation layer 320 away from the semiconductor substrate 100.

[0150] The dielectric layer 600 can be made of a dielectric material, including at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, or titanium oxide. It is understood that the dielectric layer 600 can be fabricated using processes such as ALD, PECVD, and PEALD; no limitation is made here. Furthermore, before forming the dielectric layer 600, the top barrier layer 402 can be removed to form... Figure 14 The structure shown.

[0151] S600: Form the first electrode 700.

[0152] One end of the first electrode 700 penetrates the dielectric layer 600 and is electrically connected to the doped passivation layer 320, while the other end of the first electrode 700 extends away from the semiconductor substrate 100. Exemplarily, the first electrode 700 can be formed by screen printing and sintering, or by laser delamination and electroplating; no limitation is made here.

[0153] In one embodiment, if the method for fabricating a solar cell further includes the step of alternately forming a plurality of undoped initial intrinsic material layers 310 and a plurality of doped layers 401 containing dopants on the surface of the tunneling layer 200, or includes the step of forming a buffer layer 403 in the initial intrinsic material layer 310, then the solar cell may include a plurality of doped passivation layers 320 and a plurality of barrier layers 402. For example, Figure 15 This is a second schematic diagram of the structure of the solar cell after step S600 in one embodiment, referencing... Figure 15 The solar cell includes three doped passivation layers 320 and two barrier layers 402. Both barrier layers 402 can be formed by converting doped layers 401, or the barrier layer 402 furthest from the semiconductor substrate 100 can be formed by converting doped layer 401, while the barrier layer 402 closest to the semiconductor substrate 100 can be formed by converting buffer layer 403; this is not limited here. When there are multiple doped passivation layers 320, one end of the first electrode 700 is electrically connected to any one of the doped passivation layers 320 and penetrates the dielectric layer 600 located on the side of the doped passivation layer 320 electrically connected to the first electrode 700 furthest from the semiconductor substrate 100.

[0154] Figure 16 This is the third schematic diagram of the structure of the solar cell after step S600 in one embodiment. Figure 17 This is the fourth schematic diagram of the structure of the solar cell after step S600 in one embodiment, in conjunction with reference to [reference needed]. Figure 16 and Figure 17 The solar cell includes three doped passivation layers 320 and three barrier layers 402. The formation method of the multiple barrier layers 402 is similar to... Figure 15Similarly, as will not be repeated here, except that the barrier layer 402 formed by the transformation of the first doped layer 410 was not removed after heat treatment. Furthermore, the first electrode 700 can also be as follows... Figure 16 As shown, it further penetrates at least one barrier layer 402, or as Figure 17 The electrode further penetrates at least one barrier layer 402 and at least one doped passivation layer 320. Specifically, the closer the end of the first electrode 700 is to the semiconductor substrate 100, the shorter the carrier transport path, resulting in better carrier transport performance. However, it is understood that a closer distance between the end of the first electrode 700 and the semiconductor substrate 100 also means a higher risk of burn-through to the semiconductor substrate 100 during metallization ablation. In the embodiments of the application, by providing multiple doped layers 401, protection can be provided during the metallization ablation stage, thereby reducing the risk of burn-through to the semiconductor substrate 100. Furthermore, the end depth of the first electrode 700 can be flexibly set as needed, expanding the process window and reducing the process difficulty of the metallization ablation stage.

[0155] In one embodiment, the solar cell is a back contact (BC) cell, in which passivation contact structures with different doping types are provided in different regions on the same side of the semiconductor substrate 100. Accordingly, doped layers 401 containing different types of dopants can be prepared in different regions of the solar cell, and after depositing all the initial intrinsic material layers 310 and doped layers 401, different types of doping are performed on the initial intrinsic material layers 310 in different regions through the same heat treatment step to form the desired solar cell.

[0156] It should be understood that although the steps in each flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in each flowchart may include multiple steps or stages, which are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0157] This application also provides a solar cell, which is prepared using the solar cell preparation method described above.

[0158] Continue to refer to Figure 14This application also provides a solar cell, including a semiconductor substrate 100, a tunneling layer 200, a doped passivation layer 320, a dielectric layer 600, and a first electrode 700. The tunneling layer 200 is located on the surface of the semiconductor substrate 100. The doped passivation layer 320 is stacked on the side of the tunneling layer 200 away from the semiconductor substrate 100. The dielectric layer 600 is disposed on the side of the doped passivation layer 320 away from the tunneling layer 200. One end of the first electrode 700 is electrically connected to the doped passivation layer 320 and penetrates the dielectric layer 600, while the other end of the first electrode 700 extends in a direction away from the semiconductor substrate 100. Further, the first electrode 700 can extend further into the interior of the doped passivation layer 320. It is understood that by having one end of the first electrode 700 penetrate the dielectric layer 600 and extend into the interior of the passivation contact structure, the connection area between the first electrode 700 and the passivation contact structure can be larger, resulting in a better electrical connection. Furthermore, the solar cell also includes an emitter, an antireflection layer, and a second electrode. The emitter and the antireflection layer are stacked sequentially on the front side of the semiconductor substrate 100. A highly doped region is provided on the emitter, and the second electrode is electrically connected to the highly doped region.

[0159] Continue to refer to Figure 15 In one embodiment, the number of doped passivation layers 320 is multiple, and the solar cell further includes at least one barrier layer 402 located on the side of any doped passivation layer 320 away from the semiconductor substrate 100. One end of the first electrode 700 extends to a target doped passivation layer 320 among the multiple doped passivation layers 320 and penetrates each film layer of the target doped passivation layer 320 on the side away from the semiconductor substrate 100. The film layer penetrated by the first electrode 700 includes a dielectric layer 600.

[0160] In one embodiment, the film through which the first electrode 700 penetrates further includes at least one doped passivation layer 320 and / or at least one barrier layer 402.

[0161] In one embodiment, the thickness of the barrier layer 402 is 0.5 nm to 10 nm.

[0162] In one embodiment, the thickness of the barrier layer 402 is greater than or equal to the thickness of the tunneling layer 200.

[0163] In one embodiment, the thickness of the tunneling layer 200 is 0.5 nm to 2 nm.

[0164] In one embodiment, the thickness of the doped passivation layer 320 is 2 nm to 50 nm.

[0165] This application also provides a photovoltaic module, including a battery string, which is formed by connecting multiple solar cells as described above.

[0166] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0167] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0168] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for preparing a solar cell, characterized in that, include: Provide semiconductor substrates; A tunneling layer is formed on the surface of the semiconductor substrate; An undoped initial intrinsic material layer and a doped layer containing a dopant are sequentially formed on the surface of the tunneling layer; the dopant includes either an N-type dopant or a P-type dopant. The initial intrinsic material layer and the doped layer are subjected to heat treatment to diffuse the dopant in the doped layer into the initial intrinsic material layer and to at least partially crystallize the initial intrinsic material layer, thereby transforming the initial intrinsic material layer into a doped passivation layer.

2. The preparation method according to claim 1, characterized in that, The process of sequentially forming an undoped initial intrinsic material layer and a doped layer containing dopant on the surface of the tunneling layer includes: Multiple undoped initial intrinsic material layers and multiple doped layers containing dopants are alternately formed on the surface of the tunneling layer.

3. The preparation method according to claim 2, characterized in that, The thickness of the first doped layer is 5 nm to 30 nm; and / or The thickness of the second doped layer is 1 nm to 10 nm; Wherein, the first doped layer is the one furthest from the semiconductor substrate among the plurality of doped layers; the second doped layer is any of the other doped layers besides the first doped layer.

4. The preparation method according to claim 3, characterized in that, When the thickness of the first doped layer is less than 10 nm, the preparation method further includes: A mask layer is formed on the surface of the first doped layer; the sum of the thicknesses of the mask layer and the first doped layer is greater than 20 nm.

5. The preparation method according to claim 4, characterized in that, The mask layer is made of undoped silicon compound.

6. The preparation method according to claim 2, characterized in that, The doping concentration of the second doped layer is greater than that of the first doped layer; Wherein, the first doped layer is the one furthest from the semiconductor substrate among the plurality of doped layers, and the second doped layer is any of the other doped layers besides the first doped layer.

7. The preparation method according to claim 2, characterized in that, The preparation method further includes: After heat treatment of the initial intrinsic material layer and the doped layer, the barrier layer formed by the transformation of the first doped layer during the heat treatment process is removed. The first doped layer is the one furthest from the semiconductor substrate among the plurality of doped layers.

8. The preparation method according to claim 2, characterized in that, The thickness of the first doped layer is greater than the thickness of the tunneling layer, and the thickness of the second doped layer is greater than or equal to the thickness of the tunneling layer; Wherein, the first doped layer is the one furthest from the semiconductor substrate among the plurality of doped layers, and the second doped layer is any of the other doped layers besides the first doped layer.

9. The preparation method according to claim 2, characterized in that, Both the doped layer and the tunneling layer are made of silicon oxide compounds, and the silicon-to-oxygen ratio of the second doped layer is greater than or equal to the silicon-to-oxygen ratio of the first doped layer and the tunneling layer. Wherein, the first doped layer is the one furthest from the semiconductor substrate among the plurality of doped layers, and the second doped layer is any of the other doped layers besides the first doped layer.

10. The preparation method according to claim 9, characterized in that, The silicon-to-oxygen ratio of the second doped layer is greater than 1:2, and the silicon-to-oxygen ratio of the tunneling layer is less than 1:1.

5.

11. The preparation method according to any one of claims 1 to 10, characterized in that, The thickness of the tunneling layer is 0.5 nm to 2 nm.

12. The preparation method according to any one of claims 1 to 10, characterized in that, The process of sequentially forming an undoped initial intrinsic material layer and a doped layer containing dopant on the surface of the tunneling layer includes: In the same plasma-enhanced chemical vapor deposition apparatus, the initial intrinsic material layer and the doped layer are formed on the surface of the tunneling layer.

13. The preparation method according to any one of claims 1 to 10, characterized in that, The doping concentration of the doped layer is greater than 1e21 atoms / cm². 3 .

14. The preparation method according to any one of claims 1 to 10, characterized in that, The heat treatment is also used to diffuse the dopant into the semiconductor substrate to form an inner extension layer in the semiconductor substrate.

15. The preparation method according to claim 14, characterized in that, The heat treatment conditions include a heat treatment temperature greater than 800°C and a heat treatment time greater than 20 minutes.

16. The preparation method according to claim 14, characterized in that, The thickness of the inner expansion layer is 0.02 μm to 1 μm.

17. The preparation method according to any one of claims 1 to 10, characterized in that, The material of the initial intrinsic material layer includes any one of intrinsic amorphous silicon, intrinsic microcrystalline silicon, and intrinsic polycrystalline silicon.

18. The preparation method according to any one of claims 1 to 10, characterized in that, The preparation method further includes: A buffer layer is formed in the initial intrinsic material layer; the buffer layer comprises an undoped silicon compound; The heat treatment of the initial intrinsic material layer and the doped layer includes: The initial intrinsic material layer, the buffer layer, and the doped layer are subjected to heat treatment; the heat treatment includes multiple processing stages, and the temperatures of the multiple processing stages are not exactly the same.

19. The preparation method according to claim 18, characterized in that, The heat treatment includes a first treatment stage and a second treatment stage performed sequentially, wherein the temperature of the second treatment stage is greater than the temperature of the first treatment stage or the temperature of the second treatment stage is less than the temperature of the first treatment stage.

20. The preparation method according to claim 18, characterized in that, One of the first processing stage and the second processing stage uses 800°C to 910°C, and the other of the first processing stage and the second processing stage uses 900°C to 1000°C.

21. The preparation method according to claim 18, characterized in that, The heat treatment includes a first treatment stage, a second treatment stage, and a third treatment stage performed sequentially. The temperature of the second treatment stage is higher than the temperature of the first treatment stage and also higher than the temperature of the third treatment stage.

22. The preparation method according to claim 18, characterized in that, When there are multiple initial intrinsic material layers, forming a buffer layer in the initial intrinsic material layers includes: A buffer layer is formed in one of the initial intrinsic material layers closest to the semiconductor substrate.

23. The preparation method according to claim 18, characterized in that, The thickness of the buffer layer is 0.5 nm to 2 nm.

24. The preparation method according to claim 18, characterized in that, The buffer layer is made of silicon oxide compounds.

25. The preparation method according to any one of claims 1 to 10, characterized in that, The preparation method further includes: A dielectric layer is formed on the side of the doped passivation layer away from the semiconductor substrate; A first electrode is formed on the side of the doped passivation layer away from the semiconductor substrate; one end of the first electrode penetrates the dielectric layer and is electrically connected to the doped passivation layer, and the other end of the first electrode extends in a direction away from the semiconductor substrate.

26. The preparation method according to claim 25, characterized in that, When there are multiple doped passivation layers, one end of the first electrode extends to the target doped passivation layer among the multiple doped passivation layers and penetrates each film layer of the target doped passivation layer on the side away from the semiconductor substrate.

27. A solar cell, characterized in that, The solar cell is prepared using the method described in claims 1 to 26.

28. A solar cell, characterized in that, include: Semiconductor substrate; A tunneling layer is located on the surface of the semiconductor substrate; A doped passivation layer is stacked on the side of the tunneling layer away from the semiconductor substrate; A dielectric layer is disposed on the side of the doped passivation layer away from the tunneling layer; A first electrode, one end of which is electrically connected to the doped passivation layer and penetrates the dielectric layer, and the other end of which extends away from the semiconductor substrate.

29. The solar cell according to claim 28, characterized in that, The number of doped passivation layers is multiple, and the solar cell further includes at least one barrier layer located on the side of any of the doped passivation layers away from the semiconductor substrate; One end of the first electrode extends to a target doped passivation layer among the plurality of doped passivation layers and penetrates each film layer of the target doped passivation layer on the side away from the semiconductor substrate, wherein the film layer penetrated by the first electrode includes the dielectric layer.

30. The solar cell according to claim 29, characterized in that, The film layer through which the first electrode penetrates also includes at least one of the doped passivation layers and / or at least one of the barrier layers.

31. The solar cell according to claim 29, characterized in that, The thickness of the barrier layer is from 0.5 nm to 10 nm.

32. The solar cell according to claim 29, characterized in that, The thickness of the barrier layer is greater than or equal to the thickness of the tunneling layer.

33. The solar cell according to claim 28, characterized in that, The thickness of the tunneling layer is 0.5 nm to 2 nm.

34. The solar cell according to any one of claims 28 to 33, characterized in that, The thickness of the single-layer doped passivation layer is 2 nm to 150 nm.

35. A photovoltaic module, characterized in that, It includes a battery string, which is formed by connecting multiple solar cells as described in any one of claims 25 to 34.

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