Power conversion device

Abstract

This power conversion device is provided with: a semiconductor package having a built-in semiconductor element and having a connection terminal protruding to the outside; and a wiring substrate on which the semiconductor package is mounted, in which the terminal has a bent portion bent in a plane parallel to the wiring substrate and a terminal connection portion provided closer to the tip side than the bent portion. The wiring substrate has a first wiring portion and another second wiring portion which are provided on the surface of the substrate and which are joined to the terminal, the first wiring portion extending from a connection region to which the terminal is connected in the direction of the semiconductor package in which the terminal faces the first wiring portion, and the second wiring portion being connected to an end portion on the extension side.

Description

Technical Field

[0001] This invention relates to a power conversion device. Background Technology

[0002] Traditionally, in power conversion devices such as inverters, semiconductor packages constituting the inverter circuit are mounted on a wiring board. In such power conversion devices, in order to improve reliability (e.g., cycle life), it is necessary to alleviate the stress at the solder joints between the terminals of the semiconductor package and the wiring board.

[0003] For example, Patent Document 1 discloses a terminal structure in which a bend is provided on the terminal to alleviate stress at the solder joint. By providing the bend, stress at the solder joint can be alleviated.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent No. 4476465 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] However, if the terminals are made into a bent structure, the terminals become longer, which leads to an increase in inductance in the terminal portion. This increase in inductance needs to be avoided in main terminals carrying large currents, making it difficult to apply a bent structure to the main terminals.

[0009] Methods for solving problems

[0010] The power conversion device of the present invention includes: a semiconductor package having a built-in semiconductor element and having an outwardly protruding terminal for connection; and a wiring substrate on which the semiconductor package is mounted, wherein the terminal has a bent portion that bends in a plane parallel to the wiring substrate and a terminal connection portion disposed on the top side relative to the bent portion, the wiring substrate having a first wiring portion disposed on the substrate surface and engaging the terminal and a second wiring portion, the first wiring portion extending from a connection area connecting the terminal along the direction opposite to the terminal toward the semiconductor package, and the second wiring portion being connected at the end of the extension side.

[0011] The effects of the invention

[0012] According to the present invention, stress relief and inductance reduction can be achieved simultaneously. Attached Figure Description

[0013] Figure 1 It is a diagram showing the general structure of a power conversion device.

[0014] Figure 2 This is a diagram showing the configuration of an inverter circuit.

[0015] Figure 3 This is a diagram showing a semiconductor package mounted on a wiring substrate.

[0016] Figure 4 yes Figure 3 AA sectional view.

[0017] Figure 5 This is a diagram illustrating an example of the configuration of semiconductor packages on the upper and lower arms of a wiring substrate.

[0018] Figure 6 It means Figure 4 The diagram shows a modified example of the configuration.

[0019] Figure 7 This is a diagram showing the configuration of the inverter circuit in the second embodiment.

[0020] Figure 8 This is a schematic diagram showing the component configuration of a U-phase inverter circuit on a wiring board.

[0021] Figure 9 yes Figure 8 BB cross-section.

[0022] Figure 10 This is a diagram representing a comparative example. Detailed Implementation

[0023] Hereinafter, embodiments for carrying out the present invention will be described with reference to the accompanying drawings. The following description and drawings are examples for illustrating the present invention; appropriate omissions and simplifications have been made for clarity of explanation. Furthermore, in the following description, the same or similar elements and processes are given the same reference numerals, and repeated descriptions are sometimes omitted. Additionally, the following description represents only one example of an embodiment of the present invention; the present invention is not limited to the described embodiments and can be implemented in various other ways.

[0024] (First Implementation)

[0025] Figure 1This diagram shows a schematic configuration of the power conversion device 1. The power conversion device 1 converts DC power supplied from a DC voltage source 2, such as a battery, into AC power to drive a motor 3. Furthermore, during braking of the motor 3, regenerative control is performed on the power conversion device 1 to convert AC power back to DC power. The power conversion device 1 includes an inverter circuit 10, a gate drive circuit 11, and a control circuit 12. The inverter circuit 10 includes multiple semiconductor elements that perform switching operations. The inverter circuit 10 is connected to the DC voltage source 2 via a positive terminal wiring 103p and a negative terminal wiring 103n. The control circuit 12 is configured as a microcomputer or CPU, etc.

[0026] Figure 2 This diagram illustrates the configuration of inverter circuit 10. In inverter circuit 10, each of the U-phase, V-phase, and W-phase has a pair of semiconductor elements 100a and 100b forming the upper and lower arms, respectively. Semiconductor elements 100a and 100b utilize IGBTs (Insulated Gate Bipolar Transistors) or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), etc. Semiconductor elements 100a and 100b have three terminals: a high-voltage side terminal for the main circuit (collector terminal for IGBTs, drain terminal for MOSFETs), a low-voltage side terminal for the main circuit (emitter terminal for IGBTs, source terminal for MOSFETs), and a signal terminal (gate terminal, etc.).

[0027] The semiconductor elements 100a and 100b of the upper and lower arms of the U-phase, V-phase, and W-phase are connected in parallel between the positive wiring 103p and the negative wiring 103n, which are connected to the DC voltage source 2. The capacitor 102 disposed between the positive wiring 103p and the negative wiring 103n is a smoothing capacitor used to smooth the current generated by the switching on / off of the semiconductor elements 100a and 100b.

[0028] The low-voltage side terminals of the main circuit of semiconductor element 100a on the upper arm of phase U and the high-voltage side terminals of the main circuit of semiconductor element 100b on the lower arm are connected to the U-phase output wiring 104U. The low-voltage side terminals of the main circuit of semiconductor element 100a on the upper arm of phase V and the high-voltage side terminals of the main circuit of semiconductor element 100b on the lower arm are connected to the V-phase output wiring 104V. The low-voltage side terminals of the main circuit of semiconductor element 100a on the upper arm of phase W and the high-voltage side terminals of the main circuit of semiconductor element 100b on the lower arm are connected to the W-phase output wiring 104W. The output wirings 104U, 104V, and 104W of each phase are connected to motor 3. The signal terminals of each semiconductor element 100a and 100b are connected to... Figure 1The gate drive circuit 11 is connected to turn on or off semiconductor elements 100a and 100b based on the signal input from the control circuit 12.

[0029] Figure 3 This is a diagram showing a semiconductor package 30 mounted on a wiring substrate 20. Additionally, Figure 4 It is a schematic representation Figure 3 A cross-sectional view of section AA. Semiconductor elements 100a and 100b are respectively embedded in semiconductor packages 30 made of insulating material. Figure 3 The semiconductor package 30 shown contains the aforementioned semiconductor element 100a or semiconductor element 100b. Multiple terminals 301, 302, and 303 protrude parallel to the substrate surface of the wiring substrate 20 from the semiconductor package 30.

[0030] Terminal 301 is the high-voltage side terminal of the main circuit described above. Terminal 302 is the low-voltage side terminal of the main circuit described above. Terminal 303 is the signal terminal described above. Bends 310 are formed on terminals 301, 302, and 303 respectively. Additionally, as... Figure 4 As shown, a terminal connection portion 311 is provided on the top of each terminal 301 to 303. The terminal connection portion 311 is bonded to the wiring portions 201 to 203 of the wiring board 20 by a bonding material 50 such as solder.

[0031] A wiring portion 201, disposed on the substrate surface of the wiring substrate 20, extends along the protruding direction of the terminal 301 and is configured to face the terminal 301. A terminal connection portion 311 of the terminal 301 is soldered to one end of the wiring portion 201 (shown on the right side of the diagram). The other end 201b of the wiring portion 201 is connected to other wiring portions (not shown). For example, a wiring portion 201 is built into a semiconductor package 30. Figure 2 In the case of the semiconductor element 100a shown, the wiring portion 201 is connected to the positive electrode wiring 103p. Additionally, in the case where the semiconductor element 100a has a lower arm of the U-phase built into the semiconductor package 30, the wiring portion 201 is connected to the U-phase output wiring 104U. Similarly, wiring portions 202 and 203 extend along the protruding direction of terminals 302 and 303, respectively, and are arranged opposite to terminals 302 and 303. Terminal connection portions 311 of terminals 302 and 303 are soldered to one end of the wiring portions 202 and 203.

[0032] like Figure 3 , 4 As shown, in this embodiment, a bent portion 310 is provided on terminals 301 to 303. Therefore, by slightly deforming the bent portion 310, the stress applied to the terminal connection portion 311 is relieved, and stress relief at the solder joint can be achieved.

[0033] Figure 3 ,4 The dashed arrow L1 schematically represents the flow of current from wiring portion 201 into semiconductor package 30 through terminal 302. Similarly, dashed arrow L2 represents the flow of current from semiconductor package 30 into wiring portion 202 through terminal 302. As shown by dashed arrows L1 and L2, the direction of the current flowing through terminals 301 and 302 is opposite to the direction of the current flowing through the opposing wiring portions 201 and 202. Therefore, the magnetic flux generated by the current cancels each other out, thereby reducing the inductance of the terminal portion. That is, in this embodiment, stress relief and inductance reduction of terminal connection portion 311 can be achieved simultaneously. In addition, the relationship between terminal 303, which is a signal terminal, and wiring portion 203 is preferably configured in the same way as that of terminals 301 and 302.

[0034] Figure 10 This is a diagram representing comparative examples. In Figure 10 In the wiring sections 221-223 shown, the ends 201a, 202a, and 203a of the terminal connection portions 311 of terminals 301-303 that are soldered together form a configuration that connects to other wiring sections. Therefore, the current flowing into the semiconductor package 30 via terminal 301 flows as shown by the dashed line L11. On the other hand, the current flowing out of the semiconductor package 30 via terminal 302 flows as shown by the dashed line L12. Therefore, with... Figure 3 , 4 Unlike other cases, the current flowing through wiring sections 221 and 222 is neither opposite nor opposite to the current flowing through terminals 301 and 302. As a result, in the comparative example, the inductance reduction effect caused by the current flowing through the wiring section cannot be expected. Therefore, a current is formed on terminals 301 to 303... Figure 3 , 4 In the case of the bent portion 310 shown, although it is possible to alleviate the stress at the solder joint, it has the disadvantage of increasing the inductance.

[0035] However, as Figure 3 As shown, the bent portions 310 of terminals 301 and 302, protruding from the same side of the semiconductor package 30, are bent in a direction approaching each other. That is, the bent portion 310 of terminal 301 bends towards terminal 302 (downward direction in the illustration), and the bent portion 310 of terminal 302 bends towards terminal 301 (upward direction in the illustration). In this way, by bending adjacent bent portions 310 in a direction approaching each other, inductance can be further reduced. Furthermore, by aligning the left-right positions of the opposing bent portions 310 in the illustration, the inductance reduction effect can be further improved. Additionally, as... Figure 3 As shown, for the pair of terminals 303 protruding to the left side of the semiconductor package 30, it is also preferable that their configuration with respect to the bend 310 be the same as that of terminals 301 and 302.

[0036] Furthermore, comparing the terminals 301 and 303 on the upper side of the illustration with the terminals 302 and 303 on the lower side, the shape and arrangement of the terminals form a structure that is linearly symmetrical about the line L10 passing through the upper and lower centers of the semiconductor package 30. In this way, by making the shape and arrangement of the terminals linearly symmetrical, displacement of the semiconductor package 30 in the planar direction can be suppressed when the terminals 301 to 303 elongate or contract due to temperature changes. For example, when a cooler is provided on the upper surface of the semiconductor package 30 through an insulating member, the stress applied to the insulating member is mitigated, and reliability related to cooling can be improved.

[0037] Figure 5 This diagram shows an example of the arrangement of semiconductor packages 30a and 30b on the upper and lower arms of the wiring substrate 20. Figure 5 In the example shown, a semiconductor package 30a has a built-in Figure 2 The upper arm semiconductor element 100a of the U-phase shown has a lower arm semiconductor element 100b housed within a semiconductor package 30b. The terminals 301-303 of the semiconductor package 30a and the wiring portions 201-203 connected to the terminals 301-303 are... Figure 3 , 4 The same structure is shown.

[0038] In the semiconductor package 30b containing the semiconductor element 100b with a built-in lower arm, terminals 301 and 302, serving as main circuit terminals, are located on the left side of the package illustration, while terminal 303, serving as a signal terminal, is located on the right side. Furthermore, terminal 301, serving as the high-voltage side terminal of the main circuit, is located on the lower side of the illustration, and terminal 302, serving as the low-voltage side terminal of the main circuit, is located on the upper side. Terminal 301 of the semiconductor package 30b is coupled to wiring portion 202, and terminal 302 is coupled to wiring portion 204. Wiring portion 202 and... Figure 2 The U-phase output wiring 104U shown is connected. On the other hand, the wiring section 204 is connected to the negative wiring 103n.

[0039] exist Figure 5 In the case shown, by providing bending portions 310 on terminals 301-302, stress relief of the terminal connection portion 311 can also be achieved. Furthermore, since the bending portions 310 of the vertically adjacent terminals shown bend in a direction approaching each other, [the stress relief is achieved]. Figure 3 , 4 The same situation applies, which can improve the inductance reduction effect. Additionally, in Figure 5In the case shown, the shape and arrangement of the terminals of the semiconductor packages 30a and 30b arranged side by side are also a line-symmetric structure about line L10a. Therefore, when the terminals elongate or contract due to temperature changes, displacement of the semiconductor packages 30a and 30b in the planar direction can be suppressed.

[0040] (Modified example)

[0041] Figure 6 It means Figure 4 The diagram shows a modified example of the configuration. In Figure 4 In the configuration shown, the semiconductor package 30 is disposed on the surface side of the wiring substrate 20. On the other hand, in Figure 6 In the modified example shown, a through-hole 210 is formed on the wiring substrate 20, and the semiconductor package 30 is inserted into the through-hole 210, configured such that its back side protrudes towards the back side of the wiring substrate 20. Therefore, the gap dimension G between the terminals 301-303 and the wiring portions 201-203 can be made more than... Figure 4 The structure shown is small, which can further improve the inductance reduction effect.

[0042] In this way, in the structure where the semiconductor package 30 is inserted into the through hole 210, the gap size G can be reduced regardless of the thickness of the semiconductor package 30. Furthermore, when the semiconductor package 30 has heat dissipation surfaces 320 and 321 on both its inner and outer surfaces, by configuring the semiconductor package 30 to be inserted into the through hole 210, coolers 40 can be disposed on the heat dissipation surfaces 320 and 321 respectively. That is, the semiconductor package 30 can be cooled from both the top and bottom surfaces, thereby improving cooling performance. Figure 6 The cooler 40 shown uses a heat sink with multiple fins 400, but a cooler using refrigerant can also be used. An electrically insulating heat-conducting member 60 is provided between the cooler 40 and the semiconductor package 30.

[0043] (Second Implementation)

[0044] In the first embodiment described above, such as Figure 2 As shown, the upper and lower arms of each phase are composed of a pair of semiconductor elements 100a and 100b. On the other hand, in the second embodiment, as... Figure 7 As shown, the case where the upper and lower arms of each phase are composed of multiple pairs of semiconductor elements 100a and 100b will be explained. Figure 7 It means Figure 1 The diagram shows the configuration of inverter circuit 10. Inverter circuit 10 consists of U-phase inverter circuit 10U, V-phase inverter circuit 10V, and W-phase inverter circuit 10W.

[0045] The U-phase inverter circuit 10U, the V-phase inverter circuit 10V, and the W-phase inverter circuit 10W are each composed of multiple sets of upper and lower arm semiconductor elements. Figure 7 In the example shown, four semiconductor elements 100a and 100b, connected in series in the upper and lower arms, are connected in parallel to increase the output current of the power conversion device 1. The U-phase, V-phase, and W-phase inverter circuits 10U, 10V, and 10W are respectively paired with the series-connected semiconductor elements 100a and 100b in the upper and lower arms, and the capacitor 101. The positive terminal of the capacitor 101 is connected to the high-voltage side terminal of the main circuit of the semiconductor element 100a in the upper arm via positive wiring 103p. The negative terminal of the capacitor 101 is connected to the low-voltage side terminal of the main circuit of the semiconductor element 100b in the lower arm via negative wiring 103n.

[0046] The low-voltage side terminal of the main circuit of semiconductor element 100a in the upper arm of the U-phase inverter circuit 10U is connected to the high-voltage side terminal of the main circuit of semiconductor element 100b in the lower arm via U-phase output wiring 104U. The low-voltage side terminal of the main circuit of semiconductor element 100a in the upper arm of the V-phase inverter circuit 10V is connected to the high-voltage side terminal of the main circuit of semiconductor element 100b in the lower arm via V-phase output wiring 104V. The low-voltage side terminal of the main circuit of semiconductor element 100a in the upper arm of the W-phase inverter circuit 10W is connected to the high-voltage side terminal of the main circuit of semiconductor element 100b in the lower arm via W-phase output wiring 104W. The output wirings 104U, 104V, and 104W of each phase are connected to motor 3 (see reference). Figure 1 )connect.

[0047] The U-phase, V-phase, and W-phase inverter circuits 10U, 10V, and 10W are connected in parallel with capacitor 102. Capacitor 101 is a small ceramic capacitor, and capacitor 102 is a film capacitor with large capacitance. By placing capacitors 101 and 102 near semiconductor elements 100a and 100b, the wiring inductance of the positive wiring 103p and the negative wiring 103n can be reduced.

[0048] Figure 8 This diagram shows a portion of the inverter circuit 10, and schematically illustrates the component arrangement of the U-phase inverter circuit 10U on the wiring board 20. Additionally, Figure 9 It is a schematic representation Figure 8 A cross-sectional view of BB. Figure 8 The arrangement of semiconductor packages 30a and 30b in the diagram is equivalent to arranging 4 sets in the vertical direction as shown. Figure 5 The pair of semiconductor packages 30a and 30b are shown. However, in Figure 5In this process, the wiring portion 202 connected to the terminal 302 of the semiconductor package 30a and the wiring portion 202 connected to the terminal 301 of the semiconductor package 30b are separated, but... Figure 8 In the middle, the shared wiring sections 202A and 202B are designated.

[0049] In addition, Figure 8 Only the area containing components related to the U phase is shown in the illustration; the areas containing components for the V and W phases are omitted. The V and W phase components are located in... Figure 8 The right-hand side region of the wiring substrate 20 (not shown).

[0050] Wiring substrate 20 uses a multilayer substrate, such as Figure 9 As shown, wiring layers (conductor layers) 20a1 to 20a4 and insulating layers 20b are stacked alternately. Figure 8 The wiring portions 200p, 200n, 201, 201A, 202A, 202B, 203A, and 204A shown are formed on the wiring layer 20a1 on the surface side of the wiring substrate 20.

[0051] The wiring section 200p is equivalent to Figure 7 The positive electrode wiring 103p is a wiring section. Wiring sections 200p and 201, 201A are interconnected via interlayer connection sections 20c formed in the substrate thickness direction and at least one of the other wiring layers 20a2 to 20a4. Wiring section 200n is equivalent to Figure 7 The wiring section 103n is a negative terminal wiring section. The wiring section 200n and the wiring section 204A are interconnected via the interlayer connection section 20c and at least one of the other wiring layers 20a2 to 20a4.

[0052] Cabling section 202A, 202B are equivalent to Figure 5 The wiring section 202 is a wiring section of the wiring section 202. Wiring sections 202A and 202B are interconnected via interlayer connection section 20c and at least one of the other wiring layers 20a2 to 20a4. Wiring section 202B is connected to the U-phase output wiring 104U (see reference 104U), which is another wiring section. Figure 7 )connect.

[0053] and Figure 6 Similarly, through-holes 210 are formed on the wiring substrate 20, and each semiconductor package 30a, 30b is mounted on the wiring substrate 20 by inserting into the through-holes 210. Figure 9As shown, a heat sink with multiple pin fins 400 is disposed on the back side (lower side of the figure) of the wiring substrate 20 as a cooler 40. The cooler 40 is thermally connected to the semiconductor package bodies 30a and 30b and the back side of the wiring substrate 20 via an electrically insulating heat-conducting member 60. As the cooler 40, a cooler using a refrigerant may also be used instead of the heat sink.

[0054] When the semiconductor elements 100a and 100b within the semiconductor packages 30a and 30b are switched on and off, the temperatures of the semiconductor packages 30a and 30b and terminals 301 and 302 rise. For example... Figure 9 As shown, by providing the cooler 40, the heat of the semiconductor packages 30a, 30b and terminals 301, 302 is effectively dissipated, thereby reducing the temperature rise of the semiconductor packages 30a, 30b, terminals 301, 302 and wiring substrate 20. This suppresses deformation of components caused by temperature rise and alleviates stress at solder joints.

[0055] Additionally, although the illustration is omitted, coolers 40 can also be disposed on the surface side of semiconductor packages 30a and 30b to cool semiconductor packages 30a and 30b from both the top and bottom. This allows for further improvement in cooling performance.

[0056] As described above, in the second embodiment, a bent portion 310 is also provided on the terminals 301-303, and each wiring portion arranged opposite to the terminals 301-303 extends along the terminal protrusion direction. A terminal connection portion 311 of the terminals 301-303 is soldered to one end of each wiring portion, and an interlayer connection portion 20c is connected to the other end. For example, as... Figure 9 As shown by the dashed line L3, when current flows from terminal 301 to semiconductor package 30a, in wiring section 201A, the current flows in the opposite direction to that from interlayer connection section 20c provided at the other end 202b of wiring section 201A to terminal connection section 311. Therefore, similar to the case in the first embodiment, stress relief and inductance reduction of terminal connection section 311 can be achieved simultaneously.

[0057] Furthermore, since the semiconductor packages 30a and 30b are mounted on the wiring substrate 20 by means of through-holes 210, the gap size between the opposing terminals 301-303 and the wiring portion can be further reduced. As a result, inductance reduction can be further improved.

[0058] In addition, Figure 8In the example shown, multiple semiconductor packages 30a and 30b are configured such that the package positions are arranged along the alignment direction in a direction orthogonal to the terminal protrusion direction (vertical direction as shown in the figure). Therefore, regarding the multiple semiconductor packages 30a, on the right side of the package, multiple terminals 301 and 302 are arranged in a straight line in the vertical direction, and on the left side of the package, multiple terminals 303 are arranged in a straight line in the vertical direction. The same applies to the multiple semiconductor packages 30b. In this way, by aligning the terminals with each other in the vertical direction (orthogonal to the terminal protrusion direction as shown in the figure), inductance reduction can be further improved. In addition, the structure (cooling surface structure) of the cooler 40 for cooling the semiconductor packages 30a and 30b and the wiring substrate 20 is simplified.

[0059] Based on the embodiments and variations of the present invention described above, the following effects are achieved.

[0060] (1) such as Figure 3 , 4 As shown, the power conversion device includes: a semiconductor package 30 containing a semiconductor element and having terminals 301-303 protruding outwards for connection; and a wiring substrate 20 on which the semiconductor package 30 is mounted. Terminals 301-303 have a bent portion 310 that bends in a plane parallel to the wiring substrate 20, and a terminal connection portion 311 located further to the top of the bent portion 310. The wiring substrate 20 includes first wiring portions 201-203 disposed on the substrate surface and joined to terminals 301-303, and other second wiring portions (positive wiring 103p, negative wiring 103n, U-phase output wiring 104U, V-phase output wiring 104V, and W-phase output wiring 104W). Furthermore, the first wiring portions 201 to 203 extend from one end 201a, 202a, 203a, which is the connection area of ​​the connection terminals 301 to 303, toward the semiconductor package 30, opposite to the terminals 301 to 303, and the second wiring portions are connected to the other ends 201b, 202b, 203b, which are the extension side ends.

[0061] In other words, one end 201a, 202a, 203a of the first wiring portions 201-203 is connected to the terminal connection portion 311, and the other end 201b, 202b, 203b is connected to the second wiring portion, so that they are opposite to the terminals 301-303 in a direction from the other end 201b, 202b, 203b toward one end 201a, 202a, 203a along the terminal protrusion direction. Therefore, the direction of the current in the wiring portions 201-203 is opposite to the direction of the current in the terminals 301-303, which can simultaneously achieve stress relief and inductance reduction in the terminal connection portion 311.

[0062] In addition, Figure 8 , Figure 9In the configuration shown, the first wiring portions 201, 202A, 202B, and 204A extend from the connection area connected to the terminal connection portion 311 along the direction opposite to the terminals 301 to 303 toward the semiconductor package bodies 30a and 30b, at the ends on the extension side (corresponding to...) Figure 3 , Figure 4 In the case of the second wiring section, the interlayer connection section 20c is connected to the other end 201b, 202b, 203b. In this case, the direction of the current in the terminals 301 to 303 is opposite to the direction of the current in the opposite wiring section, which can simultaneously achieve stress relief and inductance reduction in the terminal connection section 311.

[0063] (2) In (1) above, such as Figure 6 As shown, the wiring substrate 20 has a through hole 210, and the semiconductor package 30 is mounted on the wiring substrate 20 by inserting into the through hole 210. Therefore, the gap size G between the terminals 301-303 and the wiring portions 201-203 can be further reduced, and the inductance reduction effect can be further improved.

[0064] (3) Furthermore, when the semiconductor package 30 has heat dissipation surfaces 320 and 321 on both the inner and outer surfaces, the cooling performance of the semiconductor package 30 can be improved by providing a cooler 40 on the heat dissipation surfaces 320 and 321 exposed on the substrate surface side and back side of the through hole 210.

[0065] (4) In (2) above, such as Figure 3 As shown, the semiconductor package 30 has a plurality of terminals 301, 302 protruding from the same side, and the bent portions 310 provided on adjacent pairs of terminals 301, 302 are bent toward each other. In this way, by bending the bent portions 310 toward each other, the inductance can be further reduced.

[0066] (5) In (1) above, such as Figure 8 As shown, a plurality of semiconductor packages 30a and 30b are arranged on the wiring substrate 20 in a direction orthogonal to the protrusion direction of terminals 301 to 303, and the plurality of semiconductor packages 30a and 30b are arranged in the arrangement direction. Therefore, by aligning the terminals with each other in a direction orthogonal to the protrusion direction of the terminals, the inductance reduction can be further improved. In addition, the cooling surface structure of the cooler 40 for cooling the semiconductor packages 30a and 30b and the wiring substrate 20 is simplified.

[0067] (6) In (1) above, such as Figure 8 , 9As shown, the wiring substrate 20 is a multilayer substrate in which multiple wiring layers 20a1 to 20a4 are stacked with an insulating layer 20b in the substrate thickness direction. First wiring portions 201, 201A, 202A, 202B, 203A, and 204A are formed on the wiring layer 20a1 provided on the surface side of the wiring substrate 20, and at the end on the extended side (for example, the other end 202b), they are connected to at least one of the other wiring layers provided in the substrate thickness direction through interlayer connection portions 20c. With this configuration, the current of the terminal and the current of the first wiring portion are in opposite directions, which can simultaneously achieve stress relief and inductance reduction of the terminal connection portion 311.

[0068] (7) In (6) above, such as Figure 9 As shown, the wiring substrate 20 has a wiring layer 20a4 on the back side of the substrate. Other wiring layers connected by interlayer connections 20c include the wiring layer 20a4 on the back side of the substrate. It also includes a cooler 40 for cooling the wiring layer 20a4 on the back side of the substrate. With this configuration, the temperature rise of the wiring substrate 20 can be reduced, the deformation of the components caused by the temperature rise can be suppressed, and the stress at the solder joint can be eased.

[0069] The embodiments and modifications described above are merely examples, and the invention is not limited to these descriptions as long as they do not impair the characteristics of the invention. Furthermore, while various embodiments and modifications have been described above, the invention is not limited to these descriptions. Other methods that can be considered within the scope of the technical concept of the invention are also included within the scope of the invention.

[0070] Explanation of symbols

[0071] 1…Power conversion device, 2…DC voltage source, 3…Motor, 10…Inverter circuit, 11…Gate drive circuit, 12…Control circuit, 20…Wiring substrate, 20a1~20a4…Conductor layer (wiring layer), 20b…Insulating layer, 20c…Interlayer connection, 30, 30a, 30b…Semiconductor package, 40…Cooler, 100a, 100b…Semiconductor element, 101, 102…Capacitor, 103p…Positive wiring, 103n…Negative wiring Lines, 104U…U-phase output wiring, 104V…V-phase output wiring, 104W…W-phase output wiring, 201~204, 201A~204A, 202B, 200p, 200n…wiring section, 201a, 202a, 203a…one end, 201b, 202b, 203b…the other end, 210…through hole, 301, 302, 303…terminals, 310…bending section, 311…terminal connection section, 320, 321…heat dissipation surface.

Claims

1. A power conversion device, characterized by, Possessing: a semiconductor package that internally houses a semiconductor element and has a terminal that protrudes outward for connection; and a wiring substrate that mounts the semiconductor package, the terminal has a bent portion that is bent in a plane parallel to the wiring substrate, and a terminal connection portion that is provided on a tip side relative to the bent portion, the wiring substrate has a first wiring portion that is provided on a substrate surface and joins the terminal, and another second wiring portion, the first wiring portion extends from a connection area that connects the terminal, in a direction toward the semiconductor package opposite the terminal, and connects the second wiring portion at an end portion on the extending side.

2. The power conversion device according to claim 1, wherein the wiring substrate has a through-hole, the semiconductor package is mounted on the wiring substrate in a manner that the semiconductor package is inserted into the through-hole.

3. The power conversion device according to claim 2, wherein the semiconductor package has a first heat dissipation surface that is exposed on a substrate surface side of the through-hole, and a second heat dissipation surface that is exposed on a substrate back surface side of the through-hole, a first cooler that cools the first heat dissipation surface and a second cooler that cools the second heat dissipation surface are further provided.

4. The power conversion device according to claim 1, wherein the semiconductor package has a plurality of the terminals that protrude from the same side surface, the bent portions provided on a pair of adjacent terminals are bent in directions that approach each other, respectively.

5. The power conversion device according to claim 1, wherein a plurality of the semiconductor packages are arranged on the wiring substrate in a direction orthogonal to a protruding direction of the terminal, the plurality of the semiconductor packages are arranged in a manner that the plurality of the semiconductor packages are arranged in the arrangement direction.

6. The power conversion device according to claim 1, wherein the wiring substrate is a multilayer substrate in which a plurality of wiring layers are stacked in a substrate thickness direction with an insulating layer interposed therebetween, the first wiring portion is formed on the wiring layer provided on a surface side of the wiring substrate, and, at the end portion on the extending side, is connected to at least one of the other wiring layers provided in the substrate thickness direction via an interlayer connection portion.

7. The power conversion device according to claim 6, wherein the wiring substrate has the wiring layer on a substrate back surface side, the other wiring layer connected by the interlayer connection portion includes the wiring layer on the substrate back surface side, a third cooler that cools the wiring layer on the substrate back surface side is further provided.

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