Circuit-level simulation method for single event upset of NAND type flash memory array

Abstract

The invention discloses a circuit-level simulation method for single event upset of an NAND type flash memory array, which comprises the following steps of: constructing a flash memory array circuit-level model, and arranging equivalent floating gate type MOS (Metal Oxide Semiconductor) tubes in the model in a layered manner; the charge state of each storage unit on the bit line is obtained by detecting the drain current state of the first equivalent floating gate type MOS tube on each bit line layer; bombarding the floating gate type MOS tube according to different high-energy particles to obtain a threshold voltage, and taking the threshold voltage as a threshold voltage in an equivalent floating gate type MOS tube; when the standard reading voltage is applied, the current of the drain electrode of the equivalent floating gate type MOS tube at the tail end of each bit line layer is monitored, and when the current amplitude exceeds a preset logic judgment threshold value, it is confirmed that a single event upset event occurs in the storage unit. According to the method, the equivalent circuit model is constructed for the floating gate type MOS tube, simulation can be realized only by equivalence of two key parameters in the floating gate type MOS tube, and the simulation efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of memory device testing technology, and in particular to a circuit-level simulation method for single-event flip of NAND flash memory arrays. Background Technology

[0002] Compared to traditional SRAM or DRAM, NAND flash memory can retain data for extended periods after power loss, which is crucial for spacecraft operating in orbit for long periods. For example, in remote sensing satellites, NAND flash memory is used to store high-resolution image data; in deep space exploration missions, it serves as a cache and transmitter of scientific data. However, high-energy particle radiation in the space environment can cause data errors or permanent damage to storage cells.

[0003] The core storage unit of NAND flash memory chips—the flash memory array—is highly susceptible to the effects of high-energy particles in space, leading to single-event upset (SEU) failures. SEUs cause abnormal changes in the charge state of the floating gate layer within the storage unit, resulting in data errors. Currently, research on SEUs in flash memory chips, both domestically and internationally, generally employs direct irradiation testing methods, i.e., evaluating device performance through space environment measurements or ground-based accelerator irradiation. While this method offers high data accuracy, it suffers from significant limitations such as long testing cycles and complex testing procedures. Furthermore, existing SEU assessments heavily rely on large-scale irradiation experimental facilities such as heavy-ion accelerators, with single-test costs reaching hundreds of thousands of yuan, and are limited by equipment time and irradiation conditions, making it difficult to cover all possible radiation scenarios. Summary of the Invention

[0004] Purpose of the invention: The purpose of this invention is to provide a circuit-level simulation method for single-event flip (SIF) of NAND flash memory arrays, which efficiently completes the simulation evaluation of the SIF effect through the establishment of an equivalent circuit model.

[0005] Technical solution: A circuit-level simulation modeling method for single-event flip of NAND flash memory arrays, comprising: A circuit-level model of a NAND flash memory array is constructed, in which multiple equivalent floating-gate MOS transistors are layered, including two levels: page level and bit line level. The charge state of each memory cell in the NAND flash memory array circuit-level model on each bit line is obtained by detecting the drain current value of the first equivalent floating gate MOS transistor on each bit line. The threshold voltage of a floating-gate MOSFET bombarded by different high-energy particles is obtained based on actual experiments or simulations, and the threshold voltage is used as the threshold voltage in the equivalent floating-gate MOSFET. While applying the standard read voltage, the drain current of the equivalent floating gate MOS transistor at the end of each line is monitored. When the current amplitude exceeds the preset logic judgment threshold, a single-event flip event is confirmed for the memory cell; otherwise, the cell state is determined to remain stable.

[0006] Furthermore, the layered arrangement of multiple equivalent floating-gate MOS transistors includes: At the page level, multiple equivalent floating-gate MOS transistors on the same page are connected in parallel to achieve common voltage drive of the control gate of all memory cells in the page; At the bit line level, multiple equivalent floating gate MOSFETs on the same bit line are connected in series. Specifically, the source of the first MOSFET on the same bit line is connected to the power supply voltage VCC, and its drain is connected to the source of the next equivalent floating gate MOSFET, and so on to form a cascaded path.

[0007] Furthermore, the equivalent floating-gate MOS transistor includes: The first P-type MOSFET Mp1 has its source connected to the power supply VCC, its drain connected to the source of the first N-type MOSFET Mn1, and its gate connected to the gate of the second P-type MOSFET Mp2 and the source of the first N-type MOSFET Mn1. The first N-type MOSFET Mn1 has its drain grounded and its gate connected to the control gate of an equivalent floating-gate MOSFET with an external read voltage Vin1 applied. The source of the second P-type MOSFET Mp2 is connected to the power supply VCC, and the drain is connected to the source of the second N-type MOSFET Mn2 and the gate of the third N-type MOSFET Mn3. The second N-type MOSFET Mn2 has its drain grounded and its gate output is the equivalent threshold voltage Vin2, which is determined by the charge state of the floating gate layer. The third N-type MOSFET, Mn3, has its source connected to the power supply VCC.

[0008] Furthermore, the charge state of each memory cell in the NAND flash memory array circuit-level model on each bit line is obtained by detecting the current state of the drain of the first equivalent floating-gate MOS transistor on each bit line, including: A page-scanning mechanism is adopted, and ramp voltage signals are applied sequentially to the shared control gate. The drain current value of the conventional MOS transistor in the first equivalent floating gate MOS transistor on the bit line is precisely measured, and the charge state of each memory cell is determined based on the drain current value.

[0009] Furthermore, when obtaining the charge state of each memory cell, the process also includes: Differentiated data writing is performed on different storage cells in a NAND flash memory array; During the read operation, a linear ramp voltage signal of 0-3.3V is sequentially applied to the control gate of different memory cells, and the read function is verified by monitoring the change characteristics of the bit line current in real time.

[0010] A circuit-level simulation device for single-event flip of a NAND flash memory array includes: The circuit-level model building unit is used to build a circuit-level model of a NAND flash memory array. In this model, multiple equivalent floating-gate MOS transistors are layered, including two levels: the page level and the bit line level. The charge state detection unit is used to obtain the charge state of each memory cell in the NAND flash memory array circuit-level model on each bit line by detecting the drain current value of the first equivalent floating gate MOS transistor on the bit line plane. The threshold voltage acquisition unit is used to obtain the turn-on threshold voltage of a floating-gate MOS transistor bombarded by different high-energy particles based on actual experiments or simulations, and to use the turn-on threshold voltage as the threshold voltage in the equivalent floating-gate MOS transistor. The status monitoring unit is used to monitor the drain current of the equivalent floating gate MOS transistor at the end of each bit line while applying a standard read voltage. When the current amplitude exceeds the preset logic judgment threshold, it is confirmed that a single-event flip event has occurred in the memory cell; otherwise, it is determined that the cell state remains stable.

[0011] Furthermore, the layered arrangement of multiple equivalent floating-gate MOS transistors includes: At the page level, multiple equivalent floating-gate MOS transistors on the same page are connected in parallel to achieve common voltage drive of the control gate of all memory cells in the page; At the bit line level, multiple equivalent floating gate MOSFETs on the same bit line are connected in series. Specifically, the source of the first MOSFET on the same bit line is connected to the power supply voltage VCC, and its drain is connected to the source of the next equivalent floating gate MOSFET, and so on to form a cascaded path.

[0012] A computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the method described in any of the preceding claims.

[0013] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed, it performs the steps of any of the methods described above.

[0014] A computer program product comprising a computer program / instructions that, when executed by a processor, implement the steps of any of the methods described above.

[0015] Compared with the prior art, the significant advantages of this invention are as follows: 1. This invention uses a circuit-level simulation method, which only requires two key parameters: the initial threshold voltage (Vth) of the floating gate MOS transistor after data writing and the threshold voltage value after irradiation. The simulation evaluation of the single-event upset effect can be efficiently completed through the established equivalent circuit model. The advantage of this method is that it transforms the traditional experiment that requires a complex irradiation environment into a repeatable circuit simulation. 2. This invention uses simulation to replace physical experiments. At the same time, the method of this invention supports repeated simulations of the same device, avoiding the problem of irreversible damage to samples in actual irradiation tests, reducing the overall R&D cost, and providing an economical and feasible technical solution for radiation-resistant design of memory. Attached Figure Description

[0016] Figure 1 This is a flowchart of the present invention; Figure 2 This is a schematic diagram of an equivalent floating-gate MOS transistor according to an embodiment of the present invention; Figure 3 This is a schematic diagram of a NAND flash memory array circuit-level model according to an embodiment of the present invention; Figure 4 This is a SPICE simulation demonstration diagram of a NAND flash memory array circuit-level model according to an embodiment of the present invention; Figure 5 This is a SPICE simulation demonstration diagram of a NAND flash memory array circuit-level model according to an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of the present invention to facilitate a better understanding of this application. However, the technical solutions claimed in this invention can be implemented even without these technical details and with various changes and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with and referenced by each other without contradiction.

[0018] This embodiment provides a circuit-level simulation method for single-event flip (SIF) of NAND flash memory arrays, the process of which is as follows: Figure 1As shown, it includes constructing a circuit-level model of a NAND flash memory array. In this model, multiple equivalent floating-gate MOS transistors are arranged in layers, including two layers: the page layer and the bit-line layer. By detecting the drain current value of the first equivalent floating-gate MOS transistor on each bit-line layer, the charge states of each storage cell in the NAND flash memory array circuit-level model on that bit-line can be obtained. According to actual experiments or simulations, the turn-on threshold voltages of different high-energy particles bombarding the floating-gate MOS transistor are obtained, and the turn-on threshold voltage is used as the threshold voltage in the equivalent floating-gate MOS transistor. In the NAND flash memory array circuit-level model, while applying a standard read voltage, the drain current of the equivalent floating-gate MOS transistor at the end of each bit-line layer is monitored. When the current amplitude exceeds the preset logical determination threshold, it is confirmed that a single-event upset (SEU) event has occurred in this storage cell; otherwise, it is determined that the cell state remains stable. In this embodiment, by constructing an equivalent circuit model for the floating-gate MOS transistor, low-cost simulation can be achieved, and only two key parameters in the equivalent floating-gate MOS transistor are required to achieve the simulation, further improving the simulation efficiency.

[0019] In an example, the working principle of the floating-gate MOS transistor is based on the charge state of the floating gate layer. In the initial state (when no data is written), there is no charge injection in the floating gate layer, and at this time, the threshold voltage of the device is close to 0V. When a read voltage is applied to the control gate of the equivalent floating-gate MOS transistor, the channel can conduct directly, which is characterized as the logic "1" state. In the data writing stage, electrons are injected into the floating gate layer through hot electron injection or F-N tunneling effect. These stored charges will shield the control gate electric field, causing the device threshold voltage to rise to Vth. At this time, when the same read voltage is applied, since Vgs < Vth, the channel cannot conduct, which is characterized as the logic "0" state. When a high-energy single particle bombards the floating-gate MOS transistor, its energy deposition will induce a transient ionization effect in the tunnel oxide layer, forming a nanoscale conduction path. This phenomenon causes the charges stored in the floating gate layer to quickly dissipate through the radiation-induced leakage channel, thereby significantly reducing the effective threshold voltage of the device. This drift of the threshold voltage causes the storage cell that was originally in the cut-off state (Vgs < Vth) to conduct unexpectedly during the read operation, showing an incorrect flip of the storage state (i.e., single-event upset).

[0020] In this embodiment, in step 1, a circuit-level model of a NAND flash memory array is constructed. In this model, multiple equivalent floating-gate MOS transistors are arranged in layers, including two layers: the page layer and the bit-line layer.

[0021] Specifically, according to the working principle of the floating-gate MOS, this embodiment provides an equivalent floating-gate MOS transistor, the structure is as Figure 2 shown, including: In the first P-type MOSFET Mp1, the source is connected to the power supply VCC, the drain is connected to the source of the first N-type MOSFET Mn1, and the gate is connected to the gate of the second P-type MOSFET Mp2 and the source of the first N-type MOSFET Mn1. The first N-type MOSFET Mn1 has its drain grounded and its gate connected to the control gate of an equivalent floating-gate MOSFET. This control gate is connected to the first input port of the comparator and reads the applied voltage Vin1. The second P-type MOSFET Mp2 has its source connected to the power supply VCC and its drain connected to the source of the second N-type MOSFET Mn2 and the gate of the third N-type MOSFET Mn3. The second N-type MOSFET Mn2 has its drain grounded and its gate connected to the second input port of the comparator. The gate output characterizes the equivalent threshold voltage Vin2 determined by the charge state of the floating gate layer. The third N-type MOSFET Mn3 has its source connected to the power supply VCC.

[0022] This model simulates the storage characteristics of an equivalent floating-gate MOSFET by cooperating with a comparator circuit and a third N-type MOSFET, Mn3. In this equivalent circuit, the two input ports of the comparator represent the key operating parameters of the floating-gate MOSFET: Vin1 corresponds to the external read voltage controlling the gate, and Vin2 represents the equivalent threshold voltage determined by the charge state of the floating gate layer (Vth≈0V when there is no charge stored, and Vth is the set value when there is charge stored). The output terminal Vout of the comparator is connected to the gate of the third N-type MOSFET Mn3. The real-time comparison result of Vin1 and Vin2 by the comparator drives the equivalent floating-gate MOSFET to turn on and off.

[0023] Multiple equivalent floating-gate MOS transistors are arranged in layers, such as Figure 3 As shown, it includes: At the page level, multiple equivalent floating-gate MOS transistors on the same page are connected in parallel to achieve common-voltage drive of the control gates of all memory cells within the page; at the bit line level, multiple equivalent floating-gate MOS transistors on the same bit line are connected in series. Specifically, the source of the first MOS transistor on the same bit line is connected to the power supply voltage VCC, and its drain is connected to the source of the next equivalent floating-gate MOS transistor, and so on to form a cascaded path.

[0024] In step 2, the charge state of each memory cell in the NAND flash memory array circuit-level model on each bit line is obtained by detecting the current state of the drain of the first equivalent floating gate MOS transistor on each bit line.

[0025] Specifically, in the read operation of a NAND flash memory array, the data read process is achieved by detecting the charge state of the equivalent floating-gate MOSFET. The data state of each memory cell (one memory cell corresponds to one equivalent floating-gate MOSFET) is characterized by the voltage of the Vin2 node: when Vin2 is set to the high threshold voltage Vth, it indicates that the floating gate layer stores charge (logic "0"); when Vin2 is 0V, it indicates that the floating gate layer does not store charge (logic "1"). During the read process, the array adopts a page scanning mechanism: a ramp voltage signal is applied sequentially to the shared control gate, and the charge state of each memory cell can be determined by precisely measuring the drain current value of the conventional MOSFET in the first equivalent floating-gate MOSFET on the bit line.

[0026] The process of obtaining the charge state of each memory cell also includes: differentially writing data to three memory cells in the array: cell 1 (Vin2=7.4V, logic "0"), cell 2 (Vin2=0V, logic "1"), and cell 3 (Vin2=7.4V, logic "0"). During the read operation, a linear ramp voltage signal of 0-3.3V is sequentially applied to the control gate (Vin1) of the three cells. The read function is verified by monitoring the change characteristics of the bit line current i1 in real time (i.e., the data storage status of cells 1, 2, and 3 is detected by the i1 current value, cells 4, 5, and 6 are detected by the i2 current value, and cells 7, 8, and 9 are detected by the i3 current value). Figure 3 In this process, when data is written to cells 1 and 3, but not to cell 2, the input read voltage is applied sequentially to the gates of cells 1, 2, and 3 according to time. For example, if reading cells 1, 2, and 3 takes 9 seconds, during the first 3 seconds, the read voltage is applied to the gate of cell 1. Since cell 1 contains data, it is not conducting, and i1 shows a large current, i.e., logic "1". During the middle 3 seconds, the read voltage is applied to the gate of cell 2. Since cell 2 is not being written to, it conducts normally, while cells 1 and 3, which do not have gate voltage applied, are also forcibly conducted, resulting in i1 showing a small current, i.e., logic "0". During the last 3 seconds, the read voltage is applied to the gate of cell 3.

[0027] Figure 3 This is a SPICE simulation demonstration diagram of the flash array of the present invention. The simulation observation shows that i1 exhibits a typical "low-high-low" tri-state response, which accurately corresponds to the "0-1-0" storage data mode. Specifically: when the scan voltage reaches the threshold of the first cell, i1 jumps from a low level; then it remains at a high level because the second cell is in the conducting state; finally, it falls back down due to the high threshold characteristic of the third cell.

[0028] Building upon this, a single-event upset (SEE) scenario can be further simulated: Unit 1 remains in its normal state (Vin2 = 7.4V), while Unit 3 experiences a SEE (Vin2 drops from 7.4V to 1.5V). In a standard read operation, when a linear ramp voltage of 0-3.3V is applied to the control gate (Vin1) of the three units, the response characteristics of the bit line current i1 are as follows: Figure 4 As shown. Figure 5 The provided diagram demonstrates the SPICE simulation of single-event flip detection in the flash array of this invention. Simulation data shows that the current waveform changes from a "low-high-low" pattern in the baseline state to a "low-high-high" pattern. This change clearly indicates the threshold voltage reduction phenomenon in the third cell due to radiation-induced charge leakage. Specifically, when the gate Vin1 scan voltage exceeds 1.5V, the third cell abnormally turns on, causing the current, which should have fallen back, to remain at a high level.

[0029] In step 3, the turn-on threshold voltage of the floating gate MOS transistor bombarded by different high-energy particles is obtained based on actual experiments or simulations, and the turn-on threshold voltage is used as the threshold voltage in the equivalent floating gate MOS transistor.

[0030] Specifically, based on actual experiments or simulations, the value of the change in the threshold voltage caused by the leakage of stored charge due to the bombardment of floating gate MOS transistors by different high-energy particles is obtained. The changed threshold voltage value is then quantified into the voltage value of Vin2 node in the equivalent circuit model.

[0031] In step 4, in the NAND flash memory array circuit-level model, while applying the standard read voltage, the drain current of the equivalent floating gate MOS transistor at the end of each line is monitored. When the current amplitude exceeds the preset logic judgment threshold, it is confirmed that a single event flip (SEU) has occurred in the memory cell; otherwise, it is determined that the cell state remains stable.

[0032] Specifically, based on the aforementioned NAND flash memory read architecture, while applying a standard read voltage (Vin1), the drain current response of the MOS transistor at the end of the bit line is monitored using a high-precision current probe. When the observed current amplitude exceeds a preset logic threshold, a single-event flip (SEU) event can be confirmed for the memory cell; otherwise, the cell state is determined to remain stable.

[0033] A circuit-level simulation device for single-event flip of a NAND flash memory array includes: The circuit-level model building unit is used to build a circuit-level model of a NAND flash memory array. In this model, multiple equivalent floating-gate MOS transistors are layered, including two levels: the page level and the bit line level. The charge state detection unit is used to obtain the charge state of each memory cell in the NAND flash memory array circuit-level model on each bit line by detecting the drain current value of the first equivalent floating gate MOS transistor on the bit line plane. The threshold voltage acquisition unit is used to obtain the turn-on threshold voltage of a floating-gate MOS transistor bombarded by different high-energy particles based on actual experiments or simulations, and to use the turn-on threshold voltage as the threshold voltage in the equivalent floating-gate MOS transistor. The status monitoring unit is used to monitor the drain current of the equivalent floating gate MOS transistor at the end of each bit line while applying a standard read voltage. When the current amplitude exceeds the preset logic judgment threshold, it is confirmed that a single-event flip event has occurred in the memory cell; otherwise, it is determined that the cell state remains stable.

[0034] Preferably, the layered arrangement of multiple equivalent floating-gate MOS transistors includes: At the page level, multiple equivalent floating-gate MOS transistors on the same page are connected in parallel to achieve common voltage drive of the control gate of all memory cells in the page; At the bit line level, multiple equivalent floating gate MOSFETs on the same bit line are connected in series. Specifically, the source of the first MOSFET on the same bit line is connected to the power supply voltage VCC, and its drain is connected to the source of the next equivalent floating gate MOSFET, and so on to form a cascaded path.

[0035] A computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the circuit-level simulation method of the present invention. The processor contains a kernel that retrieves corresponding program units from memory.

[0036] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is executed, it implements the steps of the circuit-level simulation method of the present invention.

[0037] The memory may include non-permanent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0038] A computer program product includes a computer program / instructions that, when executed by a processor, implement the steps of the circuit-level simulation method of the present invention.

[0039] The modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those described herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular hardware and software combination.

[0040] Embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, this application may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may be implemented as a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0041] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited thereto. Various changes that can be made within the scope of knowledge possessed by those skilled in the art without departing from the spirit of the present invention are all within the protection scope of the present invention.

Claims

1. A circuit-level simulation method for single-event flip of NAND flash memory arrays, characterized in that, include: A circuit-level model of a NAND flash memory array is constructed, in which multiple equivalent floating-gate MOS transistors are layered, including two levels: page level and bit line level. The charge state of each memory cell in the NAND flash memory array circuit-level model on each bit line is obtained by detecting the drain current value of the first equivalent floating gate MOS transistor on each bit line. The threshold voltage of a floating-gate MOSFET bombarded by different high-energy particles is obtained based on actual experiments or simulations, and the threshold voltage is used as the threshold voltage in the equivalent floating-gate MOSFET. While applying the standard read voltage, the drain current of the equivalent floating gate MOS transistor at the end of each line is monitored. When the current amplitude exceeds the preset logic judgment threshold, a single-event flip event is confirmed for the memory cell; otherwise, the cell state is determined to remain stable.

2. The circuit-level simulation method for single-event flip of NAND flash memory arrays according to claim 1, characterized in that, The layered arrangement of multiple equivalent floating-gate MOSFETs includes: At the page level, multiple equivalent floating-gate MOS transistors on the same page are connected in parallel to achieve common voltage drive of the control gate of all memory cells in the page; At the bit line level, multiple equivalent floating gate MOSFETs on the same bit line are connected in series. Specifically, the source of the first MOSFET on the same bit line is connected to the power supply voltage VCC, and its drain is connected to the source of the next equivalent floating gate MOSFET, and so on to form a cascaded path.

3. The circuit-level simulation method for single-event flip of NAND flash memory arrays according to claim 2, characterized in that, The equivalent floating-gate MOS transistor includes: The first P-type MOSFET Mp1 has its source connected to the power supply VCC, its drain connected to the source of the first N-type MOSFET Mn1, and its gate connected to the gate of the second P-type MOSFET Mp2 and the source of the first N-type MOSFET Mn1. The first N-type MOSFET Mn1 has its drain grounded and its gate connected to the control gate of an equivalent floating-gate MOSFET with an external read voltage Vin1 applied. The source of the second P-type MOSFET Mp2 is connected to the power supply VCC, and the drain is connected to the source of the second N-type MOSFET Mn2 and the gate of the third N-type MOSFET Mn3. The second N-type MOSFET Mn2 has its drain grounded and its gate output is the equivalent threshold voltage Vin2, which is determined by the charge state of the floating gate layer. The third N-type MOSFET, Mn3, has its source connected to the power supply VCC.

4. The circuit-level simulation method for single-event flip of NAND flash memory arrays according to claim 3, characterized in that, The charge state of each memory cell in the NAND flash memory array circuit-level model on each bit line is obtained by detecting the current state of the drain of the first equivalent floating-gate MOS transistor on each bit line, including: A page-scanning mechanism is adopted, and ramp voltage signals are applied sequentially to the shared control gate. The drain current value of the conventional MOS transistor in the first equivalent floating gate MOS transistor on the bit line is precisely measured, and the charge state of each memory cell is determined based on the drain current value.

5. The circuit-level simulation method for single-event flip of NAND flash memory arrays according to claim 4, characterized in that, When obtaining the charge state of each memory cell, the following is also included: Differentiated data writing is performed on different storage cells in a NAND flash memory array; During the read operation, a linear ramp voltage signal of 0-3.3V is sequentially applied to the control gate of different memory cells, and the read function is verified by monitoring the change characteristics of the bit line current in real time.

6. A circuit-level simulation device for single-event flip of a NAND flash memory array, characterized in that, include: The circuit-level model building unit is used to build a circuit-level model of a NAND flash memory array. In this model, multiple equivalent floating-gate MOS transistors are layered, including two levels: the page level and the bit line level. The charge state detection unit is used to obtain the charge state of each memory cell in the NAND flash memory array circuit-level model on each bit line by detecting the drain current value of the first equivalent floating gate MOS transistor on the bit line plane. The threshold voltage acquisition unit is used to obtain the turn-on threshold voltage of a floating-gate MOS transistor bombarded by different high-energy particles based on actual experiments or simulations, and to use the turn-on threshold voltage as the threshold voltage in the equivalent floating-gate MOS transistor. The status monitoring unit is used to monitor the drain current of the equivalent floating gate MOS transistor at the end of each bit line while applying a standard read voltage. When the current amplitude exceeds the preset logic judgment threshold, it is confirmed that a single-event flip event has occurred in the memory cell; otherwise, it is determined that the cell state remains stable.

7. The circuit-level simulation device for single-event flip of NAND flash memory arrays according to claim 6, characterized in that, The layered arrangement of multiple equivalent floating-gate MOSFETs includes: At the page level, multiple equivalent floating-gate MOS transistors on the same page are connected in parallel to achieve common voltage drive of the control gate of all memory cells in the page; At the bit line level, multiple equivalent floating gate MOSFETs on the same bit line are connected in series. Specifically, the source of the first MOSFET on the same bit line is connected to the power supply voltage VCC, and its drain is connected to the source of the next equivalent floating gate MOSFET, and so on to form a cascaded path.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1 to 5.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the computer program is executed, it implements the steps of the method as described in any one of claims 1 to 5.

10. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the method according to any one of claims 1 to 5.

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