Frequency adjusting circuit, clock generator, chip and frequency adjusting method

Abstract

The invention provides a frequency adjusting circuit, a clock generator, a chip and a frequency adjusting method, and is suitable for the technical field of integrated circuits. The frequency adjusting circuit comprises a frequency divider unit which comprises at least one frequency divider module and is used for performing frequency division processing on original clock signals based on frequency division parameters of the frequency divider modules to obtain clock signals to be selected, and the frequency of the clock signals to be selected is lower than that of the original clock signals; the frequency modulation control unit is used for generating a clock frequency selection signal based on the detection voltage of the at least one voltage detection point and an externally input target frequency control signal; and the clock selection unit is used for selecting one to-be-selected clock signal from the to-be-selected clock signals as a target clock signal to be output based on the clock frequency selection signal when any detection voltage drops. According to the embodiment of the invention, stable operation of the system can be maintained by rapidly adjusting the clock frequency of the system when the power supply voltage drops transiently.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a frequency adjustment circuit, a clock generator, a chip, and a frequency adjustment method. Background Technology

[0002] In high-performance processors, voltage doop can cause two serious clock-related problems: (1) increased clock path latency, leading to clock skew and jitter; and (2) increased data path latency, causing timing violations at a given clock frequency. Both of these situations can lead to system malfunctions.

[0003] Currently, existing technologies can employ a "stable clock" approach to make the clock generation and distribution network insensitive to voltage drops. The main methods include: using a global clock generation based on a phase-locked loop (PLL) and supplementing it with an on-chip voltage regulator with low jitter and high power supply rejection ratio to provide separate power to the PLL and clock buffer, thus constructing a "clean" clock island; or using current-mode logic circuits that are relatively insensitive to voltage changes to construct critical clock paths.

[0004] However, the "stable clock" approach only addresses the symptoms, not the root cause. The data path problem remains unresolved. Even if the clock itself is stable, the speed of the data path transistors will still decrease significantly due to voltage drops. Therefore, under a stable, fast clock, a slower data path cannot complete calculations, easily leading to latched incorrect data and causing system malfunctions. Summary of the Invention

[0005] In view of this, embodiments of this application provide a frequency adjustment circuit, a clock generator, a chip, and a frequency adjustment method to solve the problem that the use of a "stable clock" in the prior art is prone to system malfunction.

[0006] A first aspect of this application provides a frequency adjustment circuit, including:

[0007] The frequency divider unit includes at least one frequency divider module, which is used to divide the original clock signal according to the frequency division parameters of each frequency divider module to obtain each clock signal to be selected; the frequency of the clock signal to be selected is lower than that of the original clock signal. A frequency modulation control unit is used to generate a clock frequency selection signal based on the detected voltage at at least one voltage detection point and an externally input target frequency control signal. The clock selection unit, which is electrically connected to both the frequency divider unit and the frequency modulation control unit, is used to select one clock signal from the available clock signals as the target clock signal output when any detected voltage drops, based on the clock frequency selection signal.

[0008] In one possible implementation, the frequency modulation control unit includes: The voltage indication aggregation module is used to perform logical operations on the detected voltages from at least two input voltage detection points and output a voltage indication signal; The level broadening module, electrically connected to the voltage indication convergence module, is used to broaden the voltage indication signal and output a voltage detection signal; the voltage detection signal is used to indicate voltage changes. The frequency selection control module, along with the level widening module and the clock selection unit, is electrically connected to perform logical operations based on the externally input target frequency control signal and voltage detection signal to generate a clock frequency selection signal.

[0009] In one possible implementation, the frequency selection control module includes: The target frequency control module, which is electrically connected to the level broadening module, is used to perform logical operations on the target frequency control signal and the voltage detection signal, and output a frequency selection indication signal. The frequency modulation enable control module is electrically connected to both the target frequency control module and the clock selection unit. It is used to perform logical operations on the frequency selection indication signal and the externally input enable signal to output the clock frequency selection signal.

[0010] In one possible implementation, the target frequency control module is used to perform a logical AND operation on the target frequency control signal and the voltage detection signal, and output a frequency selection indication signal; or, the target frequency control signal and the voltage detection signal are sequentially inverted and then logically ORed, and the frequency selection indication signal is output. And / or, the frequency modulation enable control module is used to perform a logical AND operation on the frequency selection indicator signal and the externally input enable signal to output a clock frequency selection signal; or, it performs a signal inversion and a logical OR operation on the frequency selection indicator signal and the externally input enable signal in sequence to output a clock frequency selection signal.

[0011] In one possible implementation, the level widening module includes at least two cascaded registers, where the data input of the first register is configured with a polarity value that indicates the level to be widened. The level widening module is used to widen the voltage indication signal based on the polarity value and at least two registers to obtain the voltage detection signal.

[0012] In one possible implementation, the level broadening module is used to output the output signal of the data output terminal of the last stage register as a voltage detection signal based on a preset output polarity; or, based on a preset output polarity, the output signal of the data output terminal of the last stage register is output as a voltage detection signal via an inverter.

[0013] In one possible implementation, the target frequency control signal includes a bit width for representing the target frequency control signal, the bit width being determined based on the number of clock signals to be selected.

[0014] A second aspect of the embodiments of this application provides a clock generator, including: a frequency adjustment circuit as described in the first aspect; The frequency adjustment circuit is located on the clock path of the clock generator.

[0015] A third aspect of this application provides a chip, including: a frequency adjustment circuit according to a first aspect; or a clock generator according to a second aspect.

[0016] A fourth aspect of this application provides a frequency adjustment method applied to the frequency adjustment circuit of the first aspect, comprising: Based on the frequency division parameters of each frequency divider module, the original clock signal is divided to obtain each selectable clock signal; the frequency of the selectable clock signal is lower than that of the original clock signal. A clock frequency selection signal is generated based on the detected voltage at at least one voltage detection point and the target frequency control signal input externally. When any detection voltage drops, based on the clock frequency selection signal, select one of the candidate clock signals as the target clock signal for output.

[0017] Compared with the prior art, the embodiments of this application have at least the following technical effects: The first aspect of the frequency adjustment circuit in this application includes: a frequency divider unit, a frequency modulation control unit, and a clock selection unit electrically connected to both the frequency divider unit and the frequency modulation control unit. The frequency divider unit can perform frequency division processing on the original clock signal based on the division parameters of each frequency divider module to obtain each selectable clock signal, thereby reducing the frequency of the original clock signal. The frequency modulation control unit can generate a clock frequency selection signal based on the detected voltage at at least one voltage detection point and an externally input target frequency control signal. Thus, when the detected voltage decreases, the clock frequency selection signal can be generated based on the detected voltage and the externally input target frequency control signal. Therefore, when any detected voltage drops, the clock selection unit can select one selectable clock signal from the selectable clock signals as the target clock signal for output, based on the clock frequency selection signal. This is equivalent to reducing the frequency of the original clock signal and outputting a target clock signal that is insensitive to voltage drops. Therefore, this application embodiment can quickly adjust the system clock frequency through the frequency adjustment circuit when a transient drop in power supply voltage occurs, maintaining stable system operation and preventing system malfunctions caused by clock timing disorders.

[0018] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of a frequency adjustment circuit provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a frequency modulation control unit provided in an embodiment of this application; Figure 3 This is a schematic diagram of another frequency modulation control unit provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a frequency adjustment circuit electrically connected to a voltage detection point according to an embodiment of this application; Figure 5 This is a flowchart of a frequency adjustment method provided in an embodiment of this application.

[0021] Icon labels: 1- Frequency adjustment circuit; 11-Divider Unit; 12-Frequency modulation control unit, 121-Voltage indication convergence module, 122-Level widening module, 123-Frequency selection control module, 1231-Target frequency control module, 1232-Frequency modulation enable control module; 13-Clock selection unit. Detailed Implementation

[0022] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0023] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0024] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0025] In the description of this application, unless otherwise stated, the " / " used in this specification and appended claims indicates that the related objects are in an "or" relationship. For example, A / B can mean A or B. The "and / or" in this application merely describes the relationship between the related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a, b, and c. Here, a, b, and c can be single or multiple.

[0026] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0027] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0028] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0029] Research has revealed that existing technologies can also address system malfunctions caused by voltage dips using a "clock adaptation" approach. This "clock adaptation" approach includes DVFS (Dynamic Voltage Frequency Scaling) or AVFS (Adaptive Voltage Frequency Scaling), which uses on-chip sensors to monitor voltage, temperature, and other on-chip states, along with predicted load levels, and coordinates with system algorithms to achieve proactive or adaptive voltage frequency regulation.

[0030] However, for DVFS or AVFS, the main goal is to achieve a balance between energy efficiency and reliability. It usually involves complex on-chip sensors and control circuits, as well as software-related system control algorithms. Overall, it is a complex control system that combines hardware and software.

[0031] The frequency adjustment circuit, clock generator, chip, and frequency adjustment method provided in this application are intended to solve the above-mentioned technical problems of the prior art.

[0032] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0033] See Figure 1 As shown in the diagram, this application provides a schematic diagram of the structure of a frequency adjustment circuit 1. Figure 1 As shown, the frequency adjustment circuit 1 includes: a frequency divider unit 11, a frequency modulation control unit 12, and a clock selection unit 13.

[0034] Frequency divider unit 11 includes at least one frequency divider module. Frequency divider unit 11 is used to perform frequency division processing on the original clock signal based on the frequency division parameters of each frequency divider module to obtain each selectable clock signal; the frequency of the selectable clock signal is lower than that of the original clock signal.

[0035] The frequency division parameter can be the division ratio, and it includes the division coefficient. By dividing the frequency of the original clock signal by the division coefficient of each frequency divider module, the frequency of the clock signal to be selected can be obtained, thus reducing the frequency of the original clock signal to obtain the clock signal to be selected.

[0036] The original clock signal is the clock signal currently generated by the clock generator. The division factor is determined in advance according to system requirements. The division factor of each frequency divider module can be configured.

[0037] The frequency modulation control unit 12 is used to generate a clock frequency selection signal based on the detected voltage at at least one voltage detection point and the target frequency control signal input externally.

[0038] Optionally, the number and location of voltage detection points can be set according to the actual application requirements. The number of voltage detection points can be related to the size of the chip, and the location of the voltage detection points can be set on the critical path or in a location that is more sensitive to voltage fluctuations.

[0039] In some embodiments, the target frequency control signal includes a bit width for representing the target frequency control signal, the bit width being determined based on the number of clock signals to be selected.

[0040] The clock selection unit 13 is electrically connected to the frequency divider unit 11 and the frequency modulation control unit 12. The clock selection unit 13 is used to select one clock signal from each clock signal to be selected as the target clock signal output when any detection voltage drops, based on the clock frequency selection signal.

[0041] For example, in the input target frequency control signal target_ferq[X-1:0], X represents the bit width of the target frequency control signal, and in the frequency division parameter DIV / N0 of the frequency divider module, N represents the frequency division coefficient, and DIV can correspond to the frequency of the original clock signal.

[0042] Optionally, the clock selection unit 13 can also input a raw clock signal. The clock selection unit 13 is used to output the raw clock signal as a target clock signal when all detected voltages are within a predetermined voltage range. The target clock signal serves as the final clock signal for the clock generator.

[0043] If all detected voltages are within the predetermined voltage range, it indicates that there is no voltage drop and the chip can work normally.

[0044] For example: If there are four clock signals (both the selectable clock signal and the original clock signal) used as input clock signals for clock selection unit 13, then the "bit width" is 2, because a 2-bit binary number can select four cases. As another example: If there are five to eight input clock signals for clock selection unit 13, then the "bit width" is 3, i.e., 2^ (a) The value indicates the number of clock signals that can be selected, and 'a' corresponds to the bit width. For different systems, the number of input clock signals is set differently according to actual needs, thus determining the bit width accordingly.

[0045] Optionally, the clock selection unit 13 can employ a glitch-free clock switching module, which can avoid glitches during clock signal switching and ensure smooth switching. The glitch-free clock switching module is a purely hardware-based clock switching mechanism that achieves glitch-free clock switching through cross-feedback, enabling rapid clock frequency switching.

[0046] Specifically, in addition to using cross-feedback, the glitch-free clock switching module can also use a hardware state machine. After detecting that frequency adjustment is needed, the state machine can first shut down the original clock and then turn on the new clock.

[0047] This application embodiment supports the simultaneous detection of the detection voltage at multiple different physical points to complete the frequency control of a clock tree.

[0048] The frequency adjustment circuit 1 of this application embodiment includes: a frequency divider unit 11, a frequency modulation control unit 12, and a clock selection unit 13 electrically connected to both the frequency divider unit 11 and the frequency modulation control unit 12. The frequency divider unit 11 can perform frequency division processing on the original clock signal based on the division parameters of each frequency divider module to obtain each selectable clock signal, thereby reducing the frequency of the original clock signal through frequency division processing. The frequency modulation control unit 12 can generate a clock frequency selection signal based on the detected voltage at at least one voltage detection point and an externally input target frequency control signal. Therefore, when the detected voltage decreases, the clock frequency selection unit 13 can select one selectable clock signal from the selectable clock signals as the target clock signal for output based on the clock frequency selection signal, which is equivalent to reducing the frequency of the original clock signal and outputting a target clock signal that is insensitive to voltage reduction.

[0049] Therefore, in the embodiments of this application, when a transient drop in power supply voltage occurs, the frequency adjustment circuit 1 can quickly adjust the system clock frequency to maintain stable system operation and prevent abnormal system function caused by clock timing disorder.

[0050] This application relates to the field of clock and power management of high-performance integrated circuits, specifically to a frequency adjustment circuit 1 that maintains stable system operation and prevents malfunctions caused by clock timing disorders by rapidly adjusting the system clock frequency when a transient drop in power supply voltage occurs. The frequency adjustment circuit 1 of this application has a simple structure, is easy to integrate, and can be placed as a plug-in on the existing clock path to maintain system stability at a very low cost.

[0051] See Figure 2 As shown, this application provides a schematic diagram of the structure of a frequency modulation control unit 12. Figure 2 As shown, the frequency modulation control unit 12 includes: a voltage indication convergence module 121, a level broadening module 122, and a frequency selection control module 123.

[0052] The voltage indication aggregation module 121 is used to perform logical operations on the detected voltages of at least two input voltage detection points and output a voltage indication signal.

[0053] Specifically, when a detection voltage decreases, the voltage indication signal is a signal used to indicate that the voltage has decreased.

[0054] The level widening module 122 is electrically connected to the voltage indication convergence module 121. The level widening module 122 is used to widen the voltage indication signal and output a voltage detection signal; the voltage detection signal is used to indicate voltage changes.

[0055] Optionally, the level widening can be high-level widening or low-level widening. The level widening module 122 can widen the narrow pulses generated by rapid voltage changes to drive subsequent frequency modulation logic. Level widening can effectively filter out the narrow pulses generated by rapid voltage changes and provide a stable driving signal for subsequent frequency modulation logic.

[0056] Optionally, the voltage detection signal is 0 or 1.

[0057] The frequency selection control module 123, the level widening module 122, and the clock selection unit 13 are all electrically connected. The frequency selection control module 123 is used to perform logical operations based on the externally input target frequency control signal and voltage detection signal to generate a clock frequency selection signal.

[0058] Optionally, the target frequency control signal can be configured by an external microcontroller / processor.

[0059] See Figure 3 As shown in the diagram, this application provides another structural schematic diagram of a frequency modulation control unit 12. Figure 3 As shown, the frequency selection control module 123 includes: a target frequency control module 1231 and a frequency modulation enable control module 1232.

[0060] The target frequency control module 1231 is electrically connected to the level widening module 122. The target frequency control module 1231 is used to perform logical operations on the target frequency control signal and the voltage detection signal, and output a frequency selection indication signal. The frequency modulation enable control module 1232 is electrically connected to the target frequency control module 1231 and the clock selection unit 13. The frequency modulation enable control module 1232 is used to perform logical operations on the frequency selection indication signal and the externally input enable signal, and output the clock frequency selection signal.

[0061] Optionally, the enable signal is used to control whether clock frequency adjustment is performed. When the enable signal is active, the output clock signal can change with the voltage. When the enable signal is inactive, only the original clock signal can be output.

[0062] In some embodiments, the target frequency control module 1231 is used to perform a logical AND operation on the target frequency control signal and the voltage detection signal to output a frequency selection indication signal; or, it performs a signal inversion and a logical OR operation on the target frequency control signal and the voltage detection signal in sequence to output a frequency selection indication signal.

[0063] And / or, the frequency modulation enable control module 1232 is used to perform a logical AND operation on the frequency selection indication signal and the externally input enable signal to output a clock frequency selection signal; or, it performs a signal inversion and a logical OR operation on the frequency selection indication signal and the externally input enable signal in sequence to output a clock frequency selection signal.

[0064] In this embodiment, the frequency adjustment function is enabled and controlled by the frequency modulation enable control module 1232, and the final clock frequency selection signal is output.

[0065] See Figure 4 As shown in the diagram, this application embodiment provides a schematic diagram of the structure of a frequency adjustment circuit 1 electrically connected to a voltage detection point. See also... Figure 4 As shown, the level widening module 122 includes at least two cascaded registers. The data input terminal of the first-level register is configured with a polarity value, which is used to indicate the level that needs to be widened. The level widening module 122 is used to widen the voltage indication signal based on the polarity value and at least two registers to obtain a voltage detection signal.

[0066] Optionally, the polarity value is used as the input polarity configured by parameters. For example, polarity value 1'b1 indicates high-level broadening, and the detection input is a narrow pulse with a high level; polarity value 1'b0 indicates low-level broadening, and the detection input is a narrow pulse with a low level.

[0067] In practical applications, a low-level active voltage detection signal output means low-level broadening, while a high-level active voltage detection signal output means high-level broadening. Whether the voltage is low-level or high-level active is predetermined when detecting the output voltage at the voltage detection point.

[0068] The level widening module 122 of this application embodiment can achieve frequency adjustment by widening the narrow pulse generated when the voltage transiently drops.

[0069] In some embodiments, the level broadening module 122 is used to output the output signal of the data output terminal of the last stage register as a voltage detection signal based on a preset output polarity; or, based on a preset output polarity, to output the output signal of the data output terminal of the last stage register as a voltage detection signal via an inverter.

[0070] Optionally, the voltage detection signal is 0 or 1, and the voltage detection signal is determined based on whether the voltage detection point is active high or active low.

[0071] Optionally, the output polarity can be configured via parameters. For example, different parameters can correspond to either a non-inverting output (direct output) or an inverting output (after an inverter).

[0072] See Figure 4 As shown, the working principle of frequency adjustment circuit 1 mainly includes the following: (1) Input signals: clock_in, rst_n, enable, target_freq[X-1:0], indicator_1, ..., indicator_Y, where the number of indicators is determined according to the actual voltage detection points to be detected, and the output signal is clock_out.

[0073] In this context, `clock_in` represents the original clock signal, `rst_n` is the reset signal used for register reset, `enable` represents the enable signal, `target_freq[X-1:0]` represents the target frequency control signal, `X` represents the bit width of the target frequency control signal, `indicator_1`, ..., `indicator_Y` correspond to the detected voltages from voltage detection point 1 to voltage detection point Y, and `clock_out` corresponds to the target clock signal. In clock selection unit 13, `n-1` represents the number of input clock signals that can be switched.

[0074] (2) Construct the voltage indication aggregation logic of the voltage indication aggregation module 121, and aggregate the multiple input detection voltages, which can be voltage reduction indication signals, through a logical AND operation to obtain a voltage indication signal.

[0075] (3) Construct a level widening module 122 (high-level widening or low-level widening can be selected by parameterization). The level widening module 122 can be cascaded through multiple registers. The data input terminal of the first register is fixed to 1 or 0 (this polarity value can be configured by parameterization). The inputs of the clock signal (using the original clock signal) and the reset signal (using the voltage indication signal) are connected as shown in Figure 4. The output of the last register is output after passing through an inverter or directly output (the output polarity can be selected by parameterization). The level widening module 122 can widen the narrow pulses generated by rapid voltage changes to drive the subsequent frequency modulation logic.

[0076] (4) Perform a logical AND operation between the voltage detection signal output by the level widening module 122 and the target frequency control signal target_freq[X-1:0] input by the external input to output the clock frequency selection signal.

[0077] (5) Perform a logical AND operation between the clock frequency selection signal output in step (4) and the externally input enable signal to realize the enable control of the frequency adjustment function and output the final clock frequency selection signal.

[0078] The logical AND operation of (4) and / or (5) can also be replaced by the following method: by inverting the signal accordingly, the logical "OR" can be used, or other circuit structures that can achieve the same logical function.

[0079] (6) The input original clock signal is passed through several frequency divider modules to obtain several clock signals with different clock frequencies to be selected.

[0080] (7) Select multiple clock signals with different clock frequencies obtained in step (6) and the original input clock signal "clock_in". The glitch-free clock switching module is a pure hardware clock switching. The glitch-free clock switching module is completed through cross feedback to achieve fast clock frequency switching.

[0081] Alternatively, in addition to using cross-feedback, the glitch-free clock switching module can also use a hardware state machine, which detects the need for frequency adjustment and then uses the state machine to first turn off the original clock and then turn on the new clock.

[0082] (8) Use the clock frequency selection signal output in step (5) as the clock selection signal of the glitch-free clock switching module, and finally obtain the target clock signal "clock_out" for system functions.

[0083] Based on the above technical solution, the frequency adjustment circuit 1 of this application embodiment has at least the following technical effects: (1) Simplified structure and low resource consumption: Through the simplified circuit structure, the purpose of fast frequency adjustment is achieved when the voltage drop is detected. At a very low cost, the clock selection unit 13 completes fast clock switching through simple logic gates, registers and frequency divider modules. It is system-friendly and completes the frequency adjustment function without increasing the logic resources significantly.

[0084] (2) Easy to integrate: The interface of the frequency adjustment circuit 1 is simple and can be easily integrated into the original clock module. It is only necessary to break the original clock path and connect the "clock_in" and "clock_out" of the frequency adjustment circuit 1 to the two ends of the broken clock. At the same time, it supports the enable switch of this function and can remain transparent to the original clock structure when not needed. In the embodiments of this application, the frequency adjustment circuit 1 can be inserted into the clock path where the frequency needs to be adjusted to complete the frequency adjustment of multiple clocks in the system.

[0085] (3) Good scalability: The frequency adjustment circuit 1 can support multiple voltage detection points. That is, for the frequency adjustment of the same clock tree, the adjustment can be completed by combining the voltage conditions of multiple physical points on the chip to cover the differences of different physical points. At the same time, the frequency adjustment circuit 1 can be applied to different clock trees through multiple instances to complete the all-round control of the system and ensure the stability of the system. For the frequency divider module, multiple instances can also be added to achieve multiple target frequencies and complete fine clock adjustment.

[0086] This application provides a clock generator, including a frequency adjustment circuit 1. The frequency adjustment circuit 1 is disposed on the clock path of the clock generator.

[0087] This application provides a chip, including: a frequency adjustment circuit 1; or, a clock generator.

[0088] See Figure 5 As shown, this application provides a flowchart of a frequency adjustment method. Figure 5 As shown, the frequency adjustment method of this application embodiment is applied to the frequency adjustment circuit 1, and the frequency adjustment method includes steps S501 to S503.

[0089] S501. Based on the frequency division parameters of each frequency divider module, the original clock signal is divided to obtain each selectable clock signal; the frequency of the selectable clock signal is lower than that of the original clock signal.

[0090] Step S501 can be implemented by the frequency divider unit 11.

[0091] S502. Generate a clock frequency selection signal based on the detected voltage at at least one voltage detection point and the target frequency control signal input externally.

[0092] Step S502 can be implemented by the frequency modulation control unit 12.

[0093] S503. When any detection voltage drops, based on the clock frequency selection signal, select one of the selectable clock signals as the target clock signal for output.

[0094] Step S503 can be implemented by the clock selection unit 13.

[0095] Optionally, a clock frequency selection signal is generated based on the detected voltage at at least one voltage detection point and an externally input target frequency control signal, including: performing logical operations on the detected voltages at at least two input voltage detection points to output a voltage indication signal; performing level widening on the voltage indication signal to output a voltage detection signal; the voltage detection signal is used to indicate voltage changes; and performing logical operations on the externally input target frequency control signal and the voltage detection signal to generate the clock frequency selection signal.

[0096] Optionally, a clock frequency selection signal is generated by performing logical operations on the target frequency control signal and voltage detection signal input by external input, including: performing logical operations on the target frequency control signal and voltage detection signal to output a frequency selection indication signal; and performing logical operations on the frequency selection indication signal and an externally input enable signal to output a clock frequency selection signal.

[0097] Optionally, the voltage indication signal is level-widened, and the output voltage detection signal includes: level-widening the voltage indication signal based on the polarity value and at least two registers to obtain the voltage detection signal.

[0098] Optionally, based on the polarity value and at least two registers, the voltage indication signal is level-widened to obtain a voltage detection signal, including: outputting the output signal of the data output terminal of the last register as a voltage detection signal based on a preset output polarity; or, outputting the output signal of the data output terminal of the last register as a voltage detection signal via an inverter based on a preset output polarity.

[0099] The implementation principle of the frequency adjustment method in this application embodiment is similar to that of each unit or module of the frequency adjustment circuit 1. For a detailed functional description of the frequency adjustment method in this application embodiment, please refer to the description of each unit or module in the frequency adjustment circuit 1 shown above, which will not be repeated here.

[0100] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0101] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0102] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0103] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0104] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0105] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0106] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A frequency adjustment circuit, characterized in that, include: The frequency divider unit includes at least one frequency divider module, which is used to divide the original clock signal according to the frequency division parameters of each frequency divider module to obtain each selectable clock signal; the frequency of the selectable clock signal is lower than that of the original clock signal. A frequency modulation control unit is used to generate a clock frequency selection signal based on the detected voltage at at least one voltage detection point and an externally input target frequency control signal. The clock selection unit is electrically connected to both the frequency divider unit and the frequency modulation control unit. When any of the detection voltages drops, it selects one of the clock signals to be selected as the target clock signal based on the clock frequency selection signal.

2. The frequency adjustment circuit according to claim 1, characterized in that, The frequency modulation control unit includes: The voltage indication aggregation module is used to perform logical operations on the detected voltages from at least two input voltage detection points and output a voltage indication signal; A level broadening module, electrically connected to the voltage indication convergence module, is used to broaden the voltage indication signal and output a voltage detection signal; the voltage detection signal is used to indicate voltage changes. The frequency selection control module is electrically connected to both the level widening module and the clock selection unit. It is used to perform logical operations based on the externally input target frequency control signal and the voltage detection signal to generate a clock frequency selection signal.

3. The frequency adjustment circuit according to claim 2, characterized in that, The frequency selection control module includes: The target frequency control module is electrically connected to the level widening module and is used to perform logical operations on the target frequency control signal and the voltage detection signal to output a frequency selection indication signal. The frequency modulation enable control module is electrically connected to both the target frequency control module and the clock selection unit. It is used to perform logical operations on the frequency selection indication signal and the externally input enable signal to output a clock frequency selection signal.

4. The frequency adjustment circuit according to claim 3, characterized in that, The target frequency control module is used to perform a logical AND operation on the target frequency control signal and the voltage detection signal, and output a frequency selection indication signal; or, to sequentially perform signal inversion and logical OR operation on the target frequency control signal and the voltage detection signal, and output a frequency selection indication signal. And / or, the frequency modulation enable control module is used to perform a logical AND operation on the frequency selection indication signal and the externally input enable signal to output a clock frequency selection signal; or, the frequency selection indication signal and the externally input enable signal are sequentially inverted and then logically ORed to output a clock frequency selection signal.

5. The frequency adjustment circuit according to claim 2, characterized in that, The level widening module includes at least two cascaded registers. The data input terminal of the first register is configured with a polarity value, which is used to indicate the level that needs to be widened. The level broadening module is used to broaden the voltage indication signal based on the polarity value and at least two levels of the registers to obtain a voltage detection signal.

6. The frequency adjustment circuit according to claim 5, characterized in that, The level broadening module is used to output the output signal of the data output terminal of the last stage register as the voltage detection signal based on a preset output polarity; or, based on a preset output polarity, to output the voltage detection signal by an inverter from the output signal of the data output terminal of the last stage register.

7. The frequency adjustment circuit according to any one of claims 1-6, characterized in that, The target frequency control signal includes a bit width for representing the target frequency control signal, the bit width being determined based on the number of clock signals to be selected.

8. A clock generator, characterized in that, include: The frequency adjustment circuit as described in any one of claims 1-7; The frequency adjustment circuit is located on the clock path of the clock generator.

9. A chip, characterized in that, include: The frequency adjustment circuit as described in any one of claims 1-7; Alternatively, the clock generator as described in claim 8.

10. A frequency adjustment method, characterized in that, Applied to the frequency adjustment circuit as described in any one of claims 1-7, comprising: Based on the frequency division parameters of each frequency divider module, the original clock signal is divided to obtain each selectable clock signal; the frequency of the selectable clock signal is lower than that of the original clock signal. A clock frequency selection signal is generated based on the detected voltage at at least one voltage detection point and the target frequency control signal input externally. When any of the detected voltages drops, based on the clock frequency selection signal, one of the selected clock signals is selected as the target clock signal for output.

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