Audio and video interface protocol analysis system and method capable of being dynamically reconfigured

Abstract

The invention relates to the technical field of audio and video protocol analysis, in particular to a dynamically reconfigurable audio and video interface protocol analysis system and method. The system is composed of a pluggable physical interface switching board card, a protocol analysis hardware board card and a computer application end. The protocol analysis hardware board card takes an FPGA supporting partial reconfiguration as a core, and logic resources of the protocol analysis hardware board card are divided into a static area and a dynamic reconfiguration area. A main control unit, a reconstruction management module and an upper computer interface module are integrated in the static area; the dynamic reconfigurable area comprises a protocol coding and decoding function module, a link training function module, a protocol management function module and the like. And the physical interface switching board card is integrated with a storage unit for storing an identity label. After the adapter board card is inserted, the main control unit reads and reports the identity label of the adapter board card, and the computer application end calls the corresponding logic bit stream file from the reconstruction file warehouse according to the reported label and issues the logic bit stream file to the reconstruction management module. The module performs partial reconstruction on a dynamic reconfigurable area through an FPGA internal configuration port and loads target protocol processing logic, and then a system establishes a link, executes test cases issued by an application end, captures target protocol data and uploads the target protocol data to the application end for analysis and processing. According to the invention, an analysis function of adapting to various audio and video protocols on a single hardware platform through dynamic reconstruction of FPGA logic is realized, and the method has the remarkable advantages of plug and play, convenience in upgrading, high resource utilization rate, low cost and the like.

Description

Technical Field

[0001] This invention relates to the field of audio and video protocol analysis technology, and in particular to a dynamically reconfigurable audio and video interface protocol analysis system and method. Background Technology

[0002] With the rapid development of audio and video technology, multiple audio and video interface standards such as HDMI, DisplayPort, and USB coexist and iterate rapidly. Traditional protocol analyzers are usually designed for specific interface protocols, and supporting different protocols requires independent hardware platforms, forcing testing companies to purchase multiple devices, resulting in high costs.

[0003] While existing technologies offer solutions for integrating multiple interface circuits onto a single hardware platform to support multiple protocols, such architectures have inherent drawbacks: integration of multiple interfaces is difficult on resource-constrained chip platforms; while using high-specification chips with abundant logic resources can meet integration requirements, it significantly increases hardware costs. Furthermore, this solution lacks scalability, making it difficult to flexibly adapt to emerging audio and video interface standards, and its functional expansion is clearly limited. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a dynamically reconfigurable audio and video interface protocol analysis system and method to resolve the contradiction between multi-protocol compatibility, equipment cost and upgrade flexibility.

[0005] A dynamically reconfigurable audio / video interface protocol analysis system is characterized by comprising a pluggable physical interface adapter board, a protocol analysis hardware board, and a computer application terminal. The physical interface adapter board includes a protocol information storage unit, an electrical characteristic adaptation module, and an FMC interface; the protocol analysis hardware board includes an FPGA and on-chip logic, a host computer interface, and an FMC interface; the computer application terminal includes a reconfigurable file repository, a protocol analysis module, and a protocol test case set.

[0006] Furthermore, the reconstructed file repository is used to store logical bitstream files mapped to different identity identifiers.

[0007] Furthermore, the protocol information storage unit is used to store the identification identifiers of the audio and video interfaces used on the corresponding physical interface adapter board. Preferably, the protocol information storage unit is implemented using a non-volatile EEPROM.

[0008] Optionally, the identity identifier can be expanded to a data structure that is not limited to a protocol type identifier, and may include the following fields: protocol type identifier, protocol version number, maximum supported link rate, and electrical characteristic parameter index. The protocol type identifier is used to distinguish different audio / video interface protocols such as HDMI, DisplayPort, and USB; the protocol version number identifies the specific protocol version supported; the maximum link rate indicates the maximum link rate supported by the adapter board; and the electrical characteristic parameter index points to the electrical configuration parameters of the adapter board's electrical characteristic adaptation module, used to guide the FPGA SerDes interface in performing accurate electrical adaptation.

[0009] Furthermore, the electrical characteristic adaptation module is integrated onto the physical interface adapter board, serving as an analog front-end connecting the audio / video interface and the internal FPGA SerDes interface. Its core function is to condition and impedance match high-speed differential signals for different audio / video interface physical and electrical layer standards to ensure signal integrity.

[0010] Preferably, the FPGA of the protocol analysis hardware board is the AMD Xilinx VIRTEX Ultra SCALE+ series XCVU13P.

[0011] Furthermore, the on-chip logic resources of the FPGA are divided into a static area and a dynamically reconfigurable area. The main control unit, reconfiguration management module, and host computer interface module are assigned to the static area; the protocol high / low speed encoding / decoding module, SerDes interface and general I / O interface, protocol link training state machine, protocol management and control module, and protocol cache module are assigned to the dynamically reconfigurable area.

[0012] Furthermore, the main control unit is used to identify the insertion and removal detection of physical interface adapter cards, read the identity identifier of audio and video interfaces and forward it to the computer application terminal, and process the protocol test cases issued by the application terminal.

[0013] Furthermore, the reconstruction management module is used to receive the logical bitstream file and, under the trigger of the main control unit, reconstruct the dynamically reconfigurable area through the FPGA configuration interface to load the target protocol processing logic corresponding to the identity identifier.

[0014] Furthermore, the protocol management and control module is used to implement the management and control plane processing in the audio and video interface protocol. Based on the currently loaded protocol specification, it parses the management and control messages from the device under test and reports them to the main control unit; it receives and executes test instructions from the main control unit, generates corresponding management and control messages, and interacts with the device under test.

[0015] Furthermore, the protocol caching module is used to capture the output data from the protocol high / low speed encoding / decoding module and forward it to the computer application terminal for protocol analysis through the host computer interface module.

[0016] Furthermore, the host computer interface module is specifically implemented using the PCIe high-speed serial computer expansion bus standard. Preferably, a PCIe GEN3X16 interface link is used to provide sufficiently high data transmission bandwidth to meet the real-time upload requirements of the massive data streams generated by ultra-high-definition audio and video protocol analysis.

[0017] Furthermore, the protocol link training state machine internally encapsulates the complete link training state process, strictly follows the specification requirements of the target audio and video interface protocol standard, and achieves negotiation and establishment of a stable physical link connection with the device under test by executing the training sequence defined by the protocol.

[0018] Corresponding to the above system, the present invention also provides a dynamically reconfigurable audio / video interface protocol analysis method, the method comprising the following steps:

[0019] S1. Insert the physical interface adapter card corresponding to the audio / video interface used by the device under test into the protocol analysis hardware board.

[0020] S2. The main control unit of the protocol analysis hardware board reads the identity identifier stored in the adapter board and reports it to the computer application terminal.

[0021] S3. The computer application retrieves the corresponding logical bitstream file from the reconstructed file repository based on the identity identifier, and feeds back the retrieval result to the main control unit.

[0022] S4. The main control unit triggers the reconfiguration management module to receive the logic bitstream file. The reconfiguration management module performs partial reconfiguration of the dynamically reconfigurable area through the FPGA internal configuration port and loads the processing logic of the target protocol.

[0023] S5. Connect the device under test (DUT) using a cable. The system then trains the state machine using the protocol link already loaded in the dynamically reconfigurable zone, and executes a complete link training sequence with the DUT. The state machine sends configuration requests or training codes to the DUT through the high-speed codec module; simultaneously, the codec module receives and parses the response information from the DUT and feeds it back to the state machine; based on this, the state machine evaluates the link quality and decides on the next round of parameter adjustments. Through multiple "request-response" interaction loops, the system finally reaches an agreement with the DUT on the link configuration and establishes a stable and reliable physical connection.

[0024] S6. The computer application terminal issues test cases, and the main control unit configures and calls the management control module according to the test cases, and starts message interaction between devices through the interaction of management messages.

[0025] S7. During the test execution, audio and video protocol data from the device under test enters the system via the audio and video interface and electrical characteristic adaptation module of the physical adapter board. The encoding and decoding module of the FPGA dynamic reconfigurable area performs real-time parsing of the signal. The generated protocol data packets are captured and temporarily stored by the protocol buffer module, and then uploaded to the computer application through the host computer interface. The protocol analysis module of the computer application analyzes the uploaded data.

[0026] Furthermore, the set of protocol test cases is characterized by being designed in strict accordance with the audio and video interface standard protocol specifications and consistency test standards, including but not limited to link layer training state testing, management and control layer protocol testing, and high-speed audio and video protocol testing.

[0027] As can be seen from the technical solution, this invention achieves efficient utilization of hardware resources and adaptive compatibility of multiple protocols through dynamic reconfiguration methods and architectures. While improving system flexibility and scalability, it significantly reduces equipment costs, and has important practical value and prospects for promotion. Attached Figure Description

[0028] Figure 1 This is a block diagram of a dynamically reconfigurable audio / video interface protocol analysis system.

[0029] Figure 2 This is a schematic diagram of a dynamically reconfigurable audio / video interface protocol analysis method. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the present invention will be further analyzed and described in detail below with reference to the accompanying drawings and specific examples. It should be understood that the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0031] Taking the analysis of specific audio and video interface protocols as an example, such as Figure 1 The diagram shows a block diagram of a dynamically reconfigurable audio / video interface protocol analysis system. The system comprises three main parts: a physical interface adapter board, a protocol analysis hardware board, and a computer application terminal. The physical interface adapter board has specific audio / video interface sockets at its front end, connecting to the device under test via cables. The adapter board itself is attached to the protocol analysis hardware board via an FMC interface. The protocol analysis hardware board is a PCIe Gen3x16-based data acquisition card, plugged into a PCIe Gen3x16-compatible computer motherboard. The computer contains protocol analysis software, forming a complete analysis system.

[0032] Specifically, the core function of the physical interface adapter board is to realize physical signal adaptation and identification. Therefore, it integrates an EEPROM protocol information storage unit to meet the interface identification requirements. This storage unit is pre-programmed with structured identification data when the adapter board leaves the factory. The identification data structure includes the following key fields: protocol type identifier (ID), protocol version number (Version), and electrical configuration parameter (Electric_Param) of the electrical characteristic adaptation module.

[0033] Specifically, the physical interface adapter board and the protocol analysis hardware board are interconnected via a high-pin-count FMC interface compliant with the VITA 57.4 standard. This interface provides ample high-speed signal routing capabilities, including up to 80 pairs of differential signal channels, with a single-channel signal rate supporting over 28Gbps, and hundreds of single-ended I / O resources. The extremely high bandwidth and rich pin definitions of this type of interface can fully meet the data transmission and control signal requirements of various high-speed audio and video protocols.

[0034] Specifically, the FPGA of the protocol analysis hardware board is the AMD Xilinx VIRTEX Ultra SCALE+ series XCVU13P.

[0035] Specifically, the main control unit is implemented using a Xilinx MicroBlaze soft-core processor.

[0036] Specifically, the reconstruction management module achieves reconstruction through the internal configuration access port ICAP. The reconstruction management module obtains the logical bitstream file from the computer application terminal through the host computer interface, and writes it into the configuration memory corresponding to the dynamic reconfigurable area through the internal configuration access port ICAP, thereby completing the complete switch of the specific audio and video interface protocol analysis function logic at the hardware level.

[0037] More specifically, Figure 2 This is a schematic diagram of a dynamically reconfigurable audio / video interface protocol analysis method according to the present invention. It illustrates the workflow from replacing the specific physical adapter board of the audio / video interface, to the dynamic reconfiguration of the FPGA dynamic area, and then to executing test commands to complete the audio / video protocol analysis. The specific implementation steps are as follows:

[0038] Step 1: The user / tester inserts the corresponding physical interface adapter card into the protocol analysis hardware card of this system according to the specific audio / video interface used by the device under test.

[0039] Step 2: The main control unit detects the hardware connection event generated by the insertion operation, and then accesses the EEPROM on the adapter board through the low-speed control bus I2C to read the pre-stored identity identifier. After the identity identifier is encapsulated by the main control unit, it is reported to the computer application through the host computer interface.

[0040] Step 3: Reconstruct the file repository. Based on the index in the information, locate and retrieve the logical bitstream file that exactly matches it, and feed the retrieval results back to the main control unit of the protocol analysis hardware board.

[0041] Step four: The main control unit triggers the reconfiguration management module to start the dynamic reconfiguration process. The reconfiguration management module obtains the logic bitstream file through the host computer interface, and then precisely configures the received bitstream data into the FPGA's dynamic reconfigurable area through the FPGA's internal configuration access port, completing the logic reconfiguration.

[0042] Step 5: Connect the device under test (DUT) using a cable. The system then trains the state machine using the protocol link already loaded in the dynamically reconfigurable zone, and executes a complete link training sequence with the DUT. The state machine sends configuration requests or training codes to the DUT through the high-speed codec module; simultaneously, the codec module receives and parses the response information from the DUT and feeds it back to the state machine; based on this, the state machine evaluates the link quality and decides on the next round of parameter adjustments. Through multiple "request-response" interaction loops, the system finally reaches an agreement with the DUT on the link configuration, establishing a stable and reliable physical connection.

[0043] Step six: The computer application sends out test cases, the main control unit parses the test commands, configures or calls the protocol management and control module, and initiates protocol interaction between devices by encapsulating auxiliary control messages that conform to the protocol standard or triggering relevant protocol events.

[0044] Step seven: During the test execution, audio and video protocol data from the device under test enters the system via the audio and video interface and electrical characteristic adaptation module of the physical adapter board. The encoding and decoding module of the FPGA's dynamic reconfigurable area performs real-time parsing of the signal. The generated protocol data packets are captured and temporarily stored by the protocol caching module, and then uploaded to the computer application through the host computer interface. Finally, the protocol analysis module on the computer application performs compliance analysis, protocol consistency checks, and displays the packet content and analysis results, completing a comprehensive analysis of the entire audio and video interface protocol.

[0045] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A dynamically reconfigurable audio / video interface protocol analysis system, characterized in that, It includes a pluggable physical interface adapter board, a protocol analysis hardware board, and a computer application terminal; the physical interface adapter board includes a protocol information storage unit, an electrical characteristic adaptation module, and an FMC interface; the protocol analysis hardware board includes an FPGA and on-chip logic, a host computer interface, and an FMC interface; the computer application terminal consists of a reconstructed file repository, a protocol analysis module, and a protocol test case set.

2. The system according to claim 1, characterized in that, The physical interface adapter board is connected to the protocol analysis hardware board via the FMC interface; the protocol analysis hardware board is connected to the computer application terminal via the host computer interface module.

3. The system according to claim 1, characterized in that, The protocol information storage unit is used to store the identity identifiers of the audio and video interfaces used on the corresponding physical interface adapter board.

4. The system according to claim 1, characterized in that, The reconstructed file repository is used to store logical bitstream files corresponding to different identity identifiers.

5. The system according to claim 1, characterized in that, The protocol analysis module is used to parse and verify the captured audio and video protocol data according to predefined protocol specifications.

6. The system according to claim 1, characterized in that, The FPGA and on-chip logic have their internal logic resources divided into a static area and a dynamic reconfigurable area. The static area includes a main control unit, a reconfiguration management module, and a host computer interface module. The dynamic reconfigurable area includes a protocol high / low speed encoding / decoding module, a SerDes interface and a general IO interface, a protocol link training state machine, a protocol management and control module, and a protocol cache module.

7. The system according to claim 6, characterized in that, The SerDes interface is configured with a high-speed transceiver of the FPGA and is used to transmit and receive high-speed serial differential signals between the protocol analysis hardware board and the physical interface adapter board, thereby realizing the transmission and reception of high-speed audio and video signals. The general-purpose I / O interface is composed of the programmable input and output pin resources of the FPGA and is used to transmit and receive auxiliary signals related to the audio and video interface protocol.

8. The system according to claim 6, characterized in that, The main control unit is used for detecting the insertion and removal of the physical interface adapter board, reading the identity identifier of the audio and video interface and forwarding it to the computer application terminal, and executing the protocol test cases issued by the application terminal.

9. The system according to claim 6, characterized in that, The protocol management and control module is used to implement the management and control plane processing in the audio and video interface protocol. Based on the currently loaded protocol specification, it parses the management and control messages from the device under test and reports them to the main control unit. It also receives and executes the configuration instructions from the main control unit and generates corresponding management and control messages to be sent to the device under test.

10. The system according to claim 6, characterized in that, The reconstruction management module is used to receive the logical bitstream file and, under the trigger of the main control unit, partially reconstruct the dynamically reconfigurable area through the internal configuration access port of the FPGA to load the target protocol processing logic corresponding to the identity identifier.

11. A method for analyzing dynamically reconfigurable audio / video interface protocols, characterized in that, Based on the system implementation of claim 1, the method includes the following steps: 1) Insert the physical interface adapter card corresponding to the audio / video interface of the device under test into the protocol analysis hardware board; 2) The main control unit of the protocol analysis hardware board reads the identity identifier stored in the adapter board and reports it to the computer application terminal; 3) The computer application retrieves the corresponding logical bitstream file from the reconstructed file repository based on the identity identifier, and sends the retrieval result to the main control unit of the protocol analysis hardware board; 4) The main control unit triggers the reconfiguration management module to obtain the logic bitstream file. The reconfiguration management module reconfigures the dynamically reconfigurable area through the FPGA internal configuration port and loads the processing logic of the target protocol. 5) Connect the device under test (DUT) with a cable. The system then trains the state machine through the loaded protocol link in the dynamically reconfigurable zone and executes a complete link training sequence with the DUT. The state machine sends configuration requests or training codes to the DUT through the high-speed codec module. At the same time, the codec module receives and parses the response information of the DUT and feeds it back to the state machine. The state machine evaluates the link quality and decides on the next round of parameter adjustments based on this. Through multiple "request-response" interaction loops, the system finally reaches an agreement with the DUT on the link configuration and establishes a stable and reliable physical connection. 6) The computer application terminal issues test cases, and the main control unit configures and calls the management control module according to the test cases. It then initiates message interaction between devices by encapsulating auxiliary control messages that conform to the protocol standard or triggering relevant protocol events. 7) During the test execution, audio and video protocol data from the device under test enters the system through the audio and video interface and electrical characteristic adaptation module of the physical adapter board. The encoding and decoding module of the FPGA dynamic reconfigurable area performs real-time analysis of the signal. The generated protocol data packets are captured and temporarily stored by the protocol cache module, and then uploaded to the computer application terminal through the host computer interface. The protocol analysis module of the computer application terminal analyzes the uploaded data.

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