Verification method and verification device for standard cell library

Abstract

The invention provides a verification method and a verification device for a standard cell library. Standard units to be tested are classified into combinational logic units and sequential logic units, then classification is carried out according to the number of output ports, simulation is carried out on different types of standard units to be tested, problems can be found in time, and adjustment and debugging can be carried out in time; the input ports of the same type of the combinatorial logic unit and the sequential logic unit are integrated, so that the input ports with the same function correspond to the same bit test vector, redundant test vectors are removed, and the verification time is shortened; the simulation output in the simulation process is collected while simulation is executed, and the top layer output end and the simulation analysis end are connected at the same time, so that it is ensured that output signals of the same standard unit to be tested are simultaneously tested by a machine table and collected by a simulation test, verification accuracy is improved, excessive dependence on the test machine table is avoided, and verification efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of wafer testing, and more particularly to a verification method and apparatus for a standard cell library. Background Technology

[0002] New process platforms developed by wafer fabs are designed with corresponding standard cell libraries. These new standard cell libraries require verification under various process parameters (Pressure, Volume, Temperature, or PVT conditions) to assess logic functionality, timing, power consumption, and other aspects. This typically necessitates the design of dedicated functional test circuits or chips to test the functionality of all standard cells within the library.

[0003] However, a standard cell library typically contains thousands of different types of standard cells, making manual verification impractical. The key to the entire design verification process lies in how to quickly verify the functionality of standard cells and debug problematic parts of the design.

[0004] When testing a standard cell library using traditional functional test circuits, all possible test vectors are input into the standard cell. The output signals collected on the test equipment are then compared with the expected values ​​in the test vector (Pattern) file to determine whether the standard cell's logic function is correct. This approach has several problems: First, the test results are all output from the test equipment, so this method requires waiting for the tape-out results, making it inconvenient to simulate and analyze the output results of the entire test circuit during development, as well as to adjust and debug problems discovered during the development process in a timely manner; second, the test vectors of a standard cell library are often very long, with tens of thousands or even hundreds of thousands of lines, thus requiring the use of methods that automatically generate test vectors for comparison.

[0005] Providing a verification method for a standard cell library that can shorten the development and testing time of the entire project, improve the verification efficiency of standard test circuits, and reduce the risks of the entire development process is of great significance. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a verification method and verification device for a standard cell library, which can shorten the development and testing time of the entire project and improve the verification efficiency of the standard cell test circuit.

[0007] To address the above problems, this invention provides a method for verifying a standard cell library, comprising: The standard units under test are classified into combinational logic units and sequential logic units, both of which include single-output ports and multiple-output ports. Input-output relationships are extracted for each category of the standard units under test, and a logic relationship truth table is formed. This truth table is used to generate test vectors and expected results for different categories and numbers of input ports of the standard units under test. Input ports of the same type for both combinational logic units and sequential logic units are integrated, ensuring that input ports with the same function correspond to the same bit in the test vector. The test vector is accessed from the top-level input terminal. A simulation test file is generated and executed accordingly. The simulation output of the standard units under test is collected during the simulation process, and this simulation output is simultaneously accessed from the top-level output terminal and the simulation analysis terminal. When the simulation output of all the standard units under test meets the expected results, a machine test file is generated using the simulation output collected from the top-level output terminal, and machine testing is performed.

[0008] In some embodiments, the step of classifying the standard unit under test into combinational logic units and sequential logic units, wherein both the combinational logic units and the sequential logic units include single-output ports and multiple-output ports, specifically includes: Instances of different types of standard unit libraries under test are integrated into the same unit library file, and the name, logic information, and output port information of the standard unit under test are extracted from the unit library file. According to the name or logic information of the standard unit under test, the standard unit under test is classified into combinational logic units and sequential logic units. According to the output port information, the combinational logic units are classified into single-output-port combinational logic units and multi-output-port combinational logic units, and the sequential logic units are classified into single-output-port sequential logic units and multi-output-port sequential logic units.

[0009] In some embodiments, the type of the standard unit library to be tested includes: a basic standard unit library, an engineering change unit library, and a process matching unit library; the output port information includes the output port name and the number of output ports.

[0010] In some embodiments, the step of extracting the input-output relationship for each category of the test standard unit and summarizing it to form a logical relationship truth table further includes: For each combinational logic unit, the logical relationships of the combinational logic units are extracted from the parameter library, and corresponding combinational logic output results are generated for different test inputs; for each sequential logic unit, sequential logic verification and sequential convergence design are performed to generate sequential logic verification results; the combinational logic output results and the sequential logic verification results are summarized to form the truth table of the logical relationships.

[0011] In some embodiments, when the simulation output of all the standard units under test meets the expected results, a machine test file is generated from the simulation output collected from the top output terminal and its corresponding standard unit selection signal and test vector, and the machine test is executed. The machine test output signal is collected and compared with the machine test file to output the machine test result. When the simulation output of the standard unit under test does not meet the expected results, the standard unit under test with logical errors and its corresponding test vector are identified.

[0012] To address the above problems, the present invention also provides a verification apparatus for a standard cell library, comprising: The test standard unit module is used to access the test standard units, which are classified into combinational logic units and sequential logic units. Both the combinational logic units and the sequential logic units include single output ports and multiple output ports. The input-output relationship is extracted for each category of the test standard unit and summarized to form a logic relationship truth table. Based on the logic relationship truth table, test vectors and expected results are generated for different categories and the number of input ports of the test standard units. Input ports of the same type of combinational logic units and sequential logic units are integrated so that input ports with the same function correspond to the same bit of the test vector. The test vector is connected to the test standard unit module from the top-level input terminal and input to the input terminal of the test standard unit. The output ports of the test standard units are connected to the output ports of the test standard unit module according to the number of output ports of the test standard units. The signal selection output module consists of multiple matrix decoders. The signal of each output port of the standard unit under test module corresponds to one of the matrix decoders. The matrix decoder selects the simulation output of the standard unit under test according to the input standard unit selection signal. During the simulation process, the simulation output is simultaneously connected to the top-level output terminal and the simulation analysis terminal. When the simulation output of all the standard units under test meets the expected results, the simulation output collected by the top-level output terminal is used to generate a machine test file and perform machine testing.

[0013] In some embodiments, connecting the output ports of the standard unit under test (SUBT) to the output ports of the SUBT module according to the number of output ports of the SUBT specifically includes: When the number of output ports of the standard unit under test is a single one, the output signal of the standard unit under test is sequentially connected to a single output port of the standard unit under test module; when the number of output ports of the standard unit under test is N, the N output signals of the standard unit under test are respectively connected to and output in parallel to the N output ports of the standard unit under test module, wherein N is greater than or equal to 2.

[0014] In some embodiments, the verification apparatus for the standard cell library further includes: The delay module includes inherent delay processing and two-level registers. The delay module is used to synchronously process a preset result signal and output the desired result. The output calibration module is used to compare the simulation output of the standard unit under test with the expected result to confirm whether the simulation output of the standard unit under test meets the expected result. The output calibration module also outputs a test analysis file, which is used to calibrate the standard unit under test with logical errors and its corresponding test vector.

[0015] In some embodiments, the number of output ports of the standard unit under test module is four, the number of matrix decoders is four, and the number of output ports of the standard unit under test is less than or equal to four.

[0016] In some embodiments, the verification apparatus for the standard cell library further includes an input driving module and an output driving module, wherein the input driving module is used to enhance the strength of the input signal and the output driving module is used to enhance the strength of the output signal.

[0017] In some embodiments, the standard cell selection signal is input from the top-level input terminal to the signal selection output module and then to the matrix decoder, wherein the matrix dimension of the matrix decoder is less than or equal to 2. n * m, where n is the bit width of the selection signal of the standard unit under test; m is the bit width of the test vector.

[0018] The above technical solution, by classifying the standard unit under test into combinational logic units and sequential logic units, and further classifying them according to the number of output ports, extracts the input-output relationships of different categories of standard units under test and performs simulations, enabling timely detection, adjustment, and debugging of problems. By integrating the same type of input ports of the combinational logic units and the sequential logic units respectively, input ports with the same function correspond to the same bit test vector, eliminating redundant test vectors and shortening the verification time. By simultaneously acquiring the simulation output during the simulation process and connecting it to the top-level output terminal and the simulation analysis terminal, it ensures that the output signal of the same standard unit under test is simultaneously acquired by the machine test and simulation test, improving the accuracy of verification, solving the over-reliance on the test machine, and improving verification efficiency.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart of a verification method for a standard cell library provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a verification device for a standard unit library provided in an embodiment of the present invention; Figure 3 This is a discrete unit mapping diagram of a matrix decoder provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the delayed sampling comparison structure provided in an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] In this invention, the top-level input terminal refers to the port exposed to the outside of the chip for receiving external signals, and the top-level output terminal refers to the port exposed to the outside of the chip for outputting response signals from the internal circuitry of the chip.

[0024] Figure 1 This is a flowchart of a verification method for a standard unit library provided in an embodiment of the present invention.

[0025] like Figure 1 As shown, the verification method for the standard unit library includes: Step S11: Classify the standard unit under test into combinational logic units and sequential logic units. Both the combinational logic units and the sequential logic units include single output ports and multiple output ports.

[0026] In this embodiment, this step specifically includes: Step S111, integrating instances of different types of standard unit libraries under test into the same unit library file, and extracting the name, logic information, and output port information of the standard unit under test from the unit library file; Step S112, classifying the standard unit under test into combinational logic units and sequential logic units according to the name or logic information of the standard unit under test; Step S113, classifying the combinational logic units into single-output-port combinational logic units and multi-output-port combinational logic units according to the output port information, and classifying the sequential logic units into single-output-port sequential logic units and multi-output-port sequential logic units.

[0027] In step S111, instances of different types of standard unit libraries to be tested are integrated into a single file with the .v extension. The types of standard unit libraries to be tested include: base standard unit libraries, engineering change order (ECO) unit libraries, and process-matched kit (PMK) unit libraries.

[0028] The output port information includes the output port name and the number of output ports. The information extracted from the unit library file also includes input port information, which includes the input port name and the number of input ports.

[0029] In step S112, if the standard unit name contains the logical information of the unit, the standard unit under test can be classified into combinational logic units and sequential logic units according to the standard unit name of each standard unit under test; or the standard unit under test can be classified into combinational logic units and sequential logic units directly according to the logical information of the standard unit under test.

[0030] In step S113, the multi-output port combinational logic unit refers to a combinational logic unit with more than one output port, and the multi-output port sequential logic unit refers to a sequential logic unit with more than one output port. In some embodiments, the combinational logic units are classified according to the number of output ports as: single-port output combinational logic units, dual-port output combinational logic units, and other multi-port output combinational logic units; the sequential logic units are classified according to the number of output ports as: single-port output sequential logic units, dual-port output sequential logic units, and other multi-port output sequential logic units. The number of output ports for the other multi-port output combinational logic units and the other multi-port output sequential logic units is greater than 2 and less than or equal to 4. Further, the other multi-port output combinational logic units can be classified as three-port output combinational logic units and four-port output combinational logic units, and the other multi-port output sequential logic units can be classified as three-port output sequential logic units and four-port output sequential logic units.

[0031] Step S11 classifies the data in two ways: according to logical type and according to the number of port outputs.

[0032] Step S12: Extract the input-output relationship for each category of the test standard unit and summarize it to form a logical relationship truth table. The logical relationship truth table is used to generate test vectors and expected results for different categories and the number of input ports of the test standard unit.

[0033] Since the sequential logic unit requires clock driving and can store historical states, while the combinational logic unit's output is determined solely by the current input, the combinational logic unit and the sequential logic unit need to be processed separately.

[0034] This step further includes: Step S121, for each category of combinational logic units with a certain number of output ports, extracting the logical relationships of the combinational logic units from the parameter library, and generating corresponding combinational logic output results for different test inputs; for each category of sequential logic units with a certain number of output ports, performing sequential logic verification and sequential convergence design, and generating sequential logic verification results; Step S122, summarizing the combinational logic output results and the sequential logic verification results to form the logical relationship truth table.

[0035] In this embodiment, the parameter library is a feature characterization library, or K library for short.

[0036] The logic truth table describes the expected output of each test unit under all possible input signals, and does not necessarily have to be presented in tabular form. All possible inputs in the logic truth table can be used to generate test vectors of corresponding bit widths, and the expected simulation test results can be generated based on the correspondence between inputs and outputs in the logic truth table.

[0037] In this embodiment, test vectors are generated according to the different categories of the standard unit under test and the number of input ports.

[0038] Step S13: Integrate the input ports of the same type of combinational logic unit and sequential logic unit respectively, so that the input ports with the same function correspond to the same bit of the test vector, and the test vector is accessed from the top-level input terminal.

[0039] This step performs port mapping on the combinational logic units and sequential logic units according to their input port types to integrate the input ports of various types. For example, test vectors are generated for combinational logic units with the same number of input ports, and during circuit connection, input ports of the same type from these combinational logic units are connected to the same bit of the test vector. Input ports of the same type refer to input ports with the same functional type, including clock signals, reset signals, D signals, etc. This allows for the compression of the test vectors, ensuring that no redundant test vectors are generated during test vector traversal. Thus, the test time can be reduced while completing the test of the logic function of the standard unit under test.

[0040] Step S14: Generate a simulation test file and execute the simulation accordingly. Collect the simulation output of the standard unit under test during the simulation process. The simulation output is simultaneously connected to the top-level output terminal and the simulation analysis terminal.

[0041] In this embodiment, a simulation test file is generated based on the logical truth table, and the simulation is executed based on the simulation test file, wherein the simulation test file is a Testbench file.

[0042] The simulation outputs of different test standard units are selected via a standard unit selection signal. The standard unit selection signal and the test vector are connected to the top-level input terminal. Correspondingly, in the top-level module, the simulation output of the test standard unit during the simulation process is obtained from the top-level output terminal. The simulation output, along with the corresponding standard unit selection signal and the test vector, can be used to generate a machine test file.

[0043] In this step, the simulation output is collected, but the machine test file is not generated.

[0044] In this embodiment, the machine test is an Automatic Test Equipment (ATE) test, and the machine test file is a test pattern file.

[0045] The simulation analysis terminal is used to compare the simulation output of the standard unit under test with the expected result to determine whether the simulation output of the standard unit under test meets the expected result. The expected result can be generated based on the logic relationship truth table.

[0046] Step S15: When the simulation output of all the standard units under test meets the expected results, generate the machine test file using the simulation output collected from the top-level output terminal and perform machine test.

[0047] In this embodiment, the simulation output of the standard unit under test is compared with the expected result, and a test analysis file is generated. If the simulation output in the test analysis file does not match the expected result, an output of '1' is generated, thus identifying the standard unit under test with a simulation logic error. When the analysis result of the test analysis file shows that the simulation output of all the standard units under test meets the expected result, the simulation output, its corresponding standard unit selection signal, and the test vector are used to generate a machine test file.

[0048] During machine testing, the machine test output signal is collected and compared with the machine test file to output the machine test result.

[0049] In this embodiment, the machine test is an Automatic Test Equipment (ATE) test, and the machine test file is a test pattern file. When the ATE test is performed, the collected ATE test signals are compared with the test pattern file, and the test unit with problems in the ATE test will be marked in the test results.

[0050] If the simulation output of the test unit does not meet the expected results, the test unit with logical errors and its corresponding test vector are identified. The test unit with logical errors is then corrected and the simulation test is repeated.

[0051] This invention categorizes the standard units under test (DUTs) into combinational logic units and sequential logic units, and further categorizes them according to the number of output ports. Simulations are then performed on different categories of DUTs separately, enabling timely problem detection and adjustment. By integrating the same type of input ports of the combinational logic units and sequential logic units, input ports with the same function correspond to the same test vector, eliminating redundant test vectors and shortening verification time. Furthermore, by simultaneously acquiring the simulation output during simulation and connecting it to both the top-level output and simulation analysis terminals, the output signal of the same DUT is simultaneously acquired by both the machine test and simulation test, improving verification accuracy, reducing over-reliance on test equipment, and increasing verification efficiency.

[0052] Based on the same inventive concept, the present invention also provides a verification device for a standard unit library.

[0053] Figure 2 This is a schematic diagram of the structure of a verification device for a standard unit library provided in an embodiment of the present invention. Figure 2 As shown, the verification device 2 of the standard unit library includes: a standard unit module 11 to be tested and a signal selection output module 12.

[0054] The test standard unit module 11 is used to access the test standard units, which are classified into combinational logic units and sequential logic units. Both the combinational logic units and the sequential logic units include single output ports and multiple output ports. Input-output relationships are extracted for each category of the test standard units, and a logic relationship truth table is formed. Test vectors and expected results are generated for different categories and the number of input ports of the test standard units based on the logic relationship truth table. Input ports of the same type for the combinational logic units and the sequential logic units are integrated so that input ports with the same function correspond to the same bit of the test vector. The test vector is connected to the test standard unit module 11 from the top-level input terminal and input to the input terminal of each test standard unit. The output ports of the test standard units are connected to the output ports of the test standard unit module 11 according to the number of output ports of the test standard units.

[0055] The signal selection output module 12 consists of multiple matrix decoders. The signal of each output port of the standard unit under test module 11 is input to one of the matrix decoders. The matrix decoder selects the simulation output of the standard unit under test according to the input standard unit selection signal. During the simulation process, the simulation output is simultaneously connected to the top-level output terminal and the simulation analysis terminal. When the simulation output of all the standard units under test meets the expected results, the simulation output collected by the top-level output terminal is used to generate a machine test file and perform machine testing.

[0056] The classification of the standard units under test, the generation of a logical relationship truth table, the formation of test vectors and expected results, and the integration of input ports are all performed before the simulation is executed. See steps S11 to S13 for details.

[0057] In some embodiments, the design document contains the name and logic information of the standard unit to be tested, and test vectors can be generated directly from the design document.

[0058] like Figure 2 As shown, the test vector FUNC_CODE is input to the input port of the standard unit module 11 under test. The bit width of the test vector FUNC_CODE is m. The test vector FUNC_CODE is connected to the top-level input terminal and multiplexed by the top-level signal input interface, and connected to the input terminal of each standard unit under test.

[0059] The clock signal FUNC_CLK is also connected to the input port of the standard unit under test module 11. When testing combinational logic units, the circuit does not need the clock signal FUNC_CLK and does not drive the enable signal EN of the clock gating unit to prevent clock propagation and reduce power consumption; when testing sequential logic units, the enable signal EN of the input clock gating unit drives the clock FUNC_CLK input to ensure better dynamic power consumption management.

[0060] In this embodiment, the number of matrix decoders is the same as the number of output ports of the standard unit module 11 under test. Specifically, the standard unit module 11 under test has four output ports, and correspondingly, the number of matrix decoders is four.

[0061] The test cell selection signal FUNC_SEL_CELL is connected to the signal selection output module 12 and input into the matrix decoder. The bit width of the test cell selection signal FUNC_SEL_CELL is n, which can be used to select 2. n One standard unit to be tested.

[0062] Furthermore, the matrix dimension of the matrix decoder is less than or equal to 2. n * m, where n is the bit width of the FUNC_SEL_CELL selection signal for the standard cell under test; and m is the bit width of the test vector FUNC_CODE.

[0063] During the simulation, the output signal of the test standard unit module 11 is selected by the matrix decoder to form a simulation output corresponding to each test standard unit. The simulation output is divided into two paths.

[0064] One of the simulation outputs is connected to the top-level output terminal, which is used for machine tool testing. Specifically, the output is sent to the top-level output terminal. In the top-level module, the simulation output during the simulation process of the standard unit under test is obtained from the top-level output terminal. The simulation output, along with the corresponding standard unit selection signal and the test vector, can be used to generate a machine tool test file for machine tool testing. In this embodiment, the machine tool test is an ATE test. Figure 2 As shown, each matrix decoder corresponds to a simulation output FUNC_OUT. During the simulation process, the simulation output FUNC_OUT, along with its corresponding standard cell selection signal FUNC_SEL_CELL and test vector FUNC_CODE, generates a test pattern file. When the test equipment performs ATE testing, the acquired ATE test signals are compared with the test pattern file, and any problematic standard cells under test are identified in the test results.

[0065] Simultaneously, another path of the simulation output is connected to a simulation analysis terminal, which compares the simulation output of the test standard unit with the expected result to determine whether the simulation output of the test standard unit meets the expected result. When the simulation analysis result shows that the simulation output of all the test standard units meets the expected result, the simulation output is used for machine testing.

[0066] When connecting the output ports of the standard unit under test (SUBT) to the output ports of the standard unit under test module 11 according to the number of output ports of the standard unit under test, the following further includes: when the number of output ports of the standard unit under test is one, the output signal of the standard unit under test is sequentially connected to a single output port of the standard unit under test module 11; when the number of output ports of the standard unit under test is N, the N paths of the output signal of the standard unit under test are respectively connected to and output in parallel to the N output ports of the standard unit under test module 11.

[0067] The number of output ports of the standard unit under test does not exceed four.

[0068] In this embodiment, the combinational logic unit and the sequential logic unit are classified according to single-port output, dual-port output, and other multi-port output, respectively.

[0069] Specifically, the combinational logic units are classified according to the number of output ports as: single-port output combinational logic units, dual-port output combinational logic units, and other multi-port output combinational logic units; the sequential logic units are classified according to the number of output ports as: single-port output sequential logic units, dual-port output sequential logic units, and other multi-port output sequential logic units. Further, the other multi-port output combinational logic units can be classified as: three-port output combinational logic units and four-port output combinational logic units; the other multi-port output sequential logic units can be classified as: three-port multi-port output sequential logic units and four-port output sequential logic units.

[0070] Figure 3 This is a discrete unit mapping diagram of a matrix decoder provided in an embodiment of the present invention. For example... Figure 3 As shown, FUNC_CODE is the test vector with a bit width of m; the test standard unit module 11 has four output ports, namely A, B, C, and D, each with a bit width of n, which can correspond to n test standard units. Each output port of the test standard unit module 11 is connected to a matrix decoder, and the output signals in A, B, C, and D are selected and output through the matrix decoder.

[0071] For example, Figure 3 The standard unit under test shown in the figure, from top to bottom, is a NOT gate, a buffer, an AND gate, an OR gate, a half adder (HA), and a multiplexer (MB).

[0072] Among them, the NOT gate, buffer, AND gate, and OR gate have only one output port. Correspondingly, the output signal of the test standard unit output by the above single port is sequentially connected to the single output port of the test standard unit module 11. Figure 3 As an example, the output signal of the NOT gate is connected to A, specifically output to bit A[0], the output signal of the buffer is connected to B, specifically output to bit B[0], the output signal of the AND gate is connected to C, specifically output to bit C[0], and the output signal of the OR gate is connected to D, specifically output to bit D[0].

[0073] The half-adder (HA) has two output ports. Accordingly, the two output signals of the half-adder are simultaneously connected to A and B, specifically A[x] bits and B[x] bits. The two output signals of the half-adder can be output in parallel to A[x] bits and B[x] bits, ensuring that the output signals of the same test standard unit are acquired simultaneously. Here, x represents the sequence number of a certain bit in A and B.

[0074] The multiplexer (MB) has four output ports. Correspondingly, the four output signals of the half-adder are simultaneously connected to A, B, C, and D, specifically bits A[y], B[y], C[y], and D[y]. Furthermore, the four output signals of the multiplexer can be output in parallel to bits A[y], B[y], C[y], and D[y], ensuring that the output signals of the same test unit are acquired simultaneously. Here, y represents the sequence number of a specific bit in A, B, C, or D.

[0075] like Figure 2 As shown, the verification device 1 of the standard unit library further includes an input driving module 15 and an output driving module 16. The input driving module 15 is used to enhance the strength of the input signal, and the output driving module 16 is used to enhance the strength of the output signal.

[0076] Figure 4 This is a schematic diagram of the delayed sampling comparison structure provided in an embodiment of the present invention.

[0077] like Figure 4 As shown, the verification device for the standard unit library also includes a delay module 13 and an output calibration module 14.

[0078] The delay module 13 includes inherent delay processing and two-level registers. The delay module 13 is used to synchronously process the preset result signal FUNC_REF and output the expected result.

[0079] In this embodiment, the register is constructed using D flip-flops, and the preset result signal FUNC_REF is a 4-bit output expectation signal used to compare with the simulation output of the standard unit under test selected by the matrix decoder. FUNC_REF is generated according to the logic truth table. The expectation result Q, after being delayed by the delay module 13, is output to the calibration module 14, and the expectation result Q also includes four signals.

[0080] The output calibration module 14 is used to compare the simulation output of the standard unit under test with the expected result Q to confirm whether the simulation output of the standard unit under test meets the expected result.

[0081] In this embodiment, the output calibration module 14 performs the comparison using XOR gates (multiple XOR gates). Specifically, when the simulated output of the standard unit under test is identical to each bit of the expected result Q, the output calibration module 14 outputs 0, indicating that the simulated output of the standard unit under test meets the expected result; when any bit of the simulated output of the standard unit under test differs from the expected result Q, the output calibration module 14 outputs 1, indicating that the simulated output of the standard unit under test does not meet the expected result.

[0082] The output calibration module also outputs a test analysis file, which is used to calibrate the test standard unit with logical errors and its corresponding test vector.

[0083] When the simulation output of all the standard units under test meets the expected result Q, a machine test file is generated based on the simulation output and its corresponding standard unit selection signal and test vector, and the machine test is executed. The machine test output signal is collected and compared with the machine test file, and the machine test result is output.

[0084] The delay module 13 and the output calibration module 14 together realize the function of the simulation analysis terminal.

[0085] The verification device for the aforementioned standard unit library, by setting up a standard unit under test module, performs simulation tests on the standard units under test, which are classified according to combinational logic units and sequential logic units, and further classified according to the number of output ports. This allows for timely detection of problems and prompt adjustment and debugging. By setting up a signal selection output module to simultaneously collect the simulation output during simulation and connect it to both the top-level output terminal and the simulation analysis terminal, the device ensures that the output signal of the same standard unit under test is simultaneously collected by both the machine test and the simulation test. This improves the accuracy of verification, reduces over-reliance on the test machine, and increases verification efficiency.

[0086] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion. The various embodiments in this specification are described in a related manner, and similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments.

[0087] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A verification method for a standard cell library, characterized in that, include: The standard unit under test is classified into combinational logic unit and sequential logic unit. Both the combinational logic unit and the sequential logic unit include single output port and multiple output port. For each category of the test standard unit, the input-output relationship is extracted and summarized to form a logical relationship truth table. The logical relationship truth table is used to generate test vectors and expected results for different categories and the number of input ports of the test standard unit. The input ports of the same type in the combinational logic unit and the sequential logic unit are integrated respectively, so that the input ports with the same function correspond to the same bit of the test vector, and the test vector is accessed from the top-level input terminal; A simulation test file is generated and the simulation is executed accordingly. The simulation output of the standard unit under test is collected during the simulation process. The simulation output is simultaneously connected to the top-level output terminal and the simulation analysis terminal. When the simulation outputs of all the test standard units meet the expected results, the simulation outputs collected from the top-level output terminal are used to generate machine test files and perform machine tests.

2. The verification method for the standard cell library according to claim 1, characterized in that, The step of classifying the standard unit under test into combinational logic units and sequential logic units, wherein both the combinational logic units and the sequential logic units include single-output ports and multiple-output ports, specifically includes: Instances of different types of standard cell libraries under test are integrated into the same cell library file, and the name, logic information and output port information of the standard cell under test are extracted from the cell library file; Based on the name or logic information of the standard unit under test, the standard unit under test is classified into combinational logic units and sequential logic units; Based on the output port information, the combinational logic units are classified into single-output-port combinational logic units and multi-output-port combinational logic units, and the sequential logic units are classified into single-output-port sequential logic units and multi-output-port sequential logic units.

3. The verification method for the standard cell library according to claim 2, characterized in that, The types of the standard unit library to be tested include: basic standard unit library, engineering change unit library, and process matching unit library; the output port information includes the output port name and the number of output ports.

4. The verification method for the standard cell library according to claim 1, characterized in that, The step of extracting the input-output relationships for each category of the test standard unit and summarizing them to form a logical relationship truth table further includes: For each combinational logic unit, the logical relationships of the combinational logic units are extracted from the parameter library, and corresponding combinational logic output results are generated for different test inputs; For each sequential logic unit, sequential logic verification and sequential convergence design are performed to generate sequential logic verification results. The combinational logic outputs and the timing logic verification results are combined to form the logic relationship truth table.

5. The verification method for the standard cell library according to claim 1, characterized in that, When the simulation output of all the standard units under test meets the expected results, the simulation output collected from the top output terminal and its corresponding standard unit selection signal and test vector will be used to generate a machine test file and execute the machine test. The machine test output signal will be collected and compared with the machine test file to output the machine test result. If the simulation output of the test unit does not meet the expected results, the test unit and its corresponding test vector are identified as having logical errors.

6. A verification device for a standard cell library, characterized in that, include: The test standard unit module is used to access the test standard units, which are classified into combinational logic units and sequential logic units. Both the combinational logic units and the sequential logic units include single output ports and multiple output ports. The input-output relationship is extracted for each category of the test standard unit and summarized to form a logic relationship truth table. Based on the logic relationship truth table, test vectors and expected results are generated for different categories and the number of input ports of the test standard units. Input ports of the same type of combinational logic units and sequential logic units are integrated so that input ports with the same function correspond to the same bit of the test vector. The test vector is connected to the test standard unit module from the top-level input terminal and input to the input terminal of the test standard unit. The output ports of the test standard units are connected to the output ports of the test standard unit module according to the number of output ports of the test standard units. The signal selection output module consists of multiple matrix decoders. The signal of each output port of the standard unit under test module corresponds to one of the matrix decoders. The matrix decoder selects the simulation output of the standard unit under test according to the input standard unit selection signal. During the simulation process, the simulation output is simultaneously connected to the top-level output terminal and the simulation analysis terminal. When the simulation output of all the standard units under test meets the expected results, the simulation output collected by the top-level output terminal is used to generate a machine test file and perform machine testing.

7. The verification apparatus for the standard cell library according to claim 6, characterized in that, Connecting the output ports of the standard unit under test to the output ports of the standard unit under test module according to the number of output ports of the standard unit under test specifically includes: When the number of output ports of the standard unit under test is a single one, the output signal of the standard unit under test is sequentially connected to a single output port of the standard unit under test module; When the number of output ports of the standard unit under test is N, the N output signals of the standard unit under test are respectively connected to and output in parallel to the N output ports of the standard unit under test module, where N is greater than or equal to 2.

8. The verification apparatus for the standard cell library according to claim 6, characterized in that, The verification device for the standard unit library further includes a delay module, which includes inherent delay processing and two-level registers. The delay module is used to synchronously process the preset result signal and output the expected result. The output calibration module is used to compare the simulation output of the standard unit under test with the expected result to confirm whether the simulation output of the standard unit under test meets the expected result. The output calibration module also outputs a test analysis file, which is used to calibrate the standard unit under test with logical errors and its corresponding test vector.

9. The verification apparatus for the standard cell library according to claim 6, characterized in that, The number of output ports of the standard unit module under test is four, the number of matrix decoders is four, and the number of output ports of the standard unit under test is less than or equal to four.

10. The verification apparatus for the standard cell library according to claim 6, characterized in that, The standard cell selection signal is input from the top-level input terminal to the signal selection output module and then input to the matrix decoder. The matrix dimension of the matrix decoder is less than or equal to 2. n * m, where n is the bit width of the selection signal of the standard unit under test; m is the bit width of the test vector.

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