Oscillator and electronic device

Abstract

The invention provides an oscillator and electronic equipment. The oscillator comprises a current control oscillator, a frequency divider, a ping-pong active integrator and an error amplifier which are electrically connected in sequence, the current control oscillator is used for generating an initial clock signal with an initial clock frequency; the frequency divider is used for performing frequency division processing on the initial clock signal to generate a frequency division clock signal; the ping-pong active integrator is used for generating a feedback voltage based on the frequency division clock signal; the error amplifier is used for generating error current based on the feedback voltage and the reference voltage; the current-controlled oscillator is further configured to output a target clock signal having a target clock frequency based on the error current. The feedback voltage is generated through the ping-pong active integrator, so that the error amplifier generates the error current to control the target clock frequency of the target clock signal to be within the preset range, closed-loop adjustment of the clock signal is achieved, the temperature stability of the clock signal is improved, the clock signal can cope with more complex use scenes, and universality is achieved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuit design, and in particular to an oscillator and an electronic device. BACKGROUND

[0002] With the continuous development of current electronic technology, the amount of data processed by electronic products is getting larger and larger, the working frequency is getting higher and higher, and the frequency of data interaction is getting higher and higher. The implementation of these electronic products all need high-precision high-frequency oscillators as time base units to participate in the operation of the overall system.

[0003] The comparison delay of the operational amplifier in the current oscillator will change greatly with temperature, resulting in a large change range of the clock frequency of the clock signal output by the oscillator at different temperatures, i.e., the temperature stability of the clock signal is low, which cannot cope with more complex use scenarios and has poor universality. SUMMARY

[0004] The technical problem to be solved by the present disclosure is to overcome the defects in the prior art that the comparison delay of the oscillator changes greatly with temperature, resulting in low temperature stability of the clock signal output by the oscillator, poor universality, etc., and to provide an oscillator and an electronic device.

[0005] The present disclosure solves the above technical problems by the following technical solutions:

[0006] The present disclosure provides an oscillator, which comprises a current-controlled oscillator, a frequency divider, a ping-pong active integrator and an error amplifier connected in sequence.

[0007] The error amplifier is electrically connected with the current-controlled oscillator.

[0008] The current-controlled oscillator is configured to generate an initial clock signal with an initial clock frequency.

[0009] The frequency divider is configured to perform frequency division processing on the initial clock signal to generate a frequency-division clock signal.

[0010] The ping-pong active integrator is configured to generate a feedback voltage based on the frequency-division clock signal.

[0011] The error amplifier is configured to generate an error current based on the feedback voltage and a reference voltage.

[0012] The current-controlled oscillator is further configured to output a target clock signal with a target clock frequency based on the error current.

[0013] The actual difference value between the target clock frequency and the initial clock frequency is within a preset difference value range.

[0014] Optionally, the error amplifier comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor and an operational amplifier;

[0015] A first input terminal of the operational amplifier is electrically connected with the first resistor and the second resistor respectively;

[0016] A second input terminal of the operational amplifier is electrically connected with the third resistor and the first capacitor respectively;

[0017] An output terminal of the operational amplifier is electrically connected with the first capacitor and the fourth resistor respectively;

[0018] The fourth resistor is electrically connected with the second capacitor.

[0019] Optionally, the first resistor is electrically connected with a voltage source, and the second resistor and the second capacitor are grounded.

[0020] Optionally, the ping-pong active integrator comprises a first PMOS (P-type metal oxide semiconductor) tube, a second NMOS (N-type metal oxide semiconductor) tube, a third PMOS tube, a fourth NMOS tube, a fifth PMOS tube, a sixth NMOS tube, a seventh PMOS tube, an eighth NMOS tube, a fifth resistor, a sixth resistor, a third capacitor, a fourth capacitor, a first inverter, a second inverter and a third inverter;

[0021] A gate of the first PMOS tube is electrically connected with a gate of the second NMOS tube, an input terminal of the first inverter, an input terminal of the second inverter and an output terminal of the frequency divider respectively, and a drain of the first PMOS tube is electrically connected with a first terminal of the fifth resistor;

[0022] A drain of the second NMOS tube is electrically connected with a second terminal of the fifth resistor, the third capacitor, a source of the fifth PMOS tube and a drain of the sixth NMOS tube respectively;

[0023] A gate of the third PMOS tube is electrically connected with a gate of the fourth NMOS tube, an output terminal of the second inverter and an input terminal of the third inverter respectively, and a drain of the third PMOS tube is electrically connected with a first terminal of the sixth resistor;

[0024] A drain of the fourth NMOS tube is electrically connected with a second terminal of the sixth resistor, the fourth capacitor, a source of the seventh PMOS tube and a drain of the eighth NMOS tube respectively;

[0025] A drain of the fifth PMOS tube and a drain of the seventh PMOS tube are electrically connected with the third resistor respectively;

[0026] A gate of the sixth NMOS tube is electrically connected with an output terminal of the first inverter;

[0027] The gate of the eighth NMOS transistor is electrically connected to the output terminal of the third inverter.

[0028] Optionally, the source of the first PMOS transistor and the source of the third PMOS transistor are electrically connected to a voltage source, respectively.

[0029] The source of the second NMOS transistor, the source of the fourth NMOS transistor, the third capacitor, and the fourth capacitor are grounded.

[0030] Optionally, the oscillator further includes a ninth NMOS transistor and a seventh resistor;

[0031] The gate of the ninth NMOS transistor is electrically connected to the output terminal of the operational amplifier, the first capacitor, and the fourth resistor, respectively. The drain of the ninth NMOS transistor is electrically connected to the input terminal of the current-controlled oscillator, and the source of the ninth NMOS transistor is electrically connected to the seventh resistor.

[0032] Optionally, the reference voltage is obtained by dividing the power supply voltage of the voltage source using the first resistor and the second resistor.

[0033] Optionally, the calculation formula for the feedback voltage is as follows:

[0034] ;

[0035] Wherein, Vout represents the feedback voltage, R5 represents the fifth resistor, C3 represents the third capacitor, Vin represents the power supply voltage, and t represents the time required for the feedback voltage to reach a preset multiple of the power supply voltage.

[0036] Optionally, the calculation formula for the target clock frequency is as follows:

[0037] ;

[0038] Wherein, Fout represents the target clock frequency, N represents the division factor of the frequency divider, R5 represents the fifth resistor, C3 represents the third capacitor, R1 represents the first resistor, and R2 represents the second resistor.

[0039] This disclosure also provides an electronic device that includes an oscillator as described above.

[0040] Based on common knowledge in the field, the above-mentioned preferred conditions can be combined arbitrarily to obtain various preferred embodiments of this disclosure.

[0041] The positive and progressive effects of this disclosure are as follows:

[0042] This disclosure utilizes a ping-pong active integrator to generate a feedback voltage based on an initial clock signal. This allows an error amplifier to compare the feedback voltage with a reference voltage, generating an error current to control the target clock frequency of the oscillator output within a preset range. This achieves closed-loop regulation of the clock signal, reduces the impact of the error amplifier's comparison delay on the clock frequency, improves the temperature stability of the clock signal, and can handle more complex application scenarios, demonstrating versatility. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the oscillator module according to Embodiment 1 of this disclosure;

[0044] Figure 2 This is a schematic diagram of the oscillator according to Embodiment 1 of this disclosure;

[0045] Figure 3 The waveform diagram shows the output voltage of the ping-pong active integrator in the oscillator of Embodiment 1 of this disclosure. Detailed Implementation

[0046] The present disclosure is further illustrated below by way of embodiments, but the present disclosure is not limited to the scope of the embodiments described herein.

[0047] The prefixes such as "first" and "second" used in this disclosure are merely for distinguishing different descriptive objects and do not limit the position, order, priority, quantity, or content of the described objects. The use of ordinal numbers and other prefixes used to distinguish descriptive objects in this disclosure does not constitute a limitation on the described objects. The description of the described objects is given in the context of the embodiments, and the use of such prefixes should not constitute unnecessary restrictions. Furthermore, in the description of this embodiment, unless otherwise stated, "multiple" means two or more.

[0048] Example 1

[0049] This embodiment provides an oscillator, such as Figure 1 As shown, the oscillator includes a current-controlled oscillator 1, a frequency divider 2, a ping-pong active integrator 3, and an error amplifier 4, which are connected in sequence.

[0050] The error amplifier 4 is electrically connected to the current-controlled oscillator 1;

[0051] The current-controlled oscillator 1 is used to generate an initial clock signal with an initial clock frequency;

[0052] Frequency divider 2 is used to divide the initial clock signal to generate a frequency-divided clock signal;

[0053] The ping-pong active integrator 3 is used to generate a feedback voltage based on a frequency-divided clock signal;

[0054] Error amplifier 4 is used to generate an error current based on the feedback voltage and the reference voltage;

[0055] The current-controlled oscillator 1 is also used to output a target clock signal with a target clock frequency based on the error current;

[0056] The actual difference between the target clock frequency and the initial clock frequency is within the preset difference range.

[0057] Specifically, the oscillator in this embodiment is a high-precision oscillator that does not require an external crystal. This oscillator achieves a 3% clock frequency variation within a temperature range of -40℃ to 125℃ and a power supply voltage variation range of ±10%.

[0058] In this solution, the present disclosure uses a ping-pong active integrator to generate a feedback voltage based on the initial clock signal, which enables the error amplifier to compare the feedback voltage with the reference voltage and generate an error current to control the current to control the target clock frequency of the target clock signal output by the oscillator within a preset range, thereby realizing closed-loop regulation of the clock signal, reducing the impact of the comparison delay of the error amplifier on the clock frequency, improving the temperature stability of the clock signal, and being able to cope with more complex application scenarios, thus having universality.

[0059] In a feasible solution, such as Figure 2 As shown, the error amplifier 4 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, and an operational amplifier OP;

[0060] The first input terminal of the operational amplifier OP is electrically connected to the first resistor R1 and the second resistor R2, respectively.

[0061] The second input terminal of the operational amplifier OP is electrically connected to the third resistor R3 and the first capacitor C1, respectively.

[0062] The output of the operational amplifier OP is electrically connected to the first capacitor C1 and the fourth resistor R4, respectively.

[0063] The fourth resistor R4 is electrically connected to the second capacitor C2.

[0064] Specifically, the error amplifier dynamically adjusts the input current of the current-controlled oscillator to stabilize the frequency of the clock signal output by the current-controlled oscillator at the desired frequency.

[0065] In this scheme, by setting a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, and an operational amplifier, the error amplifier can dynamically adjust the input current of the current-controlled oscillator based on the feedback voltage and the reference voltage, so that the frequency of the clock signal output by the current-controlled oscillator is stabilized at the desired frequency, thus ensuring the reliability of the error amplifier.

[0066] In one feasible solution, the first resistor R1 is electrically connected to a voltage source, and the second resistor R2 and the second capacitor C2 are grounded.

[0067] In this scheme, by setting the first resistor to be electrically connected to the voltage source and the second resistor and second capacitor to be grounded, the normal operation of the error amplifier is ensured.

[0068] In one feasible embodiment, the ping-pong active integrator 3 includes a first PMOS transistor M1, a second NMOS transistor M2, a third PMOS transistor M3, a fourth NMOS transistor M4, a fifth PMOS transistor M5, a sixth NMOS transistor M6, a seventh PMOS transistor M7, an eighth NMOS transistor M8, a fifth resistor R5, a sixth resistor R6, a third capacitor C3, a fourth capacitor C4, a first inverter G1, a second inverter G2, and a third inverter G3;

[0069] The gate of the first PMOS transistor M1 is electrically connected to the gate of the second NMOS transistor M2, the input terminal of the first inverter G1, the input terminal of the second inverter G2, and the output terminal of the frequency divider 2, respectively. The drain of the first PMOS transistor M1 is electrically connected to the first terminal of the fifth resistor R5.

[0070] The drain of the second NMOS transistor M2 is electrically connected to the second terminal of the fifth resistor R5, the third capacitor C3, the source of the fifth PMOS transistor M5, and the drain of the sixth NMOS transistor M6, respectively.

[0071] The gate of the third PMOS transistor M3 is electrically connected to the gate of the fourth NMOS transistor M4, the output of the second inverter G2, and the input of the third inverter G3, respectively. The drain of the third PMOS transistor M3 is electrically connected to the first end of the sixth resistor R6.

[0072] The drain of the fourth NMOS transistor M4 is electrically connected to the second terminal of the sixth resistor R6, the fourth capacitor C4, the source of the seventh PMOS transistor M7, and the drain of the eighth NMOS transistor M8, respectively.

[0073] The drains of the fifth PMOS transistor M5 and the seventh PMOS transistor M7 are electrically connected to the third resistor R3, respectively.

[0074] The gate of the sixth NMOS transistor M6 is electrically connected to the output terminal of the first inverter G1;

[0075] The gate of the eighth NMOS transistor M8 is electrically connected to the output of the third inverter G3.

[0076] Specifically, resistor R5 and capacitor C3, and resistor R7 and capacitor C4 are the core components of the ping-pong active integrator.

[0077] The voltage source charges capacitor C3 through resistor R5. The charging frequency is one-Nth of the frequency of the clock signal output by the current-controlled oscillator, where N represents the division factor of the frequency divider.

[0078] like Figure 3 The figure shows the waveform of the output voltage of the ping-pong active integrator. The output voltage fluctuates periodically between 0 and the maximum value. The fluctuation period of the output voltage is T=N / (2*Fout), where Fout represents the frequency of the output clock signal.

[0079] In this scheme, by setting up MOSFETs, resistors, capacitors, and inverters, the ping-pong active integrator generates a feedback voltage based on the initial clock signal, thus ensuring the accuracy and reliability of the ping-pong active integrator.

[0080] In one feasible scheme, the source of the first PMOS transistor M1 and the source of the third PMOS transistor M3 are electrically connected to a voltage source, respectively.

[0081] The source of the second NMOS transistor M2, the source of the fourth NMOS transistor M4, the third capacitor C3, and the fourth capacitor C4 are grounded.

[0082] In this scheme, by setting the first PMOS transistor and the third PMOS transistor to be electrically connected to the voltage source, and the second NMOS transistor, the fourth NMOS transistor, the third capacitor, and the fourth capacitor to be grounded, the normal operation of the ping-pong active integrator is ensured.

[0083] In one feasible embodiment, the oscillator also includes a ninth NMOS transistor M9 and a seventh resistor R7;

[0084] The gate of the ninth NMOS transistor M9 is electrically connected to the output terminal of the operational amplifier OP, the first capacitor C1, and the fourth resistor R4, respectively. The drain of the ninth NMOS transistor M9 is electrically connected to the input terminal 2 of the current-controlled oscillator, and the source of the ninth NMOS transistor M9 is electrically connected to the seventh resistor R7.

[0085] In this scheme, by setting the ninth NMOS transistor and the seventh resistor, the error current generated by the error amplifier can control the frequency of the clock signal output by the oscillator, thus ensuring the accuracy and reliability of the oscillator.

[0086] In one feasible approach, the reference voltage is obtained by dividing the power supply voltage of the voltage source using a first resistor R1 and a second resistor R2.

[0087] Specifically, the first resistor R1 and the second resistor R2 divide the power supply voltage, and the reference voltage Vref = R2 / (R1 + R2) * VDD, where VDD represents the power supply voltage.

[0088] In this scheme, the power supply voltage of the voltage source is divided by the first resistor and the second resistor to obtain the reference voltage, thus ensuring the accuracy and reliability of the reference voltage.

[0089] In a feasible solution, the formula for calculating the feedback voltage is as follows:

[0090] ;

[0091] Where Vout represents the feedback voltage, R5 represents the fifth resistor, C3 represents the third capacitor, Vin represents the power supply voltage, and t represents the time required for the feedback voltage to reach a preset multiple of the power supply voltage.

[0092] Specifically, the above calculation formula is the calculation formula corresponding to the first-order RC step response. When the RC time constant is fixed, the time required for the feedback voltage generated by the ping-pong active integrator, i.e., the output voltage Vout, to reach k*Vin is fixed, where Vout is k<1, k=R1 / (R1+R2), and the RC time constant=R5*C3.

[0093] In this scheme, the feedback voltage is obtained based on the calculation formula corresponding to the first-order RC step response, which ensures the accuracy and reliability of the feedback voltage.

[0094] In a feasible solution, the formula for calculating the target clock frequency is as follows:

[0095] ;

[0096] Where Fout represents the target clock frequency, N represents the division factor of the frequency divider, R5 represents the fifth resistor, C3 represents the third capacitor, R1 represents the first resistor, and R2 represents the second resistor.

[0097] In this scheme, the target clock frequency is determined by calculation formula, and the relationship between the target clock frequency and the division multiple of the first resistor, second resistor, fifth resistor, third capacitor and frequency divider is established, which ensures the accuracy and reliability of the target clock frequency.

[0098] The working principle of the oscillator in this embodiment is as follows:

[0099] A current-controlled oscillator 1 generates an initial clock signal with an initial clock frequency. A frequency divider 2 divides the initial clock signal to generate a divided clock signal. The divided clock signal controls the switching of the ping-pong active integrator 3 to generate an average voltage ripple, i.e., a feedback voltage, across the third resistor R3. An error amplifier 4 performs integration filtering and error amplification. A clamping equalization is generated across the operational amplifier OP, producing an error current based on the feedback voltage and the reference voltage. When the clock signal frequency is low, the error current increases, which in turn increases the current of the current-controlled oscillator, thus increasing the frequency and achieving clock signal frequency adjustment.

[0100] The ping-pong active integrator 3 can be considered as two parts, namely the first part and the second part. The first part includes the first PMOS transistor M1, the second NMOS transistor M2, the fifth PMOS transistor M5, the sixth NMOS transistor M6, the fifth resistor R5, the third capacitor C3, and the first inverter G1. The second part includes the third PMOS transistor M3, the fourth NMOS transistor M4, the seventh PMOS transistor M7, the eighth NMOS transistor M8, the sixth resistor R6, the fourth capacitor C4, the second inverter G2, and the third inverter G3. At the same time, one part works and the other part does not work.

[0101] Taking the first part as an example, M5 and M6 form a transmission gate. When M1 is on, M2 is off. When the frequency divider 2 outputs a high-level clock signal, C3 is charged through R5. This charging frequency is transmitted to R3 through the transmission gate, a transmission process from low to high level. The power supply voltage forms an envelope from low to high. When the frequency divider 2 outputs a low-level clock signal, the first part is cut off, and the second part begins transmission, another transmission process from low to high level.

[0102] In this embodiment, a ping-pong active integrator generates a feedback voltage based on the initial clock signal, which in turn compares the feedback voltage with the reference voltage to generate an error current. This current controls the target clock frequency of the oscillator output to remain within a preset range, thus achieving closed-loop regulation of the clock signal. This reduces the impact of the error amplifier's comparison delay on the clock frequency, improves the temperature stability of the clock signal, and enables the system to handle more complex application scenarios, demonstrating versatility.

[0103] Example 2

[0104] This embodiment provides an electronic device that includes an oscillator as described above.

[0105] The electronic device in this embodiment integrates the aforementioned oscillator, ensuring the accuracy and reliability of the clock signal and improving the device's performance.

[0106] While specific embodiments of this disclosure have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this disclosure, but all such changes and modifications fall within the scope of protection of this disclosure.

Claims

1. An oscillator, characterized in that, The oscillator includes a current-controlled oscillator, a frequency divider, a ping-pong active integrator, and an error amplifier connected in sequence. The error amplifier is electrically connected to the current-controlled oscillator. The current-controlled oscillator is used to generate an initial clock signal with an initial clock frequency; The frequency divider is used to divide the initial clock signal to generate a frequency-divided clock signal; The ping-pong active integrator is used to generate a feedback voltage based on the frequency-divided clock signal; The error amplifier is used to generate an error current based on the feedback voltage and the reference voltage; The current-controlled oscillator is also used to output a target clock signal with a target clock frequency based on the error current. The actual difference between the target clock frequency and the initial clock frequency is within a preset difference range.

2. The oscillator as claimed in claim 1, characterized in that, The error amplifier includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, and an operational amplifier; The first input terminal of the operational amplifier is electrically connected to the first resistor and the second resistor, respectively. The second input terminal of the operational amplifier is electrically connected to the third resistor and the first capacitor, respectively. The output terminal of the operational amplifier is electrically connected to the first capacitor and the fourth resistor, respectively. The fourth resistor is electrically connected to the second capacitor.

3. The oscillator as described in claim 2, characterized in that, The first resistor is electrically connected to the voltage source, and the second resistor and the second capacitor are grounded.

4. The oscillator as claimed in claim 2, characterized in that, The ping-pong active integrator includes a first PMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor, a seventh PMOS transistor, an eighth NMOS transistor, a fifth resistor, a sixth resistor, a third capacitor, a fourth capacitor, a first inverter, a second inverter, and a third inverter. The gate of the first PMOS transistor is electrically connected to the gate of the second NMOS transistor, the input terminal of the first inverter, the input terminal of the second inverter, and the output terminal of the frequency divider, respectively. The drain of the first PMOS transistor is electrically connected to the first terminal of the fifth resistor. The drain of the second NMOS transistor is electrically connected to the second terminal of the fifth resistor, the third capacitor, the source of the fifth PMOS transistor, and the drain of the sixth NMOS transistor, respectively. The gate of the third PMOS transistor is electrically connected to the gate of the fourth NMOS transistor, the output terminal of the second inverter, and the input terminal of the third inverter, respectively. The drain of the third PMOS transistor is electrically connected to the first terminal of the sixth resistor. The drain of the fourth NMOS transistor is electrically connected to the second terminal of the sixth resistor, the fourth capacitor, the source of the seventh PMOS transistor, and the drain of the eighth NMOS transistor, respectively. The drain of the fifth PMOS transistor and the drain of the seventh PMOS transistor are respectively electrically connected to the third resistor; The gate of the sixth NMOS transistor is electrically connected to the output terminal of the first inverter. The gate of the eighth NMOS transistor is electrically connected to the output terminal of the third inverter.

5. The oscillator as described in claim 4, characterized in that, The source of the first PMOS transistor and the source of the third PMOS transistor are respectively electrically connected to a voltage source; The source of the second NMOS transistor, the source of the fourth NMOS transistor, the third capacitor, and the fourth capacitor are grounded.

6. The oscillator as claimed in claim 4, characterized in that, The oscillator also includes a ninth NMOS transistor and a seventh resistor; The gate of the ninth NMOS transistor is electrically connected to the output terminal of the operational amplifier, the first capacitor, and the fourth resistor, respectively. The drain of the ninth NMOS transistor is electrically connected to the input terminal of the current-controlled oscillator, and the source of the ninth NMOS transistor is electrically connected to the seventh resistor.

7. The oscillator as claimed in claim 3, characterized in that, The reference voltage is obtained by dividing the power supply voltage of the voltage source using the first resistor and the second resistor.

8. The oscillator as claimed in claim 4, characterized in that, The calculation formula for the feedback voltage is as follows: ； Wherein, Vout represents the feedback voltage, R5 represents the fifth resistor, C3 represents the third capacitor, Vin represents the power supply voltage, and t represents the time required for the feedback voltage to reach a preset multiple of the power supply voltage.

9. The oscillator as claimed in claim 4, characterized in that, The calculation formula for the target clock frequency is as follows: ； Wherein, Fout represents the target clock frequency, N represents the division factor of the frequency divider, R5 represents the fifth resistor, C3 represents the third capacitor, R1 represents the first resistor, and R2 represents the second resistor.

10. An electronic device, characterized in that, The electronic device includes an oscillator as described in any one of claims 1-9.

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