Gate oxide layer and forming method thereof

Abstract

The invention provides a gate oxide layer and a forming method thereof. A formed first gate oxide layer covers substrates of a first gate oxide layer definition region, a second gate oxide layer definition region and a third gate oxide layer definition region; removing the first gate oxide layer on the second gate oxide layer definition region, and retaining the first gate oxide layer on the first gate oxide layer definition region and the third gate oxide layer definition region; the formed second gate oxide layer covers the substrate of the second gate oxide layer definition area; removing the first gate oxide layer on the third gate oxide layer definition region; the formed third gate oxide layer covers the substrate of the third gate oxide layer defining region. When the first gate oxide layer on the second gate oxide layer definition region is removed, the first gate oxide layer on the third gate oxide layer definition region is reserved, so that the substrate on the third gate oxide layer definition region only has one-time acid contact, and the acid pickling influence of the substrate on the third gate oxide layer definition region is reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a gate oxide layer and a method for forming the same. Background Technology

[0002] In processes involving three or more gate oxides, the formation of the three oxides generally follows these steps: First, the thickest oxide layer is grown as the first gate oxide (gate OX1); second, a first photolithography step is performed to define the region of the first gate oxide; third, wet etching is used to remove the regions of the second gate oxide (Gate OX2) and the third gate oxide (Gate OX3), leaving only the region of the first gate oxide; fourth, a second gate oxide layer (Gate OX2) of intermediate thickness is grown; fifth, a second photolithography step is performed to define the regions of Gate OX1 and Gate OX2; sixth, wet etching is used to remove the region of Gate OX1; seventh, the thinnest third gate oxide layer is grown. This ultimately results in the desired thickness of the three oxides.

[0003] In the three traditional oxide formation methods, the thinnest gate OX3 region is acid-cleaned twice, which can cause changes in the step height and divot in this region, resulting in electrical shifts. This method has little impact in mature processes, but in advanced processes, the quality of the gate OX3 and the nearby step height and divot have a significant impact on the electrical properties of the core device. Summary of the Invention

[0004] The purpose of this invention is to provide a gate oxide layer and a method for forming the same, in order to solve the problem that the substrate of the thinnest third gate oxide layer region is acid-washed twice, resulting in changes in step height and pits in this region, which in turn leads to electrical shift.

[0005] To solve the above-mentioned technical problems, the present invention provides a method for forming a gate oxide layer, comprising:

[0006] A substrate is provided, the substrate including a first gate oxide layer definition region, a second gate oxide layer definition region and a third gate oxide layer definition region;

[0007] A first gate oxide layer is formed, which covers the substrate of the first gate oxide layer definition region, the second gate oxide layer definition region, and the third gate oxide layer definition region.

[0008] Remove the first gate oxide layer on the second gate oxide layer definition region, and retain the first gate oxide layer on the first gate oxide layer definition region and the third gate oxide layer definition region;

[0009] A second gate oxide layer is formed, the second gate oxide layer covering the substrate of the region defined by the second gate oxide layer;

[0010] Remove the first gate oxide layer on the third gate oxide layer definition region;

[0011] A third gate oxide layer is formed, which covers the substrate of the region defined by the third gate oxide layer.

[0012] Optionally, the step of removing the first gate oxide layer on the second gate oxide layer definition region includes:

[0013] A patterned first photoresist layer is formed, the patterned first photoresist layer covering the first gate oxide layer on the first gate oxide layer definition region and the first gate oxide layer definition region, and exposing the top surface of the first gate oxide layer on the second gate oxide layer definition region;

[0014] The first etching process is performed, using the patterned first photoresist layer as a mask, to etch the first gate oxide layer on the second gate oxide layer definition region, while retaining the first gate oxide layer on the first gate oxide layer definition region and the first gate oxide layer on the third gate oxide layer definition region.

[0015] Optionally, the step of removing the first gate oxide layer on the third gate oxide layer definition region includes:

[0016] A patterned second photoresist layer is formed, which covers the first gate oxide layer in the first gate oxide layer definition region and the second gate oxide layer in the second gate oxide layer definition region, and exposes the top surface of the first gate oxide layer in the third gate oxide layer definition region;

[0017] A second etching process is performed, using the patterned second photoresist layer as a mask, to etch the first gate oxide layer on the third gate oxide layer definition region, while retaining the first gate oxide layer on the first gate oxide layer definition region and the second gate oxide layer on the second gate oxide layer definition region.

[0018] Optionally, both the first etching process and the second etching process are wet etching processes.

[0019] Optionally, the etching solution for the first etching process and the second etching process includes hydrofluoric acid.

[0020] Optionally, the thicknesses of the first gate oxide layer, the second gate oxide layer, and the third gate oxide layer are different.

[0021] Optionally, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, and the thickness of the second gate oxide layer is greater than the thickness of the third gate oxide layer.

[0022] Optionally, the first gate oxide layer, the second gate oxide layer, and the third gate oxide layer are formed using a thermal oxidation process.

[0023] Based on the same inventive concept, the present invention also provides a gate oxide layer, prepared by any of the gate oxide layer formation methods described above, comprising:

[0024] The substrate includes a first gate oxide layer definition region, a second gate oxide layer definition region, and a third gate oxide layer definition region;

[0025] A first gate oxide layer is located on the substrate within the region defined by the first gate oxide layer;

[0026] A second gate oxide layer is located on the substrate within the region defined by the second gate oxide layer;

[0027] A third gate oxide layer is located on the substrate within the defined region of the third gate oxide layer.

[0028] Optionally, the thicknesses of the first gate oxide layer, the second gate oxide layer, and the third gate oxide layer are different.

[0029] In a method for forming a gate oxide layer provided by the present invention, the substrate includes a first gate oxide layer definition region, a second gate oxide layer definition region, and a third gate oxide layer definition region; a first gate oxide layer is formed, covering the substrate of the first gate oxide layer definition regions, the second gate oxide layer definition regions, and the third gate oxide layer definition regions; the first gate oxide layer on the second gate oxide layer definition region is removed, while retaining the first gate oxide layers on the first gate oxide layer definition regions and the third gate oxide layer definition regions; a second gate oxide layer is formed, covering the substrate of the second gate oxide layer definition region; the first gate oxide layer on the third gate oxide layer definition region is removed; and a third gate oxide layer is formed, covering the substrate of the third gate oxide layer definition region. The present invention, by retaining the first gate oxide layers on the first gate oxide layer definition regions and the third gate oxide layer definition regions during the removal of the first gate oxide layer on the second gate oxide layer definition region, ensures that the substrate on the third gate oxide layer definition region only has one acid contact, reducing the impact of acid pickling on the substrate on the third gate oxide layer definition region. Attached Figure Description

[0030] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0031] Figure 1 This is a flowchart of a method for forming a gate oxide layer according to an embodiment of the present invention.

[0032] Figures 2 to 8 This is a structural schematic diagram of the corresponding steps in a method for forming a gate oxide layer according to an embodiment of the present invention.

[0033] In the attached image:

[0034] 10-Substrate; 10a-First gate oxide layer definition region; 10b-Second gate oxide layer definition region; 10c-Third gate oxide layer definition region; 11-First gate oxide layer; 12-Patterned first photoresist layer; 13-Second gate oxide layer; 14-Patterned second photoresist layer; 15-Third gate oxide layer. Detailed Implementation

[0035] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0036] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. Additionally, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, which can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0037] Figure 1 This is a flowchart illustrating a method for forming a gate oxide layer according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a gate oxide layer, including:

[0038] Step S10: Provide a substrate, the substrate including a first gate oxide layer definition region, a second gate oxide layer definition region and a third gate oxide layer definition region;

[0039] Step S20: A first gate oxide layer is formed, which covers the substrate of the first gate oxide layer definition region, the second gate oxide layer definition region, and the third gate oxide layer definition region.

[0040] Step S30: Remove the first gate oxide layer on the second gate oxide layer definition region, and retain the first gate oxide layer on the first gate oxide layer definition region and the third gate oxide layer definition region;

[0041] Step S40: Form a second gate oxide layer, wherein the second gate oxide layer covers the substrate of the defined region of the second gate oxide layer;

[0042] Step S50: Remove the first gate oxide layer on the third gate oxide layer definition region;

[0043] Step S60: Form a third gate oxide layer, wherein the third gate oxide layer covers the substrate of the defined region of the third gate oxide layer.

[0044] Figures 2 to 8 This is a structural schematic diagram of the corresponding steps in a method for forming a gate oxide layer according to an embodiment of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 2 to 8 Specific embodiments of the present invention will be described in detail below.

[0045] like Figure 2 As shown, a substrate 10 is provided. In some embodiments, the substrate 10 can be a semiconductor substrate, made of any semiconductor material suitable for semiconductor devices (such as Si, SiC, SiGe, etc.). In other embodiments, the substrate 10 can also be various composite substrates such as silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGOI). The electron mobility of the silicon-germanium layer is higher than that of pure silicon. This high electron mobility can not only reduce noise, bias current, and feed power, but also increase the operating frequency. Compared with pure silicon, silicon-germanium can also achieve stable operating characteristics over a very wide temperature range. Therefore, silicon-germanium is widely used in bipolar and advanced CMOS devices. Those skilled in the art will understand that the substrate is not limited in any way, but can be selected according to the actual application. The substrate 10 includes a first gate oxide layer defining region 10a, a second gate oxide layer defining region 10b, and a third gate oxide layer defining region 10c.

[0046] Please continue to refer to this. Figure 2 A first gate oxide layer 11 is formed, which covers the substrate of the first gate oxide layer definition region 10a, the second gate oxide layer definition region 10b, and the third gate oxide layer definition region 10c. The material of the first gate oxide layer 11 is, for example, silicon oxide, and it can be formed using a thermal oxidation process, such as ISSG (In-Situ Steam Generation). The thickness of the first gate oxide layer 11 is, for example, 50 angstroms to 60 angstroms.

[0047] like Figure 3 and Figure 4 As shown, the first gate oxide layer 11 on the second gate oxide layer definition region 10b is removed, while the first gate oxide layer 11 on the first gate oxide layer definition region 10a and the third gate oxide layer definition region 10c is retained. Specifically, the step of removing the first gate oxide layer on the second gate oxide layer definition region includes: as shown in the figure. Figure 3As shown, a patterned first photoresist layer 12 is formed, which covers the first gate oxide layer 11 on the first gate oxide layer definition region 10a and the third gate oxide layer definition region 10c, and exposes the top surface of the first gate oxide layer 11 on the second gate oxide layer definition region 10b. Figure 4 As shown, a first etching process is performed, using the patterned first photoresist layer 12 as a mask to etch the first gate oxide layer 11 on the second gate oxide layer definition region 10b, while retaining the first gate oxide layer 11 on the first gate oxide layer definition region 10a and the third gate oxide layer definition region 10c. The first etching process is a wet etching process. The etching solution for the first etching process includes hydrofluoric acid.

[0048] like Figure 5 As shown, a second gate oxide layer 13 is formed, which covers the substrate of the defined region 10b of the second gate oxide layer. The material of the second gate oxide layer 13 is, for example, silicon oxide, and it can be formed using a thermal oxidation process, such as ISSG (In-Situ Steam Generation). The thickness of the second gate oxide layer 13 is different from the thickness of the first gate oxide layer 11, and the thickness of the second gate oxide layer 13 is less than the thickness of the first gate oxide layer 11. In this embodiment, the thickness of the second gate oxide layer 13 is controlled to grow to the target thickness by controlling the process time of the thermal oxidation process. The thickness of the second gate oxide layer 13 is, for example, 30 angstroms to 35 angstroms.

[0049] like Figure 6 and Figure 7 As shown, the first gate oxide layer 11 on the third gate oxide layer definition region 10c is removed. Specifically, the step of removing the first gate oxide layer 11 on the third gate oxide layer definition region 10c includes: as shown... Figure 6 As shown, a patterned second photoresist layer 14 is formed, which covers the first gate oxide layer 11 on the first gate oxide layer definition region 10a and the second gate oxide layer 13 on the second gate oxide layer definition region 10b, and exposes the top surface of the first gate oxide layer 11 on the third gate oxide layer definition region 10c. Figure 7As shown, a second etching process is performed, using the patterned second photoresist layer 14 as a mask to etch the first gate oxide layer 11 on the third gate oxide layer definition region 10c, while retaining the first gate oxide layer 11 on the first gate oxide layer definition region 10a and the second gate oxide layer 13 on the second gate oxide layer definition region 10b. The second etching process is a wet etching process. The etching solution for the second etching process includes hydrofluoric acid.

[0050] like Figure 8 As shown, a third gate oxide layer 15 is formed, which covers the substrate of the third gate oxide layer definition region 10c. The material of the third gate oxide layer 15 is, for example, silicon oxide, and it can be formed using a thermal oxidation process, such as ISSG (In-Situ Steam Generation). The thickness of the third gate oxide layer 15 is different from the thickness of the second gate oxide layer 13 and the first gate oxide layer 11, and the thickness of the third gate oxide layer 15 is less than the thickness of the second gate oxide layer 13 and also less than the thickness of the first gate oxide layer 11. In this embodiment, the thickness of the third gate oxide layer 15 is controlled to grow to the target thickness by controlling the process time of the thermal oxidation process. The thickness of the third gate oxide layer 15 is, for example, 15 angstroms to 20 angstroms.

[0051] like Figure 8 As shown, this embodiment also provides a gate oxide layer, which is prepared using the gate oxide layer formation method described in any one of the above claims, including:

[0052] Substrate 10, the substrate 10 includes a first gate oxide layer definition region 10a, a second gate oxide layer definition region 10b and a third gate oxide layer definition region 10c.

[0053] A first gate oxide layer 11 is located on the substrate of the first gate oxide layer definition region 10a.

[0054] A second gate oxide layer 13 is located on the substrate of the second gate oxide layer definition region 10b.

[0055] A third gate oxide layer 15 is located on the substrate of the third gate oxide layer definition region 10c.

[0056] The first gate oxide layer 11, the second gate oxide layer 13, and the third gate oxide layer 15 have different thicknesses.

[0057] In summary, in the method for forming a gate oxide layer provided by the embodiments of the present invention, the substrate includes a first gate oxide layer definition region, a second gate oxide layer definition region, and a third gate oxide layer definition region; a first gate oxide layer is formed, covering the substrate of the first gate oxide layer definition region, the second gate oxide layer definition region, and the third gate oxide layer definition region; the first gate oxide layer on the second gate oxide layer definition region is removed, while retaining the first gate oxide layers on the first gate oxide layer definition region and the third gate oxide layer definition region; a second gate oxide layer is formed, covering the substrate of the second gate oxide layer definition region; the first gate oxide layer on the third gate oxide layer definition region is removed; and a third gate oxide layer is formed, covering the substrate of the third gate oxide layer definition region. The present invention, by retaining the first gate oxide layers on the first gate oxide layer definition regions and the third gate oxide layer definition regions during the removal of the first gate oxide layer on the second gate oxide layer definition region, ensures that the substrate on the third gate oxide layer definition region only has one acid contact, reducing the impact of acid pickling on the substrate on the third gate oxide layer definition region.

[0058] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, the different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0059] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A method for forming a gate oxide layer, characterized in that, include: A substrate is provided, the substrate including a first gate oxide layer definition region, a second gate oxide layer definition region and a third gate oxide layer definition region; A first gate oxide layer is formed, which covers the substrate of the first gate oxide layer definition region, the second gate oxide layer definition region, and the third gate oxide layer definition region. Remove the first gate oxide layer on the second gate oxide layer definition region, and retain the first gate oxide layer on the first gate oxide layer definition region and the third gate oxide layer definition region; A second gate oxide layer is formed, the second gate oxide layer covering the substrate of the region defined by the second gate oxide layer; Remove the first gate oxide layer on the third gate oxide layer definition region; A third gate oxide layer is formed, which covers the substrate of the region defined by the third gate oxide layer.

2. The method for forming a gate oxide layer according to claim 1, characterized in that, The step of removing the first gate oxide layer on the second gate oxide layer definition region includes: A patterned first photoresist layer is formed, the patterned first photoresist layer covering the first gate oxide layer on the first gate oxide layer definition region and the first gate oxide layer definition region, and exposing the top surface of the first gate oxide layer on the second gate oxide layer definition region; The first etching process is performed, using the patterned first photoresist layer as a mask, to etch the first gate oxide layer on the second gate oxide layer definition region, while retaining the first gate oxide layer on the first gate oxide layer definition region and the first gate oxide layer on the third gate oxide layer definition region.

3. The method for forming a gate oxide layer according to claim 2, characterized in that, The step of removing the first gate oxide layer on the third gate oxide layer definition region includes: A patterned second photoresist layer is formed, which covers the first gate oxide layer in the first gate oxide layer definition region and the second gate oxide layer in the second gate oxide layer definition region, and exposes the top surface of the first gate oxide layer in the third gate oxide layer definition region; A second etching process is performed, using the patterned second photoresist layer as a mask, to etch the first gate oxide layer on the third gate oxide layer definition region, while retaining the first gate oxide layer on the first gate oxide layer definition region and the second gate oxide layer on the second gate oxide layer definition region.

4. The method for forming a gate oxide layer according to claim 3, characterized in that, Both the first etching process and the second etching process are wet etching processes.

5. The method for forming a gate oxide layer according to claim 4, characterized in that, The etching solutions for the first etching process and the second etching process include hydrofluoric acid.

6. The method for forming a gate oxide layer according to claim 1, characterized in that, The first gate oxide layer, the second gate oxide layer, and the third gate oxide layer have different thicknesses.

7. The method for forming a gate oxide layer according to claim 6, characterized in that, The thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, and the thickness of the second gate oxide layer is greater than the thickness of the third gate oxide layer.

8. The method for forming a gate oxide layer according to claim 1, characterized in that, The first gate oxide layer, the second gate oxide layer, and the third gate oxide layer are formed by a thermal oxidation process.

9. A gate oxide layer, characterized in that, The gate oxide layer is prepared by the method for forming the gate oxide layer as described in any one of claims 1 to 8, comprising: The substrate includes a first gate oxide layer definition region, a second gate oxide layer definition region, and a third gate oxide layer definition region; A first gate oxide layer is located on the substrate within the region defined by the first gate oxide layer; A second gate oxide layer is located on the substrate within the region defined by the second gate oxide layer; A third gate oxide layer is located on the substrate within the defined region of the third gate oxide layer.

10. The gate oxide layer according to claim 9, characterized in that, The first gate oxide layer, the second gate oxide layer, and the third gate oxide layer have different thicknesses.

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